summaryrefslogtreecommitdiff
path: root/arch/riscv
diff options
context:
space:
mode:
Diffstat (limited to 'arch/riscv')
-rw-r--r--arch/riscv/config.mk18
-rw-r--r--arch/riscv/cpu/th1520/Kconfig1
-rw-r--r--arch/riscv/cpu/th1520/Makefile2
-rw-r--r--arch/riscv/cpu/th1520/cache.c2
-rw-r--r--arch/riscv/cpu/th1520/cpu.c29
-rw-r--r--arch/riscv/cpu/th1520/spl.c83
-rw-r--r--arch/riscv/dts/Makefile2
-rw-r--r--arch/riscv/dts/th1520.dtsi29
-rw-r--r--arch/riscv/dts/thead-th1520-binman.dtsi32
-rw-r--r--arch/riscv/include/asm/arch-th1520/cpu.h1
-rw-r--r--arch/riscv/include/asm/byteorder.h2
-rw-r--r--arch/riscv/include/asm/global_data.h2
-rw-r--r--arch/riscv/lib/aclint_ipi.c5
-rw-r--r--arch/riscv/lib/spl.c2
14 files changed, 196 insertions, 14 deletions
diff --git a/arch/riscv/config.mk b/arch/riscv/config.mk
index 9f16dda92a0..eddd6a3b9a2 100644
--- a/arch/riscv/config.mk
+++ b/arch/riscv/config.mk
@@ -10,19 +10,29 @@
# Rick Chen, Andes Technology Corporation <rick@andestech.com>
#
-32bit-emul := elf32lriscv
-64bit-emul := elf64lriscv
+ifdef CONFIG_SYS_BIG_ENDIAN
+small-endian := b
+large-endian := big
+PLATFORM_CPPFLAGS += -mbig-endian
+KBUILD_LDFLAGS += -mbig-endian
+else
+small-endian := l
+large-endian := little
+endif
+
+32bit-emul := elf32$(small-endian)riscv
+64bit-emul := elf64$(small-endian)riscv
ifdef CONFIG_32BIT
KBUILD_LDFLAGS += -m $(32bit-emul)
EFI_LDS := elf_riscv32_efi.lds
-PLATFORM_ELFFLAGS += -B riscv -O elf32-littleriscv
+PLATFORM_ELFFLAGS += -B riscv -O elf32-$(large-endian)riscv
endif
ifdef CONFIG_64BIT
KBUILD_LDFLAGS += -m $(64bit-emul)
EFI_LDS := elf_riscv64_efi.lds
-PLATFORM_ELFFLAGS += -B riscv -O elf64-littleriscv
+PLATFORM_ELFFLAGS += -B riscv -O elf64-$(large-endian)riscv
endif
PLATFORM_CPPFLAGS += -ffixed-x3 -fpic
diff --git a/arch/riscv/cpu/th1520/Kconfig b/arch/riscv/cpu/th1520/Kconfig
index 4d44191bd22..c73462c04b8 100644
--- a/arch/riscv/cpu/th1520/Kconfig
+++ b/arch/riscv/cpu/th1520/Kconfig
@@ -11,6 +11,7 @@ config THEAD_TH1520
select BINMAN if SPL
select SYS_CACHE_THEAD_CMO
select CLK_THEAD
+ select PINCTRL_TH1520
imply CPU
imply CPU_RISCV
imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE)
diff --git a/arch/riscv/cpu/th1520/Makefile b/arch/riscv/cpu/th1520/Makefile
index 5d806c06e2e..d971ea7390d 100644
--- a/arch/riscv/cpu/th1520/Makefile
+++ b/arch/riscv/cpu/th1520/Makefile
@@ -5,4 +5,4 @@
obj-y += cache.o
obj-y += cpu.o
obj-y += dram.o
-obj-y += spl.o
+obj-$(CONFIG_SPL_BUILD) += spl.o
diff --git a/arch/riscv/cpu/th1520/cache.c b/arch/riscv/cpu/th1520/cache.c
index 08aa1f789fd..b2fec229363 100644
--- a/arch/riscv/cpu/th1520/cache.c
+++ b/arch/riscv/cpu/th1520/cache.c
@@ -11,6 +11,7 @@
#define CSR_MHCR_IE BIT(0)
#define CSR_MHCR_DE BIT(1)
+#if CONFIG_IS_ENABLED(RISCV_MMODE)
void icache_enable(void)
{
csr_write(CSR_MHCR, csr_read(CSR_MHCR) | CSR_MHCR_IE);
@@ -30,3 +31,4 @@ int dcache_status(void)
{
return (csr_read(CSR_MHCR) & CSR_MHCR_DE) != 0;
}
+#endif /* CONFIG_IS_ENABLED(RISCV_MMODE) */
diff --git a/arch/riscv/cpu/th1520/cpu.c b/arch/riscv/cpu/th1520/cpu.c
index b83f1272c67..f60446fd772 100644
--- a/arch/riscv/cpu/th1520/cpu.c
+++ b/arch/riscv/cpu/th1520/cpu.c
@@ -9,8 +9,35 @@
#include <asm/io.h>
#include <cpu_func.h>
+#include <linux/bitops.h>
-#define TH1520_PMP_BASE (void *)0xffdc020000
+#define TH1520_C910_RST (void __iomem *)(0xffef014000 + 0x004)
+#define TH1520_C910_CORE_RST_N(n) BIT((n) + 1)
+#define TH1520_SYSCFG_AP_BASE (void __iomem *)(0xffef018000)
+#define TH1520_SYSCFG_CORE_START_L(n) (TH1520_SYSCFG_AP_BASE + 0x50 + 8 * (n))
+#define TH1520_SYSCFG_CORE_START_H(n) (TH1520_SYSCFG_AP_BASE + 0x54 + 8 * (n))
+#define TH1520_PMP_BASE (void *)0xffdc020000
+
+void th1520_kick_secondary_cores(void)
+{
+ int i;
+
+ /*
+ * On coldboot, only HART 0 is brought up by hardware, and resets for
+ * secondary cores are asserted. Set reset address of secondary cores
+ * to the entry of SPL, then deassert the resets to bring them up.
+ */
+ for (i = 1; i < 4; i++) {
+ writel(CONFIG_SPL_TEXT_BASE & 0xffffffff,
+ TH1520_SYSCFG_CORE_START_L(i));
+ writel(CONFIG_SPL_TEXT_BASE >> 32,
+ TH1520_SYSCFG_CORE_START_H(i));
+ }
+
+ setbits_le32(TH1520_C910_RST, TH1520_C910_CORE_RST_N(1) |
+ TH1520_C910_CORE_RST_N(2) |
+ TH1520_C910_CORE_RST_N(3));
+}
void th1520_invalidate_pmp(void)
{
diff --git a/arch/riscv/cpu/th1520/spl.c b/arch/riscv/cpu/th1520/spl.c
index 362fe895f86..b95470485f6 100644
--- a/arch/riscv/cpu/th1520/spl.c
+++ b/arch/riscv/cpu/th1520/spl.c
@@ -4,6 +4,7 @@
*/
#include <asm/arch/iopmp.h>
#include <asm/io.h>
+#include <cpu_func.h>
#include <dm.h>
#include <linux/sizes.h>
#include <log.h>
@@ -21,6 +22,52 @@ DECLARE_GLOBAL_DATA_PTR;
#define TH1520_SUBSYS_RST_VI_N BIT(1)
#define TH1520_SUBSYS_RST_DSP_N BIT(0)
+#define CSR_MXSTATUS 0x7c0
+#define CSR_MXSTATUS_THEADISAEE BIT(22)
+#define CSR_MXSTATUS_MAEE BIT(21)
+#define CSR_MXSTATUS_CLINTEE BIT(17)
+#define CSR_MXSTATUS_UCME BIT(16)
+#define CSR_MXSTATUS_MM BIT(15)
+#define CSR_MHCR 0x7c1
+#define CSR_MHCR_WBR BIT(8)
+#define CSR_MHCR_BTB BIT(6)
+#define CSR_MHCR_BPE BIT(5)
+#define CSR_MHCR_RS BIT(4)
+#define CSR_MHCR_WB BIT(3)
+#define CSR_MHCR_WA BIT(2)
+#define CSR_MHCR_DE BIT(1)
+#define CSR_MHCR_IE BIT(0)
+#define CSR_MCOR 0x7c2
+#define CSR_MCOR_IBP_INV BIT(18)
+#define CSR_MCOR_BTB_INV BIT(17)
+#define CSR_MCOR_BHT_INV BIT(16)
+#define CSR_MCOR_CACHE_INV BIT(4)
+#define CSR_MCCR2 0x7c3
+#define CSR_MCCR2_TPRF BIT(31)
+#define CSR_MCCR2_IPRF(n) ((n) << 29)
+#define CSR_MCCR2_TSETUP BIT(25)
+#define CSR_MCCR2_TLNTCY(n) ((n) << 22)
+#define CSR_MCCR2_DSETUP BIT(19)
+#define CSR_MCCR2_DLNTCY(n) ((n) << 16)
+#define CSR_MCCR2_L2EN BIT(3)
+#define CSR_MCCR2_RFE BIT(0)
+#define CSR_MHINT 0x7c5
+#define CSR_MHINT_FENCERW_BROAD_DIS BIT(22)
+#define CSR_MHINT_TLB_BRAOD_DIS BIT(21)
+#define CSR_MHINT_NSFE BIT(18)
+#define CSR_MHINT_L2_PREF_DIST(n) ((n) << 16)
+#define CSR_MHINT_L2PLD BIT(15)
+#define CSR_MHINT_DCACHE_PREF_DIST(n) ((n) << 13)
+#define CSR_MHINT_LPE BIT(9)
+#define CSR_MHINT_ICACHE_PREF BIT(8)
+#define CSR_MHINT_AMR BIT(3)
+#define CSR_MHINT_DCACHE_PREF BIT(2)
+#define CSR_MHINT2 0x7cc
+#define CSR_MHINT2_LOCAL_ICG_EN(n) BIT((n) + 14)
+#define CSR_MHINT4 0x7ce
+#define CSR_MSMPR 0x7f3
+#define CSR_MSMPR_SMPEN BIT(0)
+
int spl_dram_init(void)
{
int ret;
@@ -77,6 +124,42 @@ void harts_early_init(void)
{
int i;
+ /* Invalidate cache and buffer entries */
+ csr_write(CSR_MCOR, CSR_MCOR_IBP_INV | CSR_MCOR_BTB_INV |
+ CSR_MCOR_BHT_INV | CSR_MCOR_CACHE_INV | 0x3);
+
+ /* Enable cache snooping */
+ csr_write(CSR_MSMPR, CSR_MSMPR_SMPEN);
+
+ /*
+ * Configure and enable L2 cache,
+ * Enable tag/data RAM prefetch, both cost 2 cycles
+ * Prefetch 3 cache lines of instructions
+ * Enable read allocation
+ */
+ csr_write(CSR_MCCR2, CSR_MCCR2_TPRF | CSR_MCCR2_IPRF(3) |
+ CSR_MCCR2_TSETUP | CSR_MCCR2_TLNTCY(1) |
+ CSR_MCCR2_DSETUP | CSR_MCCR2_DLNTCY(1) |
+ CSR_MCCR2_L2EN | CSR_MCCR2_RFE);
+ csr_write(CSR_MXSTATUS, CSR_MXSTATUS_THEADISAEE | CSR_MXSTATUS_MAEE |
+ CSR_MXSTATUS_CLINTEE | CSR_MXSTATUS_UCME |
+ CSR_MXSTATUS_MM);
+ csr_write(CSR_MHINT, CSR_MHINT_FENCERW_BROAD_DIS |
+ CSR_MHINT_TLB_BRAOD_DIS |
+ CSR_MHINT_NSFE |
+ CSR_MHINT_L2_PREF_DIST(2) |
+ CSR_MHINT_L2PLD |
+ CSR_MHINT_DCACHE_PREF_DIST(3) |
+ CSR_MHINT_LPE |
+ CSR_MHINT_ICACHE_PREF |
+ CSR_MHINT_AMR |
+ CSR_MHINT_DCACHE_PREF);
+ csr_write(CSR_MHCR, CSR_MHCR_WBR | CSR_MHCR_BTB | CSR_MHCR_BPE |
+ CSR_MHCR_RS | CSR_MHCR_WB | CSR_MHCR_WA | 0x3);
+ csr_write(CSR_MHINT2, CSR_MHINT2_LOCAL_ICG_EN(8) |
+ CSR_MHINT2_LOCAL_ICG_EN(3));
+ csr_write(CSR_MHINT4, 0x410);
+
/*
* Set IOPMPs to the default attribute, allowing the application
* processor to access various peripherals. Subsystem clocks should be
diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile
index cf1872f3fdc..2b10c2d6c01 100644
--- a/arch/riscv/dts/Makefile
+++ b/arch/riscv/dts/Makefile
@@ -19,4 +19,4 @@ dtb-$(CONFIG_TARGET_ASPEED_AST2700_IBEX) += ast2700-ibex.dtb
include $(srctree)/scripts/Makefile.dts
# Add any required device tree compiler flags here
-DTC_FLAGS += -R 4 -p 0x1000
+DTC_FLAGS += -R 4
diff --git a/arch/riscv/dts/th1520.dtsi b/arch/riscv/dts/th1520.dtsi
index 28107a9f354..8306eda5521 100644
--- a/arch/riscv/dts/th1520.dtsi
+++ b/arch/riscv/dts/th1520.dtsi
@@ -128,6 +128,13 @@
#clock-cells = <0>;
};
+ aonsys_clk: clock-73728000 {
+ compatible = "fixed-clock";
+ clock-frequency = <73728000>;
+ clock-output-names = "aonsys_clk";
+ #clock-cells = <0>;
+ };
+
soc {
compatible = "simple-bus";
interrupt-parent = <&plic>;
@@ -151,6 +158,7 @@
clint: timer@ffdc000000 {
compatible = "thead,th1520-clint", "thead,c900-clint";
reg = <0xff 0xdc000000 0x0 0x00010000>;
+ bootph-pre-ram;
interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
<&cpu1_intc 3>, <&cpu1_intc 7>,
<&cpu2_intc 3>, <&cpu2_intc 7>,
@@ -258,6 +266,13 @@
};
};
+ padctrl1_apsys: pinctrl@ffe7f3c000 {
+ compatible = "thead,th1520-pinctrl";
+ reg = <0xff 0xe7f3c000 0x0 0x1000>;
+ clocks = <&clk CLK_PADCTRL1>;
+ thead,pad-group = <2>;
+ };
+
gpio0: gpio@ffec005000 {
compatible = "snps,dw-apb-gpio";
reg = <0xff 0xec005000 0x0 0x1000>;
@@ -298,6 +313,13 @@
};
};
+ padctrl0_apsys: pinctrl@ffec007000 {
+ compatible = "thead,th1520-pinctrl";
+ reg = <0xff 0xec007000 0x0 0x1000>;
+ clocks = <&clk CLK_PADCTRL0>;
+ thead,pad-group = <3>;
+ };
+
uart2: serial@ffec010000 {
compatible = "snps,dw-apb-uart";
reg = <0xff 0xec010000 0x0 0x4000>;
@@ -438,6 +460,13 @@
};
};
+ padctrl_aosys: pinctrl@fffff4a000 {
+ compatible = "thead,th1520-pinctrl";
+ reg = <0xff 0xfff4a000 0x0 0x2000>;
+ clocks = <&aonsys_clk>;
+ thead,pad-group = <1>;
+ };
+
ao_gpio1: gpio@fffff52000 {
compatible = "snps,dw-apb-gpio";
reg = <0xff 0xfff52000 0x0 0x1000>;
diff --git a/arch/riscv/dts/thead-th1520-binman.dtsi b/arch/riscv/dts/thead-th1520-binman.dtsi
index f060639e1c6..7b535e8402c 100644
--- a/arch/riscv/dts/thead-th1520-binman.dtsi
+++ b/arch/riscv/dts/thead-th1520-binman.dtsi
@@ -30,24 +30,48 @@
fit,fdt-list = "of-list";
images {
+ opensbi {
+ description = "OpenSBI fw_dynamic Firmware";
+ type = "firmware";
+ os = "opensbi";
+ arch = "riscv";
+ load = /bits/ 64 <CONFIG_SPL_OPENSBI_LOAD_ADDR>;
+ entry = /bits/ 64 <CONFIG_SPL_OPENSBI_LOAD_ADDR>;
+
+ opensbi_blob: opensbi {
+ filename = "fw_dynamic.bin";
+ missing-msg = "opensbi";
+ };
+ };
+
uboot {
description = "U-Boot";
type = "standalone";
+ firmware = "opensbi";
os = "U-boot";
arch = "riscv";
compression = "none";
load = /bits/ 64 <CONFIG_TEXT_BASE>;
- uboot_blob: u-boot {
+ uboot_nodtb_blob: u-boot-nodtb {
};
};
+
+ @fdt-SEQ {
+ fit,operation = "gen-fdt-nodes";
+ description = "NAME";
+ type = "flat_dt";
+ compression = "none";
+ };
};
configurations {
- default = "conf-th1520-lichee-pi-4a";
+ default = "@conf-DEFAULT-SEQ";
- conf-th1520-lichee-pi-4a {
- description = "th1520-lichee-pi-4a";
+ @conf-SEQ {
+ description = "NAME";
+ fdt = "fdt-SEQ";
+ firmware = "opensbi";
loadables = "uboot";
};
};
diff --git a/arch/riscv/include/asm/arch-th1520/cpu.h b/arch/riscv/include/asm/arch-th1520/cpu.h
index 837f0b8d06b..e164e9ab979 100644
--- a/arch/riscv/include/asm/arch-th1520/cpu.h
+++ b/arch/riscv/include/asm/arch-th1520/cpu.h
@@ -5,5 +5,6 @@
#ifndef _ASM_TH1520_CPU_H_
#define _ASM_TH1520_CPU_H_
+void th1520_kick_secondary_cores(void);
void th1520_invalidate_pmp(void);
#endif /* _ASM_TH1520_CPU_H_ */
diff --git a/arch/riscv/include/asm/byteorder.h b/arch/riscv/include/asm/byteorder.h
index d26ac5688fa..3140c1f585e 100644
--- a/arch/riscv/include/asm/byteorder.h
+++ b/arch/riscv/include/asm/byteorder.h
@@ -26,7 +26,7 @@
# define __SWAB_64_THRU_32__
#endif
-#ifdef __RISCVEB__
+#if defined(__RISCVEB__) || (defined(__BYTE_ORDER__) && __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__)
#include <linux/byteorder/big_endian.h>
#else
#include <linux/byteorder/little_endian.h>
diff --git a/arch/riscv/include/asm/global_data.h b/arch/riscv/include/asm/global_data.h
index 47b5e2cfc8f..33f2b5ec5c8 100644
--- a/arch/riscv/include/asm/global_data.h
+++ b/arch/riscv/include/asm/global_data.h
@@ -68,7 +68,7 @@ static inline gd_t *get_gd(void)
#endif
-static inline void set_gd(volatile gd_t *gd_ptr)
+static inline void set_gd(gd_t *gd_ptr)
{
#ifdef CONFIG_64BIT
asm volatile("ld gp, %0\n" : : "m"(gd_ptr));
diff --git a/arch/riscv/lib/aclint_ipi.c b/arch/riscv/lib/aclint_ipi.c
index dcd7e5e6b34..1c9a2d70301 100644
--- a/arch/riscv/lib/aclint_ipi.c
+++ b/arch/riscv/lib/aclint_ipi.c
@@ -29,6 +29,10 @@ int riscv_init_ipi(void)
ret = uclass_get_device_by_driver(UCLASS_TIMER,
DM_DRIVER_GET(riscv_aclint_timer), &dev);
+ if (ret == -ENODEV)
+ ret = uclass_get_device_by_driver(UCLASS_SYSCON,
+ DM_DRIVER_GET(riscv_aclint_swi), &dev);
+
if (ret)
return ret;
@@ -66,6 +70,7 @@ int riscv_get_ipi(int hart, int *pending)
static const struct udevice_id riscv_aclint_swi_ids[] = {
{ .compatible = "riscv,aclint-mswi", .data = RISCV_SYSCON_ACLINT },
+ { .compatible = "thead,c900-clint", .data = RISCV_SYSCON_ACLINT },
{ }
};
diff --git a/arch/riscv/lib/spl.c b/arch/riscv/lib/spl.c
index 9a7a4f6ac8d..38a5ab27dd8 100644
--- a/arch/riscv/lib/spl.c
+++ b/arch/riscv/lib/spl.c
@@ -36,7 +36,7 @@ __weak void board_init_f(ulong dummy)
panic("spl_board_init_f() failed: %d\n", ret);
}
-void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
+void __noreturn jump_to_image(struct spl_image_info *spl_image)
{
typedef void __noreturn (*image_entry_riscv_t)(ulong hart, void *dtb);
void *fdt_blob;
generated by cgit v1.2.3 (git 2.0.4) at 2025-07-17 07:34:46 +0000