3 files changed, 11 insertions, 19 deletions

diff --git a/arch/x86/cpu/broadwell/cpu.c b/arch/x86/cpu/broadwell/cpu.c
index bba8cd1e942..297f1e0b682 100644
--- a/arch/x86/cpu/broadwell/cpu.c
+++ b/arch/x86/cpu/broadwell/cpu.c
@@ -103,11 +103,8 @@ int print_cpuinfo(void)
 
 void board_debug_uart_init(void)
 {
-	struct udevice *bus = NULL;
-
 	/* com1 / com2 decode range */
-	pci_x86_write_config(bus, PCH_DEV_LPC, LPC_IO_DEC, 1 << 4, PCI_SIZE_16);
+	pci_x86_write_config(PCH_DEV_LPC, LPC_IO_DEC, 1 << 4, PCI_SIZE_16);
 
-	pci_x86_write_config(bus, PCH_DEV_LPC, LPC_EN, COMA_LPC_EN,
-			     PCI_SIZE_16);
+	pci_x86_write_config(PCH_DEV_LPC, LPC_EN, COMA_LPC_EN, PCI_SIZE_16);
 }
diff --git a/arch/x86/cpu/ivybridge/cpu.c b/arch/x86/cpu/ivybridge/cpu.c
index c8b16e32c03..6db9da81b71 100644
--- a/arch/x86/cpu/ivybridge/cpu.c
+++ b/arch/x86/cpu/ivybridge/cpu.c
@@ -199,6 +199,5 @@ int print_cpuinfo(void)
 void board_debug_uart_init(void)
 {
 	/* This enables the debug UART */
-	pci_x86_write_config(NULL, PCH_LPC_DEV, LPC_EN, COMA_LPC_EN,
-			     PCI_SIZE_16);
+	pci_x86_write_config(PCH_LPC_DEV, LPC_EN, COMA_LPC_EN, PCI_SIZE_16);
 }
diff --git a/arch/x86/cpu/pci.c b/arch/x86/cpu/pci.c
index 0ccde194d9a..e1aae158ce5 100644
--- a/arch/x86/cpu/pci.c
+++ b/arch/x86/cpu/pci.c
@@ -16,12 +16,8 @@
 #include <asm/io.h>
 #include <asm/pci.h>
 
-/*
- * TODO(sjg@chromium.org): Drop the first parameter from each of these
- * functions since it is not used.
- */
-int pci_x86_read_config(struct udevice *bus, pci_dev_t bdf, uint offset,
-			ulong *valuep, enum pci_size_t size)
+int pci_x86_read_config(pci_dev_t bdf, uint offset, ulong *valuep,
+			enum pci_size_t size)
 {
 	outl(bdf | (offset & 0xfc) | PCI_CFG_EN, PCI_REG_ADDR);
 	switch (size) {
@@ -39,8 +35,8 @@ int pci_x86_read_config(struct udevice *bus, pci_dev_t bdf, uint offset,
 	return 0;
 }
 
-int pci_x86_write_config(struct udevice *bus, pci_dev_t bdf, uint offset,
-			 ulong value, enum pci_size_t size)
+int pci_x86_write_config(pci_dev_t bdf, uint offset, ulong value,
+			 enum pci_size_t size)
 {
 	outl(bdf | (offset & 0xfc) | PCI_CFG_EN, PCI_REG_ADDR);
 	switch (size) {
@@ -58,19 +54,19 @@ int pci_x86_write_config(struct udevice *bus, pci_dev_t bdf, uint offset,
 	return 0;
 }
 
-int pci_x86_clrset_config(struct udevice *bus, pci_dev_t bdf, uint offset,
-			  ulong clr, ulong set, enum pci_size_t size)
+int pci_x86_clrset_config(pci_dev_t bdf, uint offset, ulong clr, ulong set,
+			  enum pci_size_t size)
 {
 	ulong value;
 	int ret;
 
-	ret = pci_x86_read_config(bus, bdf, offset, &value, size);
+	ret = pci_x86_read_config(bdf, offset, &value, size);
 	if (ret)
 		return ret;
 	value &= ~clr;
 	value |= set;
 
-	return pci_x86_write_config(bus, bdf, offset, value, size);
+	return pci_x86_write_config(bdf, offset, value, size);
 }
 
 void pci_assign_irqs(int bus, int device, u8 irq[4])