diff options
Diffstat (limited to 'arch')
71 files changed, 5121 insertions, 403 deletions
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 8a366e5369b..dabd3b91859 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -174,6 +174,8 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \ dtb-$(CONFIG_ROCKCHIP_RK3568) += \ rk3566-anbernic-rgxx3.dtb \ + rk3566-pinetab2-v0.1.dtb \ + rk3566-pinetab2-v2.0.dtb \ rk3566-quartz64-a.dtb \ rk3566-quartz64-b.dtb \ rk3566-radxa-cm3-io.dtb \ @@ -191,16 +193,20 @@ dtb-$(CONFIG_ROCKCHIP_RK3568) += \ rk3568-rock-3a.dtb dtb-$(CONFIG_ROCKCHIP_RK3588) += \ + rk3588s-coolpi-4b.dts \ + rk3588-coolpi-cm5-evb.dts \ rk3588-edgeble-neu6a-io.dtb \ rk3588-edgeble-neu6b-io.dtb \ rk3588-evb1-v10.dtb \ + rk3588-generic.dtb \ + rk3588-jaguar.dtb \ rk3588-nanopc-t6.dtb \ rk3588s-orangepi-5.dtb \ rk3588-orangepi-5-plus.dtb \ rk3588-quartzpro64.dtb \ - rk3588-turing-rk1.dtb \ rk3588s-rock-5a.dtb \ - rk3588-rock-5b.dtb + rk3588-rock-5b.dtb \ + rk3588-turing-rk1.dtb dtb-$(CONFIG_ROCKCHIP_RV1108) += \ rv1108-elgin-r1.dtb \ diff --git a/arch/arm/dts/rk3328-evb-u-boot.dtsi b/arch/arm/dts/rk3328-evb-u-boot.dtsi index 12b68df1ac6..38ad3cc16d0 100644 --- a/arch/arm/dts/rk3328-evb-u-boot.dtsi +++ b/arch/arm/dts/rk3328-evb-u-boot.dtsi @@ -44,3 +44,7 @@ /* Integrated PHY unsupported by U-Boot */ status = "broken"; }; + +&vcc_sd { + bootph-pre-ram; +}; diff --git a/arch/arm/dts/rk3328-evb.dts b/arch/arm/dts/rk3328-evb.dts index ff6b466e0e0..1eef5504445 100644 --- a/arch/arm/dts/rk3328-evb.dts +++ b/arch/arm/dts/rk3328-evb.dts @@ -11,6 +11,7 @@ compatible = "rockchip,rk3328-evb", "rockchip,rk3328"; aliases { + ethernet0 = &gmac2phy; mmc0 = &sdmmc; mmc1 = &sdio; mmc2 = &emmc; diff --git a/arch/arm/dts/rk3328-nanopi-r2c-plus-u-boot.dtsi b/arch/arm/dts/rk3328-nanopi-r2c-plus-u-boot.dtsi index f8adb9e5e1f..1dc3c022c50 100644 --- a/arch/arm/dts/rk3328-nanopi-r2c-plus-u-boot.dtsi +++ b/arch/arm/dts/rk3328-nanopi-r2c-plus-u-boot.dtsi @@ -1,9 +1,3 @@ // SPDX-License-Identifier: GPL-2.0-or-later #include "rk3328-nanopi-r2c-u-boot.dtsi" - -/ { - chosen { - u-boot,spl-boot-order = "same-as-spl", &sdmmc, &emmc; - }; -}; diff --git a/arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi b/arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi index 78d37ab4755..4fa170eeaf8 100644 --- a/arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi +++ b/arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi @@ -6,35 +6,23 @@ #include "rk3328-u-boot.dtsi" #include "rk3328-sdram-ddr4-666.dtsi" -/ { - chosen { - u-boot,spl-boot-order = "same-as-spl", &sdmmc, &emmc; - }; -}; -&gpio0 { +&gpio1 { bootph-pre-ram; }; -&pinctrl { - bootph-pre-ram; +&sdio_vcc_pin { + bootph-all; }; -&sdmmc0m1_pin { - bootph-pre-ram; +&usb20_otg { + dr_mode = "peripheral"; }; -&pcfg_pull_up_4ma { +&vcc_io_sdio { bootph-pre-ram; }; -/* Need this and all the pinctrl/gpio stuff above to set pinmux */ &vcc_sd { bootph-pre-ram; }; - -&gmac2io { - snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 50000>; -}; diff --git a/arch/arm/dts/rk3328-nanopi-r2s.dts b/arch/arm/dts/rk3328-nanopi-r2s.dts index 3857d487ab8..a4399da7d8b 100644 --- a/arch/arm/dts/rk3328-nanopi-r2s.dts +++ b/arch/arm/dts/rk3328-nanopi-r2s.dts @@ -14,6 +14,7 @@ compatible = "friendlyarm,nanopi-r2s", "rockchip,rk3328"; aliases { + ethernet0 = &gmac2io; ethernet1 = &rtl8153; mmc0 = &sdmmc; }; @@ -34,7 +35,7 @@ pinctrl-0 = <&reset_button_pin>; pinctrl-names = "default"; - reset { + key-reset { label = "reset"; gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>; linux,code = <KEY_RESTART>; diff --git a/arch/arm/dts/rk3328-orangepi-r1-plus-lts-u-boot.dtsi b/arch/arm/dts/rk3328-orangepi-r1-plus-lts-u-boot.dtsi index ebe33e48cb9..0a9423cd9c7 100644 --- a/arch/arm/dts/rk3328-orangepi-r1-plus-lts-u-boot.dtsi +++ b/arch/arm/dts/rk3328-orangepi-r1-plus-lts-u-boot.dtsi @@ -6,41 +6,37 @@ #include "rk3328-u-boot.dtsi" #include "rk3328-sdram-lpddr3-666.dtsi" -/ { - chosen { - u-boot,spl-boot-order = "same-as-spl", &sdmmc, &emmc; - }; -}; -&gpio0 { +&spi0 { bootph-pre-ram; + bootph-some-ram; + + flash@0 { + bootph-pre-ram; + bootph-some-ram; + }; }; -&pinctrl { +&spi0m2_clk { bootph-pre-ram; }; -&sdmmc0m1_pin { +&spi0m2_cs0 { bootph-pre-ram; }; -&pcfg_pull_up_4ma { +&spi0m2_rx { bootph-pre-ram; }; -/* Need this and all the pinctrl/gpio stuff above to set pinmux */ -&vcc_sd { +&spi0m2_tx { bootph-pre-ram; }; -&gmac2io { - snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 50000>; +&usb20_otg { + dr_mode = "peripheral"; }; -&spi0 { - spi_flash: spiflash@0 { - bootph-all; - }; +&vcc_sd { + bootph-pre-ram; }; diff --git a/arch/arm/dts/rk3328-orangepi-r1-plus-lts.dts b/arch/arm/dts/rk3328-orangepi-r1-plus-lts.dts index 5d7d567283e..4237f2ee8fe 100644 --- a/arch/arm/dts/rk3328-orangepi-r1-plus-lts.dts +++ b/arch/arm/dts/rk3328-orangepi-r1-plus-lts.dts @@ -26,9 +26,11 @@ compatible = "ethernet-phy-ieee802.3-c22"; reg = <0>; + motorcomm,auto-sleep-disabled; motorcomm,clk-out-frequency-hz = <125000000>; motorcomm,keep-pll-enabled; - motorcomm,auto-sleep-disabled; + motorcomm,rx-clk-drv-microamp = <5020>; + motorcomm,rx-data-drv-microamp = <5020>; pinctrl-0 = <ð_phy_reset_pin>; pinctrl-names = "default"; diff --git a/arch/arm/dts/rk3328-orangepi-r1-plus-u-boot.dtsi b/arch/arm/dts/rk3328-orangepi-r1-plus-u-boot.dtsi index 637c70adf19..1096821fc5d 100644 --- a/arch/arm/dts/rk3328-orangepi-r1-plus-u-boot.dtsi +++ b/arch/arm/dts/rk3328-orangepi-r1-plus-u-boot.dtsi @@ -6,41 +6,37 @@ #include "rk3328-u-boot.dtsi" #include "rk3328-sdram-ddr4-666.dtsi" -/ { - chosen { - u-boot,spl-boot-order = "same-as-spl", &sdmmc, &emmc; - }; -}; -&gpio0 { +&spi0 { bootph-pre-ram; + bootph-some-ram; + + flash@0 { + bootph-pre-ram; + bootph-some-ram; + }; }; -&pinctrl { +&spi0m2_clk { bootph-pre-ram; }; -&sdmmc0m1_pin { +&spi0m2_cs0 { bootph-pre-ram; }; -&pcfg_pull_up_4ma { +&spi0m2_rx { bootph-pre-ram; }; -/* Need this and all the pinctrl/gpio stuff above to set pinmux */ -&vcc_sd { +&spi0m2_tx { bootph-pre-ram; }; -&gmac2io { - snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 50000>; +&usb20_otg { + dr_mode = "peripheral"; }; -&spi0 { - spi_flash: spiflash@0 { - bootph-all; - }; +&vcc_sd { + bootph-pre-ram; }; diff --git a/arch/arm/dts/rk3328-orangepi-r1-plus.dts b/arch/arm/dts/rk3328-orangepi-r1-plus.dts index dc83d74045a..f20662929c7 100644 --- a/arch/arm/dts/rk3328-orangepi-r1-plus.dts +++ b/arch/arm/dts/rk3328-orangepi-r1-plus.dts @@ -15,6 +15,7 @@ compatible = "xunlong,orangepi-r1-plus", "rockchip,rk3328"; aliases { + ethernet0 = &gmac2io; ethernet1 = &rtl8153; mmc0 = &sdmmc; }; diff --git a/arch/arm/dts/rk3328-roc-cc-u-boot.dtsi b/arch/arm/dts/rk3328-roc-cc-u-boot.dtsi index 2062f34bf82..582d6ba49b4 100644 --- a/arch/arm/dts/rk3328-roc-cc-u-boot.dtsi +++ b/arch/arm/dts/rk3328-roc-cc-u-boot.dtsi @@ -5,11 +5,8 @@ #include "rk3328-u-boot.dtsi" #include "rk3328-sdram-ddr4-666.dtsi" -/ { - chosen { - u-boot,spl-boot-order = "same-as-spl", &sdmmc, &emmc; - }; +/ { smbios { compatible = "u-boot,sysinfo-smbios"; @@ -32,23 +29,10 @@ }; }; -&gpio0 { - bootph-pre-ram; -}; - -&pinctrl { - bootph-pre-ram; -}; - -&sdmmc0m1_pin { - bootph-pre-ram; -}; - -&pcfg_pull_up_4ma { - bootph-pre-ram; +&usb20_otg { + hnp-srp-disable; }; -/* Need this and all the pinctrl/gpio stuff above to set pinmux */ &vcc_sd { bootph-pre-ram; }; diff --git a/arch/arm/dts/rk3328-roc-cc.dts b/arch/arm/dts/rk3328-roc-cc.dts index aa22a0c2226..414897a57e7 100644 --- a/arch/arm/dts/rk3328-roc-cc.dts +++ b/arch/arm/dts/rk3328-roc-cc.dts @@ -11,6 +11,7 @@ compatible = "firefly,roc-rk3328-cc", "rockchip,rk3328"; aliases { + ethernet0 = &gmac2io; mmc0 = &sdmmc; mmc1 = &emmc; }; @@ -96,7 +97,6 @@ linux,default-trigger = "heartbeat"; gpios = <&rk805 1 GPIO_ACTIVE_LOW>; default-state = "on"; - mode = <0x23>; }; user_led: led-1 { @@ -104,7 +104,6 @@ linux,default-trigger = "mmc1"; gpios = <&rk805 0 GPIO_ACTIVE_LOW>; default-state = "off"; - mode = <0x05>; }; }; }; diff --git a/arch/arm/dts/rk3328-rock-pi-e-u-boot.dtsi b/arch/arm/dts/rk3328-rock-pi-e-u-boot.dtsi index 1f220c6dcd0..d314bfad6fc 100644 --- a/arch/arm/dts/rk3328-rock-pi-e-u-boot.dtsi +++ b/arch/arm/dts/rk3328-rock-pi-e-u-boot.dtsi @@ -29,23 +29,15 @@ }; }; -&gpio0 { - bootph-pre-ram; -}; - -&pinctrl { - bootph-pre-ram; +&u2phy_host { + phy-supply = <&vcc_host_5v>; }; -&sdmmc0m1_pin { - bootph-pre-ram; -}; - -&pcfg_pull_up_4ma { - bootph-pre-ram; +&vcc_host_5v { + /delete-property/ regulator-always-on; + /delete-property/ regulator-boot-on; }; -/* Need this and all the pinctrl/gpio stuff above to set pinmux */ &vcc_sd { bootph-pre-ram; }; diff --git a/arch/arm/dts/rk3328-rock-pi-e.dts b/arch/arm/dts/rk3328-rock-pi-e.dts index 018a3a5075c..3cda6c627b6 100644 --- a/arch/arm/dts/rk3328-rock-pi-e.dts +++ b/arch/arm/dts/rk3328-rock-pi-e.dts @@ -21,6 +21,8 @@ compatible = "radxa,rockpi-e", "rockchip,rk3328"; aliases { + ethernet0 = &gmac2io; + ethernet1 = &gmac2phy; mmc0 = &sdmmc; mmc1 = &emmc; }; @@ -180,6 +182,59 @@ status = "okay"; }; +&gpio0 { + gpio-line-names = + /* GPIO0_A0 - A7 */ + "", "", "", "", "", "", "", "", + /* GPIO0_B0 - B7 */ + "", "", "", "", "", "", "", "", + /* GPIO0_C0 - C7 */ + "", "", "", "", "", "", "", "", + /* GPIO0_D0 - D7 */ + "", "", "", "pin-15 [GPIO0_D3]", "", "", "", ""; +}; + +&gpio1 { + gpio-line-names = + /* GPIO1_A0 - A7 */ + "", "", "", "", "", "", "", "", + /* GPIO1_B0 - B7 */ + "", "", "", "", "", "", "", "", + /* GPIO1_C0 - C7 */ + "", "", "", "", "", "", "", "", + /* GPIO1_D0 - D7 */ + "", "", "", "", "pin-07 [GPIO1_D4]", "", "", ""; +}; + +&gpio2 { + gpio-line-names = + /* GPIO2_A0 - A7 */ + "pin-08 [GPIO2_A0]", "pin-10 [GPIO2_A1]", "pin-11 [GPIO2_A2]", + "pin-13 [GPIO2-A3]", "pin-27 [GPIO2_A4]", "pin-28 [GPIO2_A5]", + "pin-33 [GPIO2_A6]", "", + /* GPIO2_B0 - B7 */ + "", "", "", "", "pin-26 [GPIO2_B4]", "", "", "pin-36 [GPIO2_B7]", + /* GPIO2_C0 - C7 */ + "pin-32 [GPIO2_C0]", "pin-35 [GPIO2_C1]", "pin-12 [GPIO2_C2]", + "pin-38 [GPIO2_C3]", "pin-29 [GPIO2_C4]", "pin-31 [GPIO2_C5]", + "pin-37 [GPIO2_C6]", "pin-40 [GPIO2_C7]", + /* GPIO2_D0 - D7 */ + "", "", "", "", "", "", "", ""; +}; + +&gpio3 { + gpio-line-names = + /* GPIO3_A0 - A7 */ + "pin-23 [GPIO3_A0]", "pin-19 [GPIO3_A1]", "pin-21 [GPIO3_A2]", + "", "pin-03 [GPIO3_A4]", "", "pin-05 [GPIO3_A6]", "", + /* GPIO3_B0 - B7 */ + "pin-24 [GPIO3_B0]", "", "", "", "", "", "", "", + /* GPIO3_C0 - C7 */ + "", "", "", "", "", "", "", "", + /* GPIO3_D0 - D7 */ + "", "", "", "", "", "", "", ""; +}; + &i2c1 { status = "okay"; diff --git a/arch/arm/dts/rk3328-rock64-u-boot.dtsi b/arch/arm/dts/rk3328-rock64-u-boot.dtsi index 6904515b969..551cff6f24f 100644 --- a/arch/arm/dts/rk3328-rock64-u-boot.dtsi +++ b/arch/arm/dts/rk3328-rock64-u-boot.dtsi @@ -5,11 +5,8 @@ #include "rk3328-u-boot.dtsi" #include "rk3328-sdram-lpddr3-1600.dtsi" -/ { - chosen { - u-boot,spl-boot-order = "same-as-spl", &sdmmc, &emmc; - }; +/ { smbios { compatible = "u-boot,sysinfo-smbios"; @@ -32,29 +29,36 @@ }; }; -&gpio0 { +&spi0 { bootph-pre-ram; + bootph-some-ram; + + flash@0 { + bootph-pre-ram; + bootph-some-ram; + }; }; -&pinctrl { +&spi0m2_clk { bootph-pre-ram; }; -&sdmmc0m1_pin { +&spi0m2_cs0 { bootph-pre-ram; }; -&pcfg_pull_up_4ma { +&spi0m2_rx { bootph-pre-ram; }; -/* Need this and all the pinctrl/gpio stuff above to set pinmux */ -&vcc_sd { +&spi0m2_tx { bootph-pre-ram; }; -&spi0 { - spi_flash: flash@0 { - bootph-all; - }; +&usb20_otg { + hnp-srp-disable; +}; + +&vcc_sd { + bootph-pre-ram; }; diff --git a/arch/arm/dts/rk3328-rock64.dts b/arch/arm/dts/rk3328-rock64.dts index 0a27fa5271f..229fe9da9c2 100644 --- a/arch/arm/dts/rk3328-rock64.dts +++ b/arch/arm/dts/rk3328-rock64.dts @@ -11,6 +11,7 @@ compatible = "pine64,rock64", "rockchip,rk3328"; aliases { + ethernet0 = &gmac2io; mmc0 = &sdmmc; mmc1 = &emmc; }; diff --git a/arch/arm/dts/rk3328-u-boot.dtsi b/arch/arm/dts/rk3328-u-boot.dtsi index a9f2536de2a..e0c6aee58ab 100644 --- a/arch/arm/dts/rk3328-u-boot.dtsi +++ b/arch/arm/dts/rk3328-u-boot.dtsi @@ -13,7 +13,7 @@ }; chosen { - u-boot,spl-boot-order = &emmc, &sdmmc; + u-boot,spl-boot-order = "same-as-spl", &sdmmc, &emmc; }; dmc: dmc { @@ -26,45 +26,117 @@ 0x0 0xff720000 0x0 0x1000 0x0 0xff798000 0x0 0x1000>; }; - - rng: rng@ff060000 { - compatible = "rockchip,cryptov1-rng"; - reg = <0x0 0xff060000 0x0 0x4000>; - status = "okay"; - }; }; &cru { bootph-all; }; +&emmc { + bootph-pre-ram; + bootph-some-ram; + + /* mmc to sram can't do dma, prevent aborts transferring TF-A parts */ + u-boot,spl-fifo-mode; +}; + +&emmc_bus8 { + bootph-pre-ram; +}; + +&emmc_clk { + bootph-pre-ram; +}; + +&emmc_cmd { + bootph-pre-ram; +}; + +&gpio0 { + bootph-pre-ram; +}; + &grf { bootph-all; }; -&uart2 { +&pcfg_pull_none { bootph-all; - clock-frequency = <24000000>; }; -&emmc { +&pcfg_pull_none_8ma { + bootph-pre-ram; +}; + +&pcfg_pull_none_12ma { + bootph-pre-ram; +}; + +&pcfg_pull_up { bootph-all; +}; - /* mmc to sram can't do dma, prevent aborts transfering TF-A parts */ - u-boot,spl-fifo-mode; +&pcfg_pull_up_4ma { + bootph-pre-ram; +}; + +&pcfg_pull_up_8ma { + bootph-pre-ram; +}; + +&pcfg_pull_up_12ma { + bootph-pre-ram; +}; + +&pinctrl { + bootph-pre-ram; + bootph-some-ram; }; &sdmmc { - bootph-all; + bootph-pre-ram; + bootph-some-ram; - /* mmc to sram can't do dma, prevent aborts transfering TF-A parts */ + /* mmc to sram can't do dma, prevent aborts transferring TF-A parts */ u-boot,spl-fifo-mode; }; -&usb20_otg { - hnp-srp-disable; +&sdmmc0_bus4 { + bootph-pre-ram; +}; + +&sdmmc0_clk { + bootph-pre-ram; }; -&spi0 { +&sdmmc0_cmd { + bootph-pre-ram; +}; + +&sdmmc0_dectn { + bootph-pre-ram; +}; + +&sdmmc0m1_pin { + bootph-pre-ram; +}; + +&uart2 { bootph-all; + clock-frequency = <24000000>; +}; + +&uart2m1_xfer { + bootph-all; +}; + +#ifdef CONFIG_ROCKCHIP_SPI_IMAGE +&binman { + simple-bin-spi { + mkimage { + args = "-n", CONFIG_SYS_SOC, "-T", "rksd"; + offset = <0x8000>; + }; + }; }; +#endif diff --git a/arch/arm/dts/rk3328.dtsi b/arch/arm/dts/rk3328.dtsi index e8d8f00be8a..fb5dcf6e932 100644 --- a/arch/arm/dts/rk3328.dtsi +++ b/arch/arm/dts/rk3328.dtsi @@ -20,6 +20,10 @@ #size-cells = <2>; aliases { + gpio0 = &gpio0; + gpio1 = &gpio1; + gpio2 = &gpio2; + gpio3 = &gpio3; serial0 = &uart0; serial1 = &uart1; serial2 = &uart2; @@ -27,8 +31,6 @@ i2c1 = &i2c1; i2c2 = &i2c2; i2c3 = &i2c3; - ethernet0 = &gmac2io; - ethernet1 = &gmac2phy; }; cpus { @@ -102,10 +104,12 @@ l2: l2-cache0 { compatible = "cache"; + cache-level = <2>; + cache-unified; }; }; - cpu0_opp_table: opp_table0 { + cpu0_opp_table: opp-table-0 { compatible = "operating-points-v2"; opp-shared; @@ -306,6 +310,10 @@ }; power-domain@RK3328_PD_VIDEO { reg = <RK3328_PD_VIDEO>; + clocks = <&cru ACLK_RKVDEC>, + <&cru HCLK_RKVDEC>, + <&cru SCLK_VDEC_CABAC>, + <&cru SCLK_VDEC_CORE>; #power-domain-cells = <0>; }; power-domain@RK3328_PD_VPU { @@ -489,7 +497,7 @@ status = "disabled"; }; - dmac: dmac@ff1f0000 { + dmac: dma-controller@ff1f0000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x0 0xff1f0000 0x0 0x4000>; interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, @@ -599,7 +607,7 @@ gpu: gpu@ff300000 { compatible = "rockchip,rk3328-mali", "arm,mali-450"; - reg = <0x0 0xff300000 0x0 0x40000>; + reg = <0x0 0xff300000 0x0 0x30000>; interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, @@ -623,7 +631,6 @@ compatible = "rockchip,iommu"; reg = <0x0 0xff330200 0 0x100>; interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "h265e_mmu"; clocks = <&cru ACLK_H265>, <&cru PCLK_H265>; clock-names = "aclk", "iface"; #iommu-cells = <0>; @@ -634,7 +641,6 @@ compatible = "rockchip,iommu"; reg = <0x0 0xff340800 0x0 0x40>; interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "vepu_mmu"; clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; clock-names = "aclk", "iface"; #iommu-cells = <0>; @@ -656,22 +662,34 @@ compatible = "rockchip,iommu"; reg = <0x0 0xff350800 0x0 0x40>; interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "vpu_mmu"; clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; clock-names = "aclk", "iface"; #iommu-cells = <0>; power-domains = <&power RK3328_PD_VPU>; }; - rkvdec_mmu: iommu@ff360480 { + vdec: video-codec@ff360000 { + compatible = "rockchip,rk3328-vdec", "rockchip,rk3399-vdec"; + reg = <0x0 0xff360000 0x0 0x480>; + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>, + <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>; + clock-names = "axi", "ahb", "cabac", "core"; + assigned-clocks = <&cru ACLK_RKVDEC>, <&cru SCLK_VDEC_CABAC>, + <&cru SCLK_VDEC_CORE>; + assigned-clock-rates = <400000000>, <400000000>, <300000000>; + iommus = <&vdec_mmu>; + power-domains = <&power RK3328_PD_VIDEO>; + }; + + vdec_mmu: iommu@ff360480 { compatible = "rockchip,iommu"; reg = <0x0 0xff360480 0x0 0x40>, <0x0 0xff3604c0 0x0 0x40>; interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "rkvdec_mmu"; clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>; clock-names = "aclk", "iface"; #iommu-cells = <0>; - status = "disabled"; + power-domains = <&power RK3328_PD_VIDEO>; }; vop: vop@ff370000 { @@ -700,7 +718,6 @@ compatible = "rockchip,iommu"; reg = <0x0 0xff373f00 0x0 0x100>; interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "vop_mmu"; clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; clock-names = "aclk", "iface"; #iommu-cells = <0>; @@ -901,6 +918,8 @@ resets = <&cru SRST_GMAC2IO_A>; reset-names = "stmmaceth"; rockchip,grf = <&grf>; + tx-fifo-depth = <2048>; + rx-fifo-depth = <4096>; snps,txpbl = <0x4>; status = "disabled"; }; @@ -923,6 +942,8 @@ reset-names = "stmmaceth"; phy-mode = "rmii"; phy-handle = <&phy>; + tx-fifo-depth = <2048>; + rx-fifo-depth = <4096>; snps,txpbl = <0x4>; clock_in_out = "output"; status = "disabled"; @@ -944,6 +965,22 @@ }; }; + usb20_otg: usb@ff580000 { + compatible = "rockchip,rk3328-usb", "rockchip,rk3066-usb", + "snps,dwc2"; + reg = <0x0 0xff580000 0x0 0x40000>; + interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru HCLK_OTG>; + clock-names = "otg"; + dr_mode = "otg"; + g-np-tx-fifo-size = <16>; + g-rx-fifo-size = <280>; + g-tx-fifo-size = <256 128 128 64 32 16>; + phys = <&u2phy_otg>; + phy-names = "usb2-phy"; + status = "disabled"; + }; + usb_host0_ehci: usb@ff5c0000 { compatible = "generic-ehci"; reg = <0x0 0xff5c0000 0x0 0x10000>; @@ -983,31 +1020,6 @@ status = "disabled"; }; - /* - * U-Boot Specific Change - * - * The OTG controller must come after the USB host pair for it - * to work. This is likely due to lack of support for the USB - * PHYs. This must be manually changed after each device tree - * sync. There is no clean way to handle this in -u-boot.dtsi - * files. - */ - usb20_otg: usb@ff580000 { - compatible = "rockchip,rk3328-usb", "rockchip,rk3066-usb", - "snps,dwc2"; - reg = <0x0 0xff580000 0x0 0x40000>; - interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru HCLK_OTG>; - clock-names = "otg"; - dr_mode = "otg"; - g-np-tx-fifo-size = <16>; - g-rx-fifo-size = <280>; - g-tx-fifo-size = <256 128 128 64 32 16>; - phys = <&u2phy_otg>; - phy-names = "usb2-phy"; - status = "disabled"; - }; - gic: interrupt-controller@ff811000 { compatible = "arm,gic-400"; #interrupt-cells = <3>; @@ -1021,6 +1033,17 @@ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; }; + crypto: crypto@ff060000 { + compatible = "rockchip,rk3328-crypto"; + reg = <0x0 0xff060000 0x0 0x4000>; + interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru HCLK_CRYPTO_MST>, <&cru HCLK_CRYPTO_SLV>, + <&cru SCLK_CRYPTO>; + clock-names = "hclk_master", "hclk_slave", "sclk"; + resets = <&cru SRST_CRYPTO>; + reset-names = "crypto-rst"; + }; + pinctrl: pinctrl { compatible = "rockchip,rk3328-pinctrl"; rockchip,grf = <&grf>; @@ -1028,7 +1051,7 @@ #size-cells = <2>; ranges; - gpio0: gpio0@ff210000 { + gpio0: gpio@ff210000 { compatible = "rockchip,gpio-bank"; reg = <0x0 0xff210000 0x0 0x100>; interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; @@ -1041,7 +1064,7 @@ #interrupt-cells = <2>; }; - gpio1: gpio1@ff220000 { + gpio1: gpio@ff220000 { compatible = "rockchip,gpio-bank"; reg = <0x0 0xff220000 0x0 0x100>; interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; @@ -1054,7 +1077,7 @@ #interrupt-cells = <2>; }; - gpio2: gpio2@ff230000 { + gpio2: gpio@ff230000 { compatible = "rockchip,gpio-bank"; reg = <0x0 0xff230000 0x0 0x100>; interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; @@ -1067,7 +1090,7 @@ #interrupt-cells = <2>; }; - gpio3: gpio3@ff240000 { + gpio3: gpio@ff240000 { compatible = "rockchip,gpio-bank"; reg = <0x0 0xff240000 0x0 0x100>; interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; diff --git a/arch/arm/dts/rk3399-u-boot.dtsi b/arch/arm/dts/rk3399-u-boot.dtsi index 3423b882c43..87b173e5957 100644 --- a/arch/arm/dts/rk3399-u-boot.dtsi +++ b/arch/arm/dts/rk3399-u-boot.dtsi @@ -30,7 +30,7 @@ }; rng: rng@ff8b8000 { - compatible = "rockchip,cryptov1-rng"; + compatible = "rockchip,rk3399-crypto"; reg = <0x0 0xff8b8000 0x0 0x1000>; status = "okay"; }; diff --git a/arch/arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi b/arch/arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi index fa3df73c33d..791f16b206f 100644 --- a/arch/arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi +++ b/arch/arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi @@ -14,37 +14,6 @@ }; }; -&cru { - assigned-clocks = - <&pmucru CLK_RTC_32K>, - <&pmucru PLL_PPLL>, - <&pmucru PCLK_PMU>, <&cru PLL_CPLL>, - <&cru PLL_GPLL>, - <&cru ACLK_BUS>, <&cru PCLK_BUS>, - <&cru ACLK_TOP_HIGH>, <&cru ACLK_TOP_LOW>, - <&cru HCLK_TOP>, <&cru PCLK_TOP>, - <&cru ACLK_PERIMID>, <&cru HCLK_PERIMID>, - <&cru CPLL_500M>, <&cru CPLL_333M>, - <&cru CPLL_250M>, <&cru CPLL_125M>, - <&cru CPLL_100M>, <&cru CPLL_62P5M>, - <&cru CPLL_50M>, <&cru CPLL_25M>; - assigned-clock-rates = - <32768>, - <200000000>, - <100000000>, <1000000000>, - <1188000000>, - <150000000>, <100000000>, - <500000000>, <400000000>, - <150000000>, <100000000>, - <300000000>, <150000000>, - <500000000>, <333333333>, - <250000000>, <125000000>, - <100000000>, <62500000>, - <50000000>, <25000000>; - assigned-clock-parents = - <&pmucru CLK_RTC32K_FRAC>; -}; - &dsi_dphy0 { status = "okay"; }; diff --git a/arch/arm/dts/rk3566-anbernic-rgxx3.dts b/arch/arm/dts/rk3566-anbernic-rgxx3.dts index 404dddfafbf..c393c8d07af 100644 --- a/arch/arm/dts/rk3566-anbernic-rgxx3.dts +++ b/arch/arm/dts/rk3566-anbernic-rgxx3.dts @@ -12,7 +12,17 @@ * set the correct dtb name for loading mainline Linux automatically. */ model = "RGXX3"; - compatible = "anbernic,rg353m", "anbernic,rg353p", - "anbernic,rg353v", "anbernic,rg353vs", - "anbernic,rg503", "rockchip,rk3566"; + compatible = "anbernic,rg-arc-d", "anbernic,rg-arc-s", + "anbernic,rg353m", "anbernic,rg353p", + "anbernic,rg353ps", "anbernic,rg353v", + "anbernic,rg353vs", "anbernic,rg503", + "powkiddy,rgb10max3", "powkiddy,rgb30", + "powkiddy,rk2023", "rockchip,rk3566"; +}; + +&cru { + assigned-clocks = <&pmucru CLK_RTC_32K>, <&cru PLL_GPLL>, + <&pmucru PLL_PPLL>, <&cru PLL_VPLL>; + assigned-clock-rates = <32768>, <1200000000>, + <200000000>, <241500000>; }; diff --git a/arch/arm/dts/rk3566-pinetab2-u-boot.dtsi b/arch/arm/dts/rk3566-pinetab2-u-boot.dtsi new file mode 100644 index 00000000000..4aa6ab1c848 --- /dev/null +++ b/arch/arm/dts/rk3566-pinetab2-u-boot.dtsi @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include "rk356x-u-boot.dtsi" + +&fspi_dual_io_pins { + bootph-all; +}; + +&gpio0 { + bootph-all; +}; + +&i2c0 { + bootph-pre-ram; +}; + +&rk817 { + bootph-pre-ram; + + regulators { + bootph-pre-ram; + }; +}; + +&sdhci { + cap-mmc-highspeed; +}; + +&sdmmc_pwren_l { + bootph-all; +}; + +&sfc { + bootph-pre-ram; + u-boot,spl-sfc-no-dma; + + flash@0 { + bootph-pre-ram; + }; +}; + +&vcc3v3_sd { + bootph-pre-ram; +}; diff --git a/arch/arm/dts/rk3566-pinetab2-v0.1-u-boot.dtsi b/arch/arm/dts/rk3566-pinetab2-v0.1-u-boot.dtsi new file mode 100644 index 00000000000..061dc3c2c37 --- /dev/null +++ b/arch/arm/dts/rk3566-pinetab2-v0.1-u-boot.dtsi @@ -0,0 +1,3 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include "rk3566-pinetab2-u-boot.dtsi" diff --git a/arch/arm/dts/rk3566-pinetab2-v0.1.dts b/arch/arm/dts/rk3566-pinetab2-v0.1.dts new file mode 100644 index 00000000000..5fe6ca5da9d --- /dev/null +++ b/arch/arm/dts/rk3566-pinetab2-v0.1.dts @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include "rk3566-pinetab2.dtsi" + +/ { + model = "Pine64 PineTab2 v0.1"; + compatible = "pine64,pinetab2-v0.1", "pine64,pinetab2", "rockchip,rk3566"; +}; + +&lcd { + reset-gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_pwren_h &lcd0_rst_l>; +}; + +&pinctrl { + lcd0 { + lcd0_rst_l: lcd0-rst-l { + rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&sdmmc1 { + vmmc-supply = <&vcc3v3_sys>; +}; diff --git a/arch/arm/dts/rk3566-pinetab2-v2.0-u-boot.dtsi b/arch/arm/dts/rk3566-pinetab2-v2.0-u-boot.dtsi new file mode 100644 index 00000000000..061dc3c2c37 --- /dev/null +++ b/arch/arm/dts/rk3566-pinetab2-v2.0-u-boot.dtsi @@ -0,0 +1,3 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include "rk3566-pinetab2-u-boot.dtsi" diff --git a/arch/arm/dts/rk3566-pinetab2-v2.0.dts b/arch/arm/dts/rk3566-pinetab2-v2.0.dts new file mode 100644 index 00000000000..9349541cbbd --- /dev/null +++ b/arch/arm/dts/rk3566-pinetab2-v2.0.dts @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include "rk3566-pinetab2.dtsi" + +/ { + model = "Pine64 PineTab2 v2.0"; + compatible = "pine64,pinetab2-v2.0", "pine64,pinetab2", "rockchip,rk3566"; +}; + +&gpio_keys { + pinctrl-0 = <&kb_id_det>, <&hall_int_l>; + + event-hall-sensor { + debounce-interval = <20>; + gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_LOW>; + label = "Hall Sensor"; + linux,code = <SW_LID>; + linux,input-type = <EV_SW>; + wakeup-event-action = <EV_ACT_DEASSERTED>; + wakeup-source; + }; +}; + +&lcd { + reset-gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_pwren_h &lcd0_rst_l>; +}; + +&pinctrl { + lcd0 { + lcd0_rst_l: lcd0-rst-l { + rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + hall { + hall_int_l: hall-int-l { + rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&sdmmc1 { + vmmc-supply = <&vcc_sys>; +}; diff --git a/arch/arm/dts/rk3566-pinetab2.dtsi b/arch/arm/dts/rk3566-pinetab2.dtsi new file mode 100644 index 00000000000..db40281eafb --- /dev/null +++ b/arch/arm/dts/rk3566-pinetab2.dtsi @@ -0,0 +1,943 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/gpio-keys.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/leds/common.h> +#include <dt-bindings/pinctrl/rockchip.h> +#include <dt-bindings/soc/rockchip,vop2.h> +#include <dt-bindings/usb/pd.h> +#include "rk3566.dtsi" + +/ { + chassis-type = "tablet"; + + aliases { + mmc0 = &sdhci; + mmc1 = &sdmmc0; + }; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 0>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <25>; + + button-vol-up { + label = "Volume Up"; + linux,code = <KEY_VOLUMEUP>; + press-threshold-microvolt = <297500>; + }; + + button-vol-down { + label = "Volume Down"; + linux,code = <KEY_VOLUMEDOWN>; + press-threshold-microvolt = <1750>; + }; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm4 0 25000 0>; + brightness-levels = <20 220>; + num-interpolated-steps = <200>; + default-brightness-level = <100>; + power-supply = <&vcc_sys>; + }; + + battery: battery { + compatible = "simple-battery"; + charge-full-design-microamp-hours = <6000000>; + charge-term-current-microamp = <300000>; + constant-charge-current-max-microamp = <2000000>; + constant-charge-voltage-max-microvolt = <4300000>; + voltage-max-design-microvolt = <4350000>; + voltage-min-design-microvolt = <3400000>; + + ocv-capacity-celsius = <20>; + ocv-capacity-table-0 = <4322000 100>, <4250000 95>, <4192000 90>, <4136000 85>, + <4080000 80>, <4022000 75>, <3972000 70>, <3928000 65>, + <3885000 60>, <3833000 55>, <3798000 50>, <3780000 45>, + <3776000 40>, <3773000 35>, <3755000 30>, <3706000 25>, + <3640000 20>, <3589000 15>, <3535000 10>, <3492000 5>, + <3400000 0>; + }; + + gpio_keys: gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&kb_id_det>; + + tablet-mode-switch { + debounce-interval = <20>; + gpios = <&gpio4 RK_PA4 GPIO_ACTIVE_HIGH>; + label = "Tablet Mode"; + linux,input-type = <EV_SW>; + linux,code = <SW_TABLET_MODE>; + }; + }; + + hdmi-connector { + compatible = "hdmi-connector"; + type = "d"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + + led-0 { + compatible = "regulator-led"; + vled-supply = <&vcc5v0_flashled>; + color = <LED_COLOR_ID_WHITE>; + function = LED_FUNCTION_FLASH; + }; + + rk817-sound { + compatible = "simple-audio-card"; + pinctrl-names = "default"; + pinctrl-0 = <&hp_det_l>; + simple-audio-card,format = "i2s"; + simple-audio-card,name = "rk817_ext"; + simple-audio-card,mclk-fs = <256>; + + simple-audio-card,widgets = + "Microphone", "Mic Jack", + "Headphone", "Headphones", + "Speaker", "Internal Speakers"; + + simple-audio-card,routing = + "MICR", "Mic Jack", + "Headphones", "HPOL", + "Headphones", "HPOR", + "Internal Speakers", "Speaker Amplifier OUTL", + "Internal Speakers", "Speaker Amplifier OUTR", + "Speaker Amplifier INL", "HPOL", + "Speaker Amplifier INR", "HPOR"; + simple-audio-card,hp-det-gpio = <&gpio4 RK_PC6 GPIO_ACTIVE_LOW>; + simple-audio-card,aux-devs = <&speaker_amp>; + simple-audio-card,pin-switches = "Internal Speakers"; + + simple-audio-card,cpu { + sound-dai = <&i2s1_8ch>; + }; + + simple-audio-card,codec { + sound-dai = <&rk817>; + }; + }; + + speaker_amp: speaker-amplifier { + compatible = "simple-audio-amplifier"; + pinctrl-names = "default"; + pinctrl-0 = <&spk_ctl>; + enable-gpios = <&gpio4 RK_PC2 GPIO_ACTIVE_HIGH>; + sound-name-prefix = "Speaker Amplifier"; + VCC-supply = <&vcc_bat>; + }; + + vcc_3v3: vcc-3v3-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc3v3_sys>; + }; + + vcc3v3_minipcie: vcc3v3-minipcie-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio4 RK_PC3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_pwren_h>; + regulator-name = "vcc3v3_minipcie"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_sys>; + }; + + vcc3v3_sd: vcc3v3-sd-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_pwren_l>; + regulator-name = "vcc3v3_sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc3v3_sys>; + }; + + vcc5v0_flashled: vcc5v0-flashled-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&flash_led_en_h>; + regulator-name = "vcc5v0_flashled"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v_midu>; + }; + + vcc5v0_usb_host0: vcc5v0-usb-host0-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio4 RK_PC4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb_host_pwren1_h>; + regulator-name = "vcc5v0_usb_host0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v_midu>; + }; + + vcc5v0_usb_host2: vcc5v0-usb-host2-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio4 RK_PC5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb_host_pwren2_h>; + regulator-name = "vcc5v0_usb_host2"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v_midu>; + }; + + vcc_bat: vcc-bat-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_bat"; + regulator-always-on; + regulator-boot-on; + }; + + vcc_sys: vcc-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_sys"; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc_bat>; + }; + + vdd1v2_dvp: vdd1v2-dvp-regulator { + compatible = "regulator-fixed"; + regulator-name = "vdd1v2_dvp"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + vin-supply = <&vcc_3v3>; + }; +}; + +&combphy1 { + status = "okay"; +}; + +&combphy2 { + status = "okay"; +}; + +&cpu0 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu1 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu2 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu3 { + cpu-supply = <&vdd_cpu>; +}; + +&cru { + assigned-clocks = <&pmucru CLK_RTC_32K>, <&cru PLL_GPLL>, + <&pmucru PLL_PPLL>, <&cru PLL_VPLL>; + assigned-clock-rates = <32768>, <1200000000>, <200000000>, <500000000>; + assigned-clock-parents = <&pmucru CLK_RTC32K_FRAC>; +}; + +&csi_dphy { + status = "okay"; +}; + +&dsi0 { + status = "okay"; + clock-master; + #address-cells = <1>; + #size-cells = <0>; + + lcd: panel@0 { + compatible = "boe,th101mb31ig002-28a"; + reg = <0>; + backlight = <&backlight>; + enable-gpios = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; + rotation = <90>; + power-supply = <&vcc_3v3>; + + port@0 { + panel_in_dsi: endpoint@0 { + remote-endpoint = <&dsi0_out_con>; + }; + }; + }; +}; + +&dsi0_in { + dsi0_in_vp1: endpoint { + remote-endpoint = <&vp1_out_dsi0>; + }; +}; + +&dsi0_out { + dsi0_out_con: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; +}; + +&dsi_dphy0 { + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_gpu_npu>; + status = "okay"; +}; + +&hdmi { + avdd-0v9-supply = <&vdda_0v9_p>; + avdd-1v8-supply = <&vcc_1v8>; + status = "okay"; +}; + +&hdmi_in { + hdmi_in_vp0: endpoint { + remote-endpoint = <&vp0_out_hdmi>; + }; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&hdmi_sound { + status = "okay"; +}; + +&i2c0 { + clock-frequency = <400000>; + status = "okay"; + + vdd_cpu: regulator@1c { + compatible = "tcs,tcs4525"; + reg = <0x1c>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1150000>; + regulator-ramp-delay = <2300>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + rk817: pmic@20 { + compatible = "rockchip,rk817"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>; + assigned-clocks = <&cru I2S1_MCLKOUT_TX>; + assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>; + clock-names = "mclk"; + clocks = <&cru I2S1_MCLKOUT_TX>; + clock-output-names = "rk808-clkout1", "rk808-clkout2"; + #clock-cells = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>, <&i2s1m0_mclk>; + rockchip,system-power-controller; + #sound-dai-cells = <0>; + wakeup-source; + + vcc1-supply = <&vcc_sys>; + vcc2-supply = <&vcc_sys>; + vcc3-supply = <&vcc_sys>; + vcc4-supply = <&vcc_sys>; + vcc5-supply = <&vcc_sys>; + vcc6-supply = <&vcc_sys>; + vcc7-supply = <&vcc_sys>; + vcc8-supply = <&vcc_sys>; + vcc9-supply = <&vcc5v_midu>; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_logic"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu_npu: DCDC_REG2 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_gpu_npu"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-name = "vcc_ddr"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc3v3_sys: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-initial-mode = <0x2>; + regulator-name = "vcc3v3_sys"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_pmu: LDO_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca1v8_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdda_0v9_p: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda_0v9_p"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_pmu: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda0v9_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vccio_acodec: LDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_acodec"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_sd"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_pmu: LDO_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc3v3_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_1v8: LDO_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc1v8_dvp: LDO_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc1v8_dvp"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc2v8_dvp: LDO_REG9 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-name = "vcc2v8_dvp"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc5v_midu: BOOST { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-name = "boost"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vbus: OTG_SWITCH { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-name = "otg_switch"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + + charger { + monitored-battery = <&battery>; + rockchip,resistor-sense-micro-ohms = <10000>; + rockchip,sleep-enter-current-microamp = <300000>; + rockchip,sleep-filter-current-microamp = <100000>; + }; + }; +}; + +&i2c1 { + clock-frequency = <400000>; + status = "okay"; + + touchscreen@5d { + compatible = "goodix,gt911"; + reg = <0x5d>; + interrupt-parent = <&gpio0>; + interrupts = <RK_PB0 IRQ_TYPE_EDGE_FALLING>; + pinctrl-names = "default"; + pinctrl-0 = <&tp_int_l_pmuio2>, <&tp_rst_l_pmuio2>; + AVDD28-supply = <&vcc3v3_pmu>; + VDDIO-supply = <&vcca1v8_pmu>; + irq-gpios = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio0 RK_PC2 GPIO_ACTIVE_HIGH>; + }; +}; + +&i2c2 { + clock-frequency = <400000>; + pinctrl-0 = <&i2c2m1_xfer>; + status = "okay"; + + vcm@c { + compatible = "dongwoon,dw9714"; + reg = <0x0c>; + vcc-supply = <&vcc1v8_dvp>; + }; + + camera@36 { + compatible = "ovti,ov5648"; + reg = <0x36>; + pinctrl-names = "default"; + pinctrl-0 = <&camerab_pdn_l &camerab_rst_l>; + + clocks = <&cru CLK_CIF_OUT>; + assigned-clocks = <&cru CLK_CIF_OUT>; + assigned-clock-rates = <24000000>; + + avdd-supply = <&vcc2v8_dvp>; + dvdd-supply = <&vdd1v2_dvp>; + dovdd-supply = <&vcc1v8_dvp>; + powerdown-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_LOW>; + reset-gpios = <&gpio4 RK_PB1 GPIO_ACTIVE_LOW>; + + port { + endpoint { + data-lanes = <1 2>; + remote-endpoint = <0>; + link-frequencies = /bits/ 64 <210000000 168000000>; + }; + }; + }; +}; + +&i2c5 { + clock-frequency = <400000>; + status = "okay"; + + accelerometer@18 { + compatible = "silan,sc7a20"; + reg = <0x18>; + interrupt-parent = <&gpio3>; + interrupts = <RK_PA2 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&gsensor_int_l>; + st,drdy-int-pin = <1>; + vdd-supply = <&vcc_1v8>; + vddio-supply = <&vcc_1v8>; + mount-matrix = "1", "0", "0", + "0", "0", "1", + "0", "1", "0"; + }; +}; + +&i2s0_8ch { + status = "okay"; +}; + +&i2s1_8ch { + pinctrl-names = "default"; + pinctrl-0 = <&i2s1m0_sclktx + &i2s1m0_lrcktx + &i2s1m0_sdi0 + &i2s1m0_sdo0>; + rockchip,trcm-sync-tx-only; + status = "okay"; +}; + +&pcie2x1 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie_reset_h>; + reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_minipcie>; + status = "okay"; +}; + +&pinctrl { + camerab { + camerab_pdn_l: camerab-pdn-l { + rockchip,pins = <4 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + camerab_rst_l: camerab-rst-l { + rockchip,pins = <4 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + cameraf { + cameraf_pdn_l: cameraf-pdn-l { + rockchip,pins = <4 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + cameraf_rst_l: cameraf-rst-l { + rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + flash { + flash_led_en_h: flash-led-en-h { + rockchip,pins = <4 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + fspi { + fspi_dual_io_pins: fspi-dual-io-pins { + rockchip,pins = + /* fspi_clk */ + <1 RK_PD0 1 &pcfg_pull_none>, + /* fspi_cs0n */ + <1 RK_PD3 1 &pcfg_pull_none>, + /* fspi_d0 */ + <1 RK_PD1 1 &pcfg_pull_none>, + /* fspi_d1 */ + <1 RK_PD2 1 &pcfg_pull_none>; + }; + }; + + gsensor { + gsensor_int_l: gsensor-int-l { + rockchip,pins = <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + kb { + kb_id_det: kb-id-det { + rockchip,pins = <4 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + lcd { + lcd_pwren_h: lcd-pwren-h { + rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pcie { + pcie_pwren_h: pcie-pwren-h { + rockchip,pins = <4 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pcie_reset_h: pcie-reset-h { + rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + sdmmc { + sdmmc_pwren_l: sdmmc-pwren-l { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sound { + hp_det_l: hp-det-l { + rockchip,pins = <4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + spk_ctl: spk-ctl { + rockchip,pins = <4 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + tp { + tp_int_l_pmuio2: tp-int-l-pmuio2 { + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + tp_rst_l_pmuio2: tp-rst-l-pmuio2 { + rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + usbcc_int_l: usbcc-int-l { + rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + usb_host_pwren1_h: usb-host-pwren1-h { + rockchip,pins = <4 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + usb_host_pwren2_h: usb-host-pwren2-h { + rockchip,pins = <4 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wifi { + host_wake_wl: host-wake-wl { + rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + wifi_wake_host_h: wifi-wake-host-h { + rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; +}; + +&pmu_io_domains { + pmuio1-supply = <&vcc3v3_pmu>; + pmuio2-supply = <&vcca1v8_pmu>; + vccio1-supply = <&vccio_acodec>; + vccio2-supply = <&vcc_1v8>; + vccio3-supply = <&vccio_sd>; + vccio4-supply = <&vcc_1v8>; + vccio5-supply = <&vcc_1v8>; + vccio6-supply = <&vcc1v8_dvp>; + vccio7-supply = <&vcc_3v3>; + status = "okay"; +}; + +&pwm4 { + status = "okay"; +}; + +&saradc { + vref-supply = <&vcc_1v8>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + no-sdio; + no-sd; + non-removable; + max-frequency = <200000000>; + mmc-hs200-1_8v; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_bus8 + &emmc_clk + &emmc_cmd + &emmc_datastrobe + &emmc_rstnout>; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vcc_1v8>; + status = "okay"; +}; + +&sdmmc0 { + bus-width = <4>; + cap-sd-highspeed; + cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; + disable-wp; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_bus4 + &sdmmc0_clk + &sdmmc0_cmd + &sdmmc0_det>; + sd-uhs-sdr104; + vmmc-supply = <&vcc3v3_sd>; + vqmmc-supply = <&vccio_sd>; + status = "okay"; +}; + +&sdmmc1 { + bus-width = <4>; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc1_bus4 + &sdmmc1_cmd + &sdmmc1_clk>; + sd-uhs-sdr104; + vqmmc-supply = <&vcca1v8_pmu>; + status = "okay"; +}; + +&sfc { + pinctrl-names = "default"; + pinctrl-0 = <&fspi_dual_io_pins>; + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <100000000>; + spi-rx-bus-width = <2>; + spi-tx-bus-width = <1>; + }; +}; + +&tsadc { + rockchip,hw-tshut-mode = <1>; + rockchip,hw-tshut-polarity = <0>; + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host0_xhci { + status = "okay"; +}; + +&usb_host1_xhci { + status = "okay"; +}; + +&usb2phy0 { + status = "okay"; +}; + +&usb2phy0_host { + phy-supply = <&vcc5v0_usb_host0>; + status = "okay"; +}; + +&usb2phy0_otg { + status = "okay"; +}; + +&usb2phy1 { + status = "okay"; +}; + +&usb2phy1_otg { + phy-supply = <&vcc5v0_usb_host2>; + status = "okay"; +}; + +&vop { + assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; + assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +&vp0 { + vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { + reg = <ROCKCHIP_VOP2_EP_HDMI0>; + remote-endpoint = <&hdmi_in_vp0>; + }; +}; + +&vp1 { + vp1_out_dsi0: endpoint@ROCKCHIP_VOP2_EP_MIPI0 { + reg = <ROCKCHIP_VOP2_EP_MIPI0>; + remote-endpoint = <&dsi0_in_vp1>; + }; +}; diff --git a/arch/arm/dts/rk3588-coolpi-cm5-evb-u-boot.dtsi b/arch/arm/dts/rk3588-coolpi-cm5-evb-u-boot.dtsi new file mode 100644 index 00000000000..ed15b14ea0e --- /dev/null +++ b/arch/arm/dts/rk3588-coolpi-cm5-evb-u-boot.dtsi @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +#include "rk3588-u-boot.dtsi" + +&fspim2_pins { + bootph-all; +}; + +&sdhci { + cap-mmc-highspeed; + mmc-hs200-1_8v; +}; + +&sfc { + bootph-pre-ram; + u-boot,spl-sfc-no-dma; + pinctrl-names = "default"; + pinctrl-0 = <&fspim2_pins>; + status = "okay"; + + flash@0 { + bootph-pre-ram; + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <24000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <1>; + }; +}; diff --git a/arch/arm/dts/rk3588-coolpi-cm5-evb.dts b/arch/arm/dts/rk3588-coolpi-cm5-evb.dts new file mode 100644 index 00000000000..a4946cdc3bb --- /dev/null +++ b/arch/arm/dts/rk3588-coolpi-cm5-evb.dts @@ -0,0 +1,216 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include <dt-bindings/leds/common.h> +#include "rk3588-coolpi-cm5.dtsi" + +/ { + model = "RK3588 CoolPi CM5 EVB"; + compatible = "coolpi,pi-cm5-evb", "coolpi,pi-cm5", "rockchip,rk3588"; + + backlight: backlight { + compatible = "pwm-backlight"; + enable-gpios = <&gpio4 RK_PA3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&bl_en>; + power-supply = <&vcc12v_dcin>; + pwms = <&pwm2 0 25000 0>; + }; + + leds: leds { + compatible = "gpio-leds"; + + green_led: led-0 { + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_STATUS; + gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + vcc12v_dcin: vcc12v-dcin-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc5v0_sys: vcc5v0-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc3v3_sys: vcc3v3-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc3v3_lcd: vcc3v3-lcd-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_lcd"; + enable-active-high; + gpio = <&gpio1 RK_PC4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&lcdpwr_en>; + vin-supply = <&vcc3v3_sys>; + }; + + vcc5v0_usb_host1: vcc5v0_usb_host2: vcc5v0-usb-host-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_host"; + regulator-boot-on; + regulator-always-on; + enable-active-high; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb_host_pwren>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_usb30_otg: vcc5v0-usb30-otg-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_otg"; + regulator-boot-on; + regulator-always-on; + enable-active-high; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb_otg_pwren>; + vin-supply = <&vcc5v0_sys>; + }; +}; + +/* M.2 E-Key */ +&pcie2x1l1 { + reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_sys>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_clkreq &pcie_wake &pcie_rst &wifi_pwron &bt_pwron>; + status = "okay"; +}; + +&pcie30phy { + status = "okay"; +}; + +/* Standard pcie */ +&pcie3x2 { + reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_sys>; + status = "okay"; +}; + +/* M.2 M-Key ssd */ +&pcie3x4 { + num-lanes = <2>; + reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_sys>; + status = "okay"; +}; + +&pinctrl { + lcd { + lcdpwr_en: lcdpwr-en { + rockchip,pins = <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + bl_en: bl-en { + rockchip,pins = <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + usb_host_pwren: usb-host-pwren { + rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + usb_otg_pwren: usb-otg-pwren { + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + wifi { + bt_pwron: bt-pwron { + rockchip,pins = <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + pcie_clkreq: pcie-clkreq { + rockchip,pins = <4 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + pcie_rst: pcie-rst { + rockchip,pins = <4 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + wifi_pwron: wifi-pwron { + rockchip,pins = <3 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + pcie_wake: pcie-wake { + rockchip,pins = <4 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&pwm2 { + status = "okay"; +}; + +&sata1 { + status = "okay"; +}; + +&u2phy2 { + status = "okay"; +}; + +&u2phy3 { + status = "okay"; +}; + +&u2phy2_host { + phy-supply = <&vcc5v0_usb_host1>; + status = "okay"; +}; + +&u2phy3_host { + phy-supply = <&vcc5v0_usb_host2>; + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; diff --git a/arch/arm/dts/rk3588-coolpi-cm5.dtsi b/arch/arm/dts/rk3588-coolpi-cm5.dtsi new file mode 100644 index 00000000000..9cb6d566da6 --- /dev/null +++ b/arch/arm/dts/rk3588-coolpi-cm5.dtsi @@ -0,0 +1,649 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/pwm/pwm.h> +#include <dt-bindings/pinctrl/rockchip.h> +#include "rk3588.dtsi" + +/ { + compatible = "coolpi,pi-cm5", "rockchip,rk3588"; + + aliases { + mmc0 = &sdhci; + mmc1 = &sdmmc; + mmc2 = &sdio; + }; + + analog-sound { + compatible = "audio-graph-card"; + dais = <&i2s0_8ch_p0>; + label = "rk3588-es8316"; + routing = "MIC2", "Mic Jack", + "Headphones", "HPOL", + "Headphones", "HPOR"; + widgets = "Microphone", "Mic Jack", + "Headphone", "Headphones"; + }; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + avdd0v85_pcie20: avdd0v85-pcie20-regulator { + compatible = "regulator-fixed"; + regulator-name = "avdd0v85_pcie20"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + vin-supply = <&vdd_0v85_s0>; + }; + + avdd1v8_pcie20: avdd1v8-pcie20-regulator { + compatible = "regulator-fixed"; + regulator-name = "avdd1v8_pcie20"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&avcc_1v8_s0>; + }; + + avdd0v75_pcie30: avdd0v75-pcie30-regulator { + compatible = "regulator-fixed"; + regulator-name = "avdd0v75_pcie30"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + vin-supply = <&avdd_0v75_s0>; + }; + + pcie30_avdd1v8: avdd1v8-pcie30-regulator { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd1v8"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&avcc_1v8_s0>; + }; +}; + +&combphy0_ps { + status = "okay"; +}; + +&combphy1_ps { + status = "okay"; +}; + +&combphy2_psu { + status = "okay"; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_big0_s0>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu_big0_s0>; +}; + +&cpu_b2 { + cpu-supply = <&vdd_cpu_big1_s0>; +}; + +&cpu_b3 { + cpu-supply = <&vdd_cpu_big1_s0>; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&gmac0 { + clock_in_out = "output"; + phy-handle = <&rgmii_phy>; + phy-mode = "rgmii-rxid"; + pinctrl-0 = <&gmac0_miim + &gmac0_tx_bus2 + &gmac0_rx_bus2 + &gmac0_rgmii_clk + &gmac0_rgmii_bus>; + pinctrl-names = "default"; + rx_delay = <0x00>; + tx_delay = <0x43>; + status = "okay"; +}; + +&i2c0 { + pinctrl-0 = <&i2c0m2_xfer>; + status = "okay"; + + vdd_cpu_big0_s0: regulator@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu_big0_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big1_s0: regulator@43 { + compatible = "rockchip,rk8603", "rockchip,rk8602"; + reg = <0x43>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu_big1_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c2 { + status = "okay"; + + vdd_npu_s0: regulator@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_npu_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c6 { + status = "okay"; + + hym8563: rtc@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + interrupt-parent = <&gpio0>; + interrupts = <RK_PD4 IRQ_TYPE_LEVEL_LOW>; + #clock-cells = <0>; + clock-output-names = "hym8563"; + pinctrl-names = "default"; + pinctrl-0 = <&hym8563_int>; + wakeup-source; + }; +}; + +&i2c7 { + pinctrl-0 = <&i2c7m0_xfer>; + status = "okay"; + + es8316: audio-codec@11 { + compatible = "everest,es8316"; + reg = <0x11>; + assigned-clocks = <&cru I2S0_8CH_MCLKOUT>; + assigned-clock-rates = <12288000>; + clocks = <&cru I2S0_8CH_MCLKOUT>; + clock-names = "mclk"; + #sound-dai-cells = <0>; + + port { + es8316_p0_0: endpoint { + remote-endpoint = <&i2s0_8ch_p0_0>; + }; + }; + }; +}; + +&i2s0_8ch { + pinctrl-0 = <&i2s0_lrck + &i2s0_mclk + &i2s0_sclk + &i2s0_sdi0 + &i2s0_sdo0>; + status = "okay"; + + i2s0_8ch_p0: port { + i2s0_8ch_p0_0: endpoint { + dai-format = "i2s"; + mclk-fs = <256>; + remote-endpoint = <&es8316_p0_0>; + }; + }; +}; + +&mdio0 { + rgmii_phy: ethernet-phy@1 { + /* YT8531C/H */ + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + pinctrl-names = "default"; + pinctrl-0 = <&yt8531_rst>; + reset-assert-us = <20000>; + reset-deassert-us = <100000>; + reset-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_LOW>; + }; +}; + +/* ethernet */ +&pcie2x1l2 { + reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_sys>; + pinctrl-names = "default"; + pinctrl-0 = <&yt6801_isolate>; + status = "okay"; +}; + +&pinctrl { + hym8563 { + hym8563_int: hym8563-int { + rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + yt6801 { + yt6801_isolate: yt6801-isolate { + rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + yt8531 { + yt8531_rst: yt8531-rst { + rockchip,pins = <4 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&saradc { + vref-supply = <&vcc_1v8_s0>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + max-frequency = <200000000>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + no-sdio; + no-sd; + non-removable; + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + max-frequency = <150000000>; + no-sdio; + no-mmc; + sd-uhs-sdr104; + vqmmc-supply = <&vccio_sd_s0>; + status = "okay"; +}; + +&spi2 { + assigned-clocks = <&cru CLK_SPI2>; + assigned-clock-rates = <200000000>; + num-cs = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; + status = "okay"; + + pmic@0 { + compatible = "rockchip,rk806"; + reg = <0x0>; + interrupt-parent = <&gpio0>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + gpio-controller; + #gpio-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, + <&rk806_dvs2_null>, <&rk806_dvs3_null>; + spi-max-frequency = <1000000>; + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc5-supply = <&vcc5v0_sys>; + vcc6-supply = <&vcc5v0_sys>; + vcc7-supply = <&vcc5v0_sys>; + vcc8-supply = <&vcc5v0_sys>; + vcc9-supply = <&vcc5v0_sys>; + vcc10-supply = <&vcc5v0_sys>; + vcc11-supply = <&vcc_2v0_pldo_s3>; + vcc12-supply = <&vcc5v0_sys>; + vcc13-supply = <&vcc_2v0_pldo_s3>; + vcc14-supply = <&vcc_2v0_pldo_s3>; + vcca-supply = <&vcc5v0_sys>; + + rk806_dvs1_null: dvs1-null-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_dvs2_null: dvs2-null-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_dvs3_null: dvs3-null-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun0"; + }; + + regulators { + vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 { + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_gpu_s0"; + regulator-enable-ramp-delay = <400>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_cpu_lit_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_log_s0: dcdc-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <750000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_log_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_vdenc_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_ddr_s0: dcdc-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <900000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_ddr_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + vdd2_ddr_s3: dcdc-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vdd2_ddr_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_2v0_pldo_s3: dcdc-reg7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_2v0_pldo_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <2000000>; + }; + }; + + vcc_3v3_s3: dcdc-reg8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_3v3_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vddq_ddr_s0: dcdc-reg9 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vddq_ddr_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s3: dcdc-reg10 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + avcc_1v8_s0: pldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "avcc_1v8_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s0: pldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + avdd_1v2_s0: pldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-name = "avdd_1v2_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3_s0: pldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <12500>; + regulator-name = "vcc_3v3_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd_s0: pldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <12500>; + regulator-name = "vccio_sd_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + pldo6_s3: pldo-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "pldo6_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_0v75_s3: nldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "vdd_0v75_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdd_ddr_pll_s0: nldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-name = "vdd_ddr_pll_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + avdd_0v75_s0: nldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "avdd_0v75_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v85_s0: nldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-name = "vdd_0v85_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v75_s0: nldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "vdd_0v75_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&tsadc { + status = "okay"; +}; + +&uart2 { + pinctrl-0 = <&uart2m0_xfer>; + status = "okay"; +}; diff --git a/arch/arm/dts/rk3588-generic-u-boot.dtsi b/arch/arm/dts/rk3588-generic-u-boot.dtsi new file mode 100644 index 00000000000..853ed58cfe5 --- /dev/null +++ b/arch/arm/dts/rk3588-generic-u-boot.dtsi @@ -0,0 +1,3 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +#include "rk3588s-u-boot.dtsi" diff --git a/arch/arm/dts/rk3588-generic.dts b/arch/arm/dts/rk3588-generic.dts new file mode 100644 index 00000000000..e4721d97a87 --- /dev/null +++ b/arch/arm/dts/rk3588-generic.dts @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Minimal generic DT for RK3588S/RK3588 with eMMC and SD-card enabled + */ + +/dts-v1/; +#include "rk3588s.dtsi" + +/ { + model = "Generic RK3588S/RK3588"; + compatible = "rockchip,rk3588"; + + aliases { + mmc0 = &sdhci; + mmc1 = &sdmmc; + }; + + chosen { + stdout-path = "serial2:1500000n8"; + }; +}; + +&sdhci { + bus-width = <8>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + no-sd; + no-sdio; + non-removable; + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-sd-highspeed; + disable-wp; + no-mmc; + no-sdio; + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; diff --git a/arch/arm/dts/rk3588-jaguar-u-boot.dtsi b/arch/arm/dts/rk3588-jaguar-u-boot.dtsi new file mode 100644 index 00000000000..dcda4f99d6e --- /dev/null +++ b/arch/arm/dts/rk3588-jaguar-u-boot.dtsi @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Theobroma Systems Design und Consulting GmbH + */ + +#include "rk3588-u-boot.dtsi" + +/ { + chosen { + u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc; + }; +}; + +&emmc_pwrseq { + bootph-pre-ram; + bootph-some-ram; +}; + +&emmc_reset { + bootph-pre-ram; + bootph-some-ram; +}; + +&gpio2 { + bootph-pre-ram; + bootph-some-ram; +}; + +&sdhci { + /* U-Boot currently cannot handle anything below HS200 for eMMC on RK3588 */ + /delete-property/ mmc-ddr-1_8v; + /delete-property/ cap-mmc-highspeed; +}; diff --git a/arch/arm/dts/rk3588-jaguar.dts b/arch/arm/dts/rk3588-jaguar.dts new file mode 100644 index 00000000000..4ce70fb75a3 --- /dev/null +++ b/arch/arm/dts/rk3588-jaguar.dts @@ -0,0 +1,803 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Theobroma Systems Design und Consulting GmbH + */ + +/dts-v1/; +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/leds/common.h> +#include <dt-bindings/pinctrl/rockchip.h> +#include <dt-bindings/usb/pd.h> +#include "rk3588.dtsi" + +/ { + model = "Theobroma Systems RK3588-SBC Jaguar"; + compatible = "tsd,rk3588-jaguar", "rockchip,rk3588"; + + adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 0>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + + /* Can be controlled through SW2 but also GPIO1 on CP2102 on P20 */ + button-bios-disable { + label = "BIOS_DISABLE"; + linux,code = <KEY_VENDOR>; + press-threshold-microvolt = <0>; + }; + }; + + aliases { + ethernet0 = &gmac0; + mmc0 = &sdhci; + mmc1 = &sdmmc; + rtc0 = &rtc_twi; + }; + + chosen { + stdout-path = "serial2:115200n8"; + }; + + /* DCIN is 12-24V but standard is 12V */ + dc_12v: dc-12v-regulator { + compatible = "regulator-fixed"; + regulator-name = "dc_12v"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + emmc_pwrseq: emmc-pwrseq { + compatible = "mmc-pwrseq-emmc"; + pinctrl-0 = <&emmc_reset>; + pinctrl-names = "default"; + reset-gpios = <&gpio2 RK_PA3 GPIO_ACTIVE_HIGH>; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led1_pin>; + status = "okay"; + + /* LED1 on PCB */ + led-1 { + gpios = <&gpio1 RK_PD4 GPIO_ACTIVE_HIGH>; + function = LED_FUNCTION_HEARTBEAT; + linux,default-trigger = "heartbeat"; + color = <LED_COLOR_ID_AMBER>; + }; + }; + + pps { + compatible = "pps-gpio"; + gpios = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>; + }; + + vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v1_nldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc_1v2_s3: vcc-1v2-s3-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v2_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + vin-supply = <&vcc5v0_sys>; + }; + + /* Exposed on P14 and P15 */ + vcc_2v8_s3: vcc-2v8-s3-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_2v8_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + vin-supply = <&vcc_3v3_s3>; + }; + + vcc_5v0_usb_a: vcc-5v0-usb-a-regulator { + compatible = "regulator-fixed"; + regulator-name = "usb_a_vcc"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_sys>; + gpio = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vcc_5v0_usb_c1: vcc-5v0-usb-c1-regulator { + compatible = "regulator-fixed"; + regulator-name = "5v_usbc1"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_usb>; + gpio = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vcc_5v0_usb_c2: vcc-5v0-usb-c2-regulator { + compatible = "regulator-fixed"; + regulator-name = "5v_usbc2"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_usb>; + gpio = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vcc3v3_mdot2: vcc3v3-mdot2-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_mdot2"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&dc_12v>; + }; + + vcc5v0_sys: vcc5v0-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&dc_12v>; + }; + + vcc5v0_usb: vcc5v0-usb-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_sys>; + }; +}; + +&combphy1_ps { + status = "okay"; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_big0_s0>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu_big0_s0>; +}; + +&cpu_b2 { + cpu-supply = <&vdd_cpu_big1_s0>; +}; + +&cpu_b3 { + cpu-supply = <&vdd_cpu_big1_s0>; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&gmac0 { + clock_in_out = "output"; + phy-handle = <&rgmii_phy>; + phy-mode = "rgmii"; + phy-supply = <&vcc_1v2_s3>; + pinctrl-names = "default"; + pinctrl-0 = <&gmac0_miim + &gmac0_rx_bus2 + &gmac0_tx_bus2 + &gmac0_rgmii_clk + &gmac0_rgmii_bus + ð0_pins + ð_reset>; + tx_delay = <0x10>; + rx_delay = <0x10>; + snps,reset-gpio = <&gpio4 RK_PC3 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 100000>; + + status = "okay"; +}; + +&gpio1 { + mdot2e-w-disable1-n-hog { + gpios = <RK_PB1 GPIO_ACTIVE_LOW>; + output-low; + line-name = "m.2 E-key W_DISABLE1#"; + gpio-hog; + }; +}; + +&gpio4 { + mdot2e-w-disable2-n-hog { + gpios = <RK_PC1 GPIO_ACTIVE_LOW>; + output-low; + line-name = "m.2 E-key W_DISABLE2#"; + gpio-hog; + }; +}; + +&i2c0 { + pinctrl-0 = <&i2c0m2_xfer>; + status = "okay"; + + fan@18 { + compatible = "ti,amc6821"; + reg = <0x18>; + }; + + vdd_npu_s0: regulator@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_npu_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big1_s0: regulator@43 { + compatible = "rockchip,rk8603", "rockchip,rk8602"; + reg = <0x43>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu_big1_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + rtc_twi: rtc@6f { + compatible = "isil,isl1208"; + reg = <0x6f>; + }; +}; + +&i2c1 { + pinctrl-0 = <&i2c1m4_xfer>; +}; + +&i2c6 { + pinctrl-0 = <&i2c6m4_xfer>; +}; + +&i2c7 { + status = "okay"; + + /* SE050 Secure Element at 0x48; GPIO1_A4 for enable pin */ + + /* Also on 0x55 */ + eeprom@54 { + compatible = "st,24c04", "atmel,24c04"; + reg = <0x54>; + pagesize = <16>; + vcc-supply = <&vcc_3v3_s3>; + }; +}; + +&i2c8 { + pinctrl-0 = <&i2c8m2_xfer>; + status = "okay"; + + vdd_cpu_big0_s0: regulator@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu_big0_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&mdio0 { + rgmii_phy: ethernet-phy@6 { + /* KSZ9031 or KSZ9131 */ + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x6>; + clocks = <&cru REFCLKO25M_ETH0_OUT>; + }; +}; + +&pcie2x1l0 { + reset-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_HIGH>; /* WIFI_PERST0# */ + vpcie3v3-supply = <&vcc3v3_mdot2>; + status = "okay"; +}; + +&pinctrl { + emmc { + emmc_reset: emmc-reset { + rockchip,pins = <2 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + ethernet { + eth_reset: eth-reset { + rockchip,pins = <4 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + leds { + led1_pin: led1-pin { + rockchip,pins = <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&saradc { + vref-supply = <&vcc_1v8_s0>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + cap-mmc-highspeed; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + mmc-pwrseq = <&emmc_pwrseq>; + no-sdio; + no-sd; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_bus8 &emmc_cmd &emmc_clk &emmc_data_strobe>; + supports-cqe; + vmmc-supply = <&vcc_3v3_s3>; + vqmmc-supply = <&vcc_1v8_s3>; + status = "okay"; +}; + +&sdmmc { + broken-cd; + bus-width = <4>; + cap-sd-highspeed; + disable-wp; + max-frequency = <150000000>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_bus4 &sdmmc_cmd &sdmmc_clk>; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-ddr50; + sd-uhs-sdr104; + vmmc-supply = <&vcc_3v3_s3>; + vqmmc-supply = <&vccio_sd_s0>; + status = "okay"; +}; + +&spi2 { + assigned-clocks = <&cru CLK_SPI2>; + assigned-clock-rates = <200000000>; + num-cs = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; + status = "okay"; + + pmic@0 { + compatible = "rockchip,rk806"; + reg = <0x0>; + interrupt-parent = <&gpio0>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + gpio-controller; + #gpio-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, + <&rk806_dvs2_null>, <&rk806_dvs3_null>; + spi-max-frequency = <1000000>; + system-power-controller; + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc5-supply = <&vcc5v0_sys>; + vcc6-supply = <&vcc5v0_sys>; + vcc7-supply = <&vcc5v0_sys>; + vcc8-supply = <&vcc5v0_sys>; + vcc9-supply = <&vcc5v0_sys>; + vcc10-supply = <&vcc5v0_sys>; + vcc11-supply = <&vcc_2v0_pldo_s3>; + vcc12-supply = <&vcc5v0_sys>; + vcc13-supply = <&vcc_1v1_nldo_s3>; + vcc14-supply = <&vcc_1v1_nldo_s3>; + vcca-supply = <&vcc5v0_sys>; + + rk806_dvs1_null: dvs1-null-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_dvs2_null: dvs2-null-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_dvs3_null: dvs3-null-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun0"; + }; + + regulators { + vdd_gpu_s0: dcdc-reg1 { + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_gpu_s0"; + regulator-enable-ramp-delay = <400>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_lit_s0: dcdc-reg2 { + regulator-name = "vdd_cpu_lit_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_log_s0: dcdc-reg3 { + regulator-name = "vdd_log_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <750000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdd_vdenc_s0: dcdc-reg4 { + regulator-name = "vdd_vdenc_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_ddr_s0: dcdc-reg5 { + regulator-name = "vdd_ddr_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <900000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + vdd2_ddr_s3: dcdc-reg6 { + regulator-name = "vdd2_ddr_s3"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_2v0_pldo_s3: dcdc-reg7 { + regulator-name = "vdd_2v0_pldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <2000000>; + }; + }; + + vcc_3v3_s3: dcdc-reg8 { + regulator-name = "vcc_3v3_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vddq_ddr_s0: dcdc-reg9 { + regulator-name = "vddq_ddr_s0"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s3: dcdc-reg10 { + regulator-name = "vcc_1v8_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcca_1v8_s0: pldo-reg1 { + regulator-name = "vcca_1v8_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s0: pldo-reg2 { + regulator-name = "vcc_1v8_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdda_1v2_s0: pldo-reg3 { + regulator-name = "vdda_1v2_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca_3v3_s0: pldo-reg4 { + regulator-name = "vcca_3v3_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd_s0: pldo-reg5 { + regulator-name = "vccio_sd_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + pldo6_s3: pldo-reg6 { + regulator-name = "pldo6_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_0v75_s3: nldo-reg1 { + regulator-name = "vdd_0v75_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdda_ddr_pll_s0: nldo-reg2 { + regulator-name = "vdda_ddr_pll_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + vdda_0v75_s0: nldo-reg3 { + regulator-name = "vdda_0v75_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_0v85_s0: nldo-reg4 { + regulator-name = "vdda_0v85_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v75_s0: nldo-reg5 { + regulator-name = "vdd_0v75_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&tsadc { + status = "okay"; +}; + +&u2phy2 { + status = "okay"; +}; + +&u2phy2_host { + phy-supply = <&vcc_5v0_usb_a>; + status = "okay"; +}; + +&u2phy3 { + status = "okay"; +}; + +&u2phy3_host { + status = "okay"; +}; + +/* Mule-ATtiny debug UART; typically baudrate 9600 */ +&uart0 { + pinctrl-0 = <&uart0m0_xfer>; + status = "okay"; +}; + +/* Main debug interface on P20 micro-USB B port and P21 header */ +&uart2 { + pinctrl-0 = <&uart2m0_xfer>; + status = "okay"; +}; + +/* RS485 on P19 */ +&uart3 { + pinctrl-0 = <&uart3m2_xfer &uart3_rtsn>; + linux,rs485-enabled-at-boot-time; + status = "okay"; +}; + +/* Mule-ATtiny UPDI flashing UART */ +&uart7 { + pinctrl-0 = <&uart7m0_xfer>; + status = "okay"; +}; + +/* host0 on P10 USB-A */ +&usb_host0_ehci { + status = "okay"; +}; + +/* host0 on P10 USB-A */ +&usb_host0_ohci { + status = "okay"; +}; + +/* host1 on M.2 E-key */ +&usb_host1_ehci { + status = "okay"; +}; + +/* host1 on M.2 E-key */ +&usb_host1_ohci { + status = "okay"; +}; diff --git a/arch/arm/dts/rk3588-toybrick-x0-u-boot.dtsi b/arch/arm/dts/rk3588-toybrick-x0-u-boot.dtsi new file mode 100644 index 00000000000..1aeb5410e43 --- /dev/null +++ b/arch/arm/dts/rk3588-toybrick-x0-u-boot.dtsi @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2024 Rockchip Electronics Co., Ltd. + */ + +#include "rk3588-u-boot.dtsi" + +/ { + chosen { + u-boot,spl-boot-order = "same-as-spl", &sdhci; + }; +}; diff --git a/arch/arm/dts/rk3588-toybrick-x0.dts b/arch/arm/dts/rk3588-toybrick-x0.dts new file mode 100644 index 00000000000..9090c5c99f2 --- /dev/null +++ b/arch/arm/dts/rk3588-toybrick-x0.dts @@ -0,0 +1,688 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2024 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/pinctrl/rockchip.h> +#include "rk3588.dtsi" + +/ { + model = "Rockchip Toybrick TB-RK3588X Board"; + compatible = "rockchip,rk3588-toybrick-x0", "rockchip,rk3588"; + + aliases { + mmc0 = &sdhci; + }; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 1>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + + button-vol-up { + label = "Volume Up"; + linux,code = <KEY_VOLUMEUP>; + press-threshold-microvolt = <17000>; + }; + + button-vol-down { + label = "Volume Down"; + linux,code = <KEY_VOLUMEDOWN>; + press-threshold-microvolt = <417000>; + }; + + button-menu { + label = "Menu"; + linux,code = <KEY_MENU>; + press-threshold-microvolt = <890000>; + }; + + button-escape { + label = "Escape"; + linux,code = <KEY_ESC>; + press-threshold-microvolt = <1235000>; + }; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + power-supply = <&vcc12v_dcin>; + pwms = <&pwm2 0 25000 0>; + }; + + pcie20_avdd0v85: pcie20-avdd0v85-regulator { + compatible = "regulator-fixed"; + regulator-name = "pcie20_avdd0v85"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + vin-supply = <&vdd_0v85_s0>; + }; + + pcie20_avdd1v8: pcie20-avdd1v8-regulator { + compatible = "regulator-fixed"; + regulator-name = "pcie20_avdd1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&avcc_1v8_s0>; + }; + + pcie30_avdd0v75: pcie30-avdd0v75-regulator { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd0v75"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + vin-supply = <&avdd_0v75_s0>; + }; + + pcie30_avdd1v8: pcie30-avdd1v8-regulator { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&avcc_1v8_s0>; + }; + + vcc12v_dcin: vcc12v-dcin-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc5v0_host: vcc5v0-host-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en>; + regulator-name = "vcc5v0_host"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_usb>; + }; + + vcc5v0_sys: vcc5v0-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_usbdcin: vcc5v0-usbdcin-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usbdcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_usb: vcc5v0-usb-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_usbdcin>; + }; + + vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v1_nldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc5v0_sys>; + }; +}; + +&combphy0_ps { + status = "okay"; +}; + +&combphy2_psu { + status = "okay"; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_big0_s0>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu_big0_s0>; +}; + +&cpu_b2 { + cpu-supply = <&vdd_cpu_big1_s0>; +}; + +&cpu_b3 { + cpu-supply = <&vdd_cpu_big1_s0>; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&gmac0 { + clock_in_out = "output"; + phy-handle = <&rgmii_phy>; + phy-mode = "rgmii-rxid"; + pinctrl-0 = <&gmac0_miim + &gmac0_tx_bus2 + &gmac0_rx_bus2 + &gmac0_rgmii_clk + &gmac0_rgmii_bus>; + pinctrl-names = "default"; + rx_delay = <0x00>; + tx_delay = <0x43>; + status = "okay"; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0m2_xfer>; + status = "okay"; + + vdd_cpu_big0_s0: regulator@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu_big0_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big1_s0: regulator@43 { + compatible = "rockchip,rk8603", "rockchip,rk8602"; + reg = <0x43>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu_big1_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c2 { + status = "okay"; + + hym8563: rtc@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-output-names = "hym8563"; + interrupt-parent = <&gpio0>; + interrupts = <RK_PD4 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&hym8563_int>; + wakeup-source; + }; +}; + +&mdio0 { + rgmii_phy: ethernet-phy@1 { + /* RTL8211F */ + compatible = "ethernet-phy-id001c.c916"; + reg = <0x1>; + pinctrl-names = "default"; + pinctrl-0 = <&rtl8211f_rst>; + reset-assert-us = <20000>; + reset-deassert-us = <100000>; + reset-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_LOW>; + }; +}; + +&pinctrl { + rtl8211f { + rtl8211f_rst: rtl8211f-rst { + rockchip,pins = <4 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + }; + + hym8563 { + hym8563_int: hym8563-int { + rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pwm2 { + status = "okay"; +}; + +&saradc { + vref-supply = <&vcc_1v8_s0>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + no-sdio; + no-sd; + non-removable; + status = "okay"; +}; + +&spi2 { + assigned-clocks = <&cru CLK_SPI2>; + assigned-clock-rates = <200000000>; + num-cs = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; + status = "okay"; + + pmic@0 { + compatible = "rockchip,rk806"; + reg = <0x0>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gpio0>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, + <&rk806_dvs2_null>, <&rk806_dvs3_null>; + spi-max-frequency = <1000000>; + system-power-controller; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc5-supply = <&vcc5v0_sys>; + vcc6-supply = <&vcc5v0_sys>; + vcc7-supply = <&vcc5v0_sys>; + vcc8-supply = <&vcc5v0_sys>; + vcc9-supply = <&vcc5v0_sys>; + vcc10-supply = <&vcc5v0_sys>; + vcc11-supply = <&vcc_2v0_pldo_s3>; + vcc12-supply = <&vcc5v0_sys>; + vcc13-supply = <&vcc_1v1_nldo_s3>; + vcc14-supply = <&vcc_1v1_nldo_s3>; + vcca-supply = <&vcc5v0_sys>; + + rk806_dvs1_null: dvs1-null-pins { + pins = "gpio_pwrctrl1"; + function = "pin_fun0"; + }; + + rk806_dvs2_null: dvs2-null-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_dvs3_null: dvs3-null-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun0"; + }; + + regulators { + vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 { + regulator-name = "vdd_gpu_s0"; + regulator-boot-on; + regulator-enable-ramp-delay = <400>; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 { + regulator-name = "vdd_cpu_lit_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_log_s0: dcdc-reg3 { + regulator-name = "vdd_log_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <750000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 { + regulator-name = "vdd_vdenc_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-init-microvolt = <750000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_ddr_s0: dcdc-reg5 { + regulator-name = "vdd_ddr_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <900000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + vdd2_ddr_s3: dcdc-reg6 { + regulator-name = "vdd2_ddr_s3"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_2v0_pldo_s3: dcdc-reg7 { + regulator-name = "vdd_2v0_pldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <2000000>; + }; + }; + + vcc_3v3_s3: dcdc-reg8 { + regulator-name = "vcc_3v3_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vddq_ddr_s0: dcdc-reg9 { + regulator-name = "vddq_ddr_s0"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s3: dcdc-reg10 { + regulator-name = "vcc_1v8_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + avcc_1v8_s0: pldo-reg1 { + regulator-name = "avcc_1v8_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s0: pldo-reg2 { + regulator-name = "vcc_1v8_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + avdd_1v2_s0: pldo-reg3 { + regulator-name = "avdd_1v2_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3_s0: pldo-reg4 { + regulator-name = "vcc_3v3_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd_s0: pldo-reg5 { + regulator-name = "vccio_sd_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + pldo6_s3: pldo-reg6 { + regulator-name = "pldo6_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_0v75_s3: nldo-reg1 { + regulator-name = "vdd_0v75_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdd_ddr_pll_s0: nldo-reg2 { + regulator-name = "vdd_ddr_pll_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + avdd_0v75_s0: nldo-reg3 { + regulator-name = "avdd_0v75_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <837500>; + regulator-max-microvolt = <837500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v85_s0: nldo-reg4 { + regulator-name = "vdd_0v85_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v75_s0: nldo-reg5 { + regulator-name = "vdd_0v75_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&u2phy2 { + status = "okay"; +}; + +&u2phy2_host { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&u2phy3 { + status = "okay"; +}; + +&u2phy3_host { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&uart2 { + pinctrl-0 = <&uart2m0_xfer>; + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; diff --git a/arch/arm/dts/rk3588s-coolpi-4b-u-boot.dtsi b/arch/arm/dts/rk3588s-coolpi-4b-u-boot.dtsi new file mode 100644 index 00000000000..6e4b97028d7 --- /dev/null +++ b/arch/arm/dts/rk3588s-coolpi-4b-u-boot.dtsi @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +#include "rk3588s-u-boot.dtsi" + +&fspim2_pins { + bootph-all; +}; + +&sdhci { + cap-mmc-highspeed; + mmc-hs200-1_8v; +}; + +&sfc { + bootph-pre-ram; + u-boot,spl-sfc-no-dma; + pinctrl-names = "default"; + pinctrl-0 = <&fspim2_pins>; + status = "okay"; + + flash@0 { + bootph-pre-ram; + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <24000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <1>; + }; +}; diff --git a/arch/arm/dts/rk3588s-coolpi-4b.dts b/arch/arm/dts/rk3588s-coolpi-4b.dts new file mode 100644 index 00000000000..e037bf9db75 --- /dev/null +++ b/arch/arm/dts/rk3588s-coolpi-4b.dts @@ -0,0 +1,812 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + * + * https://cool-pi.com/topic/130/coolpi-4b-product-spec-introduction + * + */ + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/leds/common.h> +#include <dt-bindings/pinctrl/rockchip.h> +#include "rk3588s.dtsi" + +/ { + model = "RK3588S CoolPi 4 Model B"; + compatible = "coolpi,pi-4b", "rockchip,rk3588s"; + + aliases { + mmc0 = &sdhci; + mmc1 = &sdmmc; + mmc2 = &sdio; + }; + + analog-sound { + compatible = "audio-graph-card"; + dais = <&i2s0_8ch_p0>; + label = "rk3588-es8316"; + routing = "MIC2", "Mic Jack", + "Headphones", "HPOL", + "Headphones", "HPOR"; + widgets = "Microphone", "Mic Jack", + "Headphone", "Headphones"; + }; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + leds: leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&gpio_leds>; + + led0: led-green { + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_STATUS; + gpios = <&gpio0 RK_PD0 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + + led1: led-red { + color = <LED_COLOR_ID_RED>; + default-state = "off"; + function = LED_FUNCTION_WLAN; + gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "phy0tx"; + }; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&hym8563>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + post-power-on-delay-ms = <200>; + reset-gpios = <&gpio0 RK_PC7 GPIO_ACTIVE_LOW>; + }; + + vcc12v_dcin: vcc12v-dcin-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc5v0_sys: vcc5v0-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_usbdcin: vcc5v0-usbdcin-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usbdcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_usb: vcc5v0-usb-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_usbdcin>; + }; + + avdd0v85_pcie20: avdd0v85-pcie20-regulator { + compatible = "regulator-fixed"; + regulator-name = "avdd0v85_pcie20"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + vin-supply = <&vdd_0v85_s0>; + }; + + avdd1v8_pcie20: avdd1v8-pcie20-regulator { + compatible = "regulator-fixed"; + regulator-name = "avdd1v8_pcie20"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&avcc_1v8_s0>; + }; + + vcc3v3_mipi: vcc3v3-mipi-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio3 RK_PC2 GPIO_ACTIVE_HIGH>; + regulator-name = "vcc3v3_mipi"; + regulator-boot-on; + regulator-always-on; + vin-supply = <&vcc_3v3_s3>; + }; + + vcc5v0_host: vcc5v0-host-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio3 RK_PC0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en>; + regulator-name = "vcc5v0_host"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_otg: vcc5v0-otg-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_u3host_en>; + regulator-name = "vcc5v0_otg"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v1_nldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc5v0_sys>; + }; +}; + +&combphy0_ps { + status = "okay"; +}; + +&combphy2_psu { + status = "okay"; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_big0_s0>; +}; + +&cpu_b2 { + cpu-supply = <&vdd_cpu_big1_s0>; +}; + +&i2c0 { + pinctrl-0 = <&i2c0m2_xfer>; + status = "okay"; + + vdd_cpu_big0_s0: regulator@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu_big0_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big1_s0: regulator@43 { + compatible = "rockchip,rk8603", "rockchip,rk8602"; + reg = <0x43>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu_big1_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c2 { + status = "okay"; + + vdd_npu_s0: regulator@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_npu_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c6 { + pinctrl-0 = <&i2c6m3_xfer>; + status = "okay"; + + hym8563: rtc@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + interrupt-parent = <&gpio0>; + interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>; + #clock-cells = <0>; + clock-output-names = "hym8563"; + pinctrl-names = "default"; + pinctrl-0 = <&hym8563_int>; + }; +}; + +&i2c7 { + pinctrl-0 = <&i2c7m0_xfer>; + status = "okay"; + + es8316: audio-codec@11 { + compatible = "everest,es8316"; + reg = <0x11>; + assigned-clocks = <&cru I2S0_8CH_MCLKOUT>; + assigned-clock-rates = <12288000>; + clocks = <&cru I2S0_8CH_MCLKOUT>; + clock-names = "mclk"; + #sound-dai-cells = <0>; + + port { + es8316_p0_0: endpoint { + remote-endpoint = <&i2s0_8ch_p0_0>; + }; + }; + }; +}; + +&i2s0_8ch { + pinctrl-0 = <&i2s0_lrck + &i2s0_mclk + &i2s0_sclk + &i2s0_sdi0 + &i2s0_sdo0>; + status = "okay"; + + i2s0_8ch_p0: port { + i2s0_8ch_p0_0: endpoint { + dai-format = "i2s"; + mclk-fs = <256>; + remote-endpoint = <&es8316_p0_0>; + }; + }; +}; + +&pcie2x1l2 { + pinctrl-names = "default"; + pinctrl-0 = <&rtl8111_isolate>; + reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&pinctrl { + hym8563 { + hym8563_int: hym8563-int { + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + led { + gpio_leds: gpio-leds { + rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_down>, + <0 RK_PD0 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + rtl8111 { + rtl8111_isolate: rtl8111-isolate { + rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>, + <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + vcc5v0_u3host_en: vcc5v0-u3host-en { + rockchip,pins = <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wireless-bluetooth { + bt_reset_gpio: bt-reset-pin { + rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_wake_gpio: bt-wake-pin { + rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_wake_host_irq: bt-wake-host-irq { + rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + wireless-wlan { + wifi_host_wake_irq: wifi-host-wake-irq { + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + wifi_poweren_pin: wifi-poweren-pin { + rockchip,pins = <1 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&pwm2 { + pinctrl-0 = <&pwm2m1_pins>; + status = "okay"; +}; + +&pwm13 { + pinctrl-names = "active"; + pinctrl-0 = <&pwm13m2_pins>; + status = "okay"; +}; + +&saradc { + vref-supply = <&vcc_1v8_s0>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + max-frequency = <200000000>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + no-sdio; + no-sd; + non-removable; + status = "okay"; +}; + +&sdio { + bus-width = <4>; + cap-sd-highspeed; + cap-sdio-irq; + disable-wp; + keep-power-in-suspend; + max-frequency = <150000000>; + mmc-pwrseq = <&sdio_pwrseq>; + no-sd; + no-mmc; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdiom1_pins>,<&wifi_poweren_pin>; + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + max-frequency = <150000000>; + no-sdio; + no-mmc; + sd-uhs-sdr104; + vmmc-supply = <&vcc_3v3_s3>; + vqmmc-supply = <&vccio_sd_s0>; + status = "okay"; +}; + +&spi2 { + assigned-clocks = <&cru CLK_SPI2>; + assigned-clock-rates = <200000000>; + num-cs = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; + status = "okay"; + + pmic@0 { + compatible = "rockchip,rk806"; + reg = <0x0>; + interrupt-parent = <&gpio0>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + gpio-controller; + #gpio-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, + <&rk806_dvs2_null>, <&rk806_dvs3_null>; + spi-max-frequency = <1000000>; + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc5-supply = <&vcc5v0_sys>; + vcc6-supply = <&vcc5v0_sys>; + vcc7-supply = <&vcc5v0_sys>; + vcc8-supply = <&vcc5v0_sys>; + vcc9-supply = <&vcc5v0_sys>; + vcc10-supply = <&vcc5v0_sys>; + vcc11-supply = <&vcc_2v0_pldo_s3>; + vcc12-supply = <&vcc5v0_sys>; + vcc13-supply = <&vcc_1v1_nldo_s3>; + vcc14-supply = <&vcc_1v1_nldo_s3>; + vcca-supply = <&vcc5v0_sys>; + + rk806_dvs1_null: dvs1-null-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_dvs2_null: dvs2-null-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_dvs3_null: dvs3-null-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun0"; + }; + + regulators { + vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 { + regulator-name = "vdd_gpu_s0"; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-enable-ramp-delay = <400>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 { + regulator-name = "vdd_cpu_lit_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_log_s0: dcdc-reg3 { + regulator-name = "vdd_log_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <750000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 { + regulator-name = "vdd_vdenc_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_ddr_s0: dcdc-reg5 { + regulator-name = "vdd_ddr_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <900000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + vdd2_ddr_s3: dcdc-reg6 { + regulator-name = "vdd2_ddr_s3"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_2v0_pldo_s3: dcdc-reg7 { + regulator-name = "vdd_2v0_pldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <2000000>; + }; + }; + + vcc_3v3_s3: dcdc-reg8 { + regulator-name = "vcc_3v3_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vddq_ddr_s0: dcdc-reg9 { + regulator-name = "vddq_ddr_s0"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s3: dcdc-reg10 { + regulator-name = "vcc_1v8_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + avcc_1v8_s0: pldo-reg1 { + regulator-name = "avcc_1v8_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s0: pldo-reg2 { + regulator-name = "vcc_1v8_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + avdd_1v2_s0: pldo-reg3 { + regulator-name = "avdd_1v2_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3_s0: pldo-reg4 { + regulator-name = "vcc_3v3_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd_s0: pldo-reg5 { + regulator-name = "vccio_sd_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + pldo6_s3: pldo-reg6 { + regulator-name = "pldo6_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_0v75_s3: nldo-reg1 { + regulator-name = "vdd_0v75_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdd_ddr_pll_s0: nldo-reg2 { + regulator-name = "vdd_ddr_pll_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + avdd_0v75_s0: nldo-reg3 { + regulator-name = "avdd_0v75_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v85_s0: nldo-reg4 { + regulator-name = "vdd_0v85_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v75_s0: nldo-reg5 { + regulator-name = "vdd_0v75_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&tsadc { + status = "okay"; +}; + +&u2phy2 { + status = "okay"; +}; + +&u2phy3 { + status = "okay"; +}; + +&u2phy2_host { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&u2phy3_host { + status = "okay"; +}; + +&uart2 { + pinctrl-0 = <&uart2m0_xfer>; + status = "okay"; +}; + +/* bt */ +&uart9 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart9m2_xfer &uart9m2_ctsn>; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; diff --git a/arch/arm/dts/rk3588s-u-boot.dtsi b/arch/arm/dts/rk3588s-u-boot.dtsi index bf3b1ea8a3c..ac67c777ade 100644 --- a/arch/arm/dts/rk3588s-u-boot.dtsi +++ b/arch/arm/dts/rk3588s-u-boot.dtsi @@ -188,11 +188,13 @@ &sdmmc { bootph-pre-ram; + bootph-some-ram; u-boot,spl-fifo-mode; }; &sdhci { bootph-pre-ram; + bootph-some-ram; u-boot,spl-fifo-mode; }; diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3588.h b/arch/arm/include/asm/arch-rockchip/cru_rk3588.h index 7f4a9085392..a4507e5fdd7 100644 --- a/arch/arm/include/asm/arch-rockchip/cru_rk3588.h +++ b/arch/arm/include/asm/arch-rockchip/cru_rk3588.h @@ -63,6 +63,8 @@ struct rk3588_pll { unsigned int reserved0[3]; }; +#define CRU_BASE 0xfd7c0000 + struct rk3588_cru { struct rk3588_pll pll[18]; unsigned int reserved0[16];/* Address Offset: 0x0240 */ diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3588.h b/arch/arm/include/asm/arch-rockchip/grf_rk3588.h index e0694068bb1..f0ecff97f0b 100644 --- a/arch/arm/include/asm/arch-rockchip/grf_rk3588.h +++ b/arch/arm/include/asm/arch-rockchip/grf_rk3588.h @@ -32,4 +32,28 @@ struct rk3588_pmu1grf { check_member(rk3588_pmu1grf, sd_detect_cnt, 0x03b0); +#define SYS_GRF_BASE 0xfd58c000 + +struct rk3588_sysgrf { + unsigned int wdt_con0; + unsigned int reserved0[(0x0010 - 0x0000) / 4 - 1]; + unsigned int uart_con[2]; + unsigned int reserved1[(0x00c0 - 0x0014) / 4 - 1]; + unsigned int gic_con0; + unsigned int reserved2[(0x0200 - 0x00c0) / 4 - 1]; + unsigned int memcfg_con[32]; + unsigned int reserved3[(0x0300 - 0x027c) / 4 - 1]; + /* soc_con0 is reserved */ + unsigned int soc_con[14]; + unsigned int reserved4[(0x0380 - 0x0334) / 4 - 1]; + unsigned int soc_status[4]; + unsigned int reserved5[(0x0500 - 0x038c) / 4 - 1]; + unsigned int otp_key08; + unsigned int otp_key0d; + unsigned int otp_key0e; + unsigned int reserved6[(0x0600 - 0x0508) / 4 - 1]; + unsigned int chip_id; +}; + +check_member(rk3588_sysgrf, chip_id, 0x0600); #endif /*__SOC_ROCKCHIP_RK3588_GRF_H__ */ diff --git a/arch/arm/include/asm/arch-rockchip/hardware.h b/arch/arm/include/asm/arch-rockchip/hardware.h index 62e8bed8f31..e4662a2d52d 100644 --- a/arch/arm/include/asm/arch-rockchip/hardware.h +++ b/arch/arm/include/asm/arch-rockchip/hardware.h @@ -6,6 +6,8 @@ #ifndef _ASM_ARCH_HARDWARE_H #define _ASM_ARCH_HARDWARE_H +#include <asm/io.h> + #define RK_CLRSETBITS(clr, set) ((((clr) | (set)) << 16) | (set)) #define RK_SETBITS(set) RK_CLRSETBITS(0, set) #define RK_CLRBITS(clr) RK_CLRSETBITS(clr, 0) diff --git a/arch/arm/include/asm/arch-rockchip/ioc_rk3588.h b/arch/arm/include/asm/arch-rockchip/ioc_rk3588.h index 5a656f850c7..7ad98466c39 100644 --- a/arch/arm/include/asm/arch-rockchip/ioc_rk3588.h +++ b/arch/arm/include/asm/arch-rockchip/ioc_rk3588.h @@ -5,6 +5,8 @@ #ifndef _ASM_ARCH_IOC_RK3588_H #define _ASM_ARCH_IOC_RK3588_H +#define BUS_IOC_BASE 0xfd5f8000 + struct rk3588_bus_ioc { unsigned int reserved0000[3]; /* Address Offset: 0x0000 */ unsigned int gpio0b_iomux_sel_h; /* Address Offset: 0x000C */ @@ -48,6 +50,8 @@ struct rk3588_bus_ioc { check_member(rk3588_bus_ioc, gpio4d_iomux_sel_h, 0x009C); +#define PMU1_IOC_BASE 0xfd5f0000 + struct rk3588_pmu1_ioc { unsigned int gpio0a_iomux_sel_l; /* Address Offset: 0x0000 */ unsigned int gpio0a_iomux_sel_h; /* Address Offset: 0x0004 */ @@ -70,6 +74,8 @@ struct rk3588_pmu1_ioc { check_member(rk3588_pmu1_ioc, xin_con, 0x0040); +#define PMU2_IOC_BASE 0xfd5f4000 + struct rk3588_pmu2_ioc { unsigned int gpio0b_iomux_sel_h; /* Address Offset: 0x0000 */ unsigned int gpio0c_iomux_sel_l; /* Address Offset: 0x0004 */ diff --git a/arch/arm/include/asm/arch-rockchip/misc.h b/arch/arm/include/asm/arch-rockchip/misc.h deleted file mode 100644 index 4155af8c3b0..00000000000 --- a/arch/arm/include/asm/arch-rockchip/misc.h +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * RK3399: Architecture common definitions - * - * Copyright (C) 2019 Collabora Inc - https://www.collabora.com/ - * Rohan Garg <rohan.garg@collabora.com> - */ - -int rockchip_cpuid_from_efuse(const u32 cpuid_offset, - const u32 cpuid_length, - u8 *cpuid); -int rockchip_cpuid_set(const u8 *cpuid, const u32 cpuid_length); -int rockchip_setup_macaddr(void); -void rockchip_capsule_update_board_setup(void); diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index 1bc7ee90427..f68a0a48949 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -189,6 +189,9 @@ config ROCKCHIP_RK3328 select ENABLE_ARM_SOC_BOOT0_HOOK select DEBUG_UART_BOARD_INIT select SYS_NS16550 + imply MISC + imply ROCKCHIP_EFUSE + imply MISC_INIT_R help The Rockchip RK3328 is a ARM-based SoC with a quad-core Cortex-A53. including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two @@ -267,6 +270,9 @@ config ROCKCHIP_RK3399 imply SYS_BOOTCOUNT_SINGLEWORD if BOOTCOUNT_LIMIT imply BOOTSTD_FULL imply CMD_BOOTCOUNT if BOOTCOUNT_LIMIT + imply MISC + imply ROCKCHIP_EFUSE + imply MISC_INIT_R help The Rockchip RK3399 is a ARM-based SoC with a dual-core Cortex-A72 and quad-core Cortex-A53. @@ -501,6 +507,30 @@ config SPL_ROCKCHIP_EARLYRETURN_TO_BROM This enables support code in the BOOT0 hook for the SPL stage to allow multiple entries. +config ROCKCHIP_DISABLE_FORCE_JTAG + bool "Disable force_jtag feature" + default y + depends on SPL + help + Rockchip SoCs can automatically switch between jtag and sdmmc based + on the following rules: + - all the SDMMC pins including SDMMC_DET set as SDMMC function in + GRF, + - force_jtag bit in GRF is 1, + - SDMMC_DET is low (no card detected), + + Some HW design may not route the SD card card detect to SDMMC_DET + pin, thus breaking the SD card support in some cases because JTAG + would be auto-enabled by mistake. + + Also, enabling JTAG at runtime may be an undesired feature, e.g. + because it could be a security vulnerability. + + This disables force_jtag feature, which you may want for debugging + purposes. + + If unsure, say Y. + config TPL_ROCKCHIP_EARLYRETURN_TO_BROM bool "TPL requires early-return (for RK3188-style BROM) to BROM" depends on TPL && ENABLE_ARM_SOC_BOOT0_HOOK @@ -528,6 +558,21 @@ config ROCKCHIP_SPI_IMAGE config LNX_KRNL_IMG_TEXT_OFFSET_BASE default TEXT_BASE +config ROCKCHIP_COMMON_STACK_ADDR + bool + depends on SPL_SHARES_INIT_SP_ADDR + select HAS_CUSTOM_SYS_INIT_SP_ADDR + imply SPL_LIBCOMMON_SUPPORT if SPL + imply SPL_LIBGENERIC_SUPPORT if SPL + imply SPL_ROCKCHIP_COMMON_BOARD if SPL + imply SPL_SYS_MALLOC_F if SPL + imply SPL_SYS_MALLOC_SIMPLE if SPL + imply TPL_LIBCOMMON_SUPPORT if TPL + imply TPL_LIBGENERIC_SUPPORT if TPL + imply TPL_ROCKCHIP_COMMON_BOARD if TPL + imply TPL_SYS_MALLOC_F if TPL + imply TPL_SYS_MALLOC_SIMPLE if TPL + source "arch/arm/mach-rockchip/px30/Kconfig" source "arch/arm/mach-rockchip/rk3036/Kconfig" source "arch/arm/mach-rockchip/rk3066/Kconfig" @@ -543,4 +588,44 @@ source "arch/arm/mach-rockchip/rk3568/Kconfig" source "arch/arm/mach-rockchip/rk3588/Kconfig" source "arch/arm/mach-rockchip/rv1108/Kconfig" source "arch/arm/mach-rockchip/rv1126/Kconfig" + +if ROCKCHIP_COMMON_STACK_ADDR && SPL_SHARES_INIT_SP_ADDR + +config CUSTOM_SYS_INIT_SP_ADDR + default 0x3f00000 + +config SYS_MALLOC_F_LEN + default 0x10000 if CUSTOM_SYS_INIT_SP_ADDR = 0x3f00000 + +config SPL_SYS_MALLOC_F_LEN + default 0x8000 if CUSTOM_SYS_INIT_SP_ADDR = 0x3f00000 + +config TPL_SYS_MALLOC_F_LEN + default 0x4000 if CUSTOM_SYS_INIT_SP_ADDR = 0x3f00000 + +config TEXT_BASE + default 0x00200000 if ARM64 + +config SPL_TEXT_BASE + default 0x0 if ARM64 + +config SPL_HAS_BSS_LINKER_SECTION + default y if ARM64 + +config SPL_BSS_START_ADDR + default 0x3f80000 + +config SPL_BSS_MAX_SIZE + default 0x8000 if SPL_BSS_START_ADDR = 0x3f80000 + +config SPL_STACK_R + default y if CUSTOM_SYS_INIT_SP_ADDR = 0x3f00000 + +config SPL_STACK_R_ADDR + default 0x3e00000 if CUSTOM_SYS_INIT_SP_ADDR = 0x3f00000 + +config SPL_STACK_R_MALLOC_SIMPLE_LEN + default 0x200000 if SPL_STACK_R_ADDR = 0x3e00000 + +endif endif diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile index 1dc92066bbf..c07bdaee4c3 100644 --- a/arch/arm/mach-rockchip/Makefile +++ b/arch/arm/mach-rockchip/Makefile @@ -23,7 +23,6 @@ ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TPL_BUILD),) # meaning "turn it off". obj-y += boot_mode.o obj-$(CONFIG_ROCKCHIP_COMMON_BOARD) += board.o -obj-$(CONFIG_MISC_INIT_R) += misc.o endif ifeq ($(CONFIG_TPL_BUILD),) diff --git a/arch/arm/mach-rockchip/board.c b/arch/arm/mach-rockchip/board.c index 2620530e03f..cd226844b63 100644 --- a/arch/arm/mach-rockchip/board.c +++ b/arch/arm/mach-rockchip/board.c @@ -1,29 +1,41 @@ // SPDX-License-Identifier: GPL-2.0+ /* * (C) Copyright 2019 Rockchip Electronics Co., Ltd. + * + * Copyright (C) 2019 Collabora Inc - https://www.collabora.com/ + * Rohan Garg <rohan.garg@collabora.com> + * + * Based on puma-rk3399.c: + * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH */ #include <common.h> #include <clk.h> #include <cpu_func.h> +#include <env.h> #include <dm.h> +#include <dm/uclass-internal.h> #include <efi_loader.h> #include <fastboot.h> +#include <hash.h> #include <init.h> #include <log.h> #include <mmc.h> +#include <dm/uclass-internal.h> +#include <misc.h> #include <part.h> #include <ram.h> #include <syscon.h> #include <uuid.h> +#include <u-boot/crc.h> +#include <u-boot/sha256.h> #include <asm/cache.h> #include <asm/io.h> #include <asm/arch-rockchip/boot_mode.h> #include <asm/arch-rockchip/clock.h> #include <asm/arch-rockchip/periph.h> -#include <asm/arch-rockchip/misc.h> #include <power/regulator.h> -#if defined(CONFIG_EFI_HAVE_CAPSULE_SUPPORT) && defined(CONFIG_EFI_PARTITION) +#if IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT) && IS_ENABLED(CONFIG_EFI_PARTITION) #define DFU_ALT_BUF_LEN SZ_1K @@ -136,6 +148,10 @@ void set_dfu_alt_info(char *interface, char *devstr) env_set("dfu_alt_info", buf); } +__weak void rockchip_capsule_update_board_setup(void) +{ +} + static void gpt_capsule_update_setup(void) { int p, i, ret; @@ -170,10 +186,6 @@ static void gpt_capsule_update_setup(void) __weak int rk_board_late_init(void) { -#if defined(CONFIG_EFI_HAVE_CAPSULE_SUPPORT) && defined(CONFIG_EFI_PARTITION) - gpt_capsule_update_setup(); -#endif - return 0; } @@ -181,6 +193,10 @@ int board_late_init(void) { setup_boot_mode(); +#if IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT) && IS_ENABLED(CONFIG_EFI_PARTITION) + gpt_capsule_update_setup(); +#endif + return rk_board_late_init(); } @@ -205,8 +221,24 @@ void enable_caches(void) } #endif -#if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG) +#if IS_ENABLED(CONFIG_USB_GADGET) #include <usb.h> + +#if IS_ENABLED(CONFIG_USB_GADGET_DOWNLOAD) +#define ROCKCHIP_G_DNL_UMS_PRODUCT_NUM 0x0010 + +int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name) +{ + if (!strcmp(name, "usb_dnl_ums")) + put_unaligned(ROCKCHIP_G_DNL_UMS_PRODUCT_NUM, &dev->idProduct); + else + put_unaligned(CONFIG_USB_GADGET_PRODUCT_NUM, &dev->idProduct); + + return 0; +} +#endif /* CONFIG_USB_GADGET_DOWNLOAD */ + +#if IS_ENABLED(CONFIG_USB_GADGET_DWC2_OTG) && !IS_ENABLED(CONFIG_DM_USB_GADGET) #include <linux/usb/otg.h> #include <usb/dwc2_udc.h> @@ -281,6 +313,7 @@ int board_usb_cleanup(int index, enum usb_init_type init) return 0; } #endif /* CONFIG_USB_GADGET_DWC2_OTG */ +#endif /* CONFIG_USB_GADGET */ #if IS_ENABLED(CONFIG_FASTBOOT) int fastboot_set_reboot_flag(enum fastboot_reboot_reason reason) @@ -297,6 +330,124 @@ int fastboot_set_reboot_flag(enum fastboot_reboot_reason reason) #endif #ifdef CONFIG_MISC_INIT_R +int rockchip_setup_macaddr(void) +{ +#if CONFIG_IS_ENABLED(HASH) && CONFIG_IS_ENABLED(SHA256) + int ret; + const char *cpuid = env_get("cpuid#"); + u8 hash[SHA256_SUM_LEN]; + int size = sizeof(hash); + u8 mac_addr[6]; + + /* Only generate a MAC address, if none is set in the environment */ + if (env_get("ethaddr")) + return 0; + + if (!cpuid) { + debug("%s: could not retrieve 'cpuid#'\n", __func__); + return -1; + } + + ret = hash_block("sha256", (void *)cpuid, strlen(cpuid), hash, &size); + if (ret) { + debug("%s: failed to calculate SHA256\n", __func__); + return -1; + } + + /* Copy 6 bytes of the hash to base the MAC address on */ + memcpy(mac_addr, hash, 6); + + /* Make this a valid MAC address and set it */ + mac_addr[0] &= 0xfe; /* clear multicast bit */ + mac_addr[0] |= 0x02; /* set local assignment bit (IEEE802) */ + eth_env_set_enetaddr("ethaddr", mac_addr); + + /* Make a valid MAC address for ethernet1 */ + mac_addr[5] ^= 0x01; + eth_env_set_enetaddr("eth1addr", mac_addr); +#endif + return 0; +} + +int rockchip_cpuid_from_efuse(const u32 cpuid_offset, + const u32 cpuid_length, + u8 *cpuid) +{ +#if IS_ENABLED(CONFIG_ROCKCHIP_EFUSE) || IS_ENABLED(CONFIG_ROCKCHIP_OTP) + struct udevice *dev; + int ret; + + /* retrieve the device */ +#if IS_ENABLED(CONFIG_ROCKCHIP_EFUSE) + ret = uclass_get_device_by_driver(UCLASS_MISC, + DM_DRIVER_GET(rockchip_efuse), &dev); +#elif IS_ENABLED(CONFIG_ROCKCHIP_OTP) + ret = uclass_get_device_by_driver(UCLASS_MISC, + DM_DRIVER_GET(rockchip_otp), &dev); +#endif + if (ret) { + debug("%s: could not find efuse device\n", __func__); + return -1; + } + + /* read the cpu_id range from the efuses */ + ret = misc_read(dev, cpuid_offset, cpuid, cpuid_length); + if (ret < 0) { + debug("%s: reading cpuid from the efuses failed\n", + __func__); + return -1; + } +#endif + return 0; +} + +int rockchip_cpuid_set(const u8 *cpuid, const u32 cpuid_length) +{ + u8 low[cpuid_length / 2], high[cpuid_length / 2]; + char cpuid_str[cpuid_length * 2 + 1]; + u64 serialno; + char serialno_str[17]; + const char *oldid; + int i; + + memset(cpuid_str, 0, sizeof(cpuid_str)); + for (i = 0; i < cpuid_length; i++) + sprintf(&cpuid_str[i * 2], "%02x", cpuid[i]); + + debug("cpuid: %s\n", cpuid_str); + + /* + * Mix the cpuid bytes using the same rules as in + * ${linux}/drivers/soc/rockchip/rockchip-cpuinfo.c + */ + for (i = 0; i < cpuid_length / 2; i++) { + low[i] = cpuid[1 + (i << 1)]; + high[i] = cpuid[i << 1]; + } + + serialno = crc32_no_comp(0, low, cpuid_length / 2); + serialno |= (u64)crc32_no_comp(serialno, high, cpuid_length / 2) << 32; + snprintf(serialno_str, sizeof(serialno_str), "%016llx", serialno); + + oldid = env_get("cpuid#"); + if (oldid && strcmp(oldid, cpuid_str) != 0) + printf("cpuid: value %s present in env does not match hardware %s\n", + oldid, cpuid_str); + + env_set("cpuid#", cpuid_str); + + /* Only generate serial# when none is set yet */ + if (!env_get("serial#")) + env_set("serial#", serialno_str); + + return 0; +} + +__weak int rockchip_early_misc_init_r(void) +{ + return 0; +} + __weak int misc_init_r(void) { const u32 cpuid_offset = CFG_CPUID_OFFSET; @@ -304,6 +455,10 @@ __weak int misc_init_r(void) u8 cpuid[cpuid_length]; int ret; + ret = rockchip_early_misc_init_r(); + if (ret) + return ret; + ret = rockchip_cpuid_from_efuse(cpuid_offset, cpuid_length, cpuid); if (ret) return ret; @@ -349,3 +504,33 @@ __weak int board_rng_seed(struct abuf *buf) return 0; } #endif + +int mmc_get_env_dev(void) +{ + int devnum; + const char *boot_device; + struct udevice *dev; + +#ifdef CONFIG_SYS_MMC_ENV_DEV + devnum = CONFIG_SYS_MMC_ENV_DEV; +#else + devnum = 0; +#endif + + boot_device = ofnode_read_chosen_string("u-boot,spl-boot-device"); + if (!boot_device) { + debug("%s: /chosen/u-boot,spl-boot-device not set\n", __func__); + return devnum; + } + + debug("%s: booted from %s\n", __func__, boot_device); + + if (uclass_find_device_by_ofnode(UCLASS_MMC, ofnode_path(boot_device), &dev)) { + debug("%s: no U-Boot device found for %s\n", __func__, boot_device); + return devnum; + } + + devnum = dev->seq_; + debug("%s: get MMC env from mmc%d\n", __func__, devnum); + return devnum; +} diff --git a/arch/arm/mach-rockchip/boot_mode.c b/arch/arm/mach-rockchip/boot_mode.c index eb8f65ae4e9..f9be396aa55 100644 --- a/arch/arm/mach-rockchip/boot_mode.c +++ b/arch/arm/mach-rockchip/boot_mode.c @@ -40,6 +40,7 @@ void set_back_to_bootrom_dnl_flag(void) __weak int rockchip_dnl_key_pressed(void) { +#if CONFIG_IS_ENABLED(ADC) unsigned int val; struct udevice *dev; struct uclass *uc; @@ -69,6 +70,9 @@ __weak int rockchip_dnl_key_pressed(void) return true; else return false; +#else + return false; +#endif } void rockchip_dnl_mode_check(void) diff --git a/arch/arm/mach-rockchip/cpu-info.c b/arch/arm/mach-rockchip/cpu-info.c index dac24910e0c..a62ff53c6a0 100644 --- a/arch/arm/mach-rockchip/cpu-info.c +++ b/arch/arm/mach-rockchip/cpu-info.c @@ -7,7 +7,6 @@ #include <common.h> #include <env.h> #include <init.h> -#include <asm/io.h> #include <asm/arch-rockchip/clock.h> #include <asm/arch-rockchip/cru.h> #include <asm/arch-rockchip/hardware.h> diff --git a/arch/arm/mach-rockchip/misc.c b/arch/arm/mach-rockchip/misc.c deleted file mode 100644 index 7d03f0c2b67..00000000000 --- a/arch/arm/mach-rockchip/misc.c +++ /dev/null @@ -1,135 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * RK3399: Architecture common definitions - * - * Copyright (C) 2019 Collabora Inc - https://www.collabora.com/ - * Rohan Garg <rohan.garg@collabora.com> - * - * Based on puma-rk3399.c: - * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH - */ - -#include <common.h> -#include <env.h> -#include <dm.h> -#include <hash.h> -#include <log.h> -#include <dm/uclass-internal.h> -#include <misc.h> -#include <u-boot/crc.h> -#include <u-boot/sha256.h> - -#include <asm/arch-rockchip/misc.h> - -int rockchip_setup_macaddr(void) -{ -#if CONFIG_IS_ENABLED(HASH) && CONFIG_IS_ENABLED(SHA256) - int ret; - const char *cpuid = env_get("cpuid#"); - u8 hash[SHA256_SUM_LEN]; - int size = sizeof(hash); - u8 mac_addr[6]; - - /* Only generate a MAC address, if none is set in the environment */ - if (env_get("ethaddr")) - return 0; - - if (!cpuid) { - debug("%s: could not retrieve 'cpuid#'\n", __func__); - return -1; - } - - ret = hash_block("sha256", (void *)cpuid, strlen(cpuid), hash, &size); - if (ret) { - debug("%s: failed to calculate SHA256\n", __func__); - return -1; - } - - /* Copy 6 bytes of the hash to base the MAC address on */ - memcpy(mac_addr, hash, 6); - - /* Make this a valid MAC address and set it */ - mac_addr[0] &= 0xfe; /* clear multicast bit */ - mac_addr[0] |= 0x02; /* set local assignment bit (IEEE802) */ - eth_env_set_enetaddr("ethaddr", mac_addr); - - /* Make a valid MAC address for ethernet1 */ - mac_addr[5] ^= 0x01; - eth_env_set_enetaddr("eth1addr", mac_addr); -#endif - return 0; -} - -int rockchip_cpuid_from_efuse(const u32 cpuid_offset, - const u32 cpuid_length, - u8 *cpuid) -{ -#if IS_ENABLED(CONFIG_ROCKCHIP_EFUSE) || IS_ENABLED(CONFIG_ROCKCHIP_OTP) - struct udevice *dev; - int ret; - - /* retrieve the device */ -#if IS_ENABLED(CONFIG_ROCKCHIP_EFUSE) - ret = uclass_get_device_by_driver(UCLASS_MISC, - DM_DRIVER_GET(rockchip_efuse), &dev); -#elif IS_ENABLED(CONFIG_ROCKCHIP_OTP) - ret = uclass_get_device_by_driver(UCLASS_MISC, - DM_DRIVER_GET(rockchip_otp), &dev); -#endif - if (ret) { - debug("%s: could not find efuse device\n", __func__); - return -1; - } - - /* read the cpu_id range from the efuses */ - ret = misc_read(dev, cpuid_offset, cpuid, cpuid_length); - if (ret < 0) { - debug("%s: reading cpuid from the efuses failed\n", - __func__); - return -1; - } -#endif - return 0; -} - -int rockchip_cpuid_set(const u8 *cpuid, const u32 cpuid_length) -{ - u8 low[cpuid_length / 2], high[cpuid_length / 2]; - char cpuid_str[cpuid_length * 2 + 1]; - u64 serialno; - char serialno_str[17]; - const char *oldid; - int i; - - memset(cpuid_str, 0, sizeof(cpuid_str)); - for (i = 0; i < 16; i++) - sprintf(&cpuid_str[i * 2], "%02x", cpuid[i]); - - debug("cpuid: %s\n", cpuid_str); - - /* - * Mix the cpuid bytes using the same rules as in - * ${linux}/drivers/soc/rockchip/rockchip-cpuinfo.c - */ - for (i = 0; i < 8; i++) { - low[i] = cpuid[1 + (i << 1)]; - high[i] = cpuid[i << 1]; - } - - serialno = crc32_no_comp(0, low, 8); - serialno |= (u64)crc32_no_comp(serialno, high, 8) << 32; - snprintf(serialno_str, sizeof(serialno_str), "%016llx", serialno); - - oldid = env_get("cpuid#"); - if (oldid && strcmp(oldid, cpuid_str) != 0) - printf("cpuid: value %s present in env does not match hardware %s\n", - oldid, cpuid_str); - - env_set("cpuid#", cpuid_str); - - /* Only generate serial# when none is set yet */ - if (!env_get("serial#")) - env_set("serial#", serialno_str); - - return 0; -} diff --git a/arch/arm/mach-rockchip/px30/px30.c b/arch/arm/mach-rockchip/px30/px30.c index fc7456e680c..b4f655fa4b3 100644 --- a/arch/arm/mach-rockchip/px30/px30.c +++ b/arch/arm/mach-rockchip/px30/px30.c @@ -9,7 +9,6 @@ #include <init.h> #include <spl.h> #include <asm/armv8/mmu.h> -#include <asm/io.h> #include <asm/arch-rockchip/bootrom.h> #include <asm/arch-rockchip/grf_px30.h> #include <asm/arch-rockchip/hardware.h> diff --git a/arch/arm/mach-rockchip/rk3036/rk3036.c b/arch/arm/mach-rockchip/rk3036/rk3036.c index 0a072cf03a8..e8130abdd77 100644 --- a/arch/arm/mach-rockchip/rk3036/rk3036.c +++ b/arch/arm/mach-rockchip/rk3036/rk3036.c @@ -6,7 +6,6 @@ #include <common.h> #include <init.h> #include <asm/global_data.h> -#include <asm/io.h> #include <asm/arch-rockchip/grf_rk3036.h> #include <asm/arch-rockchip/hardware.h> #include <asm/arch-rockchip/sdram_rk3036.h> diff --git a/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c b/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c index fcae65b2e5a..07cd29a33e6 100644 --- a/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c +++ b/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c @@ -4,7 +4,6 @@ */ #include <common.h> #include <init.h> -#include <asm/io.h> #include <asm/types.h> #include <asm/arch-rockchip/cru_rk3036.h> #include <asm/arch-rockchip/grf_rk3036.h> diff --git a/arch/arm/mach-rockchip/rk3066/rk3066.c b/arch/arm/mach-rockchip/rk3066/rk3066.c index 78c7d894f90..9a95ff85041 100644 --- a/arch/arm/mach-rockchip/rk3066/rk3066.c +++ b/arch/arm/mach-rockchip/rk3066/rk3066.c @@ -4,9 +4,9 @@ */ #include <common.h> -#include <asm/io.h> #include <asm/arch-rockchip/bootrom.h> #include <asm/arch-rockchip/grf_rk3066.h> +#include <asm/arch-rockchip/hardware.h> #define GRF_BASE 0x20008000 diff --git a/arch/arm/mach-rockchip/rk3188/rk3188.c b/arch/arm/mach-rockchip/rk3188/rk3188.c index c807221f33f..ffdcaa49a1e 100644 --- a/arch/arm/mach-rockchip/rk3188/rk3188.c +++ b/arch/arm/mach-rockchip/rk3188/rk3188.c @@ -10,7 +10,6 @@ #include <log.h> #include <syscon.h> #include <asm/global_data.h> -#include <asm/io.h> #include <asm/arch-rockchip/bootrom.h> #include <asm/arch-rockchip/clock.h> #include <asm/arch-rockchip/grf_rk3188.h> diff --git a/arch/arm/mach-rockchip/rk322x/rk322x.c b/arch/arm/mach-rockchip/rk322x/rk322x.c index a304795fec6..712c0524266 100644 --- a/arch/arm/mach-rockchip/rk322x/rk322x.c +++ b/arch/arm/mach-rockchip/rk322x/rk322x.c @@ -3,7 +3,6 @@ * (C) Copyright 2019 Rockchip Electronics Co., Ltd */ #include <init.h> -#include <asm/io.h> #include <asm/arch-rockchip/bootrom.h> #include <asm/arch-rockchip/grf_rk322x.h> #include <asm/arch-rockchip/hardware.h> diff --git a/arch/arm/mach-rockchip/rk3288/rk3288.c b/arch/arm/mach-rockchip/rk3288/rk3288.c index d9f782e342b..c77c56c1dab 100644 --- a/arch/arm/mach-rockchip/rk3288/rk3288.c +++ b/arch/arm/mach-rockchip/rk3288/rk3288.c @@ -11,7 +11,6 @@ #include <malloc.h> #include <asm/armv7.h> #include <asm/global_data.h> -#include <asm/io.h> #include <asm/arch-rockchip/bootrom.h> #include <asm/arch-rockchip/clock.h> #include <asm/arch-rockchip/cpu_rk3288.h> diff --git a/arch/arm/mach-rockchip/rk3308/Kconfig b/arch/arm/mach-rockchip/rk3308/Kconfig index 194353e4cd9..749e9995d91 100644 --- a/arch/arm/mach-rockchip/rk3308/Kconfig +++ b/arch/arm/mach-rockchip/rk3308/Kconfig @@ -17,8 +17,11 @@ config ROCKCHIP_STIMER_BASE config SYS_SOC default "rk3308" -config SYS_MALLOC_F_LEN - default 0x400 +config ROCKCHIP_COMMON_STACK_ADDR + default y + +config TEXT_BASE + default 0x00600000 config SPL_SERIAL default y diff --git a/arch/arm/mach-rockchip/rk3308/rk3308.c b/arch/arm/mach-rockchip/rk3308/rk3308.c index 6f121bf1304..27a748327e3 100644 --- a/arch/arm/mach-rockchip/rk3308/rk3308.c +++ b/arch/arm/mach-rockchip/rk3308/rk3308.c @@ -5,7 +5,6 @@ #include <common.h> #include <init.h> #include <malloc.h> -#include <asm/io.h> #include <asm/arch/grf_rk3308.h> #include <asm/arch-rockchip/bootrom.h> #include <asm/arch-rockchip/hardware.h> diff --git a/arch/arm/mach-rockchip/rk3328/Kconfig b/arch/arm/mach-rockchip/rk3328/Kconfig index d5cb649ae6b..70770da5fdf 100644 --- a/arch/arm/mach-rockchip/rk3328/Kconfig +++ b/arch/arm/mach-rockchip/rk3328/Kconfig @@ -21,13 +21,7 @@ config ROCKCHIP_STIMER_BASE config SYS_SOC default "rk3328" -config SYS_MALLOC_F_LEN - default 0x2000 - -config SPL_LIBCOMMON_SUPPORT - default y - -config SPL_LIBGENERIC_SUPPORT +config ROCKCHIP_COMMON_STACK_ADDR default y config TPL_LDSCRIPT @@ -39,6 +33,9 @@ config TPL_TEXT_BASE config TPL_STACK default 0xff098000 +config TPL_SYS_MALLOC_F_LEN + default 0x800 + source "board/rockchip/evb_rk3328/Kconfig" endif diff --git a/arch/arm/mach-rockchip/rk3328/rk3328.c b/arch/arm/mach-rockchip/rk3328/rk3328.c index b591d38fe41..ca3fa81e127 100644 --- a/arch/arm/mach-rockchip/rk3328/rk3328.c +++ b/arch/arm/mach-rockchip/rk3328/rk3328.c @@ -10,7 +10,6 @@ #include <asm/arch-rockchip/grf_rk3328.h> #include <asm/arch-rockchip/uart.h> #include <asm/armv8/mmu.h> -#include <asm/io.h> #define CRU_BASE 0xFF440000 #define GRF_BASE 0xFF100000 @@ -36,6 +35,7 @@ const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = { [BROM_BOOTSOURCE_EMMC] = "/mmc@ff520000", + [BROM_BOOTSOURCE_SPINOR] = "/spi@ff190000/flash@0", [BROM_BOOTSOURCE_SD] = "/mmc@ff500000", }; diff --git a/arch/arm/mach-rockchip/rk3368/rk3368.c b/arch/arm/mach-rockchip/rk3368/rk3368.c index d009b8758e5..651ba109020 100644 --- a/arch/arm/mach-rockchip/rk3368/rk3368.c +++ b/arch/arm/mach-rockchip/rk3368/rk3368.c @@ -8,7 +8,6 @@ #include <init.h> #include <syscon.h> #include <asm/armv8/mmu.h> -#include <asm/io.h> #include <asm/arch-rockchip/bootrom.h> #include <asm/arch-rockchip/clock.h> #include <asm/arch-rockchip/cru_rk3368.h> diff --git a/arch/arm/mach-rockchip/rk3399/Kconfig b/arch/arm/mach-rockchip/rk3399/Kconfig index d01063ac98b..04a84e2f6a0 100644 --- a/arch/arm/mach-rockchip/rk3399/Kconfig +++ b/arch/arm/mach-rockchip/rk3399/Kconfig @@ -89,6 +89,11 @@ config TARGET_ROCK960_RK3399 * 2x USB 3.0 type A, 2x USB 2.0 type A (host mode only), 1x USB 3.0 type C OTG +config TARGET_ROCKPI4_RK3399 + bool "Radxa ROCK Pi 4 board" + help + Support for ROCK Pi 4 board family by Radxa. + config TARGET_ROCKPRO64_RK3399 bool "Pine64 Rockpro64 board" help @@ -138,8 +143,11 @@ config ROCKCHIP_STIMER_BASE config SYS_SOC default "rk3399" +config ROCKCHIP_COMMON_STACK_ADDR + default y + config SYS_MALLOC_F_LEN - default 0x4000 + default 0x4000 if !SPL_SHARES_INIT_SP_ADDR config SPL_LIBCOMMON_SUPPORT default y @@ -157,7 +165,7 @@ config TPL_TEXT_BASE default 0xff8c2000 config SPL_STACK_R_ADDR - default 0x04000000 + default 0x04000000 if !SPL_SHARES_INIT_SP_ADDR if BOOTCOUNT_LIMIT @@ -174,6 +182,7 @@ source "board/google/gru/Kconfig" source "board/pine64/pinebook-pro-rk3399/Kconfig" source "board/pine64/pinephone-pro-rk3399/Kconfig" source "board/pine64/rockpro64_rk3399/Kconfig" +source "board/radxa/rockpi4-rk3399/Kconfig" source "board/rockchip/evb_rk3399/Kconfig" source "board/theobroma-systems/puma_rk3399/Kconfig" source "board/vamrs/rock960_rk3399/Kconfig" diff --git a/arch/arm/mach-rockchip/rk3399/rk3399.c b/arch/arm/mach-rockchip/rk3399/rk3399.c index a1aa0e3e8b5..7fa1d7c7b7a 100644 --- a/arch/arm/mach-rockchip/rk3399/rk3399.c +++ b/arch/arm/mach-rockchip/rk3399/rk3399.c @@ -11,7 +11,6 @@ #include <spl_gpio.h> #include <syscon.h> #include <asm/armv8/mmu.h> -#include <asm/io.h> #include <asm/arch-rockchip/bootrom.h> #include <asm/arch-rockchip/clock.h> #include <asm/arch-rockchip/cru.h> diff --git a/arch/arm/mach-rockchip/rk3568/Kconfig b/arch/arm/mach-rockchip/rk3568/Kconfig index baa51349f4b..af537d912a6 100644 --- a/arch/arm/mach-rockchip/rk3568/Kconfig +++ b/arch/arm/mach-rockchip/rk3568/Kconfig @@ -38,8 +38,11 @@ config ROCKCHIP_STIMER_BASE config SYS_SOC default "rk3568" -config SYS_MALLOC_F_LEN - default 0x20000 +config ROCKCHIP_COMMON_STACK_ADDR + default y + +config TEXT_BASE + default 0x00a00000 source "board/rockchip/evb_rk3568/Kconfig" source "board/anbernic/rgxx3_rk3566/Kconfig" diff --git a/arch/arm/mach-rockchip/rk3568/rk3568.c b/arch/arm/mach-rockchip/rk3568/rk3568.c index 69ef19cc85a..b30ea04f737 100644 --- a/arch/arm/mach-rockchip/rk3568/rk3568.c +++ b/arch/arm/mach-rockchip/rk3568/rk3568.c @@ -6,7 +6,6 @@ #include <common.h> #include <dm.h> #include <asm/armv8/mmu.h> -#include <asm/io.h> #include <asm/arch-rockchip/bootrom.h> #include <asm/arch-rockchip/grf_rk3568.h> #include <asm/arch-rockchip/hardware.h> diff --git a/arch/arm/mach-rockchip/rk3588/Kconfig b/arch/arm/mach-rockchip/rk3588/Kconfig index a2193fbd41f..d7e4af31f24 100644 --- a/arch/arm/mach-rockchip/rk3588/Kconfig +++ b/arch/arm/mach-rockchip/rk3588/Kconfig @@ -6,6 +6,33 @@ config TARGET_EVB_RK3588 help RK3588 EVB is a evaluation board for Rockchp RK3588. +config TARGET_JAGUAR_RK3588 + bool "Theobroma Systems SBC-RK3588-AMR (Jaguar)" + select BOARD_LATE_INIT + help + The SBC-RK3588-AMR is a Single Board Computer designed by + Theobroma Systems for autonomous mobile robots. + + It provides the following features: + * up to 32GB LDDR4 + * up to 128GB on-module eMMC (with 8-bit 1.8V interface) + * SD card + * Gigabit Ethernet + * 1x USB-A 2.0 host + * PCIe M.2 2230 Key M (Gen 2 1-lane) for WiFi+BT + * PCIe M.2 2280 Key M (Gen 3 4-lane) for NVMe + * CAN + * RS485 UART + * 2x USB Type-C 3.1 host/device + * HDMI output + * 2x camera connectors (MIPI-CSI 2-lane + I2C/SPI for IMUs + GPIOs) + * EEPROM + * Secure Element + * ATtiny companion controller implementing: + - low-power RTC functionality (ISL1208 emulation) + - fan controller (AMC6821 emulation) + * 80-pin Mezzanine connector + config TARGET_NANOPCT6_RK3588 bool "FriendlyElec NanoPC-T6 RK3588 board" select BOARD_LATE_INIT @@ -155,6 +182,30 @@ config TARGET_TURINGRK1_RK3588 Gigabit Ethernet Size: 69.6mm x 45mm (260-pin SO-DIMM connector) +config TARGET_TOYBRICK_RK3588 + bool "Toybrick TB-RK3588X board" + select BOARD_LATE_INIT + help + Rockchip Toybrick TB-RK3588X is a Rockchip RK3588 based development board. + TB-RK3588X adopts core board and mainboard design. The core board is connected + with the mainboard through the MXM314Pin standard interface, which can form + a complete industry development board. + + Specifications: + + Rockchip RK3588 SoC + 4x ARM Cortex-A76, 4x ARM Cortex-A55 + 8/16GB Memory LPDDR4x + Mali G610MC4 GPU + 2× MIPI-CSI0 Connector + 1x 2Lanes PCIe3.0 Connector + 1x SATA3.0 Connector + 32GB eMMC Module + 2x USB2.0, 2x USB3.0 + 1x HDMI Output, 1x HDMI Input + 2x Ethernet Port + + config ROCKCHIP_BOOT_MODE_REG default 0xfd588080 @@ -164,15 +215,20 @@ config ROCKCHIP_STIMER_BASE config SYS_SOC default "rk3588" -config SYS_MALLOC_F_LEN - default 0x80000 +config ROCKCHIP_COMMON_STACK_ADDR + default y + +config TEXT_BASE + default 0x00a00000 source board/edgeble/neural-compute-module-6/Kconfig source board/friendlyelec/nanopc-t6-rk3588/Kconfig source board/pine64/quartzpro64-rk3588/Kconfig source board/turing/turing-rk1-rk3588/Kconfig -source board/rockchip/evb_rk3588/Kconfig source board/radxa/rock5a-rk3588s/Kconfig source board/radxa/rock5b-rk3588/Kconfig +source board/rockchip/evb_rk3588/Kconfig +source board/rockchip/toybrick_rk3588/Kconfig +source board/theobroma-systems/jaguar_rk3588/Kconfig endif diff --git a/arch/arm/mach-rockchip/rk3588/rk3588.c b/arch/arm/mach-rockchip/rk3588/rk3588.c index 38e95a6e2b2..eb65dafe3a2 100644 --- a/arch/arm/mach-rockchip/rk3588/rk3588.c +++ b/arch/arm/mach-rockchip/rk3588/rk3588.c @@ -7,8 +7,8 @@ #include <common.h> #include <spl.h> #include <asm/armv8/mmu.h> -#include <asm/io.h> #include <asm/arch-rockchip/bootrom.h> +#include <asm/arch-rockchip/grf_rk3588.h> #include <asm/arch-rockchip/hardware.h> #include <asm/arch-rockchip/ioc_rk3588.h> @@ -25,16 +25,14 @@ #define FW_SYSM_MST26_REG 0xa8 #define FW_SYSM_MST27_REG 0xac -#define PMU1_IOC_BASE 0xfd5f0000 -#define PMU2_IOC_BASE 0xfd5f4000 - -#define BUS_IOC_BASE 0xfd5f8000 #define BUS_IOC_GPIO2A_IOMUX_SEL_L 0x40 #define BUS_IOC_GPIO2B_IOMUX_SEL_L 0x48 #define BUS_IOC_GPIO2D_IOMUX_SEL_L 0x58 #define BUS_IOC_GPIO2D_IOMUX_SEL_H 0x5c #define BUS_IOC_GPIO3A_IOMUX_SEL_L 0x60 +#define SYS_GRF_FORCE_JTAG BIT(14) + /** * Boot-device identifiers used by the BROM on RK3588 when device is booted * from SPI flash. IOMUX used for SPI flash affect the value used by the BROM @@ -134,6 +132,9 @@ void rockchip_stimer_init(void) int arch_cpu_init(void) { #ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_ROCKCHIP_DISABLE_FORCE_JTAG + static struct rk3588_sysgrf * const sys_grf = (void *)SYS_GRF_BASE; +#endif int secure_reg; /* Set the SDMMC eMMC crypto_ns FSPI access secure area */ @@ -168,6 +169,11 @@ int arch_cpu_init(void) secure_reg = readl(FIREWALL_SYSMEM_BASE + FW_SYSM_MST27_REG); secure_reg &= 0xffff0000; writel(secure_reg, FIREWALL_SYSMEM_BASE + FW_SYSM_MST27_REG); + +#ifdef CONFIG_ROCKCHIP_DISABLE_FORCE_JTAG + /* Disable JTAG exposed on SDMMC */ + rk_clrreg(&sys_grf->soc_con[6], SYS_GRF_FORCE_JTAG); +#endif #endif return 0; diff --git a/arch/arm/mach-rockchip/rv1126/rv1126.c b/arch/arm/mach-rockchip/rv1126/rv1126.c index b9b898756f7..8589c46f10a 100644 --- a/arch/arm/mach-rockchip/rv1126/rv1126.c +++ b/arch/arm/mach-rockchip/rv1126/rv1126.c @@ -5,7 +5,6 @@ */ #include <common.h> -#include <asm/io.h> #include <asm/arch-rockchip/bootrom.h> #include <asm/arch-rockchip/hardware.h> #include <asm/arch-rockchip/grf_rv1126.h> diff --git a/arch/arm/mach-rockchip/spl-boot-order.c b/arch/arm/mach-rockchip/spl-boot-order.c index 2c39a215c10..79c856d2a0a 100644 --- a/arch/arm/mach-rockchip/spl-boot-order.c +++ b/arch/arm/mach-rockchip/spl-boot-order.c @@ -65,9 +65,6 @@ static int spl_node_to_boot_device(int node) default: return -ENOSYS; } - } else if (!uclass_get_device_by_of_offset(UCLASS_SPI_FLASH, node, - &parent)) { - return BOOT_DEVICE_SPI; } /* diff --git a/arch/arm/mach-rockchip/spl.c b/arch/arm/mach-rockchip/spl.c index 87280e2ba7c..1586a093fc3 100644 --- a/arch/arm/mach-rockchip/spl.c +++ b/arch/arm/mach-rockchip/spl.c @@ -3,7 +3,7 @@ * (C) Copyright 2019 Rockchip Electronics Co., Ltd */ -#include <common.h> +#include <cpu_func.h> #include <debug_uart.h> #include <dm.h> #include <hang.h> @@ -136,6 +136,20 @@ void board_init_f(ulong dummy) } gd->ram_top = gd->ram_base + get_effective_memsize(); gd->ram_top = board_get_usable_ram_top(gd->ram_size); + + if (IS_ENABLED(CONFIG_ARM64) && !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) { + gd->relocaddr = gd->ram_top; + arch_reserve_mmu(); + enable_caches(); + } #endif preloader_console_init(); } + +void spl_board_prepare_for_boot(void) +{ + if (!IS_ENABLED(CONFIG_ARM64) || CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) + return; + + cleanup_before_linux(); +} |