diff options
Diffstat (limited to 'arch')
87 files changed, 1246 insertions, 1040 deletions
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 963a77229db..eeb0839afe3 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -714,7 +714,8 @@ dtb-$(CONFIG_MACH_SUN50I_H6) += \ sun50i-h6-tanix-tx6.dtb \ sun50i-h6-tanix-tx6-mini.dtb dtb-$(CONFIG_MACH_SUN50I_H616) += \ - sun50i-h616-orangepi-zero2.dtb + sun50i-h616-orangepi-zero2.dtb \ + sun50i-h616-x96-mate.dtb dtb-$(CONFIG_MACH_SUN50I) += \ sun50i-a64-amarula-relic.dtb \ sun50i-a64-bananapi-m64.dtb \ @@ -1206,7 +1207,8 @@ dtb-$(CONFIG_STM32MP15x) += \ stm32mp15xx-dhcom-pdk2.dtb \ stm32mp15xx-dhcom-picoitx.dtb \ stm32mp15xx-dhcor-avenger96.dtb \ - stm32mp15xx-dhcor-drc-compact.dtb + stm32mp15xx-dhcor-drc-compact.dtb \ + stm32mp15xx-dhcor-testbench.dtb dtb-$(CONFIG_SOC_K3_AM654) += \ k3-am654-base-board.dtb \ diff --git a/arch/arm/dts/k3-am64-evm-ddr4-1600MTs.dtsi b/arch/arm/dts/k3-am64-evm-ddr4-1600MTs.dtsi index 9a008df7506..491412119b1 100644 --- a/arch/arm/dts/k3-am64-evm-ddr4-1600MTs.dtsi +++ b/arch/arm/dts/k3-am64-evm-ddr4-1600MTs.dtsi @@ -1,8 +1,10 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * This file was generated by the AM64x_DDR4_RegConfig_Tool, Revision: 0.6.0 - * This file was generated on Oct 26 2020 - * DDR4 Frequency = 800MHz (1600MTs) + * This file was generated with the + * AM64x SysConfig DDR Subsystem Register Configuration Tool v0.08.40 + * Wed Feb 02 2022 16:24:50 GMT-0600 (Central Standard Time) + * DDR Type: DDR4 + * Frequency = 800MHz (1600MTs) * Density: 16Gb * Number of Ranks: 1 */ @@ -49,11 +51,11 @@ #define DDRSS_CTL_35_DATA 0x00000000 #define DDRSS_CTL_36_DATA 0x00000000 #define DDRSS_CTL_37_DATA 0x00000000 -#define DDRSS_CTL_38_DATA 0x04000918 +#define DDRSS_CTL_38_DATA 0x0400091C #define DDRSS_CTL_39_DATA 0x1C1C1C1C -#define DDRSS_CTL_40_DATA 0x04000918 +#define DDRSS_CTL_40_DATA 0x0400091C #define DDRSS_CTL_41_DATA 0x1C1C1C1C -#define DDRSS_CTL_42_DATA 0x04000918 +#define DDRSS_CTL_42_DATA 0x0400091C #define DDRSS_CTL_43_DATA 0x1C1C1C1C #define DDRSS_CTL_44_DATA 0x05050404 #define DDRSS_CTL_45_DATA 0x00002706 @@ -215,22 +217,22 @@ #define DDRSS_CTL_201_DATA 0x00000000 #define DDRSS_CTL_202_DATA 0x00000000 #define DDRSS_CTL_203_DATA 0x00000000 -#define DDRSS_CTL_204_DATA 0x00041400 +#define DDRSS_CTL_204_DATA 0x00042400 #define DDRSS_CTL_205_DATA 0x00000301 #define DDRSS_CTL_206_DATA 0x00000000 -#define DDRSS_CTL_207_DATA 0x00000414 +#define DDRSS_CTL_207_DATA 0x00000424 #define DDRSS_CTL_208_DATA 0x00000301 #define DDRSS_CTL_209_DATA 0x00000000 -#define DDRSS_CTL_210_DATA 0x00000414 +#define DDRSS_CTL_210_DATA 0x00000424 #define DDRSS_CTL_211_DATA 0x00000301 #define DDRSS_CTL_212_DATA 0x00000000 -#define DDRSS_CTL_213_DATA 0x00000414 +#define DDRSS_CTL_213_DATA 0x00000424 #define DDRSS_CTL_214_DATA 0x00000301 #define DDRSS_CTL_215_DATA 0x00000000 -#define DDRSS_CTL_216_DATA 0x00000414 +#define DDRSS_CTL_216_DATA 0x00000424 #define DDRSS_CTL_217_DATA 0x00000301 #define DDRSS_CTL_218_DATA 0x00000000 -#define DDRSS_CTL_219_DATA 0x00000414 +#define DDRSS_CTL_219_DATA 0x00000424 #define DDRSS_CTL_220_DATA 0x00000301 #define DDRSS_CTL_221_DATA 0x00000000 #define DDRSS_CTL_222_DATA 0x00000000 @@ -247,12 +249,12 @@ #define DDRSS_CTL_233_DATA 0x00000000 #define DDRSS_CTL_234_DATA 0x00000000 #define DDRSS_CTL_235_DATA 0x00000000 -#define DDRSS_CTL_236_DATA 0x00000401 -#define DDRSS_CTL_237_DATA 0x00000401 -#define DDRSS_CTL_238_DATA 0x00000401 -#define DDRSS_CTL_239_DATA 0x00000401 -#define DDRSS_CTL_240_DATA 0x00000401 -#define DDRSS_CTL_241_DATA 0x00000401 +#define DDRSS_CTL_236_DATA 0x00001401 +#define DDRSS_CTL_237_DATA 0x00001401 +#define DDRSS_CTL_238_DATA 0x00001401 +#define DDRSS_CTL_239_DATA 0x00001401 +#define DDRSS_CTL_240_DATA 0x00001401 +#define DDRSS_CTL_241_DATA 0x00001401 #define DDRSS_CTL_242_DATA 0x00000493 #define DDRSS_CTL_243_DATA 0x00000493 #define DDRSS_CTL_244_DATA 0x00000493 @@ -341,9 +343,9 @@ #define DDRSS_CTL_327_DATA 0x00000C01 #define DDRSS_CTL_328_DATA 0x00000000 #define DDRSS_CTL_329_DATA 0x00000000 -#define DDRSS_CTL_330_DATA 0x01000000 +#define DDRSS_CTL_330_DATA 0x00000000 #define DDRSS_CTL_331_DATA 0x01000000 -#define DDRSS_CTL_332_DATA 0x00000000 +#define DDRSS_CTL_332_DATA 0x00000100 #define DDRSS_CTL_333_DATA 0x00010000 #define DDRSS_CTL_334_DATA 0x00000000 #define DDRSS_CTL_335_DATA 0x00000000 @@ -386,8 +388,8 @@ #define DDRSS_CTL_372_DATA 0x06060C06 #define DDRSS_CTL_373_DATA 0x00010101 #define DDRSS_CTL_374_DATA 0x02000000 -#define DDRSS_CTL_375_DATA 0x03020101 -#define DDRSS_CTL_376_DATA 0x00000303 +#define DDRSS_CTL_375_DATA 0x05020101 +#define DDRSS_CTL_376_DATA 0x00000505 #define DDRSS_CTL_377_DATA 0x02020200 #define DDRSS_CTL_378_DATA 0x02020202 #define DDRSS_CTL_379_DATA 0x02020202 @@ -403,7 +405,7 @@ #define DDRSS_CTL_389_DATA 0x00000200 #define DDRSS_CTL_390_DATA 0x0000DB60 #define DDRSS_CTL_391_DATA 0x0001E780 -#define DDRSS_CTL_392_DATA 0x0A0B0302 +#define DDRSS_CTL_392_DATA 0x0C0D0302 #define DDRSS_CTL_393_DATA 0x001E090A #define DDRSS_CTL_394_DATA 0x000030C0 #define DDRSS_CTL_395_DATA 0x00000200 @@ -412,7 +414,7 @@ #define DDRSS_CTL_398_DATA 0x00000200 #define DDRSS_CTL_399_DATA 0x0000DB60 #define DDRSS_CTL_400_DATA 0x0001E780 -#define DDRSS_CTL_401_DATA 0x0A0B0302 +#define DDRSS_CTL_401_DATA 0x0C0D0302 #define DDRSS_CTL_402_DATA 0x001E090A #define DDRSS_CTL_403_DATA 0x000030C0 #define DDRSS_CTL_404_DATA 0x00000200 @@ -421,7 +423,7 @@ #define DDRSS_CTL_407_DATA 0x00000200 #define DDRSS_CTL_408_DATA 0x0000DB60 #define DDRSS_CTL_409_DATA 0x0001E780 -#define DDRSS_CTL_410_DATA 0x0A0B0302 +#define DDRSS_CTL_410_DATA 0x0C0D0302 #define DDRSS_CTL_411_DATA 0x0000090A #define DDRSS_CTL_412_DATA 0x00000000 #define DDRSS_CTL_413_DATA 0x0302000A @@ -601,14 +603,14 @@ #define DDRSS_PI_164_DATA 0x00007800 #define DDRSS_PI_165_DATA 0x00780078 #define DDRSS_PI_166_DATA 0x00141414 -#define DDRSS_PI_167_DATA 0x00000038 -#define DDRSS_PI_168_DATA 0x00000038 -#define DDRSS_PI_169_DATA 0x00040038 +#define DDRSS_PI_167_DATA 0x0000003A +#define DDRSS_PI_168_DATA 0x0000003A +#define DDRSS_PI_169_DATA 0x0004003A #define DDRSS_PI_170_DATA 0x04000400 #define DDRSS_PI_171_DATA 0xC8040009 -#define DDRSS_PI_172_DATA 0x04000918 -#define DDRSS_PI_173_DATA 0x000918C8 -#define DDRSS_PI_174_DATA 0x0018C804 +#define DDRSS_PI_172_DATA 0x0400091C +#define DDRSS_PI_173_DATA 0x00091CC8 +#define DDRSS_PI_174_DATA 0x001CC804 #define DDRSS_PI_175_DATA 0x00000118 #define DDRSS_PI_176_DATA 0x00001860 #define DDRSS_PI_177_DATA 0x00000118 @@ -621,14 +623,14 @@ #define DDRSS_PI_184_DATA 0x010C010C #define DDRSS_PI_185_DATA 0x0000010C #define DDRSS_PI_186_DATA 0x00000000 -#define DDRSS_PI_187_DATA 0x03000000 -#define DDRSS_PI_188_DATA 0x01010303 +#define DDRSS_PI_187_DATA 0x05000000 +#define DDRSS_PI_188_DATA 0x01010505 #define DDRSS_PI_189_DATA 0x01010101 #define DDRSS_PI_190_DATA 0x00181818 #define DDRSS_PI_191_DATA 0x00000000 #define DDRSS_PI_192_DATA 0x00000000 -#define DDRSS_PI_193_DATA 0x0B000000 -#define DDRSS_PI_194_DATA 0x0A0A0B0B +#define DDRSS_PI_193_DATA 0x0D000000 +#define DDRSS_PI_194_DATA 0x0A0A0D0D #define DDRSS_PI_195_DATA 0x0303030A #define DDRSS_PI_196_DATA 0x00000000 #define DDRSS_PI_197_DATA 0x00000000 @@ -656,15 +658,15 @@ #define DDRSS_PI_219_DATA 0x001600C8 #define DDRSS_PI_220_DATA 0x010100C8 #define DDRSS_PI_221_DATA 0x00001B01 -#define DDRSS_PI_222_DATA 0x1F0F0051 -#define DDRSS_PI_223_DATA 0x03000001 -#define DDRSS_PI_224_DATA 0x001B0A0B -#define DDRSS_PI_225_DATA 0x1F0F0051 -#define DDRSS_PI_226_DATA 0x03000001 -#define DDRSS_PI_227_DATA 0x001B0A0B -#define DDRSS_PI_228_DATA 0x1F0F0051 -#define DDRSS_PI_229_DATA 0x03000001 -#define DDRSS_PI_230_DATA 0x00000A0B +#define DDRSS_PI_222_DATA 0x1F0F0053 +#define DDRSS_PI_223_DATA 0x05000001 +#define DDRSS_PI_224_DATA 0x001B0A0D +#define DDRSS_PI_225_DATA 0x1F0F0053 +#define DDRSS_PI_226_DATA 0x05000001 +#define DDRSS_PI_227_DATA 0x001B0A0D +#define DDRSS_PI_228_DATA 0x1F0F0053 +#define DDRSS_PI_229_DATA 0x05000001 +#define DDRSS_PI_230_DATA 0x00010A0D #define DDRSS_PI_231_DATA 0x0C0B0700 #define DDRSS_PI_232_DATA 0x000D0605 #define DDRSS_PI_233_DATA 0x0000C570 @@ -731,52 +733,52 @@ #define DDRSS_PI_294_DATA 0x01000000 #define DDRSS_PI_295_DATA 0x00020201 #define DDRSS_PI_296_DATA 0x00000000 -#define DDRSS_PI_297_DATA 0x00000414 +#define DDRSS_PI_297_DATA 0x00000424 #define DDRSS_PI_298_DATA 0x00000301 #define DDRSS_PI_299_DATA 0x00000000 #define DDRSS_PI_300_DATA 0x00000000 #define DDRSS_PI_301_DATA 0x00000000 -#define DDRSS_PI_302_DATA 0x00000401 +#define DDRSS_PI_302_DATA 0x00001401 #define DDRSS_PI_303_DATA 0x00000493 #define DDRSS_PI_304_DATA 0x00000000 -#define DDRSS_PI_305_DATA 0x00000414 +#define DDRSS_PI_305_DATA 0x00000424 #define DDRSS_PI_306_DATA 0x00000301 #define DDRSS_PI_307_DATA 0x00000000 #define DDRSS_PI_308_DATA 0x00000000 #define DDRSS_PI_309_DATA 0x00000000 -#define DDRSS_PI_310_DATA 0x00000401 +#define DDRSS_PI_310_DATA 0x00001401 #define DDRSS_PI_311_DATA 0x00000493 #define DDRSS_PI_312_DATA 0x00000000 -#define DDRSS_PI_313_DATA 0x00000414 +#define DDRSS_PI_313_DATA 0x00000424 #define DDRSS_PI_314_DATA 0x00000301 #define DDRSS_PI_315_DATA 0x00000000 #define DDRSS_PI_316_DATA 0x00000000 #define DDRSS_PI_317_DATA 0x00000000 -#define DDRSS_PI_318_DATA 0x00000401 +#define DDRSS_PI_318_DATA 0x00001401 #define DDRSS_PI_319_DATA 0x00000493 #define DDRSS_PI_320_DATA 0x00000000 -#define DDRSS_PI_321_DATA 0x00000414 +#define DDRSS_PI_321_DATA 0x00000424 #define DDRSS_PI_322_DATA 0x00000301 #define DDRSS_PI_323_DATA 0x00000000 #define DDRSS_PI_324_DATA 0x00000000 #define DDRSS_PI_325_DATA 0x00000000 -#define DDRSS_PI_326_DATA 0x00000401 +#define DDRSS_PI_326_DATA 0x00001401 #define DDRSS_PI_327_DATA 0x00000493 #define DDRSS_PI_328_DATA 0x00000000 -#define DDRSS_PI_329_DATA 0x00000414 +#define DDRSS_PI_329_DATA 0x00000424 #define DDRSS_PI_330_DATA 0x00000301 #define DDRSS_PI_331_DATA 0x00000000 #define DDRSS_PI_332_DATA 0x00000000 #define DDRSS_PI_333_DATA 0x00000000 -#define DDRSS_PI_334_DATA 0x00000401 +#define DDRSS_PI_334_DATA 0x00001401 #define DDRSS_PI_335_DATA 0x00000493 #define DDRSS_PI_336_DATA 0x00000000 -#define DDRSS_PI_337_DATA 0x00000414 +#define DDRSS_PI_337_DATA 0x00000424 #define DDRSS_PI_338_DATA 0x00000301 #define DDRSS_PI_339_DATA 0x00000000 #define DDRSS_PI_340_DATA 0x00000000 #define DDRSS_PI_341_DATA 0x00000000 -#define DDRSS_PI_342_DATA 0x00000401 +#define DDRSS_PI_342_DATA 0x00001401 #define DDRSS_PI_343_DATA 0x00000493 #define DDRSS_PI_344_DATA 0x00000000 #define DDRSS_PHY_0_DATA 0x04C00000 @@ -871,7 +873,7 @@ #define DDRSS_PHY_89_DATA 0x31804000 #define DDRSS_PHY_90_DATA 0x04BF0340 #define DDRSS_PHY_91_DATA 0x01008080 -#define DDRSS_PHY_92_DATA 0x04050000 +#define DDRSS_PHY_92_DATA 0x04050001 #define DDRSS_PHY_93_DATA 0x00000504 #define DDRSS_PHY_94_DATA 0x42100010 #define DDRSS_PHY_95_DATA 0x010C053E @@ -1127,7 +1129,7 @@ #define DDRSS_PHY_345_DATA 0x31804000 #define DDRSS_PHY_346_DATA 0x04BF0340 #define DDRSS_PHY_347_DATA 0x01008080 -#define DDRSS_PHY_348_DATA 0x04050000 +#define DDRSS_PHY_348_DATA 0x04050001 #define DDRSS_PHY_349_DATA 0x00000504 #define DDRSS_PHY_350_DATA 0x42100010 #define DDRSS_PHY_351_DATA 0x010C053E @@ -2113,7 +2115,7 @@ #define DDRSS_PHY_1331_DATA 0x00004410 #define DDRSS_PHY_1332_DATA 0x00000000 #define DDRSS_PHY_1333_DATA 0x00000046 -#define DDRSS_PHY_1334_DATA 0x00010000 +#define DDRSS_PHY_1334_DATA 0x00000400 #define DDRSS_PHY_1335_DATA 0x00000008 #define DDRSS_PHY_1336_DATA 0x00000000 #define DDRSS_PHY_1337_DATA 0x00000000 @@ -2184,4 +2186,4 @@ #define DDRSS_PHY_1402_DATA 0x01990000 #define DDRSS_PHY_1403_DATA 0x300D3F11 #define DDRSS_PHY_1404_DATA 0x01990000 -#define DDRSS_PHY_1405_DATA 0x20040001 +#define DDRSS_PHY_1405_DATA 0x20040004 diff --git a/arch/arm/dts/k3-am64-sk-lp4-1333MTs.dtsi b/arch/arm/dts/k3-am64-sk-lp4-1600MTs.dtsi index dde5ab150da..f225c1f0674 100644 --- a/arch/arm/dts/k3-am64-sk-lp4-1333MTs.dtsi +++ b/arch/arm/dts/k3-am64-sk-lp4-1600MTs.dtsi @@ -1,18 +1,17 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/ * This file was generated with the - * AM64x SysConfig DDR Subsystem Register Configuration Tool v0.08.00 - * Wed Oct 13 2021 10:08:29 GMT-0500 (Central Daylight Time) + * AM64x SysConfig DDR Subsystem Register Configuration Tool v0.08.40 + * Wed Feb 02 2022 16:59:34 GMT-0600 (Central Standard Time) * DDR Type: LPDDR4 - * F0 = 50MHz F1 = 666.7MHz F2 = 666.7MHz + * F0 = 50MHz F1 = 800MHz F2 = 800MHz * Density (per channel): 16Gb * Number of Ranks: 1 -*/ + */ #define DDRSS_PLL_FHS_CNT 6 -#define DDRSS_PLL_FREQUENCY_1 333350000 -#define DDRSS_PLL_FREQUENCY_2 333350000 +#define DDRSS_PLL_FREQUENCY_1 400000000 +#define DDRSS_PLL_FREQUENCY_2 400000000 #define DDRSS_CTL_0_DATA 0x00000B00 #define DDRSS_CTL_1_DATA 0x00000000 @@ -25,14 +24,14 @@ #define DDRSS_CTL_8_DATA 0x000186A0 #define DDRSS_CTL_9_DATA 0x00000005 #define DDRSS_CTL_10_DATA 0x00000064 -#define DDRSS_CTL_11_DATA 0x000208D6 -#define DDRSS_CTL_12_DATA 0x00145856 +#define DDRSS_CTL_11_DATA 0x00027100 +#define DDRSS_CTL_12_DATA 0x00186A00 #define DDRSS_CTL_13_DATA 0x00000005 -#define DDRSS_CTL_14_DATA 0x00000536 -#define DDRSS_CTL_15_DATA 0x000208D6 -#define DDRSS_CTL_16_DATA 0x00145856 +#define DDRSS_CTL_14_DATA 0x00000640 +#define DDRSS_CTL_15_DATA 0x00027100 +#define DDRSS_CTL_16_DATA 0x00186A00 #define DDRSS_CTL_17_DATA 0x00000005 -#define DDRSS_CTL_18_DATA 0x00000536 +#define DDRSS_CTL_18_DATA 0x00000640 #define DDRSS_CTL_19_DATA 0x01010100 #define DDRSS_CTL_20_DATA 0x01010100 #define DDRSS_CTL_21_DATA 0x01000110 @@ -48,8 +47,8 @@ #define DDRSS_CTL_31_DATA 0x00000000 #define DDRSS_CTL_32_DATA 0x00000000 #define DDRSS_CTL_33_DATA 0x00000000 -#define DDRSS_CTL_34_DATA 0x02000010 -#define DDRSS_CTL_35_DATA 0x00001B1B +#define DDRSS_CTL_34_DATA 0x08000010 +#define DDRSS_CTL_35_DATA 0x00002020 #define DDRSS_CTL_36_DATA 0x00000000 #define DDRSS_CTL_37_DATA 0x00000000 #define DDRSS_CTL_38_DATA 0x0000040C @@ -62,64 +61,64 @@ #define DDRSS_CTL_45_DATA 0x00000700 #define DDRSS_CTL_46_DATA 0x09090004 #define DDRSS_CTL_47_DATA 0x00000203 -#define DDRSS_CTL_48_DATA 0x00290006 -#define DDRSS_CTL_49_DATA 0x0909001D -#define DDRSS_CTL_50_DATA 0x0000150C -#define DDRSS_CTL_51_DATA 0x00290006 -#define DDRSS_CTL_52_DATA 0x0909001D -#define DDRSS_CTL_53_DATA 0x0900150C +#define DDRSS_CTL_48_DATA 0x00320007 +#define DDRSS_CTL_49_DATA 0x09090023 +#define DDRSS_CTL_50_DATA 0x0000190F +#define DDRSS_CTL_51_DATA 0x00320007 +#define DDRSS_CTL_52_DATA 0x09090023 +#define DDRSS_CTL_53_DATA 0x0900190F #define DDRSS_CTL_54_DATA 0x000A0A09 #define DDRSS_CTL_55_DATA 0x040006DB #define DDRSS_CTL_56_DATA 0x09092004 -#define DDRSS_CTL_57_DATA 0x00000A0A -#define DDRSS_CTL_58_DATA 0x05005B68 -#define DDRSS_CTL_59_DATA 0x09092005 -#define DDRSS_CTL_60_DATA 0x00000A0A -#define DDRSS_CTL_61_DATA 0x05005B68 -#define DDRSS_CTL_62_DATA 0x03042005 +#define DDRSS_CTL_57_DATA 0x00000C0A +#define DDRSS_CTL_58_DATA 0x06006DB0 +#define DDRSS_CTL_59_DATA 0x09092006 +#define DDRSS_CTL_60_DATA 0x00000C0A +#define DDRSS_CTL_61_DATA 0x06006DB0 +#define DDRSS_CTL_62_DATA 0x03042006 #define DDRSS_CTL_63_DATA 0x04050002 -#define DDRSS_CTL_64_DATA 0x0E0D0E0D +#define DDRSS_CTL_64_DATA 0x100F100F #define DDRSS_CTL_65_DATA 0x01010008 -#define DDRSS_CTL_66_DATA 0x041A1A07 -#define DDRSS_CTL_67_DATA 0x030E0E03 -#define DDRSS_CTL_68_DATA 0x00000E0E +#define DDRSS_CTL_66_DATA 0x041F1F07 +#define DDRSS_CTL_67_DATA 0x03111103 +#define DDRSS_CTL_68_DATA 0x00001111 #define DDRSS_CTL_69_DATA 0x00000101 #define DDRSS_CTL_70_DATA 0x00000000 #define DDRSS_CTL_71_DATA 0x01000000 #define DDRSS_CTL_72_DATA 0x00130803 #define DDRSS_CTL_73_DATA 0x000000BB -#define DDRSS_CTL_74_DATA 0x000000FE -#define DDRSS_CTL_75_DATA 0x00000A20 -#define DDRSS_CTL_76_DATA 0x000000FE -#define DDRSS_CTL_77_DATA 0x00000A20 +#define DDRSS_CTL_74_DATA 0x00000130 +#define DDRSS_CTL_75_DATA 0x00000C28 +#define DDRSS_CTL_76_DATA 0x00000130 +#define DDRSS_CTL_77_DATA 0x00000C28 #define DDRSS_CTL_78_DATA 0x00000005 #define DDRSS_CTL_79_DATA 0x0000000A #define DDRSS_CTL_80_DATA 0x00000010 -#define DDRSS_CTL_81_DATA 0x0000007F -#define DDRSS_CTL_82_DATA 0x0000013D -#define DDRSS_CTL_83_DATA 0x0000007F -#define DDRSS_CTL_84_DATA 0x0000013D +#define DDRSS_CTL_81_DATA 0x00000098 +#define DDRSS_CTL_82_DATA 0x0000017E +#define DDRSS_CTL_83_DATA 0x00000098 +#define DDRSS_CTL_84_DATA 0x0000017E #define DDRSS_CTL_85_DATA 0x03004000 #define DDRSS_CTL_86_DATA 0x00001201 -#define DDRSS_CTL_87_DATA 0x00050005 -#define DDRSS_CTL_88_DATA 0x00000005 +#define DDRSS_CTL_87_DATA 0x00060005 +#define DDRSS_CTL_88_DATA 0x00000006 #define DDRSS_CTL_89_DATA 0x00000000 -#define DDRSS_CTL_90_DATA 0x05101008 +#define DDRSS_CTL_90_DATA 0x05121208 #define DDRSS_CTL_91_DATA 0x05030A05 -#define DDRSS_CTL_92_DATA 0x05030A05 -#define DDRSS_CTL_93_DATA 0x01030A05 +#define DDRSS_CTL_92_DATA 0x05030C06 +#define DDRSS_CTL_93_DATA 0x01030C06 #define DDRSS_CTL_94_DATA 0x02010201 #define DDRSS_CTL_95_DATA 0x00001401 -#define DDRSS_CTL_96_DATA 0x01030014 -#define DDRSS_CTL_97_DATA 0x01030103 -#define DDRSS_CTL_98_DATA 0x00000103 +#define DDRSS_CTL_96_DATA 0x01360014 +#define DDRSS_CTL_97_DATA 0x01360136 +#define DDRSS_CTL_98_DATA 0x00000136 #define DDRSS_CTL_99_DATA 0x00000000 #define DDRSS_CTL_100_DATA 0x05010303 -#define DDRSS_CTL_101_DATA 0x0A040505 -#define DDRSS_CTL_102_DATA 0x05050203 -#define DDRSS_CTL_103_DATA 0x030A0505 -#define DDRSS_CTL_104_DATA 0x05050502 -#define DDRSS_CTL_105_DATA 0x03030305 +#define DDRSS_CTL_101_DATA 0x0C040505 +#define DDRSS_CTL_102_DATA 0x06050203 +#define DDRSS_CTL_103_DATA 0x030C0605 +#define DDRSS_CTL_104_DATA 0x05060502 +#define DDRSS_CTL_105_DATA 0x03030306 #define DDRSS_CTL_106_DATA 0x03010000 #define DDRSS_CTL_107_DATA 0x00010000 #define DDRSS_CTL_108_DATA 0x00000000 @@ -140,20 +139,20 @@ #define DDRSS_CTL_123_DATA 0x00002EC0 #define DDRSS_CTL_124_DATA 0x00000000 #define DDRSS_CTL_125_DATA 0x0000051D -#define DDRSS_CTL_126_DATA 0x00028800 -#define DDRSS_CTL_127_DATA 0x00028800 -#define DDRSS_CTL_128_DATA 0x00028800 -#define DDRSS_CTL_129_DATA 0x00028800 -#define DDRSS_CTL_130_DATA 0x00028800 +#define DDRSS_CTL_126_DATA 0x00030A00 +#define DDRSS_CTL_127_DATA 0x00030A00 +#define DDRSS_CTL_128_DATA 0x00030A00 +#define DDRSS_CTL_129_DATA 0x00030A00 +#define DDRSS_CTL_130_DATA 0x00030A00 #define DDRSS_CTL_131_DATA 0x00000000 -#define DDRSS_CTL_132_DATA 0x000046E0 -#define DDRSS_CTL_133_DATA 0x00028800 -#define DDRSS_CTL_134_DATA 0x00028800 -#define DDRSS_CTL_135_DATA 0x00028800 -#define DDRSS_CTL_136_DATA 0x00028800 -#define DDRSS_CTL_137_DATA 0x00028800 +#define DDRSS_CTL_132_DATA 0x00005518 +#define DDRSS_CTL_133_DATA 0x00030A00 +#define DDRSS_CTL_134_DATA 0x00030A00 +#define DDRSS_CTL_135_DATA 0x00030A00 +#define DDRSS_CTL_136_DATA 0x00030A00 +#define DDRSS_CTL_137_DATA 0x00030A00 #define DDRSS_CTL_138_DATA 0x00000000 -#define DDRSS_CTL_139_DATA 0x000046E0 +#define DDRSS_CTL_139_DATA 0x00005518 #define DDRSS_CTL_140_DATA 0x00000000 #define DDRSS_CTL_141_DATA 0x00000000 #define DDRSS_CTL_142_DATA 0x00000000 @@ -209,12 +208,12 @@ #define DDRSS_CTL_192_DATA 0x0005000A #define DDRSS_CTL_193_DATA 0x0404000D #define DDRSS_CTL_194_DATA 0x0000000D -#define DDRSS_CTL_195_DATA 0x00430086 -#define DDRSS_CTL_196_DATA 0x050500A7 -#define DDRSS_CTL_197_DATA 0x000000A7 -#define DDRSS_CTL_198_DATA 0x00430086 -#define DDRSS_CTL_199_DATA 0x050500A7 -#define DDRSS_CTL_200_DATA 0x000000A7 +#define DDRSS_CTL_195_DATA 0x005000A0 +#define DDRSS_CTL_196_DATA 0x060600C8 +#define DDRSS_CTL_197_DATA 0x000000C8 +#define DDRSS_CTL_198_DATA 0x005000A0 +#define DDRSS_CTL_199_DATA 0x060600C8 +#define DDRSS_CTL_200_DATA 0x000000C8 #define DDRSS_CTL_201_DATA 0x00000000 #define DDRSS_CTL_202_DATA 0x00000000 #define DDRSS_CTL_203_DATA 0x00000000 @@ -239,11 +238,11 @@ #define DDRSS_CTL_222_DATA 0x00000000 #define DDRSS_CTL_223_DATA 0x00000000 #define DDRSS_CTL_224_DATA 0x00000031 -#define DDRSS_CTL_225_DATA 0x00000031 -#define DDRSS_CTL_226_DATA 0x00000031 +#define DDRSS_CTL_225_DATA 0x000000B1 +#define DDRSS_CTL_226_DATA 0x000000B1 #define DDRSS_CTL_227_DATA 0x00000031 -#define DDRSS_CTL_228_DATA 0x00000031 -#define DDRSS_CTL_229_DATA 0x00000031 +#define DDRSS_CTL_228_DATA 0x000000B1 +#define DDRSS_CTL_229_DATA 0x000000B1 #define DDRSS_CTL_230_DATA 0x00000000 #define DDRSS_CTL_231_DATA 0x00000000 #define DDRSS_CTL_232_DATA 0x00000000 @@ -323,12 +322,12 @@ #define DDRSS_CTL_306_DATA 0x00400100 #define DDRSS_CTL_307_DATA 0x00080032 #define DDRSS_CTL_308_DATA 0x01000200 -#define DDRSS_CTL_309_DATA 0x029B0040 -#define DDRSS_CTL_310_DATA 0x00020014 +#define DDRSS_CTL_309_DATA 0x03200040 +#define DDRSS_CTL_310_DATA 0x00020018 #define DDRSS_CTL_311_DATA 0x00400100 -#define DDRSS_CTL_312_DATA 0x0014029B +#define DDRSS_CTL_312_DATA 0x00180320 #define DDRSS_CTL_313_DATA 0x00030000 -#define DDRSS_CTL_314_DATA 0x00220022 +#define DDRSS_CTL_314_DATA 0x00280028 #define DDRSS_CTL_315_DATA 0x00000100 #define DDRSS_CTL_316_DATA 0x01010000 #define DDRSS_CTL_317_DATA 0x00000000 @@ -344,9 +343,9 @@ #define DDRSS_CTL_327_DATA 0x00000C01 #define DDRSS_CTL_328_DATA 0x01000100 #define DDRSS_CTL_329_DATA 0x00000000 -#define DDRSS_CTL_330_DATA 0x01000000 +#define DDRSS_CTL_330_DATA 0x00000000 #define DDRSS_CTL_331_DATA 0x01030303 -#define DDRSS_CTL_332_DATA 0x00000000 +#define DDRSS_CTL_332_DATA 0x00000001 #define DDRSS_CTL_333_DATA 0x00000000 #define DDRSS_CTL_334_DATA 0x00000000 #define DDRSS_CTL_335_DATA 0x00000000 @@ -390,14 +389,14 @@ #define DDRSS_CTL_373_DATA 0x00010101 #define DDRSS_CTL_374_DATA 0x01050503 #define DDRSS_CTL_375_DATA 0x05020201 -#define DDRSS_CTL_376_DATA 0x08080B0B +#define DDRSS_CTL_376_DATA 0x08080C0C #define DDRSS_CTL_377_DATA 0x00080308 -#define DDRSS_CTL_378_DATA 0x000C030E -#define DDRSS_CTL_379_DATA 0x000C0310 -#define DDRSS_CTL_380_DATA 0x0C0C0810 +#define DDRSS_CTL_378_DATA 0x000B030E +#define DDRSS_CTL_379_DATA 0x000B0310 +#define DDRSS_CTL_380_DATA 0x0B0B0810 #define DDRSS_CTL_381_DATA 0x01000000 -#define DDRSS_CTL_382_DATA 0x03010301 -#define DDRSS_CTL_383_DATA 0x04000101 +#define DDRSS_CTL_382_DATA 0x03020301 +#define DDRSS_CTL_383_DATA 0x04000102 #define DDRSS_CTL_384_DATA 0x1B000004 #define DDRSS_CTL_385_DATA 0x00000176 #define DDRSS_CTL_386_DATA 0x00000200 @@ -407,24 +406,24 @@ #define DDRSS_CTL_390_DATA 0x00000693 #define DDRSS_CTL_391_DATA 0x00000E9C #define DDRSS_CTL_392_DATA 0x03050202 -#define DDRSS_CTL_393_DATA 0x00240201 -#define DDRSS_CTL_394_DATA 0x00001440 +#define DDRSS_CTL_393_DATA 0x00250201 +#define DDRSS_CTL_394_DATA 0x00001850 #define DDRSS_CTL_395_DATA 0x00000200 #define DDRSS_CTL_396_DATA 0x00000200 #define DDRSS_CTL_397_DATA 0x00000200 #define DDRSS_CTL_398_DATA 0x00000200 -#define DDRSS_CTL_399_DATA 0x00005B20 -#define DDRSS_CTL_400_DATA 0x0000CA80 -#define DDRSS_CTL_401_DATA 0x080D0402 -#define DDRSS_CTL_402_DATA 0x00240405 -#define DDRSS_CTL_403_DATA 0x00001440 +#define DDRSS_CTL_399_DATA 0x00006D68 +#define DDRSS_CTL_400_DATA 0x0000F320 +#define DDRSS_CTL_401_DATA 0x070D0402 +#define DDRSS_CTL_402_DATA 0x00250405 +#define DDRSS_CTL_403_DATA 0x00001850 #define DDRSS_CTL_404_DATA 0x00000200 #define DDRSS_CTL_405_DATA 0x00000200 #define DDRSS_CTL_406_DATA 0x00000200 #define DDRSS_CTL_407_DATA 0x00000200 -#define DDRSS_CTL_408_DATA 0x00005B20 -#define DDRSS_CTL_409_DATA 0x0000CA80 -#define DDRSS_CTL_410_DATA 0x080D0402 +#define DDRSS_CTL_408_DATA 0x00006D68 +#define DDRSS_CTL_409_DATA 0x0000F320 +#define DDRSS_CTL_410_DATA 0x070D0402 #define DDRSS_CTL_411_DATA 0x00000405 #define DDRSS_CTL_412_DATA 0x00000000 #define DDRSS_CTL_413_DATA 0x0302000A @@ -483,7 +482,7 @@ #define DDRSS_PI_43_DATA 0x00000000 #define DDRSS_PI_44_DATA 0x00000000 #define DDRSS_PI_45_DATA 0x00010100 -#define DDRSS_PI_46_DATA 0x00000014 +#define DDRSS_PI_46_DATA 0x00000015 #define DDRSS_PI_47_DATA 0x000007D0 #define DDRSS_PI_48_DATA 0x00000300 #define DDRSS_PI_49_DATA 0x00000000 @@ -602,8 +601,8 @@ #define DDRSS_PI_162_DATA 0x00000000 #define DDRSS_PI_163_DATA 0x00000000 #define DDRSS_PI_164_DATA 0x00000800 -#define DDRSS_PI_165_DATA 0x00640064 -#define DDRSS_PI_166_DATA 0x000E0E01 +#define DDRSS_PI_165_DATA 0x00780078 +#define DDRSS_PI_166_DATA 0x00101001 #define DDRSS_PI_167_DATA 0x00000034 #define DDRSS_PI_168_DATA 0x00000042 #define DDRSS_PI_169_DATA 0x00020042 @@ -614,84 +613,84 @@ #define DDRSS_PI_174_DATA 0x001C0000 #define DDRSS_PI_175_DATA 0x00000013 #define DDRSS_PI_176_DATA 0x000000BB -#define DDRSS_PI_177_DATA 0x000000FE -#define DDRSS_PI_178_DATA 0x00000A20 -#define DDRSS_PI_179_DATA 0x000000FE -#define DDRSS_PI_180_DATA 0x04000A20 +#define DDRSS_PI_177_DATA 0x00000130 +#define DDRSS_PI_178_DATA 0x00000C28 +#define DDRSS_PI_179_DATA 0x00000130 +#define DDRSS_PI_180_DATA 0x04000C28 #define DDRSS_PI_181_DATA 0x01010404 #define DDRSS_PI_182_DATA 0x00001501 -#define DDRSS_PI_183_DATA 0x001B001B +#define DDRSS_PI_183_DATA 0x001D001D #define DDRSS_PI_184_DATA 0x01000100 #define DDRSS_PI_185_DATA 0x00000100 #define DDRSS_PI_186_DATA 0x00000000 #define DDRSS_PI_187_DATA 0x05050503 -#define DDRSS_PI_188_DATA 0x01010B0B +#define DDRSS_PI_188_DATA 0x01010C0C #define DDRSS_PI_189_DATA 0x01010101 #define DDRSS_PI_190_DATA 0x000C0C0A #define DDRSS_PI_191_DATA 0x00000000 #define DDRSS_PI_192_DATA 0x00000000 #define DDRSS_PI_193_DATA 0x04000000 -#define DDRSS_PI_194_DATA 0x04020909 +#define DDRSS_PI_194_DATA 0x04020808 #define DDRSS_PI_195_DATA 0x04040204 #define DDRSS_PI_196_DATA 0x00090031 -#define DDRSS_PI_197_DATA 0x000F0037 -#define DDRSS_PI_198_DATA 0x000F0037 +#define DDRSS_PI_197_DATA 0x00110039 +#define DDRSS_PI_198_DATA 0x00110039 #define DDRSS_PI_199_DATA 0x01010101 -#define DDRSS_PI_200_DATA 0x0001000D -#define DDRSS_PI_201_DATA 0x000100A7 -#define DDRSS_PI_202_DATA 0x010000A7 +#define DDRSS_PI_200_DATA 0x0002000D +#define DDRSS_PI_201_DATA 0x000200C8 +#define DDRSS_PI_202_DATA 0x010000C8 #define DDRSS_PI_203_DATA 0x000E000E -#define DDRSS_PI_204_DATA 0x00A80100 -#define DDRSS_PI_205_DATA 0x010000A8 -#define DDRSS_PI_206_DATA 0x00A800A8 +#define DDRSS_PI_204_DATA 0x00C90100 +#define DDRSS_PI_205_DATA 0x010000C9 +#define DDRSS_PI_206_DATA 0x00C900C9 #define DDRSS_PI_207_DATA 0x32103200 #define DDRSS_PI_208_DATA 0x01013210 #define DDRSS_PI_209_DATA 0x0A070601 -#define DDRSS_PI_210_DATA 0x0B08070D -#define DDRSS_PI_211_DATA 0x0B08070D +#define DDRSS_PI_210_DATA 0x0D09070D +#define DDRSS_PI_211_DATA 0x0D09070D #define DDRSS_PI_212_DATA 0x000C000D #define DDRSS_PI_213_DATA 0x00001000 #define DDRSS_PI_214_DATA 0x00000C00 #define DDRSS_PI_215_DATA 0x00001000 #define DDRSS_PI_216_DATA 0x00000C00 #define DDRSS_PI_217_DATA 0x02001000 -#define DDRSS_PI_218_DATA 0x0015000D -#define DDRSS_PI_219_DATA 0x001500A7 -#define DDRSS_PI_220_DATA 0x000000A7 +#define DDRSS_PI_218_DATA 0x0016000D +#define DDRSS_PI_219_DATA 0x001600C8 +#define DDRSS_PI_220_DATA 0x000000C8 #define DDRSS_PI_221_DATA 0x00001900 #define DDRSS_PI_222_DATA 0x32000056 #define DDRSS_PI_223_DATA 0x06000101 #define DDRSS_PI_224_DATA 0x001D0204 -#define DDRSS_PI_225_DATA 0x32120059 +#define DDRSS_PI_225_DATA 0x32120058 #define DDRSS_PI_226_DATA 0x05000101 -#define DDRSS_PI_227_DATA 0x001D0409 -#define DDRSS_PI_228_DATA 0x32120059 +#define DDRSS_PI_227_DATA 0x001D0408 +#define DDRSS_PI_228_DATA 0x32120058 #define DDRSS_PI_229_DATA 0x05000101 -#define DDRSS_PI_230_DATA 0x00000409 +#define DDRSS_PI_230_DATA 0x00000408 #define DDRSS_PI_231_DATA 0x05030900 #define DDRSS_PI_232_DATA 0x00040900 #define DDRSS_PI_233_DATA 0x0000062B #define DDRSS_PI_234_DATA 0x20010004 #define DDRSS_PI_235_DATA 0x0A0A0A03 -#define DDRSS_PI_236_DATA 0x0E090000 -#define DDRSS_PI_237_DATA 0x0E09000D -#define DDRSS_PI_238_DATA 0x00005244 -#define DDRSS_PI_239_DATA 0x2003001D -#define DDRSS_PI_240_DATA 0x0A0A0A0A -#define DDRSS_PI_241_DATA 0x0E090000 -#define DDRSS_PI_242_DATA 0x0E09000D -#define DDRSS_PI_243_DATA 0x00005244 -#define DDRSS_PI_244_DATA 0x2003001D -#define DDRSS_PI_245_DATA 0x0A0A0A0A +#define DDRSS_PI_236_DATA 0x11090000 +#define DDRSS_PI_237_DATA 0x1009000F +#define DDRSS_PI_238_DATA 0x000062B8 +#define DDRSS_PI_239_DATA 0x20030023 +#define DDRSS_PI_240_DATA 0x0C0A0C0C +#define DDRSS_PI_241_DATA 0x11090000 +#define DDRSS_PI_242_DATA 0x1009000F +#define DDRSS_PI_243_DATA 0x000062B8 +#define DDRSS_PI_244_DATA 0x20030023 +#define DDRSS_PI_245_DATA 0x0C0A0C0C #define DDRSS_PI_246_DATA 0x00000000 #define DDRSS_PI_247_DATA 0x00000176 #define DDRSS_PI_248_DATA 0x00000E9C -#define DDRSS_PI_249_DATA 0x00001440 -#define DDRSS_PI_250_DATA 0x0000CA80 -#define DDRSS_PI_251_DATA 0x00001440 -#define DDRSS_PI_252_DATA 0x0000CA80 -#define DDRSS_PI_253_DATA 0x01030014 -#define DDRSS_PI_254_DATA 0x03030103 +#define DDRSS_PI_249_DATA 0x00001850 +#define DDRSS_PI_250_DATA 0x0000F320 +#define DDRSS_PI_251_DATA 0x00001850 +#define DDRSS_PI_252_DATA 0x0000F320 +#define DDRSS_PI_253_DATA 0x01360014 +#define DDRSS_PI_254_DATA 0x03030136 #define DDRSS_PI_255_DATA 0x00000003 #define DDRSS_PI_256_DATA 0x00000000 #define DDRSS_PI_257_DATA 0x05030503 @@ -701,23 +700,23 @@ #define DDRSS_PI_261_DATA 0x00000005 #define DDRSS_PI_262_DATA 0x00000064 #define DDRSS_PI_263_DATA 0x00000014 -#define DDRSS_PI_264_DATA 0x000208D6 +#define DDRSS_PI_264_DATA 0x00027100 #define DDRSS_PI_265_DATA 0x000186A0 #define DDRSS_PI_266_DATA 0x00000005 -#define DDRSS_PI_267_DATA 0x00000536 -#define DDRSS_PI_268_DATA 0x00000103 -#define DDRSS_PI_269_DATA 0x000208D6 +#define DDRSS_PI_267_DATA 0x00000640 +#define DDRSS_PI_268_DATA 0x00000136 +#define DDRSS_PI_269_DATA 0x00027100 #define DDRSS_PI_270_DATA 0x000186A0 #define DDRSS_PI_271_DATA 0x00000005 -#define DDRSS_PI_272_DATA 0x00000536 -#define DDRSS_PI_273_DATA 0x01000103 +#define DDRSS_PI_272_DATA 0x00000640 +#define DDRSS_PI_273_DATA 0x01000136 #define DDRSS_PI_274_DATA 0x00320040 #define DDRSS_PI_275_DATA 0x00010008 -#define DDRSS_PI_276_DATA 0x029B0040 -#define DDRSS_PI_277_DATA 0x00010014 -#define DDRSS_PI_278_DATA 0x029B0040 -#define DDRSS_PI_279_DATA 0x00000314 -#define DDRSS_PI_280_DATA 0x00280021 +#define DDRSS_PI_276_DATA 0x03200040 +#define DDRSS_PI_277_DATA 0x00010018 +#define DDRSS_PI_278_DATA 0x03200040 +#define DDRSS_PI_279_DATA 0x00000318 +#define DDRSS_PI_280_DATA 0x00280028 #define DDRSS_PI_281_DATA 0x03040404 #define DDRSS_PI_282_DATA 0x00000303 #define DDRSS_PI_283_DATA 0x02020101 @@ -745,7 +744,7 @@ #define DDRSS_PI_305_DATA 0x00000000 #define DDRSS_PI_306_DATA 0x00000024 #define DDRSS_PI_307_DATA 0x00000012 -#define DDRSS_PI_308_DATA 0x00000031 +#define DDRSS_PI_308_DATA 0x000000B1 #define DDRSS_PI_309_DATA 0x00000000 #define DDRSS_PI_310_DATA 0x00000000 #define DDRSS_PI_311_DATA 0x46000000 @@ -753,7 +752,7 @@ #define DDRSS_PI_313_DATA 0x00000000 #define DDRSS_PI_314_DATA 0x00000024 #define DDRSS_PI_315_DATA 0x00000012 -#define DDRSS_PI_316_DATA 0x00000031 +#define DDRSS_PI_316_DATA 0x000000B1 #define DDRSS_PI_317_DATA 0x00000000 #define DDRSS_PI_318_DATA 0x00000000 #define DDRSS_PI_319_DATA 0x46000000 @@ -769,7 +768,7 @@ #define DDRSS_PI_329_DATA 0x00000000 #define DDRSS_PI_330_DATA 0x00000024 #define DDRSS_PI_331_DATA 0x00000012 -#define DDRSS_PI_332_DATA 0x00000031 +#define DDRSS_PI_332_DATA 0x000000B1 #define DDRSS_PI_333_DATA 0x00000000 #define DDRSS_PI_334_DATA 0x00000000 #define DDRSS_PI_335_DATA 0x46000000 @@ -777,7 +776,7 @@ #define DDRSS_PI_337_DATA 0x00000000 #define DDRSS_PI_338_DATA 0x00000024 #define DDRSS_PI_339_DATA 0x00000012 -#define DDRSS_PI_340_DATA 0x00000031 +#define DDRSS_PI_340_DATA 0x000000B1 #define DDRSS_PI_341_DATA 0x00000000 #define DDRSS_PI_342_DATA 0x00000000 #define DDRSS_PI_343_DATA 0x46000000 @@ -869,29 +868,29 @@ #define DDRSS_PHY_84_DATA 0x00100010 #define DDRSS_PHY_85_DATA 0x00100010 #define DDRSS_PHY_86_DATA 0x00100010 -#define DDRSS_PHY_87_DATA 0x02000010 +#define DDRSS_PHY_87_DATA 0x02020010 #define DDRSS_PHY_88_DATA 0x51516041 #define DDRSS_PHY_89_DATA 0x31C06000 #define DDRSS_PHY_90_DATA 0x07AB0340 #define DDRSS_PHY_91_DATA 0x0000C0C0 -#define DDRSS_PHY_92_DATA 0x03040000 -#define DDRSS_PHY_93_DATA 0x00000403 +#define DDRSS_PHY_92_DATA 0x04050000 +#define DDRSS_PHY_93_DATA 0x00000504 #define DDRSS_PHY_94_DATA 0x42100010 #define DDRSS_PHY_95_DATA 0x010C053E -#define DDRSS_PHY_96_DATA 0x000F0C1A +#define DDRSS_PHY_96_DATA 0x000F0C1D #define DDRSS_PHY_97_DATA 0x01000140 -#define DDRSS_PHY_98_DATA 0x00660120 +#define DDRSS_PHY_98_DATA 0x007A0120 #define DDRSS_PHY_99_DATA 0x00000C00 -#define DDRSS_PHY_100_DATA 0x000001AA +#define DDRSS_PHY_100_DATA 0x000001CC #define DDRSS_PHY_101_DATA 0x20100200 -#define DDRSS_PHY_102_DATA 0x00000004 +#define DDRSS_PHY_102_DATA 0x00000005 #define DDRSS_PHY_103_DATA 0x76543210 #define DDRSS_PHY_104_DATA 0x00000008 -#define DDRSS_PHY_105_DATA 0x032A032A -#define DDRSS_PHY_106_DATA 0x032A032A -#define DDRSS_PHY_107_DATA 0x032A032A -#define DDRSS_PHY_108_DATA 0x032A032A -#define DDRSS_PHY_109_DATA 0x0000032A +#define DDRSS_PHY_105_DATA 0x034C034C +#define DDRSS_PHY_106_DATA 0x034C034C +#define DDRSS_PHY_107_DATA 0x034C034C +#define DDRSS_PHY_108_DATA 0x034C034C +#define DDRSS_PHY_109_DATA 0x0000034C #define DDRSS_PHY_110_DATA 0x00008000 #define DDRSS_PHY_111_DATA 0x00800080 #define DDRSS_PHY_112_DATA 0x00800080 @@ -901,7 +900,7 @@ #define DDRSS_PHY_116_DATA 0x00800080 #define DDRSS_PHY_117_DATA 0x00800080 #define DDRSS_PHY_118_DATA 0x00800080 -#define DDRSS_PHY_119_DATA 0x01190080 +#define DDRSS_PHY_119_DATA 0x01800080 #define DDRSS_PHY_120_DATA 0x01A00001 #define DDRSS_PHY_121_DATA 0x00000000 #define DDRSS_PHY_122_DATA 0x00000000 @@ -1125,29 +1124,29 @@ #define DDRSS_PHY_340_DATA 0x00100010 #define DDRSS_PHY_341_DATA 0x00100010 #define DDRSS_PHY_342_DATA 0x00100010 -#define DDRSS_PHY_343_DATA 0x02000010 +#define DDRSS_PHY_343_DATA 0x02020010 #define DDRSS_PHY_344_DATA 0x51516041 #define DDRSS_PHY_345_DATA 0x31C06000 #define DDRSS_PHY_346_DATA 0x07AB0340 #define DDRSS_PHY_347_DATA 0x0000C0C0 -#define DDRSS_PHY_348_DATA 0x03040000 -#define DDRSS_PHY_349_DATA 0x00000403 +#define DDRSS_PHY_348_DATA 0x04050000 +#define DDRSS_PHY_349_DATA 0x00000504 #define DDRSS_PHY_350_DATA 0x42100010 #define DDRSS_PHY_351_DATA 0x010C053E -#define DDRSS_PHY_352_DATA 0x000F0C1A +#define DDRSS_PHY_352_DATA 0x000F0C1D #define DDRSS_PHY_353_DATA 0x01000140 -#define DDRSS_PHY_354_DATA 0x00660120 +#define DDRSS_PHY_354_DATA 0x007A0120 #define DDRSS_PHY_355_DATA 0x00000C00 -#define DDRSS_PHY_356_DATA 0x000001AA +#define DDRSS_PHY_356_DATA 0x000001CC #define DDRSS_PHY_357_DATA 0x20100200 -#define DDRSS_PHY_358_DATA 0x00000004 +#define DDRSS_PHY_358_DATA 0x00000005 #define DDRSS_PHY_359_DATA 0x76543210 #define DDRSS_PHY_360_DATA 0x00000008 -#define DDRSS_PHY_361_DATA 0x032A032A -#define DDRSS_PHY_362_DATA 0x032A032A -#define DDRSS_PHY_363_DATA 0x032A032A -#define DDRSS_PHY_364_DATA 0x032A032A -#define DDRSS_PHY_365_DATA 0x0000032A +#define DDRSS_PHY_361_DATA 0x034C034C +#define DDRSS_PHY_362_DATA 0x034C034C +#define DDRSS_PHY_363_DATA 0x034C034C +#define DDRSS_PHY_364_DATA 0x034C034C +#define DDRSS_PHY_365_DATA 0x0000034C #define DDRSS_PHY_366_DATA 0x00008000 #define DDRSS_PHY_367_DATA 0x00800080 #define DDRSS_PHY_368_DATA 0x00800080 @@ -1157,7 +1156,7 @@ #define DDRSS_PHY_372_DATA 0x00800080 #define DDRSS_PHY_373_DATA 0x00800080 #define DDRSS_PHY_374_DATA 0x00800080 -#define DDRSS_PHY_375_DATA 0x01190080 +#define DDRSS_PHY_375_DATA 0x01800080 #define DDRSS_PHY_376_DATA 0x01A00001 #define DDRSS_PHY_377_DATA 0x00000000 #define DDRSS_PHY_378_DATA 0x00000000 @@ -1326,7 +1325,7 @@ #define DDRSS_PHY_541_DATA 0x003F0000 #define DDRSS_PHY_542_DATA 0x000F013F #define DDRSS_PHY_543_DATA 0x0000000F -#define DDRSS_PHY_544_DATA 0x000002CC +#define DDRSS_PHY_544_DATA 0x020002CC #define DDRSS_PHY_545_DATA 0x00030000 #define DDRSS_PHY_546_DATA 0x00000300 #define DDRSS_PHY_547_DATA 0x00000300 @@ -1582,7 +1581,7 @@ #define DDRSS_PHY_797_DATA 0x00000000 #define DDRSS_PHY_798_DATA 0x000F0000 #define DDRSS_PHY_799_DATA 0x0000000F -#define DDRSS_PHY_800_DATA 0x000002CC +#define DDRSS_PHY_800_DATA 0x020002CC #define DDRSS_PHY_801_DATA 0x00030000 #define DDRSS_PHY_802_DATA 0x00000300 #define DDRSS_PHY_803_DATA 0x00000300 @@ -1838,7 +1837,7 @@ #define DDRSS_PHY_1053_DATA 0x10000000 #define DDRSS_PHY_1054_DATA 0x000F0000 #define DDRSS_PHY_1055_DATA 0x0000000F -#define DDRSS_PHY_1056_DATA 0x000002CC +#define DDRSS_PHY_1056_DATA 0x020002CC #define DDRSS_PHY_1057_DATA 0x00030000 #define DDRSS_PHY_1058_DATA 0x00000300 #define DDRSS_PHY_1059_DATA 0x00000300 @@ -2116,7 +2115,7 @@ #define DDRSS_PHY_1331_DATA 0x00004410 #define DDRSS_PHY_1332_DATA 0x00000000 #define DDRSS_PHY_1333_DATA 0x00000076 -#define DDRSS_PHY_1334_DATA 0x00010000 +#define DDRSS_PHY_1334_DATA 0x00000400 #define DDRSS_PHY_1335_DATA 0x00000008 #define DDRSS_PHY_1336_DATA 0x00000000 #define DDRSS_PHY_1337_DATA 0x00000000 @@ -2154,7 +2153,7 @@ #define DDRSS_PHY_1369_DATA 0x00000000 #define DDRSS_PHY_1370_DATA 0x00000000 #define DDRSS_PHY_1371_DATA 0x0001F7C0 -#define DDRSS_PHY_1372_DATA 0x00000002 +#define DDRSS_PHY_1372_DATA 0x00020002 #define DDRSS_PHY_1373_DATA 0x00000000 #define DDRSS_PHY_1374_DATA 0x00001142 #define DDRSS_PHY_1375_DATA 0x03020000 @@ -2187,4 +2186,4 @@ #define DDRSS_PHY_1402_DATA 0x019900E0 #define DDRSS_PHY_1403_DATA 0x00018011 #define DDRSS_PHY_1404_DATA 0x0089FF00 -#define DDRSS_PHY_1405_DATA 0x20040001 +#define DDRSS_PHY_1405_DATA 0x20040004 diff --git a/arch/arm/dts/k3-am642-r5-sk.dts b/arch/arm/dts/k3-am642-r5-sk.dts index cf3ba0e209c..97f44e220a3 100644 --- a/arch/arm/dts/k3-am642-r5-sk.dts +++ b/arch/arm/dts/k3-am642-r5-sk.dts @@ -9,7 +9,7 @@ #include <dt-bindings/phy/phy.h> #include <dt-bindings/net/ti-dp83867.h> #include "k3-am642.dtsi" -#include "k3-am64-sk-lp4-1333MTs.dtsi" +#include "k3-am64-sk-lp4-1600MTs.dtsi" #include "k3-am64-ddr.dtsi" / { diff --git a/arch/arm/dts/stm32mp15-scmi.dtsi b/arch/arm/dts/stm32mp15-scmi.dtsi index 37d4547b3e8..543f24c2f4f 100644 --- a/arch/arm/dts/stm32mp15-scmi.dtsi +++ b/arch/arm/dts/stm32mp15-scmi.dtsi @@ -103,7 +103,3 @@ /delete-node/ &clk_lse; /delete-node/ &clk_lsi; /delete-node/ &clk_csi; -/delete-node/ ®11; -/delete-node/ ®18; -/delete-node/ &usb33; -/delete-node/ &pwr_regulators; diff --git a/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi b/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi index 8a7156c93bf..b72a2f63f16 100644 --- a/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi +++ b/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi @@ -190,6 +190,21 @@ CLK_LPTIM45_LSE >; + /* + * cfg = < DIVM1 DIVN P Q R PQR(p,q,r) >; + * frac = < f >; + * + * PRQ(p,q,r) ... for p,q,r: 0-output disabled / 1-output enabled + * DIVN ... actually multiplier, but RCC_PLL1CFGR1 calls the field DIVN + * m ... for PLL1,2: m=2 ; for PLL3,4: m=1 + * XTAL = 24 MHz + * + * VCO = ( XTAL / (DIVM1 + 1) ) * m * ( DIVN + 1 + ( f / 8192 ) ) + * P = VCO / (P + 1) + * Q = VCO / (Q + 1) + * R = VCO / (R + 1) + */ + /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */ pll2: st,pll@1 { compatible = "st,stm32mp1-pll"; @@ -208,7 +223,7 @@ u-boot,dm-pre-reloc; }; - /* VCO = 600.0 MHz => P = 50, Q = 50, R = 50 */ + /* VCO = 600.0 MHz => P = 100, Q = 50, R = 50 */ pll4: st,pll@3 { compatible = "st,stm32mp1-pll"; reg = <3>; diff --git a/arch/arm/dts/stm32mp15xx-dhcor-avenger96-u-boot.dtsi b/arch/arm/dts/stm32mp15xx-dhcor-avenger96-u-boot.dtsi index 5bed53e3fdb..6dee51dc1c2 100644 --- a/arch/arm/dts/stm32mp15xx-dhcor-avenger96-u-boot.dtsi +++ b/arch/arm/dts/stm32mp15xx-dhcor-avenger96-u-boot.dtsi @@ -19,7 +19,6 @@ }; }; - ðernet0 { phy-reset-gpios = <&gpioz 2 GPIO_ACTIVE_LOW>; @@ -102,6 +101,10 @@ hnp-srp-disable; }; +&vdd { + /delete-property/ regulator-always-on; +}; + &vdd_io { u-boot,dm-spl; }; diff --git a/arch/arm/dts/stm32mp15xx-dhcor-testbench-u-boot.dtsi b/arch/arm/dts/stm32mp15xx-dhcor-testbench-u-boot.dtsi new file mode 100644 index 00000000000..5b051b8ac45 --- /dev/null +++ b/arch/arm/dts/stm32mp15xx-dhcor-testbench-u-boot.dtsi @@ -0,0 +1,100 @@ +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +/* + * Copyright (C) 2022 Marek Vasut <marex@denx.de> + */ + +#include "stm32mp15xx-dhcor-u-boot.dtsi" + +/ { + aliases { + mmc0 = &sdmmc1; + mmc1 = &sdmmc2; + usb0 = &usbotg_hs; + }; + + config { + dh,board-coding-gpios = <&gpiog 13 0>, <&gpiod 9 0>; + }; +}; + +ðernet0 { + phy-reset-gpios = <&gpioz 2 GPIO_ACTIVE_LOW>; + + mdio0 { + ethernet-phy@7 { + reset-gpios = <&gpioz 2 GPIO_ACTIVE_LOW>; + reset-assert-us = <11000>; + reset-deassert-us = <1000>; + }; + }; +}; + +&sdmmc1 { + u-boot,dm-spl; + st,use-ckin; + st,cmd-gpios = <&gpiod 2 0>; + st,ck-gpios = <&gpioc 12 0>; + st,ckin-gpios = <&gpioe 4 0>; +}; + +&sdmmc1_b4_pins_a { + u-boot,dm-spl; + pins1 { + u-boot,dm-spl; + }; + pins2 { + u-boot,dm-spl; + }; +}; + +&sdmmc1_dir_pins_b { + u-boot,dm-spl; + pins1 { + u-boot,dm-spl; + }; + pins2 { + u-boot,dm-spl; + }; +}; + +&sdmmc2 { + u-boot,dm-spl; +}; + +&sdmmc2_b4_pins_a { + u-boot,dm-spl; + pins1 { + u-boot,dm-spl; + }; + pins2 { + u-boot,dm-spl; + }; +}; + +&sdmmc2_d47_pins_c { + u-boot,dm-spl; + pins { + u-boot,dm-spl; + }; +}; + +&uart4 { + u-boot,dm-pre-reloc; +}; + +&uart4_pins_b { + u-boot,dm-pre-reloc; + pins1 { + u-boot,dm-pre-reloc; + }; + pins2 { + u-boot,dm-pre-reloc; + /delete-property/ bias-disable; + bias-pull-up; + }; +}; + +&usbotg_hs { + u-boot,force-b-session-valid; + hnp-srp-disable; +}; diff --git a/arch/arm/dts/stm32mp15xx-dhcor-testbench.dts b/arch/arm/dts/stm32mp15xx-dhcor-testbench.dts new file mode 100644 index 00000000000..c9163e1c028 --- /dev/null +++ b/arch/arm/dts/stm32mp15xx-dhcor-testbench.dts @@ -0,0 +1,178 @@ +// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) +/* + * Copyright (C) 2022 Marek Vasut <marex@denx.de> + */ +/dts-v1/; + +#include "stm32mp151.dtsi" +#include "stm32mp15xx-dhcor-som.dtsi" + +/ { + model = "DH electronics STM32MP15xx DHCOR Testbench"; + compatible = "dh,stm32mp15xx-dhcor-testbench", "st,stm32mp1xx"; + + aliases { + ethernet0 = ðernet0; + mmc0 = &sdmmc1; + mmc1 = &sdmmc2; + serial0 = &uart4; + serial1 = &uart7; + spi0 = &qspi; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + sd_switch: regulator-sd_switch { + compatible = "regulator-gpio"; + regulator-name = "sd_switch"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2900000>; + regulator-type = "voltage"; + regulator-always-on; + + gpios = <&gpioi 5 GPIO_ACTIVE_HIGH>; + gpios-states = <0>; + states = <1800000 0x1>, + <2900000 0x0>; + }; +}; + +&adc { + pinctrl-names = "default"; + pinctrl-0 = <&adc12_ain_pins_b>; + vdd-supply = <&vdd>; + vdda-supply = <&vdda>; + vref-supply = <&vdda>; + status = "okay"; + + adc1: adc@0 { + st,adc-channels = <0 1 6>; + st,min-sample-time-nsecs = <5000>; + status = "okay"; + }; + + adc2: adc@100 { + st,adc-channels = <0 1 2>; + st,min-sample-time-nsecs = <5000>; + status = "okay"; + }; +}; + +ðernet0 { + status = "okay"; + pinctrl-0 = <ðernet0_rgmii_pins_c>; + pinctrl-1 = <ðernet0_rgmii_sleep_pins_c>; + pinctrl-names = "default", "sleep"; + phy-mode = "rgmii"; + max-speed = <1000>; + phy-handle = <&phy0>; + + mdio0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + reset-gpios = <&gpioz 2 GPIO_ACTIVE_LOW>; + reset-delay-us = <1000>; + + phy0: ethernet-phy@7 { + reg = <7>; + + rxc-skew-ps = <1500>; + rxdv-skew-ps = <540>; + rxd0-skew-ps = <420>; + rxd1-skew-ps = <420>; + rxd2-skew-ps = <420>; + rxd3-skew-ps = <420>; + + txc-skew-ps = <1440>; + txen-skew-ps = <540>; + txd0-skew-ps = <420>; + txd1-skew-ps = <420>; + txd2-skew-ps = <420>; + txd3-skew-ps = <420>; + }; + }; +}; + +&sdmmc1 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_b>; + pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_dir_pins_b>; + pinctrl-2 = <&sdmmc1_b4_sleep_pins_a &sdmmc1_dir_sleep_pins_b>; + cd-gpios = <&gpioi 8 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + disable-wp; + st,sig-dir; + st,neg-edge; + st,use-ckin; + bus-width = <4>; + vmmc-supply = <&vdd_sd>; + vqmmc-supply = <&sd_switch>; + status = "okay"; +}; + +&sdmmc2 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_c>; + pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_c>; + pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_c>; + bus-width = <8>; + mmc-ddr-1_8v; + no-sd; + no-sdio; + non-removable; + st,neg-edge; + vmmc-supply = <&v3v3>; + vqmmc-supply = <&v3v3>; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&uart4_pins_b>; + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; +}; + +&uart7 { + pinctrl-names = "default"; + pinctrl-0 = <&uart7_pins_a>; + uart-has-rtscts; + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; +}; + +&usbh_ehci { + phys = <&usbphyc_port0>; + phy-names = "usb"; + status = "okay"; +}; + +&usbotg_hs { + pinctrl-0 = <&usbotg_hs_pins_a>; + pinctrl-names = "default"; + phy-names = "usb2-phy"; + phys = <&usbphyc_port1 0>; + status = "okay"; + vbus-supply = <&vbus_otg>; +}; + +&usbphyc { + status = "okay"; +}; + +&usbphyc_port0 { + phy-supply = <&vdd_usb>; +}; + +&usbphyc_port1 { + phy-supply = <&vdd_usb>; +}; + +&vdd { + /delete-property/ regulator-always-on; + regulator-min-microvolt = <1200000>; +}; diff --git a/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi b/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi index 19f4221f876..25a288b0475 100644 --- a/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi +++ b/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi @@ -144,6 +144,21 @@ CLK_LPTIM45_LSE >; + /* + * cfg = < DIVM1 DIVN P Q R PQR(p,q,r) >; + * frac = < f >; + * + * PRQ(p,q,r) ... for p,q,r: 0-output disabled / 1-output enabled + * DIVN ... actually multiplier, but RCC_PLL1CFGR1 calls the field DIVN + * m ... for PLL1,2: m=2 ; for PLL3,4: m=1 + * XTAL = 24 MHz + * + * VCO = ( XTAL / (DIVM1 + 1) ) * m * ( DIVN + 1 + ( f / 8192 ) ) + * P = VCO / (P + 1) + * Q = VCO / (Q + 1) + * R = VCO / (R + 1) + */ + /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */ pll2: st,pll@1 { compatible = "st,stm32mp1-pll"; @@ -162,7 +177,7 @@ u-boot,dm-pre-reloc; }; - /* VCO = 600.0 MHz => P = 99, Q = 74, R = 99 */ + /* VCO = 594.0 MHz => P = 99, Q = 74, R = 99 */ pll4: st,pll@3 { compatible = "st,stm32mp1-pll"; reg = <3>; diff --git a/arch/arm/dts/sun4i-a10-inet9f-rev03.dts b/arch/arm/dts/sun4i-a10-inet9f-rev03.dts index 0a562b2cc5b..62e7aa587f8 100644 --- a/arch/arm/dts/sun4i-a10-inet9f-rev03.dts +++ b/arch/arm/dts/sun4i-a10-inet9f-rev03.dts @@ -63,7 +63,7 @@ compatible = "gpio-keys-polled"; poll-interval = <20>; - left-joystick-left { + event-left-joystick-left { label = "Left Joystick Left"; linux,code = <ABS_X>; linux,input-type = <EV_ABS>; @@ -71,7 +71,7 @@ gpios = <&pio 0 6 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA6 */ }; - left-joystick-right { + event-left-joystick-right { label = "Left Joystick Right"; linux,code = <ABS_X>; linux,input-type = <EV_ABS>; @@ -79,7 +79,7 @@ gpios = <&pio 0 5 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA5 */ }; - left-joystick-up { + event-left-joystick-up { label = "Left Joystick Up"; linux,code = <ABS_Y>; linux,input-type = <EV_ABS>; @@ -87,7 +87,7 @@ gpios = <&pio 0 8 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA8 */ }; - left-joystick-down { + event-left-joystick-down { label = "Left Joystick Down"; linux,code = <ABS_Y>; linux,input-type = <EV_ABS>; @@ -95,7 +95,7 @@ gpios = <&pio 0 9 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA9 */ }; - right-joystick-left { + event-right-joystick-left { label = "Right Joystick Left"; linux,code = <ABS_Z>; linux,input-type = <EV_ABS>; @@ -103,7 +103,7 @@ gpios = <&pio 0 1 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA1 */ }; - right-joystick-right { + event-right-joystick-right { label = "Right Joystick Right"; linux,code = <ABS_Z>; linux,input-type = <EV_ABS>; @@ -111,7 +111,7 @@ gpios = <&pio 0 0 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA0 */ }; - right-joystick-up { + event-right-joystick-up { label = "Right Joystick Up"; linux,code = <ABS_RZ>; linux,input-type = <EV_ABS>; @@ -119,7 +119,7 @@ gpios = <&pio 0 3 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA3 */ }; - right-joystick-down { + event-right-joystick-down { label = "Right Joystick Down"; linux,code = <ABS_RZ>; linux,input-type = <EV_ABS>; @@ -127,7 +127,7 @@ gpios = <&pio 0 4 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA4 */ }; - dpad-left { + event-dpad-left { label = "DPad Left"; linux,code = <ABS_HAT0X>; linux,input-type = <EV_ABS>; @@ -135,7 +135,7 @@ gpios = <&pio 7 23 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PH23 */ }; - dpad-right { + event-dpad-right { label = "DPad Right"; linux,code = <ABS_HAT0X>; linux,input-type = <EV_ABS>; @@ -143,7 +143,7 @@ gpios = <&pio 7 24 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PH24 */ }; - dpad-up { + event-dpad-up { label = "DPad Up"; linux,code = <ABS_HAT0Y>; linux,input-type = <EV_ABS>; @@ -151,7 +151,7 @@ gpios = <&pio 7 25 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PH25 */ }; - dpad-down { + event-dpad-down { label = "DPad Down"; linux,code = <ABS_HAT0Y>; linux,input-type = <EV_ABS>; @@ -159,49 +159,49 @@ gpios = <&pio 7 26 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PH26 */ }; - x { + event-x { label = "Button X"; linux,code = <BTN_X>; gpios = <&pio 0 16 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA16 */ }; - y { + event-y { label = "Button Y"; linux,code = <BTN_Y>; gpios = <&pio 0 14 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA14 */ }; - a { + event-a { label = "Button A"; linux,code = <BTN_A>; gpios = <&pio 0 17 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA17 */ }; - b { + event-b { label = "Button B"; linux,code = <BTN_B>; gpios = <&pio 0 15 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA15 */ }; - select { + event-select { label = "Select Button"; linux,code = <BTN_SELECT>; gpios = <&pio 0 11 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA11 */ }; - start { + event-start { label = "Start Button"; linux,code = <BTN_START>; gpios = <&pio 0 12 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA12 */ }; - top-left { + event-top-left { label = "Top Left Button"; linux,code = <BTN_TL>; gpios = <&pio 7 22 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PH22 */ }; - top-right { + event-top-right { label = "Top Right Button"; linux,code = <BTN_TR>; gpios = <&pio 0 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA13 */ diff --git a/arch/arm/dts/sun4i-a10-pcduino.dts b/arch/arm/dts/sun4i-a10-pcduino.dts index 1ac82376bae..a332d61fd56 100644 --- a/arch/arm/dts/sun4i-a10-pcduino.dts +++ b/arch/arm/dts/sun4i-a10-pcduino.dts @@ -77,19 +77,19 @@ gpio-keys { compatible = "gpio-keys"; - back { + key-back { label = "Key Back"; linux,code = <KEY_BACK>; gpios = <&pio 7 17 GPIO_ACTIVE_LOW>; }; - home { + key-home { label = "Key Home"; linux,code = <KEY_HOME>; gpios = <&pio 7 18 GPIO_ACTIVE_LOW>; }; - menu { + key-menu { label = "Key Menu"; linux,code = <KEY_MENU>; gpios = <&pio 7 19 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/dts/sun50i-a64-amarula-relic.dts b/arch/arm/dts/sun50i-a64-amarula-relic.dts index c7bd73f35ed..ce8f6aa164e 100644 --- a/arch/arm/dts/sun50i-a64-amarula-relic.dts +++ b/arch/arm/dts/sun50i-a64-amarula-relic.dts @@ -58,7 +58,7 @@ wifi_pwrseq: wifi-pwrseq { compatible = "mmc-pwrseq-simple"; - clocks = <&rtc 1>; + clocks = <&rtc CLK_OSC32K_FANOUT>; clock-names = "ext_clock"; reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* WL-PMU-EN: PL2 */ }; diff --git a/arch/arm/dts/sun50i-a64-bananapi-m64.dts b/arch/arm/dts/sun50i-a64-bananapi-m64.dts index f7fe9fa50cb..bf66b640816 100644 --- a/arch/arm/dts/sun50i-a64-bananapi-m64.dts +++ b/arch/arm/dts/sun50i-a64-bananapi-m64.dts @@ -56,7 +56,7 @@ wifi_pwrseq: wifi_pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */ - clocks = <&rtc 1>; + clocks = <&rtc CLK_OSC32K_FANOUT>; clock-names = "ext_clock"; }; }; @@ -355,7 +355,7 @@ bluetooth { compatible = "brcm,bcm43438-bt"; - clocks = <&rtc 1>; + clocks = <&rtc CLK_OSC32K_FANOUT>; clock-names = "lpo"; vbat-supply = <®_dldo2>; vddio-supply = <®_dldo4>; diff --git a/arch/arm/dts/sun50i-a64-nanopi-a64.dts b/arch/arm/dts/sun50i-a64-nanopi-a64.dts index 09b3c7fb82c..ffc3b4c7068 100644 --- a/arch/arm/dts/sun50i-a64-nanopi-a64.dts +++ b/arch/arm/dts/sun50i-a64-nanopi-a64.dts @@ -43,7 +43,7 @@ wifi_pwrseq: wifi_pwrseq { compatible = "mmc-pwrseq-simple"; - clocks = <&rtc 1>; + clocks = <&rtc CLK_OSC32K_FANOUT>; clock-names = "ext_clock"; reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */ }; diff --git a/arch/arm/dts/sun50i-a64-olinuxino.dts b/arch/arm/dts/sun50i-a64-olinuxino.dts index f3f8e177ab6..22d350249c1 100644 --- a/arch/arm/dts/sun50i-a64-olinuxino.dts +++ b/arch/arm/dts/sun50i-a64-olinuxino.dts @@ -58,6 +58,15 @@ }; }; +&codec { + status = "okay"; +}; + +&codec_analog { + cpvdd-supply = <®_eldo1>; + status = "okay"; +}; + &cpu0 { cpu-supply = <®_dcdc2>; }; @@ -74,6 +83,10 @@ cpu-supply = <®_dcdc2>; }; +&dai { + status = "okay"; +}; + &de { status = "okay"; }; @@ -328,6 +341,23 @@ vcc-hdmi-supply = <®_dldo1>; }; +&sound { + simple-audio-card,aux-devs = <&codec_analog>; + simple-audio-card,widgets = "Microphone", "Microphone Jack Left", + "Microphone", "Microphone Jack Right", + "Headphone", "Headphone Jack"; + simple-audio-card,routing = "Left DAC", "DACL", + "Right DAC", "DACR", + "Headphone Jack", "HP", + "ADCL", "Left ADC", + "ADCR", "Right ADC", + "Microphone Jack Left", "MBIAS", + "MIC1", "Microphone Jack Left", + "Microphone Jack Right", "MBIAS", + "MIC2", "Microphone Jack Right"; + status = "okay"; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pb_pins>; diff --git a/arch/arm/dts/sun50i-a64-orangepi-win.dts b/arch/arm/dts/sun50i-a64-orangepi-win.dts index 8eee8051ac5..714a270a558 100644 --- a/arch/arm/dts/sun50i-a64-orangepi-win.dts +++ b/arch/arm/dts/sun50i-a64-orangepi-win.dts @@ -40,7 +40,7 @@ leds { compatible = "gpio-leds"; - status { + led-0 { label = "orangepi:green:status"; gpios = <&pio 7 11 GPIO_ACTIVE_HIGH>; /* PH11 */ }; @@ -71,7 +71,7 @@ wifi_pwrseq: wifi_pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&r_pio 0 8 GPIO_ACTIVE_LOW>; /* PL8 */ - clocks = <&rtc 1>; + clocks = <&rtc CLK_OSC32K_FANOUT>; clock-names = "ext_clock"; }; }; @@ -369,7 +369,7 @@ bluetooth { compatible = "brcm,bcm43438-bt"; max-speed = <1500000>; - clocks = <&rtc 1>; + clocks = <&rtc CLK_OSC32K_FANOUT>; clock-names = "lpo"; vbat-supply = <®_dldo2>; vddio-supply = <®_dldo4>; diff --git a/arch/arm/dts/sun50i-a64-pinebook.dts b/arch/arm/dts/sun50i-a64-pinebook.dts index 68b6ab4707c..c00c4c1e9e7 100644 --- a/arch/arm/dts/sun50i-a64-pinebook.dts +++ b/arch/arm/dts/sun50i-a64-pinebook.dts @@ -35,10 +35,10 @@ stdout-path = "serial0:115200n8"; }; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; - lid_switch { + lid-switch { label = "Lid Switch"; gpios = <&r_pio 0 12 GPIO_ACTIVE_LOW>; /* PL12 */ linux,input-type = <EV_SW>; diff --git a/arch/arm/dts/sun50i-a64-pinephone-1.0.dts b/arch/arm/dts/sun50i-a64-pinephone-1.0.dts index fb65319a3bd..219f720b8b7 100644 --- a/arch/arm/dts/sun50i-a64-pinephone-1.0.dts +++ b/arch/arm/dts/sun50i-a64-pinephone-1.0.dts @@ -10,6 +10,10 @@ compatible = "pine64,pinephone-1.0", "pine64,pinephone", "allwinner,sun50i-a64"; }; +&codec_analog { + allwinner,internal-bias-resistor; +}; + &sgm3140 { enable-gpios = <&pio 2 3 GPIO_ACTIVE_HIGH>; /* PC3 */ flash-gpios = <&pio 3 24 GPIO_ACTIVE_HIGH>; /* PD24 */ diff --git a/arch/arm/dts/sun50i-a64-pinephone-1.1.dts b/arch/arm/dts/sun50i-a64-pinephone-1.1.dts index 5e59d375217..723af64a9ce 100644 --- a/arch/arm/dts/sun50i-a64-pinephone-1.1.dts +++ b/arch/arm/dts/sun50i-a64-pinephone-1.1.dts @@ -29,6 +29,10 @@ default-brightness-level = <400>; }; +&codec_analog { + allwinner,internal-bias-resistor; +}; + &sgm3140 { enable-gpios = <&pio 3 24 GPIO_ACTIVE_HIGH>; /* PD24 */ flash-gpios = <&pio 2 3 GPIO_ACTIVE_HIGH>; /* PC3 */ diff --git a/arch/arm/dts/sun50i-a64-teres-i.dts b/arch/arm/dts/sun50i-a64-teres-i.dts index 6668431dcb4..945afdb508d 100644 --- a/arch/arm/dts/sun50i-a64-teres-i.dts +++ b/arch/arm/dts/sun50i-a64-teres-i.dts @@ -197,6 +197,14 @@ status = "okay"; }; +&pio { + vcc-pc-supply = <®_dcdc1>; + vcc-pd-supply = <®_dldo2>; + vcc-pe-supply = <®_aldo1>; + vcc-pf-supply = <®_dcdc1>; /* No dedicated supply-pin for this */ + vcc-pg-supply = <®_aldo2>; +}; + &pwm { status = "okay"; }; diff --git a/arch/arm/dts/sun50i-a64.dtsi b/arch/arm/dts/sun50i-a64.dtsi index 555bc92a6f8..b04f492c0f2 100644 --- a/arch/arm/dts/sun50i-a64.dtsi +++ b/arch/arm/dts/sun50i-a64.dtsi @@ -4,6 +4,7 @@ // Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com> #include <dt-bindings/clock/sun50i-a64-ccu.h> +#include <dt-bindings/clock/sun6i-rtc.h> #include <dt-bindings/clock/sun8i-de2.h> #include <dt-bindings/clock/sun8i-r-ccu.h> #include <dt-bindings/interrupt-controller/arm-gic.h> @@ -660,7 +661,7 @@ ccu: clock@1c20000 { compatible = "allwinner,sun50i-a64-ccu"; reg = <0x01c20000 0x400>; - clocks = <&osc24M>, <&rtc 0>; + clocks = <&osc24M>, <&rtc CLK_OSC32K>; clock-names = "hosc", "losc"; #clock-cells = <1>; #reset-cells = <1>; @@ -672,7 +673,8 @@ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>; + clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, + <&rtc CLK_OSC32K>; clock-names = "apb", "hosc", "losc"; gpio-controller; #gpio-cells = <3>; @@ -1224,7 +1226,7 @@ reg-io-width = <1>; interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>, - <&ccu CLK_HDMI>, <&rtc 0>; + <&ccu CLK_HDMI>, <&rtc CLK_OSC32K>; clock-names = "iahb", "isfr", "tmds", "cec"; resets = <&ccu RST_BUS_HDMI1>; reset-names = "ctrl"; @@ -1284,7 +1286,7 @@ r_ccu: clock@1f01400 { compatible = "allwinner,sun50i-a64-r-ccu"; reg = <0x01f01400 0x100>; - clocks = <&osc24M>, <&rtc 0>, <&rtc 2>, + clocks = <&osc24M>, <&rtc CLK_OSC32K>, <&rtc CLK_IOSC>, <&ccu CLK_PLL_PERIPH0>; clock-names = "hosc", "losc", "iosc", "pll-periph"; #clock-cells = <1>; diff --git a/arch/arm/dts/sun50i-h5-nanopi-r1s-h5.dts b/arch/arm/dts/sun50i-h5-nanopi-r1s-h5.dts index 55b369534a0..a3e040da38a 100644 --- a/arch/arm/dts/sun50i-h5-nanopi-r1s-h5.dts +++ b/arch/arm/dts/sun50i-h5-nanopi-r1s-h5.dts @@ -52,10 +52,10 @@ }; }; - r-gpio-keys { + gpio-keys { compatible = "gpio-keys"; - reset { + key-reset { label = "reset"; linux,code = <KEY_RESTART>; gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/dts/sun50i-h5-orangepi-pc2.dts b/arch/arm/dts/sun50i-h5-orangepi-pc2.dts index 1010c1b22d2..b5c1ff19b4c 100644 --- a/arch/arm/dts/sun50i-h5-orangepi-pc2.dts +++ b/arch/arm/dts/sun50i-h5-orangepi-pc2.dts @@ -54,10 +54,10 @@ }; }; - r-gpio-keys { + gpio-keys { compatible = "gpio-keys"; - sw4 { + key-sw4 { label = "sw4"; linux,code = <BTN_0>; gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/dts/sun50i-h5-orangepi-prime.dts b/arch/arm/dts/sun50i-h5-orangepi-prime.dts index 74e0444af19..d7f8bad6bb9 100644 --- a/arch/arm/dts/sun50i-h5-orangepi-prime.dts +++ b/arch/arm/dts/sun50i-h5-orangepi-prime.dts @@ -48,10 +48,10 @@ }; }; - r-gpio-keys { + gpio-keys { compatible = "gpio-keys"; - sw4 { + key-sw4 { label = "sw4"; linux,code = <BTN_0>; gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/dts/sun50i-h6-orangepi-3.dts b/arch/arm/dts/sun50i-h6-orangepi-3.dts index 9f12c05e21f..f1957bb1edb 100644 --- a/arch/arm/dts/sun50i-h6-orangepi-3.dts +++ b/arch/arm/dts/sun50i-h6-orangepi-3.dts @@ -86,7 +86,7 @@ wifi_pwrseq: wifi-pwrseq { compatible = "mmc-pwrseq-simple"; - clocks = <&rtc 1>; + clocks = <&rtc CLK_OSC32K_FANOUT>; clock-names = "ext_clock"; reset-gpios = <&r_pio 1 3 GPIO_ACTIVE_LOW>; /* PM3 */ post-power-on-delay-ms = <200>; @@ -314,7 +314,7 @@ bluetooth { compatible = "brcm,bcm4345c5"; - clocks = <&rtc 1>; + clocks = <&rtc CLK_OSC32K_FANOUT>; clock-names = "lpo"; device-wakeup-gpios = <&r_pio 1 2 GPIO_ACTIVE_HIGH>; /* PM2 */ host-wakeup-gpios = <&r_pio 1 1 GPIO_ACTIVE_HIGH>; /* PM1 */ diff --git a/arch/arm/dts/sun50i-h6-orangepi-lite2.dts b/arch/arm/dts/sun50i-h6-orangepi-lite2.dts index e8770858b5d..fb31dcb1cb6 100644 --- a/arch/arm/dts/sun50i-h6-orangepi-lite2.dts +++ b/arch/arm/dts/sun50i-h6-orangepi-lite2.dts @@ -13,7 +13,7 @@ wifi_pwrseq: wifi_pwrseq { compatible = "mmc-pwrseq-simple"; - clocks = <&rtc 1>; + clocks = <&rtc CLK_OSC32K_FANOUT>; clock-names = "ext_clock"; reset-gpios = <&r_pio 1 3 GPIO_ACTIVE_LOW>; /* PM3 */ post-power-on-delay-ms = <200>; @@ -64,7 +64,7 @@ bluetooth { compatible = "brcm,bcm4345c5"; - clocks = <&rtc 1>; + clocks = <&rtc CLK_OSC32K_FANOUT>; clock-names = "lpo"; device-wakeup-gpios = <&r_pio 1 2 GPIO_ACTIVE_HIGH>; /* PM2 */ host-wakeup-gpios = <&r_pio 1 1 GPIO_ACTIVE_HIGH>; /* PM1 */ diff --git a/arch/arm/dts/sun50i-h6-tanix.dtsi b/arch/arm/dts/sun50i-h6-tanix.dtsi index edb71e4a030..4903d635811 100644 --- a/arch/arm/dts/sun50i-h6-tanix.dtsi +++ b/arch/arm/dts/sun50i-h6-tanix.dtsi @@ -78,7 +78,7 @@ wifi_pwrseq: wifi-pwrseq { compatible = "mmc-pwrseq-simple"; - clocks = <&rtc 1>; + clocks = <&rtc CLK_OSC32K_FANOUT>; clock-names = "ext_clock"; reset-gpios = <&r_pio 1 3 GPIO_ACTIVE_LOW>; /* PM3 */ }; diff --git a/arch/arm/dts/sun50i-h6.dtsi b/arch/arm/dts/sun50i-h6.dtsi index 71a45a624da..afbbfc25269 100644 --- a/arch/arm/dts/sun50i-h6.dtsi +++ b/arch/arm/dts/sun50i-h6.dtsi @@ -4,6 +4,7 @@ #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/clock/sun50i-h6-ccu.h> #include <dt-bindings/clock/sun50i-h6-r-ccu.h> +#include <dt-bindings/clock/sun6i-rtc.h> #include <dt-bindings/clock/sun8i-de2.h> #include <dt-bindings/clock/sun8i-tcon-top.h> #include <dt-bindings/reset/sun50i-h6-ccu.h> @@ -237,7 +238,7 @@ ccu: clock@3001000 { compatible = "allwinner,sun50i-h6-ccu"; reg = <0x03001000 0x1000>; - clocks = <&osc24M>, <&rtc 0>, <&rtc 2>; + clocks = <&osc24M>, <&rtc CLK_OSC32K>, <&rtc CLK_IOSC>; clock-names = "hosc", "losc", "iosc"; #clock-cells = <1>; #reset-cells = <1>; @@ -316,7 +317,7 @@ <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_APB1>, <&osc24M>, <&rtc 0>; + clocks = <&ccu CLK_APB1>, <&osc24M>, <&rtc CLK_OSC32K>; clock-names = "apb", "hosc", "losc"; gpio-controller; #gpio-cells = <3>; @@ -724,7 +725,7 @@ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_BUS_XHCI>, <&ccu CLK_BUS_XHCI>, - <&rtc 0>; + <&rtc CLK_OSC32K>; clock-names = "ref", "bus_early", "suspend"; resets = <&ccu RST_BUS_XHCI>; /* @@ -929,7 +930,7 @@ r_ccu: clock@7010000 { compatible = "allwinner,sun50i-h6-r-ccu"; reg = <0x07010000 0x400>; - clocks = <&osc24M>, <&rtc 0>, <&rtc 2>, + clocks = <&osc24M>, <&rtc CLK_OSC32K>, <&rtc CLK_IOSC>, <&ccu CLK_PLL_PERIPH0>; clock-names = "hosc", "losc", "iosc", "pll-periph"; #clock-cells = <1>; @@ -958,7 +959,8 @@ reg = <0x07022000 0x400>; interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&r_ccu CLK_R_APB1>, <&osc24M>, <&rtc 0>; + clocks = <&r_ccu CLK_R_APB1>, <&osc24M>, + <&rtc CLK_OSC32K>; clock-names = "apb", "hosc", "losc"; gpio-controller; #gpio-cells = <3>; diff --git a/arch/arm/dts/sun50i-h616-orangepi-zero2.dts b/arch/arm/dts/sun50i-h616-orangepi-zero2.dts index e6de49f89e3..02893f3ac99 100644 --- a/arch/arm/dts/sun50i-h616-orangepi-zero2.dts +++ b/arch/arm/dts/sun50i-h616-orangepi-zero2.dts @@ -49,29 +49,8 @@ regulator-max-microvolt = <5000000>; regulator-always-on; }; - - reg_usb1_vbus: usb1-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb1-vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <®_vcc5v>; - enable-active-high; - gpio = <&pio 2 16 GPIO_ACTIVE_HIGH>; /* PC16 */ - status = "okay"; - }; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; }; -/* USB 2 & 3 are on headers only. */ - &emac0 { pinctrl-names = "default"; pinctrl-0 = <&ext_rgmii_pins>; @@ -97,14 +76,6 @@ status = "okay"; }; -&ohci0 { - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - &r_rsb { status = "okay"; @@ -181,14 +152,14 @@ reg_dcdca: dcdca { regulator-always-on; regulator-min-microvolt = <810000>; - regulator-max-microvolt = <1080000>; + regulator-max-microvolt = <1100000>; regulator-name = "vdd-cpu"; }; reg_dcdcc: dcdcc { regulator-always-on; regulator-min-microvolt = <810000>; - regulator-max-microvolt = <1080000>; + regulator-max-microvolt = <990000>; regulator-name = "vdd-gpu-sys"; }; @@ -200,7 +171,7 @@ }; reg_dcdce: dcdce { - regulator-boot-on; + regulator-always-on; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-name = "vcc-eth-mmc"; @@ -213,8 +184,18 @@ }; }; +&pio { + vcc-pc-supply = <®_aldo1>; + vcc-pf-supply = <®_aldo1>; + vcc-pg-supply = <®_bldo1>; + vcc-ph-supply = <®_aldo1>; + vcc-pi-supply = <®_aldo1>; +}; + &spi0 { status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pins>, <&spi0_cs0_pin>; flash@0 { #address-cells = <1>; @@ -230,13 +211,3 @@ pinctrl-0 = <&uart0_ph_pins>; status = "okay"; }; - -&usbotg { - dr_mode = "peripheral"; - status = "okay"; -}; - -&usbphy { - usb1_vbus-supply = <®_usb1_vbus>; - status = "okay"; -}; diff --git a/arch/arm/dts/sun50i-h616-x96-mate.dts b/arch/arm/dts/sun50i-h616-x96-mate.dts new file mode 100644 index 00000000000..6619db34714 --- /dev/null +++ b/arch/arm/dts/sun50i-h616-x96-mate.dts @@ -0,0 +1,177 @@ +// SPDX-License-Identifier: (GPL-2.0+ or MIT) +/* + * Copyright (C) 2021 Arm Ltd. + */ + +/dts-v1/; + +#include "sun50i-h616.dtsi" + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/ { + model = "X96 Mate"; + compatible = "hechuang,x96-mate", "allwinner,sun50i-h616"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + reg_vcc5v: vcc5v { + /* board wide 5V supply directly from the DC input */ + compatible = "regulator-fixed"; + regulator-name = "vcc-5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; +}; + +&ir { + status = "okay"; +}; + +&mmc0 { + vmmc-supply = <®_dcdce>; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ + bus-width = <4>; + status = "okay"; +}; + +&mmc2 { + vmmc-supply = <®_dcdce>; + vqmmc-supply = <®_bldo1>; + bus-width = <8>; + non-removable; + cap-mmc-hw-reset; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + status = "okay"; +}; + +&r_rsb { + status = "okay"; + + axp305: pmic@745 { + compatible = "x-powers,axp305", "x-powers,axp805", + "x-powers,axp806"; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0x745>; + + x-powers,self-working-mode; + vina-supply = <®_vcc5v>; + vinb-supply = <®_vcc5v>; + vinc-supply = <®_vcc5v>; + vind-supply = <®_vcc5v>; + vine-supply = <®_vcc5v>; + aldoin-supply = <®_vcc5v>; + bldoin-supply = <®_vcc5v>; + cldoin-supply = <®_vcc5v>; + + regulators { + reg_aldo1: aldo1 { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-sys"; + }; + + /* Enabled by the Android BSP */ + reg_aldo2: aldo2 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc3v3-ext"; + status = "disabled"; + }; + + /* Enabled by the Android BSP */ + reg_aldo3: aldo3 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc3v3-ext2"; + status = "disabled"; + }; + + reg_bldo1: bldo1 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc1v8"; + }; + + /* Enabled by the Android BSP */ + reg_bldo2: bldo2 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc1v8-2"; + status = "disabled"; + }; + + bldo3 { + /* unused */ + }; + + bldo4 { + /* unused */ + }; + + cldo1 { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-name = "vcc2v5"; + }; + + cldo2 { + /* unused */ + }; + + cldo3 { + /* unused */ + }; + + reg_dcdca: dcdca { + regulator-always-on; + regulator-min-microvolt = <810000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-cpu"; + }; + + reg_dcdcc: dcdcc { + regulator-always-on; + regulator-min-microvolt = <810000>; + regulator-max-microvolt = <990000>; + regulator-name = "vdd-gpu-sys"; + }; + + reg_dcdcd: dcdcd { + regulator-always-on; + regulator-min-microvolt = <1360000>; + regulator-max-microvolt = <1360000>; + regulator-name = "vdd-dram"; + }; + + reg_dcdce: dcdce { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-eth-mmc"; + }; + + sw { + /* unused */ + }; + }; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_ph_pins>; + status = "okay"; +}; diff --git a/arch/arm/dts/sun50i-h616.dtsi b/arch/arm/dts/sun50i-h616.dtsi index 2f71e853e96..622a1f7d164 100644 --- a/arch/arm/dts/sun50i-h616.dtsi +++ b/arch/arm/dts/sun50i-h616.dtsi @@ -6,6 +6,7 @@ #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/clock/sun50i-h616-ccu.h> #include <dt-bindings/clock/sun50i-h6-r-ccu.h> +#include <dt-bindings/clock/sun6i-rtc.h> #include <dt-bindings/reset/sun50i-h616-ccu.h> #include <dt-bindings/reset/sun50i-h6-r-ccu.h> @@ -51,7 +52,23 @@ }; }; - osc24M: osc24M_clk { + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* + * 256 KiB reserved for Trusted Firmware-A (BL31). + * This is added by BL31 itself, but some bootloaders fail + * to propagate this into the DTB handed to kernels. + */ + secmon@40000000 { + reg = <0x0 0x40000000 0x0 0x40000>; + no-map; + }; + }; + + osc24M: osc24M-clk { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <24000000>; @@ -110,7 +127,7 @@ ccu: clock@3001000 { compatible = "allwinner,sun50i-h616-ccu"; reg = <0x03001000 0x1000>; - clocks = <&osc24M>, <&rtc 0>, <&rtc 2>; + clocks = <&osc24M>, <&rtc CLK_OSC32K>, <&rtc CLK_IOSC>; clock-names = "hosc", "losc", "iosc"; #clock-cells = <1>; #reset-cells = <1>; @@ -135,7 +152,7 @@ <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_APB1>, <&osc24M>, <&rtc 0>; + clocks = <&ccu CLK_APB1>, <&osc24M>, <&rtc CLK_OSC32K>; clock-names = "apb", "hosc", "losc"; gpio-controller; #gpio-cells = <3>; @@ -161,7 +178,7 @@ function = "i2c3"; }; - ir_rx_pin: ir_rx_pin { + ir_rx_pin: ir-rx-pin { pins = "PH10"; function = "ir_rx"; }; @@ -174,6 +191,7 @@ bias-pull-up; }; + /omit-if-no-ref/ mmc1_pins: mmc1-pins { pins = "PG0", "PG1", "PG2", "PG3", "PG4", "PG5"; @@ -191,17 +209,26 @@ bias-pull-up; }; + /omit-if-no-ref/ spi0_pins: spi0-pins { - pins = "PC0", "PC2", "PC3", "PC4"; + pins = "PC0", "PC2", "PC4"; function = "spi0"; }; + /omit-if-no-ref/ + spi0_cs0_pin: spi0-cs0-pin { + pins = "PC3"; + function = "spi0"; + }; + + /omit-if-no-ref/ spi1_pins: spi1-pins { pins = "PH6", "PH7", "PH8"; function = "spi1"; }; - spi1_cs_pin: spi1-cs-pin { + /omit-if-no-ref/ + spi1_cs0_pin: spi1-cs0-pin { pins = "PH5"; function = "spi1"; }; @@ -211,11 +238,13 @@ function = "uart0"; }; + /omit-if-no-ref/ uart1_pins: uart1-pins { pins = "PG6", "PG7"; function = "uart1"; }; + /omit-if-no-ref/ uart1_rts_cts_pins: uart1-rts-cts-pins { pins = "PG8", "PG9"; function = "uart1"; @@ -245,10 +274,10 @@ pinctrl-names = "default"; pinctrl-0 = <&mmc0_pins>; status = "disabled"; + max-frequency = <150000000>; cap-sd-highspeed; cap-mmc-highspeed; mmc-ddr-3_3v; - mmc-ddr-1_8v; cap-sdio-irq; #address-cells = <1>; #size-cells = <0>; @@ -266,10 +295,10 @@ pinctrl-names = "default"; pinctrl-0 = <&mmc1_pins>; status = "disabled"; + max-frequency = <150000000>; cap-sd-highspeed; cap-mmc-highspeed; mmc-ddr-3_3v; - mmc-ddr-1_8v; cap-sdio-irq; #address-cells = <1>; #size-cells = <0>; @@ -287,10 +316,10 @@ pinctrl-names = "default"; pinctrl-0 = <&mmc2_pins>; status = "disabled"; + max-frequency = <150000000>; cap-sd-highspeed; cap-mmc-highspeed; mmc-ddr-3_3v; - mmc-ddr-1_8v; cap-sdio-irq; #address-cells = <1>; #size-cells = <0>; @@ -364,6 +393,7 @@ i2c0: i2c@5002000 { compatible = "allwinner,sun50i-h616-i2c", + "allwinner,sun8i-v536-i2c", "allwinner,sun6i-a31-i2c"; reg = <0x05002000 0x400>; interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; @@ -378,6 +408,7 @@ i2c1: i2c@5002400 { compatible = "allwinner,sun50i-h616-i2c", + "allwinner,sun8i-v536-i2c", "allwinner,sun6i-a31-i2c"; reg = <0x05002400 0x400>; interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; @@ -390,6 +421,7 @@ i2c2: i2c@5002800 { compatible = "allwinner,sun50i-h616-i2c", + "allwinner,sun8i-v536-i2c", "allwinner,sun6i-a31-i2c"; reg = <0x05002800 0x400>; interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; @@ -402,6 +434,7 @@ i2c3: i2c@5002c00 { compatible = "allwinner,sun50i-h616-i2c", + "allwinner,sun8i-v536-i2c", "allwinner,sun6i-a31-i2c"; reg = <0x05002c00 0x400>; interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; @@ -414,6 +447,7 @@ i2c4: i2c@5003000 { compatible = "allwinner,sun50i-h616-i2c", + "allwinner,sun8i-v536-i2c", "allwinner,sun6i-a31-i2c"; reg = <0x05003000 0x400>; interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; @@ -432,8 +466,6 @@ clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; clock-names = "ahb", "mod"; resets = <&ccu RST_BUS_SPI0>; - pinctrl-names = "default"; - pinctrl-0 = <&spi0_pins>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; @@ -447,224 +479,46 @@ clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; clock-names = "ahb", "mod"; resets = <&ccu RST_BUS_SPI1>; - pinctrl-names = "default"; - pinctrl-0 = <&spi1_pins>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; }; emac0: ethernet@5020000 { - compatible = "allwinner,sun50i-h616-emac", + compatible = "allwinner,sun50i-h616-emac0", "allwinner,sun50i-a64-emac"; - syscon = <&syscon>; reg = <0x05020000 0x10000>; interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "macirq"; - resets = <&ccu RST_BUS_EMAC0>; - reset-names = "stmmaceth"; clocks = <&ccu CLK_BUS_EMAC0>; clock-names = "stmmaceth"; - status = "disabled"; - - mdio0: mdio { - compatible = "snps,dwmac-mdio"; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - emac1: ethernet@5030000 { - compatible = "allwinner,sun50i-h616-emac"; - syscon = <&syscon 1>; - reg = <0x05030000 0x10000>; - interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "macirq"; - resets = <&ccu RST_BUS_EMAC1>; + resets = <&ccu RST_BUS_EMAC0>; reset-names = "stmmaceth"; - clocks = <&ccu CLK_BUS_EMAC1>; - clock-names = "stmmaceth"; + syscon = <&syscon>; status = "disabled"; - mdio1: mdio { + mdio0: mdio { compatible = "snps,dwmac-mdio"; #address-cells = <1>; #size-cells = <0>; }; }; - usbotg: usb@5100000 { - compatible = "allwinner,sun50i-h616-musb", - "allwinner,sun8i-h3-musb"; - reg = <0x05100000 0x0400>; - clocks = <&ccu CLK_BUS_OTG>; - resets = <&ccu RST_BUS_OTG>; - interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "mc"; - phys = <&usbphy 0>; - phy-names = "usb"; - extcon = <&usbphy 0>; - status = "disabled"; - }; - - usbphy: phy@5100400 { - compatible = "allwinner,sun50i-h616-usb-phy"; - reg = <0x05100400 0x24>, - <0x05101800 0x14>, - <0x05200800 0x14>, - <0x05310800 0x14>, - <0x05311800 0x14>; - reg-names = "phy_ctrl", - "pmu0", - "pmu1", - "pmu2", - "pmu3"; - clocks = <&ccu CLK_USB_PHY0>, - <&ccu CLK_USB_PHY1>, - <&ccu CLK_USB_PHY2>, - <&ccu CLK_USB_PHY3>; - clock-names = "usb0_phy", - "usb1_phy", - "usb2_phy", - "usb3_phy"; - resets = <&ccu RST_USB_PHY0>, - <&ccu RST_USB_PHY1>, - <&ccu RST_USB_PHY2>, - <&ccu RST_USB_PHY3>; - reset-names = "usb0_reset", - "usb1_reset", - "usb2_reset", - "usb3_reset"; - status = "disabled"; - #phy-cells = <1>; - }; - - ehci0: usb@5101000 { - compatible = "allwinner,sun50i-h616-ehci", - "generic-ehci"; - reg = <0x05101000 0x100>; - interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_OHCI0>, - <&ccu CLK_BUS_EHCI0>, - <&ccu CLK_USB_OHCI0>; - resets = <&ccu RST_BUS_OHCI0>, - <&ccu RST_BUS_EHCI0>; - phys = <&usbphy 0>; - phy-names = "usb"; - status = "disabled"; - }; - - ohci0: usb@5101400 { - compatible = "allwinner,sun50i-h616-ohci", - "generic-ohci"; - reg = <0x05101400 0x100>; - interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_OHCI0>, - <&ccu CLK_USB_OHCI0>; - resets = <&ccu RST_BUS_OHCI0>; - phys = <&usbphy 0>; - phy-names = "usb"; - status = "disabled"; - }; - - ehci1: usb@5200000 { - compatible = "allwinner,sun50i-h616-ehci", - "generic-ehci"; - reg = <0x05200000 0x100>; - interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_OHCI1>, - <&ccu CLK_BUS_EHCI1>, - <&ccu CLK_USB_OHCI1>; - resets = <&ccu RST_BUS_OHCI1>, - <&ccu RST_BUS_EHCI1>; - phys = <&usbphy 1>; - phy-names = "usb"; - status = "disabled"; - }; - - ohci1: usb@5200400 { - compatible = "allwinner,sun50i-h616-ohci", - "generic-ohci"; - reg = <0x05200400 0x100>; - interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_OHCI1>, - <&ccu CLK_USB_OHCI1>; - resets = <&ccu RST_BUS_OHCI1>; - phys = <&usbphy 1>; - phy-names = "usb"; - status = "disabled"; - }; - - ehci2: usb@5310000 { - compatible = "allwinner,sun50i-h616-ehci", - "generic-ehci"; - reg = <0x05310000 0x100>; - interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_OHCI2>, - <&ccu CLK_BUS_EHCI2>, - <&ccu CLK_USB_OHCI2>; - resets = <&ccu RST_BUS_OHCI2>, - <&ccu RST_BUS_EHCI2>; - phys = <&usbphy 2>; - phy-names = "usb"; - status = "disabled"; - }; - - ohci2: usb@5310400 { - compatible = "allwinner,sun50i-h616-ohci", - "generic-ohci"; - reg = <0x05310400 0x100>; - interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_OHCI2>, - <&ccu CLK_USB_OHCI2>; - resets = <&ccu RST_BUS_OHCI2>; - phys = <&usbphy 2>; - phy-names = "usb"; - status = "disabled"; - }; - - ehci3: usb@5311000 { - compatible = "allwinner,sun50i-h616-ehci", - "generic-ehci"; - reg = <0x05311000 0x100>; - interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_OHCI3>, - <&ccu CLK_BUS_EHCI3>, - <&ccu CLK_USB_OHCI3>; - resets = <&ccu RST_BUS_OHCI3>, - <&ccu RST_BUS_EHCI3>; - phys = <&usbphy 3>; - phy-names = "usb"; - status = "disabled"; - }; - - ohci3: usb@5311400 { - compatible = "allwinner,sun50i-h616-ohci", - "generic-ohci"; - reg = <0x05311400 0x100>; - interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_OHCI3>, - <&ccu CLK_USB_OHCI3>; - resets = <&ccu RST_BUS_OHCI3>; - phys = <&usbphy 3>; - phy-names = "usb"; - status = "disabled"; - }; - rtc: rtc@7000000 { - compatible = "allwinner,sun50i-h616-rtc", - "allwinner,sun50i-h6-rtc"; + compatible = "allwinner,sun50i-h616-rtc"; reg = <0x07000000 0x400>; - interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; - clock-output-names = "osc32k", "osc32k-out", "iosc"; + interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&r_ccu CLK_R_APB1_RTC>, <&osc24M>, + <&ccu CLK_PLL_SYSTEM_32K>; + clock-names = "bus", "hosc", + "pll-32k"; #clock-cells = <1>; }; r_ccu: clock@7010000 { compatible = "allwinner,sun50i-h616-r-ccu"; - reg = <0x07010000 0x400>; - clocks = <&osc24M>, <&rtc 0>, <&rtc 2>, + reg = <0x07010000 0x210>; + clocks = <&osc24M>, <&rtc CLK_OSC32K>, <&rtc CLK_IOSC>, <&ccu CLK_PLL_PERIPH0>; clock-names = "hosc", "losc", "iosc", "pll-periph"; #clock-cells = <1>; @@ -674,14 +528,13 @@ r_pio: pinctrl@7022000 { compatible = "allwinner,sun50i-h616-r-pinctrl"; reg = <0x07022000 0x400>; - interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&r_ccu CLK_R_APB1>, <&osc24M>, <&rtc 0>; + clocks = <&r_ccu CLK_R_APB1>, <&osc24M>, + <&rtc CLK_OSC32K>; clock-names = "apb", "hosc", "losc"; gpio-controller; #gpio-cells = <3>; - interrupt-controller; - #interrupt-cells = <3>; + /omit-if-no-ref/ r_i2c_pins: r-i2c-pins { pins = "PL0", "PL1"; function = "s_i2c"; @@ -694,21 +547,22 @@ }; ir: ir@7040000 { - compatible = "allwinner,sun50i-h616-ir", - "allwinner,sun6i-a31-ir"; - reg = <0x07040000 0x400>; - interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&r_ccu CLK_R_APB1_IR>, - <&r_ccu CLK_IR>; - clock-names = "apb", "ir"; - resets = <&r_ccu RST_R_APB1_IR>; - pinctrl-names = "default"; - pinctrl-0 = <&ir_rx_pin>; - status = "disabled"; + compatible = "allwinner,sun50i-h616-ir", + "allwinner,sun6i-a31-ir"; + reg = <0x07040000 0x400>; + interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&r_ccu CLK_R_APB1_IR>, + <&r_ccu CLK_IR>; + clock-names = "apb", "ir"; + resets = <&r_ccu RST_R_APB1_IR>; + pinctrl-names = "default"; + pinctrl-0 = <&ir_rx_pin>; + status = "disabled"; }; r_i2c: i2c@7081400 { compatible = "allwinner,sun50i-h616-i2c", + "allwinner,sun8i-v536-i2c", "allwinner,sun6i-a31-i2c"; reg = <0x07081400 0x400>; interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; diff --git a/arch/arm/dts/sun5i-a13-licheepi-one.dts b/arch/arm/dts/sun5i-a13-licheepi-one.dts index 2ce361f8fed..3a6c4bd0a44 100644 --- a/arch/arm/dts/sun5i-a13-licheepi-one.dts +++ b/arch/arm/dts/sun5i-a13-licheepi-one.dts @@ -67,18 +67,18 @@ compatible = "gpio-leds"; led-0 { - label ="licheepi:red:usr"; + label = "licheepi:red:usr"; gpios = <&pio 2 5 GPIO_ACTIVE_LOW>; }; led-1 { - label ="licheepi:green:usr"; + label = "licheepi:green:usr"; gpios = <&pio 2 19 GPIO_ACTIVE_LOW>; default-state = "on"; }; led-2 { - label ="licheepi:blue:usr"; + label = "licheepi:blue:usr"; gpios = <&pio 2 4 GPIO_ACTIVE_LOW>; }; diff --git a/arch/arm/dts/sun6i-a31.dtsi b/arch/arm/dts/sun6i-a31.dtsi index d7d920e9e48..f6701ece7b7 100644 --- a/arch/arm/dts/sun6i-a31.dtsi +++ b/arch/arm/dts/sun6i-a31.dtsi @@ -46,6 +46,7 @@ #include <dt-bindings/thermal/thermal.h> #include <dt-bindings/clock/sun6i-a31-ccu.h> +#include <dt-bindings/clock/sun6i-rtc.h> #include <dt-bindings/reset/sun6i-a31-ccu.h> / { @@ -598,7 +599,7 @@ ccu: clock@1c20000 { compatible = "allwinner,sun6i-a31-ccu"; reg = <0x01c20000 0x400>; - clocks = <&osc24M>, <&rtc 0>; + clocks = <&osc24M>, <&rtc CLK_OSC32K>; clock-names = "hosc", "losc"; #clock-cells = <1>; #reset-cells = <1>; @@ -611,7 +612,8 @@ <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_APB1_PIO>, <&osc24M>, <&rtc 0>; + clocks = <&ccu CLK_APB1_PIO>, <&osc24M>, + <&rtc CLK_OSC32K>; clock-names = "apb", "hosc", "losc"; gpio-controller; interrupt-controller; @@ -1316,7 +1318,7 @@ ar100: ar100_clk { compatible = "allwinner,sun6i-a31-ar100-clk"; #clock-cells = <0>; - clocks = <&rtc 0>, <&osc24M>, + clocks = <&rtc CLK_OSC32K>, <&osc24M>, <&ccu CLK_PLL_PERIPH>, <&ccu CLK_PLL_PERIPH>; clock-output-names = "ar100"; @@ -1351,7 +1353,7 @@ ir_clk: ir_clk { #clock-cells = <0>; compatible = "allwinner,sun4i-a10-mod0-clk"; - clocks = <&rtc 0>, <&osc24M>; + clocks = <&rtc CLK_OSC32K>, <&osc24M>; clock-output-names = "ir"; }; @@ -1381,9 +1383,8 @@ reg = <0x01f02c00 0x400>; interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&apb0_gates 0>, <&osc24M>, <&rtc 0>; + clocks = <&apb0_gates 0>, <&osc24M>, <&rtc CLK_OSC32K>; clock-names = "apb", "hosc", "losc"; - resets = <&apb0_rst 0>; gpio-controller; interrupt-controller; #interrupt-cells = <3>; diff --git a/arch/arm/dts/sun7i-a20-pcduino3.dts b/arch/arm/dts/sun7i-a20-pcduino3.dts index 4f8d55d3ba7..928b86a95f3 100644 --- a/arch/arm/dts/sun7i-a20-pcduino3.dts +++ b/arch/arm/dts/sun7i-a20-pcduino3.dts @@ -78,19 +78,19 @@ gpio-keys { compatible = "gpio-keys"; - back { + key-back { label = "Key Back"; linux,code = <KEY_BACK>; gpios = <&pio 7 17 GPIO_ACTIVE_LOW>; }; - home { + key-home { label = "Key Home"; linux,code = <KEY_HOME>; gpios = <&pio 7 18 GPIO_ACTIVE_LOW>; }; - menu { + key-menu { label = "Key Menu"; linux,code = <KEY_MENU>; gpios = <&pio 7 19 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/dts/sun8i-a23-a33.dtsi b/arch/arm/dts/sun8i-a23-a33.dtsi index a42fac676b3..06809c3a1f2 100644 --- a/arch/arm/dts/sun8i-a23-a33.dtsi +++ b/arch/arm/dts/sun8i-a23-a33.dtsi @@ -44,6 +44,7 @@ #include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/clock/sun6i-rtc.h> #include <dt-bindings/clock/sun8i-a23-a33-ccu.h> #include <dt-bindings/reset/sun8i-a23-a33-ccu.h> @@ -329,7 +330,7 @@ ccu: clock@1c20000 { reg = <0x01c20000 0x400>; - clocks = <&osc24M>, <&rtc 0>; + clocks = <&osc24M>, <&rtc CLK_OSC32K>; clock-names = "hosc", "losc"; #clock-cells = <1>; #reset-cells = <1>; @@ -339,7 +340,8 @@ /* compatible gets set in SoC specific dtsi file */ reg = <0x01c20800 0x400>; /* interrupts get set in SoC specific dtsi file */ - clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>; + clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, + <&rtc CLK_OSC32K>; clock-names = "apb", "hosc", "losc"; gpio-controller; interrupt-controller; @@ -806,9 +808,8 @@ compatible = "allwinner,sun8i-a23-r-pinctrl"; reg = <0x01f02c00 0x400>; interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&apb0_gates 0>, <&osc24M>, <&rtc 0>; + clocks = <&apb0_gates 0>, <&osc24M>, <&rtc CLK_OSC32K>; clock-names = "apb", "hosc", "losc"; - resets = <&apb0_rst 0>; gpio-controller; interrupt-controller; #interrupt-cells = <3>; diff --git a/arch/arm/dts/sun8i-a23-ippo-q8h-v1.2.dts b/arch/arm/dts/sun8i-a23-ippo-q8h-v1.2.dts index 51097c77a15..c2f22fc3381 100644..120000 --- a/arch/arm/dts/sun8i-a23-ippo-q8h-v1.2.dts +++ b/arch/arm/dts/sun8i-a23-ippo-q8h-v1.2.dts @@ -1,73 +1 @@ -/* - * Copyright 2015 Hans de Goede <hdegoede@redhat.com> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun8i-a23.dtsi" -#include "sun8i-q8-common.dtsi" - -/ { - model = "Q8 A23 Tablet"; - compatible = "allwinner,q8-a23", "allwinner,sun8i-a23"; -}; - -&codec { - allwinner,pa-gpios = <&pio 7 9 GPIO_ACTIVE_HIGH>; /* PH9 */ - allwinner,audio-routing = - "Headphone", "HP", - "Headphone", "HPCOM", - "Speaker", "HP", - "MIC1", "Mic", - "MIC2", "Headset Mic", - "Mic", "MBIAS", - "Headset Mic", "HBIAS"; - status = "okay"; -}; - -&panel { - compatible = "bananapi,s070wv20-ct16"; -}; - -&tcon0_out { - tcon0_out_lcd: endpoint { - remote-endpoint = <&panel_input>; - }; -}; +sun8i-a23-q8-tablet.dts
\ No newline at end of file diff --git a/arch/arm/dts/sun8i-a23-ippo-q8h-v5.dts b/arch/arm/dts/sun8i-a23-ippo-q8h-v5.dts index 51097c77a15..c2f22fc3381 100644..120000 --- a/arch/arm/dts/sun8i-a23-ippo-q8h-v5.dts +++ b/arch/arm/dts/sun8i-a23-ippo-q8h-v5.dts @@ -1,73 +1 @@ -/* - * Copyright 2015 Hans de Goede <hdegoede@redhat.com> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun8i-a23.dtsi" -#include "sun8i-q8-common.dtsi" - -/ { - model = "Q8 A23 Tablet"; - compatible = "allwinner,q8-a23", "allwinner,sun8i-a23"; -}; - -&codec { - allwinner,pa-gpios = <&pio 7 9 GPIO_ACTIVE_HIGH>; /* PH9 */ - allwinner,audio-routing = - "Headphone", "HP", - "Headphone", "HPCOM", - "Speaker", "HP", - "MIC1", "Mic", - "MIC2", "Headset Mic", - "Mic", "MBIAS", - "Headset Mic", "HBIAS"; - status = "okay"; -}; - -&panel { - compatible = "bananapi,s070wv20-ct16"; -}; - -&tcon0_out { - tcon0_out_lcd: endpoint { - remote-endpoint = <&panel_input>; - }; -}; +sun8i-a23-q8-tablet.dts
\ No newline at end of file diff --git a/arch/arm/dts/sun8i-a33-et-q8-v1.6.dts b/arch/arm/dts/sun8i-a33-et-q8-v1.6.dts index 9c5750c2561..4519fd791a8 100644..120000 --- a/arch/arm/dts/sun8i-a33-et-q8-v1.6.dts +++ b/arch/arm/dts/sun8i-a33-et-q8-v1.6.dts @@ -1,57 +1 @@ -/* - * Copyright 2015 Hans de Goede <hdegoede@redhat.com> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun8i-a33.dtsi" -#include "sun8i-q8-common.dtsi" - -/ { - model = "Q8 A33 Tablet"; - compatible = "allwinner,q8-a33", "allwinner,sun8i-a33"; -}; - -&tcon0_out { - tcon0_out_lcd: endpoint@0 { - reg = <0>; - remote-endpoint = <&panel_input>; - }; -}; +sun8i-a33-q8-tablet.dts
\ No newline at end of file diff --git a/arch/arm/dts/sun8i-a33-ippo-q8h-v1.2.dts b/arch/arm/dts/sun8i-a33-ippo-q8h-v1.2.dts index 9c5750c2561..4519fd791a8 100644..120000 --- a/arch/arm/dts/sun8i-a33-ippo-q8h-v1.2.dts +++ b/arch/arm/dts/sun8i-a33-ippo-q8h-v1.2.dts @@ -1,57 +1 @@ -/* - * Copyright 2015 Hans de Goede <hdegoede@redhat.com> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun8i-a33.dtsi" -#include "sun8i-q8-common.dtsi" - -/ { - model = "Q8 A33 Tablet"; - compatible = "allwinner,q8-a33", "allwinner,sun8i-a33"; -}; - -&tcon0_out { - tcon0_out_lcd: endpoint@0 { - reg = <0>; - remote-endpoint = <&panel_input>; - }; -}; +sun8i-a33-q8-tablet.dts
\ No newline at end of file diff --git a/arch/arm/dts/sun8i-h2-plus-bananapi-m2-zero.dts b/arch/arm/dts/sun8i-h2-plus-bananapi-m2-zero.dts index d5c7b7984d8..d729b7c705d 100644 --- a/arch/arm/dts/sun8i-h2-plus-bananapi-m2-zero.dts +++ b/arch/arm/dts/sun8i-h2-plus-bananapi-m2-zero.dts @@ -47,10 +47,10 @@ }; }; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; - sw4 { + switch-4 { label = "power"; linux,code = <KEY_POWER>; gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; @@ -106,7 +106,7 @@ wifi_pwrseq: wifi_pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */ - clocks = <&rtc 1>; + clocks = <&rtc CLK_OSC32K_FANOUT>; clock-names = "ext_clock"; }; }; @@ -181,7 +181,7 @@ bluetooth { compatible = "brcm,bcm43438-bt"; max-speed = <1500000>; - clocks = <&rtc 1>; + clocks = <&rtc CLK_OSC32K_FANOUT>; clock-names = "lpo"; vbat-supply = <®_vcc3v3>; vddio-supply = <®_vcc3v3>; diff --git a/arch/arm/dts/sun8i-h2-plus-orangepi-zero.dts b/arch/arm/dts/sun8i-h2-plus-orangepi-zero.dts index f19ed981da9..3706216ffb4 100644 --- a/arch/arm/dts/sun8i-h2-plus-orangepi-zero.dts +++ b/arch/arm/dts/sun8i-h2-plus-orangepi-zero.dts @@ -169,7 +169,7 @@ flash@0 { #address-cells = <1>; #size-cells = <1>; - compatible = "mxicy,mx25l1606e", "winbond,w25q128"; + compatible = "mxicy,mx25l1606e", "jedec,spi-nor"; reg = <0>; spi-max-frequency = <40000000>; }; diff --git a/arch/arm/dts/sun8i-h3-beelink-x2.dts b/arch/arm/dts/sun8i-h3-beelink-x2.dts index cd9f655e4f9..27a0d51289d 100644 --- a/arch/arm/dts/sun8i-h3-beelink-x2.dts +++ b/arch/arm/dts/sun8i-h3-beelink-x2.dts @@ -93,10 +93,10 @@ }; }; - r-gpio-keys { + gpio-keys { compatible = "gpio-keys"; - power { + key-power { label = "power"; linux,code = <KEY_POWER>; gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; @@ -125,7 +125,7 @@ wifi_pwrseq: wifi_pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */ - clocks = <&rtc 1>; + clocks = <&rtc CLK_OSC32K_FANOUT>; clock-names = "ext_clock"; }; }; diff --git a/arch/arm/dts/sun8i-h3-mapleboard-mp130.dts b/arch/arm/dts/sun8i-h3-mapleboard-mp130.dts index ff0a7a952e0..f5c8ccc5b87 100644 --- a/arch/arm/dts/sun8i-h3-mapleboard-mp130.dts +++ b/arch/arm/dts/sun8i-h3-mapleboard-mp130.dts @@ -39,16 +39,16 @@ }; }; - r_gpio_keys { + gpio-keys { compatible = "gpio-keys"; - power { + key-power { label = "power"; linux,code = <KEY_POWER>; gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; /* PL3 */ }; - user { + key-user { label = "user"; linux,code = <BTN_0>; gpios = <&r_pio 0 4 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/dts/sun8i-h3-nanopi-duo2.dts b/arch/arm/dts/sun8i-h3-nanopi-duo2.dts index 8e7dfcffe1f..43641cb8239 100644 --- a/arch/arm/dts/sun8i-h3-nanopi-duo2.dts +++ b/arch/arm/dts/sun8i-h3-nanopi-duo2.dts @@ -37,10 +37,10 @@ }; }; - r_gpio_keys { + gpio-keys { compatible = "gpio-keys"; - k1 { + key-0 { label = "k1"; linux,code = <BTN_0>; gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; /* PL3 */ @@ -90,7 +90,7 @@ wifi_pwrseq: wifi_pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */ - clocks = <&rtc 1>; + clocks = <&rtc CLK_OSC32K_FANOUT>; clock-names = "ext_clock"; }; @@ -151,7 +151,7 @@ bluetooth { compatible = "brcm,bcm43438-bt"; - clocks = <&rtc 1>; + clocks = <&rtc CLK_OSC32K_FANOUT>; clock-names = "lpo"; vbat-supply = <®_vcc3v3>; vddio-supply = <®_vcc3v3>; diff --git a/arch/arm/dts/sun8i-h3-nanopi-neo-air.dts b/arch/arm/dts/sun8i-h3-nanopi-neo-air.dts index cd3df12b657..9e1a33f94ca 100644 --- a/arch/arm/dts/sun8i-h3-nanopi-neo-air.dts +++ b/arch/arm/dts/sun8i-h3-nanopi-neo-air.dts @@ -127,7 +127,7 @@ bluetooth { compatible = "brcm,bcm43438-bt"; - clocks = <&rtc 1>; + clocks = <&rtc CLK_OSC32K_FANOUT>; clock-names = "lpo"; vbat-supply = <®_vcc3v3>; vddio-supply = <®_vcc3v3>; diff --git a/arch/arm/dts/sun8i-h3-nanopi-r1.dts b/arch/arm/dts/sun8i-h3-nanopi-r1.dts index 26e2e6172e0..42cd1131adf 100644 --- a/arch/arm/dts/sun8i-h3-nanopi-r1.dts +++ b/arch/arm/dts/sun8i-h3-nanopi-r1.dts @@ -46,7 +46,7 @@ wifi_pwrseq: wifi_pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */ - clocks = <&rtc 1>; + clocks = <&rtc CLK_OSC32K_FANOUT>; clock-names = "ext_clock"; }; @@ -147,7 +147,7 @@ bluetooth { compatible = "brcm,bcm43438-bt"; - clocks = <&rtc 1>; + clocks = <&rtc CLK_OSC32K_FANOUT>; clock-names = "lpo"; vbat-supply = <®_vcc3v3>; vddio-supply = <®_vcc3v3>; diff --git a/arch/arm/dts/sun8i-h3-nanopi.dtsi b/arch/arm/dts/sun8i-h3-nanopi.dtsi index fc45d5aaa67..cf8413fba6c 100644 --- a/arch/arm/dts/sun8i-h3-nanopi.dtsi +++ b/arch/arm/dts/sun8i-h3-nanopi.dtsi @@ -73,11 +73,10 @@ }; }; - r_gpio_keys { + gpio-keys { compatible = "gpio-keys"; - input-name = "k1"; - k1 { + key-0 { label = "k1"; linux,code = <KEY_POWER>; gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/dts/sun8i-h3-orangepi-2.dts b/arch/arm/dts/sun8i-h3-orangepi-2.dts index 9daffd90c12..f1f9dbead32 100644 --- a/arch/arm/dts/sun8i-h3-orangepi-2.dts +++ b/arch/arm/dts/sun8i-h3-orangepi-2.dts @@ -88,16 +88,16 @@ }; }; - r_gpio_keys { + gpio-keys { compatible = "gpio-keys"; - sw2 { + switch-2 { label = "sw2"; linux,code = <BTN_1>; gpios = <&r_pio 0 4 GPIO_ACTIVE_LOW>; }; - sw4 { + switch-4 { label = "sw4"; linux,code = <KEY_POWER>; gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/dts/sun8i-h3-orangepi-lite.dts b/arch/arm/dts/sun8i-h3-orangepi-lite.dts index 6f9c97add54..305b34a321f 100644 --- a/arch/arm/dts/sun8i-h3-orangepi-lite.dts +++ b/arch/arm/dts/sun8i-h3-orangepi-lite.dts @@ -87,10 +87,10 @@ }; }; - r_gpio_keys { + gpio-keys { compatible = "gpio-keys"; - sw4 { + switch-4 { label = "sw4"; linux,code = <BTN_0>; gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/dts/sun8i-h3-orangepi-one.dts b/arch/arm/dts/sun8i-h3-orangepi-one.dts index 4759ba3f298..59f6f6d5e7c 100644 --- a/arch/arm/dts/sun8i-h3-orangepi-one.dts +++ b/arch/arm/dts/sun8i-h3-orangepi-one.dts @@ -86,10 +86,10 @@ }; }; - r_gpio_keys { + gpio-keys { compatible = "gpio-keys"; - sw4 { + switch-4 { label = "sw4"; linux,code = <BTN_0>; gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/dts/sun8i-h3-orangepi-pc.dts b/arch/arm/dts/sun8i-h3-orangepi-pc.dts index 90f75fa85e6..b96e015f54e 100644 --- a/arch/arm/dts/sun8i-h3-orangepi-pc.dts +++ b/arch/arm/dts/sun8i-h3-orangepi-pc.dts @@ -86,10 +86,10 @@ }; }; - r_gpio_keys { + gpio-keys { compatible = "gpio-keys"; - sw4 { + switch-4 { label = "sw4"; linux,code = <KEY_POWER>; gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/dts/sun8i-r16-bananapi-m2m.dts b/arch/arm/dts/sun8i-r16-bananapi-m2m.dts index 293016d081c..f97218e70c1 100644 --- a/arch/arm/dts/sun8i-r16-bananapi-m2m.dts +++ b/arch/arm/dts/sun8i-r16-bananapi-m2m.dts @@ -91,7 +91,7 @@ wifi_pwrseq: wifi_pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&r_pio 0 6 GPIO_ACTIVE_LOW>; /* PL06 */ - clocks = <&rtc 1>; + clocks = <&rtc CLK_OSC32K_FANOUT>; clock-names = "ext_clock"; }; }; @@ -283,7 +283,7 @@ bluetooth { compatible = "brcm,bcm43438-bt"; - clocks = <&rtc 1>; + clocks = <&rtc CLK_OSC32K_FANOUT>; clock-names = "lpo"; vbat-supply = <®_dldo1>; vddio-supply = <®_aldo3>; diff --git a/arch/arm/dts/sun8i-r40-bananapi-m2-ultra.dts b/arch/arm/dts/sun8i-r40-bananapi-m2-ultra.dts index a6a1087a0c9..28197bbcb1d 100644 --- a/arch/arm/dts/sun8i-r40-bananapi-m2-ultra.dts +++ b/arch/arm/dts/sun8i-r40-bananapi-m2-ultra.dts @@ -43,6 +43,7 @@ /dts-v1/; #include "sun8i-r40.dtsi" +#include "sun8i-r40-cpu-opp.dtsi" #include <dt-bindings/gpio/gpio.h> @@ -113,6 +114,10 @@ status = "okay"; }; +&cpu0 { + cpu-supply = <®_dcdc2>; +}; + &de { status = "okay"; }; diff --git a/arch/arm/dts/sun8i-r40-cpu-opp.dtsi b/arch/arm/dts/sun8i-r40-cpu-opp.dtsi new file mode 100644 index 00000000000..649928b361a --- /dev/null +++ b/arch/arm/dts/sun8i-r40-cpu-opp.dtsi @@ -0,0 +1,52 @@ +/{ + cpu0_opp_table: opp-table-cpu { + compatible = "operating-points-v2"; + opp-shared; + + opp-720000000 { + opp-hz = /bits/ 64 <720000000>; + opp-microvolt = <1000000 1000000 1300000>; + clock-latency-ns = <2000000>; + }; + + opp-912000000 { + opp-hz = /bits/ 64 <912000000>; + opp-microvolt = <1100000 1100000 1300000>; + clock-latency-ns = <2000000>; + }; + + opp-1008000000 { + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <1160000 1160000 1300000>; + clock-latency-ns = <2000000>; + }; + + opp-1104000000 { + opp-hz = /bits/ 64 <1104000000>; + opp-microvolt = <1240000 1240000 1300000>; + clock-latency-ns = <2000000>; + }; + + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <1300000 1300000 1300000>; + clock-latency-ns = <2000000>; + }; + }; +}; + +&cpu0 { + operating-points-v2 = <&cpu0_opp_table>; +}; + +&cpu1 { + operating-points-v2 = <&cpu0_opp_table>; +}; + +&cpu2 { + operating-points-v2 = <&cpu0_opp_table>; +}; + +&cpu3 { + operating-points-v2 = <&cpu0_opp_table>; +}; diff --git a/arch/arm/dts/sun8i-r40-feta40i.dtsi b/arch/arm/dts/sun8i-r40-feta40i.dtsi index 265e0fa57a3..9f39b5a2bb3 100644 --- a/arch/arm/dts/sun8i-r40-feta40i.dtsi +++ b/arch/arm/dts/sun8i-r40-feta40i.dtsi @@ -5,6 +5,11 @@ // Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io> #include "sun8i-r40.dtsi" +#include "sun8i-r40-cpu-opp.dtsi" + +&cpu0 { + cpu-supply = <®_dcdc2>; +}; &i2c0 { status = "okay"; diff --git a/arch/arm/dts/sun8i-r40.dtsi b/arch/arm/dts/sun8i-r40.dtsi index 03d3e5f45a0..4ef26d8f534 100644 --- a/arch/arm/dts/sun8i-r40.dtsi +++ b/arch/arm/dts/sun8i-r40.dtsi @@ -42,6 +42,7 @@ */ #include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/clock/sun6i-rtc.h> #include <dt-bindings/clock/sun8i-de2.h> #include <dt-bindings/clock/sun8i-r40-ccu.h> #include <dt-bindings/clock/sun8i-tcon-top.h> @@ -84,24 +85,36 @@ compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <0>; + clocks = <&ccu CLK_CPU>; + clock-names = "cpu"; + #cooling-cells = <2>; }; cpu1: cpu@1 { compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <1>; + clocks = <&ccu CLK_CPU>; + clock-names = "cpu"; + #cooling-cells = <2>; }; cpu2: cpu@2 { compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <2>; + clocks = <&ccu CLK_CPU>; + clock-names = "cpu"; + #cooling-cells = <2>; }; cpu3: cpu@3 { compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <3>; + clocks = <&ccu CLK_CPU>; + clock-names = "cpu"; + #cooling-cells = <2>; }; }; @@ -117,6 +130,30 @@ polling-delay-passive = <0>; polling-delay = <0>; thermal-sensors = <&ths 0>; + + trips { + cpu_hot_trip: cpu-hot { + temperature = <80000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu_very_hot_trip: cpu-very-hot { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling-maps { + cpu-hot-limit { + trip = <&cpu_hot_trip>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; gpu_thermal: gpu-thermal { @@ -485,7 +522,7 @@ ccu: clock@1c20000 { compatible = "allwinner,sun8i-r40-ccu"; reg = <0x01c20000 0x400>; - clocks = <&osc24M>, <&rtc 0>; + clocks = <&osc24M>, <&rtc CLK_OSC32K>; clock-names = "hosc", "losc"; #clock-cells = <1>; #reset-cells = <1>; @@ -504,7 +541,8 @@ compatible = "allwinner,sun8i-r40-pinctrl"; reg = <0x01c20800 0x400>; interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>; + clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, + <&rtc CLK_OSC32K>; clock-names = "apb", "hosc", "losc"; gpio-controller; interrupt-controller; @@ -1231,7 +1269,7 @@ reg-io-width = <1>; interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_BUS_HDMI0>, <&ccu CLK_HDMI_SLOW>, - <&ccu CLK_HDMI>, <&rtc 0>; + <&ccu CLK_HDMI>, <&rtc CLK_OSC32K>; clock-names = "iahb", "isfr", "tmds", "cec"; resets = <&ccu RST_BUS_HDMI1>; reset-names = "ctrl"; diff --git a/arch/arm/dts/sun8i-t3-cqa3t-bv3.dts b/arch/arm/dts/sun8i-t3-cqa3t-bv3.dts index 6931aaab238..9f472521f4a 100644 --- a/arch/arm/dts/sun8i-t3-cqa3t-bv3.dts +++ b/arch/arm/dts/sun8i-t3-cqa3t-bv3.dts @@ -45,6 +45,7 @@ /dts-v1/; #include "sun8i-r40.dtsi" +#include "sun8i-r40-cpu-opp.dtsi" #include <dt-bindings/gpio/gpio.h> @@ -88,6 +89,10 @@ status = "okay"; }; +&cpu0 { + cpu-supply = <®_dcdc2>; +}; + &de { status = "okay"; }; diff --git a/arch/arm/dts/sun8i-v3s.dtsi b/arch/arm/dts/sun8i-v3s.dtsi index 084323d5c61..db194c606fd 100644 --- a/arch/arm/dts/sun8i-v3s.dtsi +++ b/arch/arm/dts/sun8i-v3s.dtsi @@ -42,6 +42,7 @@ */ #include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/clock/sun6i-rtc.h> #include <dt-bindings/clock/sun8i-v3s-ccu.h> #include <dt-bindings/reset/sun8i-v3s-ccu.h> #include <dt-bindings/clock/sun8i-de2.h> @@ -321,7 +322,7 @@ ccu: clock@1c20000 { compatible = "allwinner,sun8i-v3s-ccu"; reg = <0x01c20000 0x400>; - clocks = <&osc24M>, <&rtc 0>; + clocks = <&osc24M>, <&rtc CLK_OSC32K>; clock-names = "hosc", "losc"; #clock-cells = <1>; #reset-cells = <1>; @@ -342,7 +343,8 @@ reg = <0x01c20800 0x400>; interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>; + clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, + <&rtc CLK_OSC32K>; clock-names = "apb", "hosc", "losc"; gpio-controller; #gpio-cells = <3>; diff --git a/arch/arm/dts/sun8i-v40-bananapi-m2-berry.dts b/arch/arm/dts/sun8i-v40-bananapi-m2-berry.dts index 47954551f57..434871040ac 100644 --- a/arch/arm/dts/sun8i-v40-bananapi-m2-berry.dts +++ b/arch/arm/dts/sun8i-v40-bananapi-m2-berry.dts @@ -42,6 +42,7 @@ /dts-v1/; #include "sun8i-r40.dtsi" +#include "sun8i-r40-cpu-opp.dtsi" #include <dt-bindings/gpio/gpio.h> @@ -107,6 +108,10 @@ status = "okay"; }; +&cpu0 { + cpu-supply = <®_dcdc2>; +}; + &de { status = "okay"; }; diff --git a/arch/arm/dts/sun9i-a80.dtsi b/arch/arm/dts/sun9i-a80.dtsi index ce4fa6706d0..7d3f3300f43 100644 --- a/arch/arm/dts/sun9i-a80.dtsi +++ b/arch/arm/dts/sun9i-a80.dtsi @@ -1218,7 +1218,6 @@ <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; clocks = <&apbs_gates 0>, <&osc24M>, <&osc32k>; clock-names = "apb", "hosc", "losc"; - resets = <&apbs_rst 0>; gpio-controller; interrupt-controller; #interrupt-cells = <3>; diff --git a/arch/arm/dts/sunxi-bananapi-m2-plus.dtsi b/arch/arm/dts/sunxi-bananapi-m2-plus.dtsi index d03f5853ef7..e899d14f38c 100644 --- a/arch/arm/dts/sunxi-bananapi-m2-plus.dtsi +++ b/arch/arm/dts/sunxi-bananapi-m2-plus.dtsi @@ -77,10 +77,10 @@ }; }; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; - sw4 { + switch-4 { label = "power"; linux,code = <KEY_POWER>; gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; @@ -101,7 +101,7 @@ wifi_pwrseq: wifi_pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */ - clocks = <&rtc 1>; + clocks = <&rtc CLK_OSC32K_FANOUT>; clock-names = "ext_clock"; }; }; @@ -221,7 +221,7 @@ bluetooth { compatible = "brcm,bcm43438-bt"; max-speed = <1500000>; - clocks = <&rtc 1>; + clocks = <&rtc CLK_OSC32K_FANOUT>; clock-names = "lpo"; vbat-supply = <®_vcc3v3>; vddio-supply = <®_vcc3v3>; diff --git a/arch/arm/dts/sunxi-h3-h5-emlid-neutis.dtsi b/arch/arm/dts/sunxi-h3-h5-emlid-neutis.dtsi index fc67e30fe21..60804b0e6c5 100644 --- a/arch/arm/dts/sunxi-h3-h5-emlid-neutis.dtsi +++ b/arch/arm/dts/sunxi-h3-h5-emlid-neutis.dtsi @@ -22,7 +22,7 @@ compatible = "mmc-pwrseq-simple"; reset-gpios = <&pio 2 7 GPIO_ACTIVE_LOW>; /* PC7 */ post-power-on-delay-ms = <200>; - clocks = <&rtc 1>; + clocks = <&rtc CLK_OSC32K_FANOUT>; clock-names = "ext_clock"; }; }; @@ -124,7 +124,7 @@ bluetooth { compatible = "brcm,bcm43438-bt"; - clocks = <&rtc 1>; + clocks = <&rtc CLK_OSC32K_FANOUT>; clock-names = "lpo"; vbat-supply = <®_vcc3v3>; vddio-supply = <®_vcc3v3>; diff --git a/arch/arm/dts/sunxi-h3-h5.dtsi b/arch/arm/dts/sunxi-h3-h5.dtsi index 6cea57e07f8..64391418609 100644 --- a/arch/arm/dts/sunxi-h3-h5.dtsi +++ b/arch/arm/dts/sunxi-h3-h5.dtsi @@ -40,6 +40,7 @@ * OTHER DEALINGS IN THE SOFTWARE. */ +#include <dt-bindings/clock/sun6i-rtc.h> #include <dt-bindings/clock/sun8i-de2.h> #include <dt-bindings/clock/sun8i-h3-ccu.h> #include <dt-bindings/clock/sun8i-r-ccu.h> @@ -386,7 +387,7 @@ ccu: clock@1c20000 { /* compatible is in per SoC .dtsi file */ reg = <0x01c20000 0x400>; - clocks = <&osc24M>, <&rtc 0>; + clocks = <&osc24M>, <&rtc CLK_OSC32K>; clock-names = "hosc", "losc"; #clock-cells = <1>; #reset-cells = <1>; @@ -397,7 +398,8 @@ reg = <0x01c20800 0x400>; interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>; + clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, + <&rtc CLK_OSC32K>; clock-names = "apb", "hosc", "losc"; gpio-controller; #gpio-cells = <3>; @@ -817,7 +819,7 @@ reg-io-width = <1>; interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>, - <&ccu CLK_HDMI>, <&rtc 0>; + <&ccu CLK_HDMI>, <&rtc CLK_OSC32K>; clock-names = "iahb", "isfr", "tmds", "cec"; resets = <&ccu RST_BUS_HDMI1>; reset-names = "ctrl"; @@ -876,7 +878,7 @@ r_ccu: clock@1f01400 { compatible = "allwinner,sun8i-h3-r-ccu"; reg = <0x01f01400 0x100>; - clocks = <&osc24M>, <&rtc 0>, <&rtc 2>, + clocks = <&osc24M>, <&rtc CLK_OSC32K>, <&rtc CLK_IOSC>, <&ccu CLK_PLL_PERIPH0>; clock-names = "hosc", "losc", "iosc", "pll-periph"; #clock-cells = <1>; @@ -928,7 +930,8 @@ compatible = "allwinner,sun8i-h3-r-pinctrl"; reg = <0x01f02c00 0x400>; interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&rtc 0>; + clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, + <&rtc CLK_OSC32K>; clock-names = "apb", "hosc", "losc"; gpio-controller; #gpio-cells = <3>; diff --git a/arch/arm/dts/sunxi-libretech-all-h3-cc.dtsi b/arch/arm/dts/sunxi-libretech-all-h3-cc.dtsi index 9e14fe5fdcd..89731bb34c6 100644 --- a/arch/arm/dts/sunxi-libretech-all-h3-cc.dtsi +++ b/arch/arm/dts/sunxi-libretech-all-h3-cc.dtsi @@ -42,10 +42,10 @@ }; }; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; - power { + key-power { label = "power"; linux,code = <KEY_POWER>; gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */ diff --git a/arch/arm/mach-k3/am642_init.c b/arch/arm/mach-k3/am642_init.c index 8428322ed9a..0e30cc47f54 100644 --- a/arch/arm/mach-k3/am642_init.c +++ b/arch/arm/mach-k3/am642_init.c @@ -23,7 +23,6 @@ #include <mmc.h> #include <dm/root.h> -#define MCU_CTRL_MMR0_BASE 0x04500000 #define CTRLMMR_MCU_RST_CTRL 0x04518170 static void ctrl_mmr_unlock(void) diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c index 14c37acbce7..227706e8dca 100644 --- a/arch/arm/mach-k3/common.c +++ b/arch/arm/mach-k3/common.c @@ -606,5 +606,9 @@ int misc_init_r(void) printf("Failed to probe am65_cpsw_nuss driver\n"); } + /* Default FIT boot on non-GP devices */ + if (get_device_type() != K3_DEVICE_TYPE_GP) + env_set("boot_fit", "1"); + return 0; } diff --git a/arch/arm/mach-k3/include/mach/am62_hardware.h b/arch/arm/mach-k3/include/mach/am62_hardware.h index 9118d052042..278beb587f1 100644 --- a/arch/arm/mach-k3/include/mach/am62_hardware.h +++ b/arch/arm/mach-k3/include/mach/am62_hardware.h @@ -44,23 +44,6 @@ /* Backup Bootmode USB Config macros */ #define MAIN_DEVSTAT_BACKUP_USB_MODE_MASK 0x01 -/* - * The CTRL_MMR0 memory space is divided into several equally-spaced - * partitions, so defining the partition size allows us to determine - * register addresses common to those partitions. - */ -#define CTRL_MMR0_PARTITION_SIZE 0x4000 - -/* - * CTRL_MMR0, WKUP_CTRL_MMR0, and MCU_CTRL_MMR0 lock/kick-mechanism - * shared register definitions. The same registers are also used for - * PADCFG_MMR lock/kick-mechanism. - */ -#define CTRLMMR_LOCK_KICK0 0x1008 -#define CTRLMMR_LOCK_KICK0_UNLOCK_VAL 0x68ef3490 -#define CTRLMMR_LOCK_KICK1 0x100c -#define CTRLMMR_LOCK_KICK1_UNLOCK_VAL 0xd172bc5a - #define MCU_CTRL_LFXOSC_CTRL (MCU_CTRL_MMR0_BASE + 0x8038) #define MCU_CTRL_LFXOSC_TRIM (MCU_CTRL_MMR0_BASE + 0x803c) #define MCU_CTRL_LFXOSC_32K_DISABLE_VAL BIT(7) diff --git a/arch/arm/mach-k3/include/mach/am64_hardware.h b/arch/arm/mach-k3/include/mach/am64_hardware.h index e06e1f9532f..6c9332e2bd9 100644 --- a/arch/arm/mach-k3/include/mach/am64_hardware.h +++ b/arch/arm/mach-k3/include/mach/am64_hardware.h @@ -7,12 +7,13 @@ #ifndef __ASM_ARCH_AM64_HARDWARE_H #define __ASM_ARCH_AM64_HARDWARE_H +#define PADCFG_MMR1_BASE 0x000f0000 +#define MCU_PADCFG_MMR1_BASE 0x04080000 +#define WKUP_CTRL_MMR0_BASE 0x43000000 +#define MCU_CTRL_MMR0_BASE 0x04500000 #define CTRL_MMR0_BASE 0x43000000 -#define CTRLMMR_MAIN_DEVSTAT (CTRL_MMR0_BASE + 0x30) - -#define PADCFG_MMR1_BASE 0xf0000 -#define MCU_PADCFG_MMR1_BASE 0x04080000 +#define CTRLMMR_MAIN_DEVSTAT (CTRL_MMR0_BASE + 0x30) #define MAIN_DEVSTAT_PRIMARY_BOOTMODE_MASK 0x00000078 #define MAIN_DEVSTAT_PRIMARY_BOOTMODE_SHIFT 3 @@ -35,23 +36,6 @@ #define MAIN_DEVSTAT_BACKUP_USB_MODE_MASK 0x01 -/* - * The CTRL_MMR and PADCFG_MMR memory space is divided into several - * equally-spaced partitions, so defining the partition size allows us to - * determine register addresses common to those partitions. - */ -#define CTRL_MMR0_PARTITION_SIZE 0x4000 - -/* - * CTRL_MMR and PADCFG_MMR lock/kick-mechanism shared register definitions. - */ -#define CTRLMMR_LOCK_KICK0 0x01008 -#define CTRLMMR_LOCK_KICK0_UNLOCK_VAL 0x68ef3490 -#define CTRLMMR_LOCK_KICK0_UNLOCKED_MASK BIT(0) -#define CTRLMMR_LOCK_KICK0_UNLOCKED_SHIFT 0 -#define CTRLMMR_LOCK_KICK1 0x0100c -#define CTRLMMR_LOCK_KICK1_UNLOCK_VAL 0xd172bc5a - #define ROM_ENTENDED_BOOT_DATA_INFO 0x701beb00 /* Use Last 2K as Scratch pad */ diff --git a/arch/arm/mach-k3/include/mach/am6_hardware.h b/arch/arm/mach-k3/include/mach/am6_hardware.h index f533e22e061..f9f32918f7c 100644 --- a/arch/arm/mach-k3/include/mach/am6_hardware.h +++ b/arch/arm/mach-k3/include/mach/am6_hardware.h @@ -13,8 +13,10 @@ #endif #define CTRL_MMR0_BASE 0x00100000 -#define CTRLMMR_MAIN_DEVSTAT (CTRL_MMR0_BASE + 0x30) +#define WKUP_CTRL_MMR0_BASE 0x43000000 +#define MCU_CTRL_MMR0_BASE 0x40f00000 +#define CTRLMMR_MAIN_DEVSTAT (CTRL_MMR0_BASE + 0x30) #define CTRLMMR_MAIN_DEVSTAT_BOOTMODE_MASK GENMASK(3, 0) #define CTRLMMR_MAIN_DEVSTAT_BOOTMODE_SHIFT 0 #define CTRLMMR_MAIN_DEVSTAT_BKUP_BOOTMODE_MASK GENMASK(6, 4) @@ -28,27 +30,6 @@ #define CTRLMMR_MAIN_DEVSTAT_USB_MODE_SHIFT 9 #define CTRLMMR_MAIN_DEVSTAT_USB_MODE_MASK GENMASK(10, 9) -#define WKUP_CTRL_MMR0_BASE 0x43000000 -#define MCU_CTRL_MMR0_BASE 0x40f00000 - -/* - * The CTRL_MMR0 memory space is divided into several equally-spaced - * partitions, so defining the partition size allows us to determine - * register addresses common to those partitions. - */ -#define CTRL_MMR0_PARTITION_SIZE 0x4000 - -/* - * CTRL_MMR0, WKUP_CTRL_MMR0, and MCU_CTR_MMR0 lock/kick-mechanism - * shared register definitions. - */ -#define CTRLMMR_LOCK_KICK0 0x01008 -#define CTRLMMR_LOCK_KICK0_UNLOCK_VAL 0x68ef3490 -#define CTRLMMR_LOCK_KICK0_UNLOCKED_MASK BIT(0) -#define CTRLMMR_LOCK_KICK0_UNLOCKED_SHIFT 0 -#define CTRLMMR_LOCK_KICK1 0x0100c -#define CTRLMMR_LOCK_KICK1_UNLOCK_VAL 0xd172bc5a - /* MCU SCRATCHPAD usage */ #define TI_SRAM_SCRATCH_BOARD_EEPROM_START CONFIG_SYS_K3_MCU_SCRATCHPAD_BASE diff --git a/arch/arm/mach-k3/include/mach/hardware.h b/arch/arm/mach-k3/include/mach/hardware.h index 028482b3b6d..d6d2cf6dc26 100644 --- a/arch/arm/mach-k3/include/mach/hardware.h +++ b/arch/arm/mach-k3/include/mach/hardware.h @@ -27,7 +27,7 @@ #endif /* Assuming these addresses and definitions stay common across K3 devices */ -#define CTRLMMR_WKUP_JTAG_ID 0x43000014 +#define CTRLMMR_WKUP_JTAG_ID (WKUP_CTRL_MMR0_BASE + 0x14) #define JTAG_ID_VARIANT_SHIFT 28 #define JTAG_ID_VARIANT_MASK (0xf << 28) #define JTAG_ID_PARTNO_SHIFT 12 @@ -43,6 +43,23 @@ #define SYS_STATUS_SUB_TYPE_MASK (0xf << 8) #define SYS_STATUS_SUB_TYPE_VAL_FS 0xa +/* + * The CTRL_MMR0 memory space is divided into several equally-spaced + * partitions, so defining the partition size allows us to determine + * register addresses common to those partitions. + */ +#define CTRL_MMR0_PARTITION_SIZE 0x4000 + +/* + * CTRL_MMR0, WKUP_CTRL_MMR0, and MCU_CTRL_MMR0 lock/kick-mechanism + * shared register definitions. The same registers are also used for + * PADCFG_MMR lock/kick-mechanism. + */ +#define CTRLMMR_LOCK_KICK0 0x1008 +#define CTRLMMR_LOCK_KICK0_UNLOCK_VAL 0x68ef3490 +#define CTRLMMR_LOCK_KICK1 0x100c +#define CTRLMMR_LOCK_KICK1_UNLOCK_VAL 0xd172bc5a + #define K3_ROM_BOOT_HEADER_MAGIC "EXTBOOT" struct rom_extended_boot_data { diff --git a/arch/arm/mach-k3/include/mach/j721e_hardware.h b/arch/arm/mach-k3/include/mach/j721e_hardware.h index b98f0a82f19..032cb2657ae 100644 --- a/arch/arm/mach-k3/include/mach/j721e_hardware.h +++ b/arch/arm/mach-k3/include/mach/j721e_hardware.h @@ -12,9 +12,11 @@ #include <linux/bitops.h> #endif +#define WKUP_CTRL_MMR0_BASE 0x43000000 +#define MCU_CTRL_MMR0_BASE 0x40f00000 #define CTRL_MMR0_BASE 0x00100000 -#define CTRLMMR_MAIN_DEVSTAT (CTRL_MMR0_BASE + 0x30) +#define CTRLMMR_MAIN_DEVSTAT (CTRL_MMR0_BASE + 0x30) #define MAIN_DEVSTAT_BOOT_MODE_B_MASK BIT(0) #define MAIN_DEVSTAT_BOOT_MODE_B_SHIFT 0 #define MAIN_DEVSTAT_BKUP_BOOTMODE_MASK GENMASK(3, 1) @@ -24,33 +26,12 @@ #define MAIN_DEVSTAT_BKUP_MMC_PORT_MASK BIT(7) #define MAIN_DEVSTAT_BKUP_MMC_PORT_SHIFT 7 -#define WKUP_CTRL_MMR0_BASE 0x43000000 -#define MCU_CTRL_MMR0_BASE 0x40f00000 - #define CTRLMMR_WKUP_DEVSTAT (WKUP_CTRL_MMR0_BASE + 0x30) #define WKUP_DEVSTAT_PRIMARY_BOOTMODE_MASK GENMASK(5, 3) #define WKUP_DEVSTAT_PRIMARY_BOOTMODE_SHIFT 3 #define WKUP_DEVSTAT_MCU_OMLY_MASK BIT(6) #define WKUP_DEVSTAT_MCU_ONLY_SHIFT 6 -/* - * The CTRL_MMR0 memory space is divided into several equally-spaced - * partitions, so defining the partition size allows us to determine - * register addresses common to those partitions. - */ -#define CTRL_MMR0_PARTITION_SIZE 0x4000 - -/* - * CTRL_MMR0, WKUP_CTRL_MMR0, and MCU_CTR_MMR0 lock/kick-mechanism - * shared register definitions. - */ -#define CTRLMMR_LOCK_KICK0 0x01008 -#define CTRLMMR_LOCK_KICK0_UNLOCK_VAL 0x68ef3490 -#define CTRLMMR_LOCK_KICK0_UNLOCKED_MASK BIT(0) -#define CTRLMMR_LOCK_KICK0_UNLOCKED_SHIFT 0 -#define CTRLMMR_LOCK_KICK1 0x0100c -#define CTRLMMR_LOCK_KICK1_UNLOCK_VAL 0xd172bc5a - /* ROM HANDOFF Structure location */ #define ROM_ENTENDED_BOOT_DATA_INFO 0x41cffb00 diff --git a/arch/arm/mach-k3/include/mach/j721s2_hardware.h b/arch/arm/mach-k3/include/mach/j721s2_hardware.h index 23dfe2e9e9d..e47f40eac25 100644 --- a/arch/arm/mach-k3/include/mach/j721s2_hardware.h +++ b/arch/arm/mach-k3/include/mach/j721s2_hardware.h @@ -12,9 +12,11 @@ #include <linux/bitops.h> #endif +#define WKUP_CTRL_MMR0_BASE 0x43000000 +#define MCU_CTRL_MMR0_BASE 0x40f00000 #define CTRL_MMR0_BASE 0x00100000 -#define CTRLMMR_MAIN_DEVSTAT (CTRL_MMR0_BASE + 0x30) +#define CTRLMMR_MAIN_DEVSTAT (CTRL_MMR0_BASE + 0x30) #define MAIN_DEVSTAT_BOOT_MODE_B_MASK BIT(0) #define MAIN_DEVSTAT_BOOT_MODE_B_SHIFT 0 #define MAIN_DEVSTAT_BKUP_BOOTMODE_MASK GENMASK(3, 1) @@ -24,33 +26,12 @@ #define MAIN_DEVSTAT_BKUP_MMC_PORT_MASK BIT(7) #define MAIN_DEVSTAT_BKUP_MMC_PORT_SHIFT 7 -#define WKUP_CTRL_MMR0_BASE 0x43000000 -#define MCU_CTRL_MMR0_BASE 0x40f00000 - #define CTRLMMR_WKUP_DEVSTAT (WKUP_CTRL_MMR0_BASE + 0x30) #define WKUP_DEVSTAT_PRIMARY_BOOTMODE_MASK GENMASK(5, 3) #define WKUP_DEVSTAT_PRIMARY_BOOTMODE_SHIFT 3 #define WKUP_DEVSTAT_MCU_OMLY_MASK BIT(6) #define WKUP_DEVSTAT_MCU_ONLY_SHIFT 6 -/* - * The CTRL_MMR0 memory space is divided into several equally-spaced - * partitions, so defining the partition size allows us to determine - * register addresses common to those partitions. - */ -#define CTRL_MMR0_PARTITION_SIZE 0x4000 - -/* - * CTRL_MMR0, WKUP_CTRL_MMR0, and MCU_CTR_MMR0 lock/kick-mechanism - * shared register definitions. - */ -#define CTRLMMR_LOCK_KICK0 0x01008 -#define CTRLMMR_LOCK_KICK0_UNLOCK_VAL 0x68ef3490 -#define CTRLMMR_LOCK_KICK0_UNLOCKED_MASK BIT(0) -#define CTRLMMR_LOCK_KICK0_UNLOCKED_SHIFT 0 -#define CTRLMMR_LOCK_KICK1 0x0100c -#define CTRLMMR_LOCK_KICK1_UNLOCK_VAL 0xd172bc5a - /* ROM HANDOFF Structure location */ #define ROM_ENTENDED_BOOT_DATA_INFO 0x41cfdb00 diff --git a/arch/arm/mach-k3/j721s2_init.c b/arch/arm/mach-k3/j721s2_init.c index 12da8136f9e..dd0c7ba18f0 100644 --- a/arch/arm/mach-k3/j721s2_init.c +++ b/arch/arm/mach-k3/j721s2_init.c @@ -164,7 +164,7 @@ void board_init_f(ulong dummy) if (ret) panic("DRAM 0 init failed: %d\n", ret); - ret = uclass_next_device(&dev); + ret = uclass_next_device_err(&dev); if (ret) panic("DRAM 1 init failed: %d\n", ret); } diff --git a/arch/arm/mach-k3/security.c b/arch/arm/mach-k3/security.c index d8d41ec5154..092588f4b5e 100644 --- a/arch/arm/mach-k3/security.c +++ b/arch/arm/mach-k3/security.c @@ -18,6 +18,7 @@ #include <mach/spl.h> #include <spl.h> #include <asm/arch/sys_proto.h> +#include <linux/dma-mapping.h> #include "common.h" @@ -47,7 +48,6 @@ void ti_secure_image_post_process(void **p_image, size_t *p_size) u32 image_size; int ret; - image_addr = (uintptr_t)*p_image; image_size = *p_size; if (!image_size) @@ -80,13 +80,12 @@ void ti_secure_image_post_process(void **p_image, size_t *p_size) return; } + /* Clean out image so it can be seen by system firmware */ + image_addr = dma_map_single(*p_image, *p_size, DMA_BIDIRECTIONAL); + debug("Authenticating image at address 0x%016llx\n", image_addr); debug("Authenticating image of size %d bytes\n", image_size); - flush_dcache_range((unsigned long)image_addr, - ALIGN((unsigned long)image_addr + image_size, - ARCH_DMA_MINALIGN)); - /* Authenticate image */ ret = proc_ops->proc_auth_boot_image(ti_sci, &image_addr, &image_size); if (ret) { @@ -94,10 +93,9 @@ void ti_secure_image_post_process(void **p_image, size_t *p_size) hang(); } + /* Invalidate any stale lines over data written by system firmware */ if (image_size) - invalidate_dcache_range((unsigned long)image_addr, - ALIGN((unsigned long)image_addr + - image_size, ARCH_DMA_MINALIGN)); + dma_unmap_single(image_addr, image_size, DMA_BIDIRECTIONAL); /* * The image_size returned may be 0 when the authentication process has diff --git a/arch/arm/mach-omap2/am33xx/board.c b/arch/arm/mach-omap2/am33xx/board.c index 7f1b84e466d..f393ff91441 100644 --- a/arch/arm/mach-omap2/am33xx/board.c +++ b/arch/arm/mach-omap2/am33xx/board.c @@ -265,8 +265,8 @@ int arch_misc_init(void) struct udevice *dev; int ret; - ret = uclass_first_device(UCLASS_MISC, &dev); - if (ret || !dev) + ret = uclass_first_device_err(UCLASS_MISC, &dev); + if (ret) return ret; #if defined(CONFIG_DM_ETH) && defined(CONFIG_USB_ETHER) diff --git a/arch/arm/mach-stm32mp/Kconfig.15x b/arch/arm/mach-stm32mp/Kconfig.15x index d516270292a..5bd9b53a5d8 100644 --- a/arch/arm/mach-stm32mp/Kconfig.15x +++ b/arch/arm/mach-stm32mp/Kconfig.15x @@ -117,7 +117,7 @@ endif if DEBUG_UART config DEBUG_UART_BOARD_INIT - default y + default y if SPL # debug on UART4 by default config DEBUG_UART_BASE diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index 57125761844..fc5d8bb3c19 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -185,6 +185,8 @@ config MACH_SUNIV select CPU_ARM926EJS select SUNXI_GEN_SUN6I select SUPPORT_SPL + select SKIP_LOWLEVEL_INIT_ONLY + select SPL_SKIP_LOWLEVEL_INIT_ONLY config MACH_SUN4I bool "sun4i (Allwinner A10)" @@ -615,6 +617,18 @@ config SYS_BOARD config SYS_SOC default "sunxi" +config SUNXI_MINIMUM_DRAM_MB + int "minimum DRAM size" + default 32 if MACH_SUNIV + default 64 if MACH_SUN8I_V3S + default 256 + ---help--- + Minimum DRAM size expected on the board. Traditionally we assumed + 256 MB, so that U-Boot would load at 160MB. With co-packaged DRAM + we have smaller sizes, though, so that U-Boot's own load address and + the default payload addresses must be shifted down. + This is expected to be fixed by the SoC selection. + config UART0_PORT_F bool "UART0 on MicroSD breakout board" ---help--- @@ -998,7 +1012,7 @@ config SPL_STACK_R_ADDR config SPL_SPI_SUNXI bool "Support for SPI Flash on Allwinner SoCs in SPL" - depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNXI_H3_H5 || MACH_SUN50I || MACH_SUN8I_R40 || MACH_SUN50I_H6 || MACH_SUNIV + depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNXI_H3_H5 || MACH_SUN50I || MACH_SUN8I_R40 || SUN50I_GEN_H6 || MACH_SUNIV help Enable support for SPI Flash. This option allows SPL to read from sunxi SPI Flash. It uses the same method as the boot ROM, so does diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c index 62bb40b8c89..220ed80ba79 100644 --- a/arch/arm/mach-sunxi/board.c +++ b/arch/arm/mach-sunxi/board.c @@ -147,6 +147,10 @@ static int gpio_init(void) sunxi_gpio_set_cfgpin(SUNXI_GPH(12), SUN9I_GPH_UART0); sunxi_gpio_set_cfgpin(SUNXI_GPH(13), SUN9I_GPH_UART0); sunxi_gpio_set_pull(SUNXI_GPH(13), SUNXI_GPIO_PULL_UP); +#elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUNIV) + sunxi_gpio_set_cfgpin(SUNXI_GPA(2), SUNIV_GPE_UART0); + sunxi_gpio_set_cfgpin(SUNXI_GPA(3), SUNIV_GPE_UART0); + sunxi_gpio_set_pull(SUNXI_GPA(3), SUNXI_GPIO_PULL_UP); #elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUN5I) sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG_UART1); sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG_UART1); @@ -488,7 +492,7 @@ void reset_cpu(void) } #endif -#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) && !defined(CONFIG_ARM64) +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) && defined(CONFIG_CPU_V7A) void enable_caches(void) { /* Enable D-cache. I-cache is already enabled in start.S */ diff --git a/arch/arm/mach-sunxi/spl_spi_sunxi.c b/arch/arm/mach-sunxi/spl_spi_sunxi.c index 925bf85f2d2..520f14e5155 100644 --- a/arch/arm/mach-sunxi/spl_spi_sunxi.c +++ b/arch/arm/mach-sunxi/spl_spi_sunxi.c @@ -78,7 +78,7 @@ #define CCM_AHB_GATING0 (0x01C20000 + 0x60) #define CCM_H6_SPI_BGR_REG (0x03001000 + 0x96c) -#ifdef CONFIG_MACH_SUN50I_H6 +#ifdef CONFIG_SUN50I_GEN_H6 #define CCM_SPI0_CLK (0x03001000 + 0x940) #else #define CCM_SPI0_CLK (0x01C20000 + 0xA0) @@ -97,7 +97,7 @@ /* * Allwinner A10/A20 SoCs were using pins PC0,PC1,PC2,PC23 for booting * from SPI Flash, everything else is using pins PC0,PC1,PC2,PC3. - * The H6 uses PC0, PC2, PC3, PC5. + * The H6 uses PC0, PC2, PC3, PC5, the H616 PC0, PC2, PC3, PC4. */ static void spi0_pinmux_setup(unsigned int pin_function) { @@ -105,11 +105,14 @@ static void spi0_pinmux_setup(unsigned int pin_function) sunxi_gpio_set_cfgpin(SUNXI_GPC(0), pin_function); sunxi_gpio_set_cfgpin(SUNXI_GPC(2), pin_function); - /* All chips except H6 use PC1, and only H6 uses PC5. */ - if (!IS_ENABLED(CONFIG_MACH_SUN50I_H6)) + /* All chips except H6 and H616 use PC1. */ + if (!IS_ENABLED(CONFIG_SUN50I_GEN_H6)) sunxi_gpio_set_cfgpin(SUNXI_GPC(1), pin_function); - else + + if (IS_ENABLED(CONFIG_MACH_SUN50I_H6)) sunxi_gpio_set_cfgpin(SUNXI_GPC(5), pin_function); + if (IS_ENABLED(CONFIG_MACH_SUN50I_H616)) + sunxi_gpio_set_cfgpin(SUNXI_GPC(4), pin_function); /* Older generations use PC23 for CS, newer ones use PC3. */ if (IS_ENABLED(CONFIG_MACH_SUN4I) || IS_ENABLED(CONFIG_MACH_SUN7I) || @@ -122,7 +125,7 @@ static void spi0_pinmux_setup(unsigned int pin_function) static bool is_sun6i_gen_spi(void) { return IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I) || - IS_ENABLED(CONFIG_MACH_SUN50I_H6); + IS_ENABLED(CONFIG_SUN50I_GEN_H6); } static uintptr_t spi0_base_address(void) @@ -130,7 +133,7 @@ static uintptr_t spi0_base_address(void) if (IS_ENABLED(CONFIG_MACH_SUN8I_R40)) return 0x01C05000; - if (IS_ENABLED(CONFIG_MACH_SUN50I_H6)) + if (IS_ENABLED(CONFIG_SUN50I_GEN_H6)) return 0x05010000; if (!is_sun6i_gen_spi() || @@ -148,14 +151,14 @@ static void spi0_enable_clock(void) uintptr_t base = spi0_base_address(); /* Deassert SPI0 reset on SUN6I */ - if (IS_ENABLED(CONFIG_MACH_SUN50I_H6)) + if (IS_ENABLED(CONFIG_SUN50I_GEN_H6)) setbits_le32(CCM_H6_SPI_BGR_REG, (1U << 16) | 0x1); else if (is_sun6i_gen_spi()) setbits_le32(SUN6I_BUS_SOFT_RST_REG0, (1 << AHB_RESET_SPI0_SHIFT)); /* Open the SPI0 gate */ - if (!IS_ENABLED(CONFIG_MACH_SUN50I_H6)) + if (!IS_ENABLED(CONFIG_SUN50I_GEN_H6)) setbits_le32(CCM_AHB_GATING0, (1 << AHB_GATE_OFFSET_SPI0)); if (IS_ENABLED(CONFIG_MACH_SUNIV)) { @@ -202,11 +205,11 @@ static void spi0_disable_clock(void) writel(0, CCM_SPI0_CLK); /* Close the SPI0 gate */ - if (!IS_ENABLED(CONFIG_MACH_SUN50I_H6)) + if (!IS_ENABLED(CONFIG_SUN50I_GEN_H6)) clrbits_le32(CCM_AHB_GATING0, (1 << AHB_GATE_OFFSET_SPI0)); /* Assert SPI0 reset on SUN6I */ - if (IS_ENABLED(CONFIG_MACH_SUN50I_H6)) + if (IS_ENABLED(CONFIG_SUN50I_GEN_H6)) clrbits_le32(CCM_H6_SPI_BGR_REG, (1U << 16) | 0x1); else if (is_sun6i_gen_spi()) clrbits_le32(SUN6I_BUS_SOFT_RST_REG0, @@ -218,7 +221,7 @@ static void spi0_init(void) unsigned int pin_function = SUNXI_GPC_SPI0; if (IS_ENABLED(CONFIG_MACH_SUN50I) || - IS_ENABLED(CONFIG_MACH_SUN50I_H6)) + IS_ENABLED(CONFIG_SUN50I_GEN_H6)) pin_function = SUN50I_GPC_SPI0; else if (IS_ENABLED(CONFIG_MACH_SUNIV)) pin_function = SUNIV_GPC_SPI0; diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 32a90b83b5a..8f9578171d3 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -152,6 +152,21 @@ config RISCV_ISA_C when building U-Boot, which results in compressed instructions in the U-Boot binary. +config RISCV_ISA_F + bool "Standard extension for Single-Precision Floating Point" + default y + help + Adds "F" to the ISA string passed to the compiler. + +config RISCV_ISA_D + bool "Standard extension for Double-Precision Floating Point" + depends on RISCV_ISA_F + default y + help + Adds "D" to the ISA string passed to the compiler and changes the + riscv32 ABI from ilp32 to ilp32d and the riscv64 ABI from lp64 to + lp64d. + config RISCV_ISA_A def_bool y diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile index 53d1194ffb6..4963b5109b2 100644 --- a/arch/riscv/Makefile +++ b/arch/riscv/Makefile @@ -5,15 +5,22 @@ ifeq ($(CONFIG_ARCH_RV64I),y) ARCH_BASE = rv64im - ABI = lp64 + ABI_BASE = lp64 endif ifeq ($(CONFIG_ARCH_RV32I),y) ARCH_BASE = rv32im - ABI = ilp32 + ABI_BASE = ilp32 endif ifeq ($(CONFIG_RISCV_ISA_A),y) ARCH_A = a endif +ifeq ($(CONFIG_RISCV_ISA_F),y) + ARCH_F = f +endif +ifeq ($(CONFIG_RISCV_ISA_D),y) + ARCH_D = d + ABI_D = d +endif ifeq ($(CONFIG_RISCV_ISA_C),y) ARCH_C = c endif @@ -24,7 +31,9 @@ ifeq ($(CONFIG_CMODEL_MEDANY),y) CMODEL = medany endif -RISCV_MARCH = $(ARCH_BASE)$(ARCH_A)$(ARCH_C) + +RISCV_MARCH = $(ARCH_BASE)$(ARCH_A)$(ARCH_F)$(ARCH_D)$(ARCH_C) +ABI = $(ABI_BASE)$(ABI_D) # Newer binutils versions default to ISA spec version 20191213 which moves some # instructions from the I extension to the Zicsr and Zifencei extensions. diff --git a/arch/riscv/lib/andes_plic.c b/arch/riscv/lib/andes_plic.c index 68514758a86..1eabcacd09d 100644 --- a/arch/riscv/lib/andes_plic.c +++ b/arch/riscv/lib/andes_plic.c @@ -27,8 +27,8 @@ /* claim register */ #define CLAIM_REG(base, hart) ((ulong)(base) + 0x200004 + (hart) * 0x1000) -#define ENABLE_HART_IPI (0x80808080) -#define SEND_IPI_TO_HART(hart) (0x80 >> (hart)) +#define ENABLE_HART_IPI (0x01010101) +#define SEND_IPI_TO_HART(hart) (0x1 << (hart)) DECLARE_GLOBAL_DATA_PTR; @@ -36,8 +36,9 @@ static int enable_ipi(int hart) { unsigned int en; - en = ENABLE_HART_IPI >> hart; + en = ENABLE_HART_IPI << hart; writel(en, (void __iomem *)ENABLE_REG(gd->arch.plic, hart)); + writel(en, (void __iomem *)ENABLE_REG(gd->arch.plic + 0x4, hart)); return 0; } diff --git a/arch/sandbox/lib/bootm.c b/arch/sandbox/lib/bootm.c index c1742f94de7..28f4a746fb6 100644 --- a/arch/sandbox/lib/bootm.c +++ b/arch/sandbox/lib/bootm.c @@ -50,8 +50,25 @@ int bootz_setup(ulong image, ulong *start, ulong *end) return ret; } +/* Subcommand: PREP */ +static int boot_prep_linux(struct bootm_headers *images) +{ + int ret; + + if (CONFIG_IS_ENABLED(LMB)) { + ret = image_setup_linux(images); + if (ret) + return ret; + } + + return 0; +} + int do_bootm_linux(int flag, int argc, char *argv[], struct bootm_headers *images) { + if (flag & BOOTM_STATE_OS_PREP) + return boot_prep_linux(images); + if (flag & (BOOTM_STATE_OS_GO | BOOTM_STATE_OS_FAKE_GO)) { bootstage_mark(BOOTSTAGE_ID_RUN_OS); printf("## Transferring control to Linux (at address %08lx)...\n", diff --git a/arch/x86/cpu/broadwell/cpu.c b/arch/x86/cpu/broadwell/cpu.c index 2adcf4b242c..7877961451a 100644 --- a/arch/x86/cpu/broadwell/cpu.c +++ b/arch/x86/cpu/broadwell/cpu.c @@ -31,11 +31,9 @@ static int broadwell_init_cpu(void *ctx, struct event *event) int ret; /* Start up the LPC so we have serial */ - ret = uclass_first_device(UCLASS_LPC, &dev); + ret = uclass_first_device_err(UCLASS_LPC, &dev); if (ret) return ret; - if (!dev) - return -ENODEV; ret = cpu_set_flex_ratio_to_tdp_nominal(); if (ret) return ret; diff --git a/arch/x86/cpu/intel_common/cpu.c b/arch/x86/cpu/intel_common/cpu.c index 96d05e2eb3a..8f489e6c651 100644 --- a/arch/x86/cpu/intel_common/cpu.c +++ b/arch/x86/cpu/intel_common/cpu.c @@ -61,11 +61,9 @@ int cpu_common_init(void) /* Early chipset init required before RAM init can work */ uclass_first_device(UCLASS_NORTHBRIDGE, &dev); - ret = uclass_first_device(UCLASS_LPC, &lpc); + ret = uclass_first_device_err(UCLASS_LPC, &lpc); if (ret) return ret; - if (!lpc) - return -ENODEV; /* Cause the SATA device to do its early init */ uclass_first_device(UCLASS_AHCI, &dev); diff --git a/arch/x86/lib/pinctrl_ich6.c b/arch/x86/lib/pinctrl_ich6.c index fd5e311b291..c93f245845d 100644 --- a/arch/x86/lib/pinctrl_ich6.c +++ b/arch/x86/lib/pinctrl_ich6.c @@ -160,11 +160,9 @@ static int ich6_pinctrl_probe(struct udevice *dev) u32 iobase = -1; debug("%s: start\n", __func__); - ret = uclass_first_device(UCLASS_PCH, &pch); + ret = uclass_first_device_err(UCLASS_PCH, &pch); if (ret) return ret; - if (!pch) - return -ENODEV; /* * Get the memory/io base address to configure every pins. |