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-rw-r--r--arch/arm/dts/k3-am625-phycore-som-binman.dtsi28
-rw-r--r--arch/arm/dts/k3-am642-phycore-som-binman.dtsi28
-rw-r--r--arch/arm/dts/rk3308-rock-s0-u-boot.dtsi12
-rw-r--r--arch/arm/dts/rk3399-nanopi-r4s-u-boot.dtsi5
-rw-r--r--arch/arm/mach-imx/imx8m/Kconfig2
-rw-r--r--arch/arm/mach-stm32mp/stm32mp1/cpu.c2
-rw-r--r--arch/arm/mach-versal2/include/mach/hardware.h3
-rw-r--r--arch/x86/cpu/intel_common/intel_opregion.c1
-rw-r--r--arch/x86/lib/fsp2/fsp_init.c3
9 files changed, 64 insertions, 20 deletions
diff --git a/arch/arm/dts/k3-am625-phycore-som-binman.dtsi b/arch/arm/dts/k3-am625-phycore-som-binman.dtsi
index 31456d23167..4a65427e877 100644
--- a/arch/arm/dts/k3-am625-phycore-som-binman.dtsi
+++ b/arch/arm/dts/k3-am625-phycore-som-binman.dtsi
@@ -321,8 +321,11 @@
compression = "none";
load = <0x8F000000>;
arch = "arm";
-
- blob-ext {
+ ti-secure {
+ content = <&am6xx_phycore_disable_rtc_dtbo>;
+ keyfile = "custMpk.pem";
+ };
+ am6xx_phycore_disable_rtc_dtbo: blob-ext {
filename = "dts/upstream/src/arm64/ti/k3-am6xx-phycore-disable-rtc.dtbo";
};
};
@@ -333,8 +336,11 @@
compression = "none";
load = <0x8F001000>;
arch = "arm";
-
- blob-ext {
+ ti-secure {
+ content = <&am6xx_phycore_disable_spi_not_dtbo>;
+ keyfile = "custMpk.pem";
+ };
+ am6xx_phycore_disable_spi_not_dtbo: blob-ext {
filename = "dts/upstream/src/arm64/ti/k3-am6xx-phycore-disable-spi-nor.dtbo";
};
};
@@ -345,8 +351,11 @@
compression = "none";
load = <0x8F002000>;
arch = "arm";
-
- blob-ext {
+ ti-secure {
+ content = <&am6xx_phycore_disable_eth_phy_dtbo>;
+ keyfile = "custMpk.pem";
+ };
+ am6xx_phycore_disable_eth_phy_dtbo: blob-ext {
filename = "dts/upstream/src/arm64/ti/k3-am6xx-phycore-disable-eth-phy.dtbo";
};
};
@@ -357,8 +366,11 @@
compression = "none";
load = <0x8F003000>;
arch = "arm";
-
- blob-ext {
+ ti-secure {
+ content = <&am6xx_phycore_disable_qspi_nor_dtbo>;
+ keyfile = "custMpk.pem";
+ };
+ am6xx_phycore_disable_qspi_nor_dtbo: blob-ext {
filename = "dts/upstream/src/arm64/ti/k3-am6xx-phycore-qspi-nor.dtbo";
};
};
diff --git a/arch/arm/dts/k3-am642-phycore-som-binman.dtsi b/arch/arm/dts/k3-am642-phycore-som-binman.dtsi
index 3710564cd4a..5228eed19bf 100644
--- a/arch/arm/dts/k3-am642-phycore-som-binman.dtsi
+++ b/arch/arm/dts/k3-am642-phycore-som-binman.dtsi
@@ -363,8 +363,11 @@
compression = "none";
load = <0x8F000000>;
arch = "arm";
-
- blob-ext {
+ ti-secure {
+ content = <&am6xx_phycore_disable_rtc_dtbo>;
+ keyfile = "custMpk.pem";
+ };
+ am6xx_phycore_disable_rtc_dtbo: blob-ext {
filename = "dts/upstream/src/arm64/ti/k3-am6xx-phycore-disable-rtc.dtbo";
};
};
@@ -375,8 +378,11 @@
compression = "none";
load = <0x8F001000>;
arch = "arm";
-
- blob-ext {
+ ti-secure {
+ content = <&am6xx_phycore_disable_spi_not_dtbo>;
+ keyfile = "custMpk.pem";
+ };
+ am6xx_phycore_disable_spi_not_dtbo: blob-ext {
filename = "dts/upstream/src/arm64/ti/k3-am6xx-phycore-disable-spi-nor.dtbo";
};
};
@@ -387,8 +393,11 @@
compression = "none";
load = <0x8F002000>;
arch = "arm";
-
- blob-ext {
+ ti-secure {
+ content = <&am6xx_phycore_disable_eth_phy_dtbo>;
+ keyfile = "custMpk.pem";
+ };
+ am6xx_phycore_disable_eth_phy_dtbo: blob-ext {
filename = "dts/upstream/src/arm64/ti/k3-am6xx-phycore-disable-eth-phy.dtbo";
};
};
@@ -399,8 +408,11 @@
compression = "none";
load = <0x8F003000>;
arch = "arm";
-
- blob-ext {
+ ti-secure {
+ content = <&am6xx_phycore_disable_qspi_nor_dtbo>;
+ keyfile = "custMpk.pem";
+ };
+ am6xx_phycore_disable_qspi_nor_dtbo: blob-ext {
filename = "dts/upstream/src/arm64/ti/k3-am6xx-phycore-qspi-nor.dtbo";
};
};
diff --git a/arch/arm/dts/rk3308-rock-s0-u-boot.dtsi b/arch/arm/dts/rk3308-rock-s0-u-boot.dtsi
index 84ca2ee0d5f..c8c56b17a15 100644
--- a/arch/arm/dts/rk3308-rock-s0-u-boot.dtsi
+++ b/arch/arm/dts/rk3308-rock-s0-u-boot.dtsi
@@ -7,6 +7,14 @@
bootph-some-ram;
};
+&gpio4 {
+ bootph-pre-ram;
+};
+
+&sdmmc_2030 {
+ bootph-pre-ram;
+};
+
&uart0 {
bootph-all;
clock-frequency = <24000000>;
@@ -16,6 +24,10 @@
bootph-all;
};
+&vcc_sd {
+ bootph-pre-ram;
+};
+
&vdd_core {
regulator-init-microvolt = <1015000>;
};
diff --git a/arch/arm/dts/rk3399-nanopi-r4s-u-boot.dtsi b/arch/arm/dts/rk3399-nanopi-r4s-u-boot.dtsi
index 69800cc368d..931499b084c 100644
--- a/arch/arm/dts/rk3399-nanopi-r4s-u-boot.dtsi
+++ b/arch/arm/dts/rk3399-nanopi-r4s-u-boot.dtsi
@@ -36,3 +36,8 @@
};
};
};
+
+&u2phy1_host {
+ phy-supply = <&vdd_5v>;
+ status = "okay";
+};
diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig
index 0fe9c46e499..89f2b50c8a2 100644
--- a/arch/arm/mach-imx/imx8m/Kconfig
+++ b/arch/arm/mach-imx/imx8m/Kconfig
@@ -92,6 +92,8 @@ config TARGET_IMX8MM_EVK
select FSL_CAAM
select ARCH_MISC_INIT
select SPL_CRYPTO if SPL
+ imply BOOTSTD_FULL
+ imply BOOTSTD_BOOTCOMMAND
imply OF_UPSTREAM
config TARGET_IMX8MM_ICORE_MX8MM
diff --git a/arch/arm/mach-stm32mp/stm32mp1/cpu.c b/arch/arm/mach-stm32mp/stm32mp1/cpu.c
index cb1b84c9af9..d5eaf6711b6 100644
--- a/arch/arm/mach-stm32mp/stm32mp1/cpu.c
+++ b/arch/arm/mach-stm32mp/stm32mp1/cpu.c
@@ -82,7 +82,7 @@ void dram_bank_mmu_setup(int bank)
option = DCACHE_DEFAULT_OPTION;
if (use_lmb &&
(lmb_is_reserved_flags(i << MMU_SECTION_SHIFT, LMB_NOMAP) ||
- addr >= gd->ram_top)
+ (gd->ram_top && addr >= gd->ram_top))
)
option = 0; /* INVALID ENTRY in TLB */
set_section_dcache(i, option);
diff --git a/arch/arm/mach-versal2/include/mach/hardware.h b/arch/arm/mach-versal2/include/mach/hardware.h
index 42e3061a0ae..15085f941e0 100644
--- a/arch/arm/mach-versal2/include/mach/hardware.h
+++ b/arch/arm/mach-versal2/include/mach/hardware.h
@@ -51,7 +51,8 @@ struct crp_regs {
#define PMC_TAP_VERSION (PMC_TAP + 0x4)
# define PMC_VERSION_MASK GENMASK(7, 0)
# define PS_VERSION_MASK GENMASK(15, 8)
-# define PS_VERSION_PRODUCTION 0x20
+# define PS_VERSION_MAJOR GENMASK(7, 4)
+# define PS_VERSION_MINOR GENMASK(3, 0)
# define RTL_VERSION_MASK GENMASK(23, 16)
# define PLATFORM_MASK GENMASK(27, 24)
# define PLATFORM_VERSION_MASK GENMASK(31, 28)
diff --git a/arch/x86/cpu/intel_common/intel_opregion.c b/arch/x86/cpu/intel_common/intel_opregion.c
index 78caff0dc12..4a2717b3584 100644
--- a/arch/x86/cpu/intel_common/intel_opregion.c
+++ b/arch/x86/cpu/intel_common/intel_opregion.c
@@ -31,6 +31,7 @@ static int locate_vbt(char **vbtp, int *sizep)
size = vbt.size;
if (size > sizeof(vbt_data))
return log_msg_ret("vbt", -E2BIG);
+ vbt.image_pos += CONFIG_ROM_SIZE;
ret = spi_flash_read_dm(dev, vbt.image_pos, size, vbt_data);
if (ret)
return log_msg_ret("read", ret);
diff --git a/arch/x86/lib/fsp2/fsp_init.c b/arch/x86/lib/fsp2/fsp_init.c
index 1a2bf46c5c5..0be892b14dc 100644
--- a/arch/x86/lib/fsp2/fsp_init.c
+++ b/arch/x86/lib/fsp2/fsp_init.c
@@ -107,7 +107,6 @@ int fsp_locate_fsp(enum fsp_type_t type, struct binman_entry *entry,
bool use_spi_flash, struct udevice **devp,
struct fsp_header **hdrp, ulong *rom_offsetp)
{
- ulong mask = CONFIG_ROM_SIZE - 1;
struct udevice *dev;
ulong rom_offset = 0;
uint map_size;
@@ -141,7 +140,7 @@ int fsp_locate_fsp(enum fsp_type_t type, struct binman_entry *entry,
if (ret)
return log_msg_ret("binman entry", ret);
if (!use_spi_flash)
- rom_offset = (map_base & mask) - CONFIG_ROM_SIZE;
+ rom_offset = map_base + CONFIG_ROM_SIZE;
} else {
ret = -ENOENT;
if (false)
generated by cgit v1.2.3 (git 2.0.4) at 2025-11-03 06:33:37 +0000