diff options
Diffstat (limited to 'arch')
38 files changed, 544 insertions, 372 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index fedfdb21457..79f60eb3f34 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1416,7 +1416,7 @@ config TARGET_TOTAL_COMPUTE select DM_SERIAL select DM_GPIO select MMC - imply OF_HAS_PRIOR_STAGE + imply OF_HAS_PRIOR_STAGE if !BLOBLIST imply MISC_INIT_R config TARGET_LS2080A_EMU diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 32b698a7f41..976dbda48c3 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -918,8 +918,7 @@ dtb-$(CONFIG_ARCH_IMX8M) += \ imx8mq-librem5-r4.dtb dtb-$(CONFIG_ARCH_IMX9) += \ - imx93-var-som-symphony.dtb \ - imx93-phyboard-segin.dtb + imx93-var-som-symphony.dtb dtb-$(CONFIG_ARCH_IMXRT) += imxrt1020-evk.dtb \ imxrt1170-evk.dtb \ diff --git a/arch/arm/dts/imx6ulz-bsh-smm-m2-u-boot.dtsi b/arch/arm/dts/imx6ulz-bsh-smm-m2-u-boot.dtsi index 7730bb60dd0..faf596255f1 100644 --- a/arch/arm/dts/imx6ulz-bsh-smm-m2-u-boot.dtsi +++ b/arch/arm/dts/imx6ulz-bsh-smm-m2-u-boot.dtsi @@ -5,8 +5,12 @@ * Author: Michael Trimarchi <michael@amarulasolutions.com> */ -&{/soc} { - bootph-all; +/ { + wdt-reboot { + compatible = "wdt-reboot"; + wdt = <&wdog1>; + bootph-pre-ram; + }; }; &aips2 { diff --git a/arch/arm/dts/imx93-phyboard-segin.dts b/arch/arm/dts/imx93-phyboard-segin.dts deleted file mode 100644 index 85fb188b057..00000000000 --- a/arch/arm/dts/imx93-phyboard-segin.dts +++ /dev/null @@ -1,117 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2023 PHYTEC Messtechnik GmbH - * Author: Wadim Egorov <w.egorov@phytec.de>, Christoph Stoidner <c.stoidner@phytec.de> - * Copyright (C) 2024 Mathieu Othacehe <m.othacehe@gmail.com> - * - * Product homepage: - * phyBOARD-Segin carrier board is reused for the i.MX93 design. - * https://www.phytec.eu/en/produkte/single-board-computer/phyboard-segin-imx6ul/ - */ -/dts-v1/; - -#include "imx93-phycore-som.dtsi" - -/{ - model = "PHYTEC phyBOARD-Segin-i.MX93"; - compatible = "phytec,imx93-phyboard-segin", "phytec,imx93-phycore-som", - "fsl,imx93"; - - chosen { - stdout-path = &lpuart1; - }; - - reg_usdhc2_vmmc: regulator-usdhc2 { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "VCC_SD"; - }; -}; - -/* Console */ -&lpuart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -/* eMMC */ -&usdhc1 { - no-1-8-v; -}; - -/* SD-Card */ -&usdhc2 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc2_default>, <&pinctrl_usdhc2_cd>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_cd>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_cd>; - bus-width = <4>; - cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>; - no-mmc; - no-sdio; - vmmc-supply = <®_usdhc2_vmmc>; - status = "okay"; -}; - -&iomuxc { - pinctrl_uart1: uart1grp { - fsl,pins = < - MX93_PAD_UART1_RXD__LPUART1_RX 0x31e - MX93_PAD_UART1_TXD__LPUART1_TX 0x30e - >; - }; - - pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { - fsl,pins = < - MX93_PAD_SD2_RESET_B__GPIO3_IO07 0x31e - >; - }; - - pinctrl_usdhc2_cd: usdhc2cdgrp { - fsl,pins = < - MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e - >; - }; - - pinctrl_usdhc2_default: usdhc2grp { - fsl,pins = < - MX93_PAD_SD2_CLK__USDHC2_CLK 0x179e - MX93_PAD_SD2_CMD__USDHC2_CMD 0x139e - MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x138e - MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x138e - MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x138e - MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x139e - MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2grp { - fsl,pins = < - MX93_PAD_SD2_CLK__USDHC2_CLK 0x179e - MX93_PAD_SD2_CMD__USDHC2_CMD 0x139e - MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x138e - MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x138e - MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x139e - MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x139e - MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e - >; - }; - - pinctrl_usdhc2_200mhz: usdhc2grp { - fsl,pins = < - MX93_PAD_SD2_CLK__USDHC2_CLK 0x178e - MX93_PAD_SD2_CMD__USDHC2_CMD 0x139e - MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x139e - MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x139e - MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x139e - MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x139e - MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e - >; - }; -}; diff --git a/arch/arm/dts/imx93-phycore-som.dtsi b/arch/arm/dts/imx93-phycore-som.dtsi deleted file mode 100644 index 88c2657b50e..00000000000 --- a/arch/arm/dts/imx93-phycore-som.dtsi +++ /dev/null @@ -1,126 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2023 PHYTEC Messtechnik GmbH - * Author: Wadim Egorov <w.egorov@phytec.de>, Christoph Stoidner <c.stoidner@phytec.de> - * Copyright (C) 2024 Mathieu Othacehe <m.othacehe@gmail.com> - * - * Product homepage: - * https://www.phytec.eu/en/produkte/system-on-modules/phycore-imx-91-93/ - */ - -#include <dt-bindings/leds/common.h> - -#include "imx93.dtsi" - -/{ - model = "PHYTEC phyCORE-i.MX93"; - compatible = "phytec,imx93-phycore-som", "fsl,imx93"; - - reserved-memory { - ranges; - #address-cells = <2>; - #size-cells = <2>; - - linux,cma { - compatible = "shared-dma-pool"; - reusable; - alloc-ranges = <0 0x80000000 0 0x40000000>; - size = <0 0x10000000>; - linux,cma-default; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_leds>; - - led-0 { - color = <LED_COLOR_ID_GREEN>; - function = LED_FUNCTION_HEARTBEAT; - gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; -}; - -/* Ethernet */ -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec>; - phy-mode = "rmii"; - phy-handle = <ðphy1>; - fsl,magic-packet; - assigned-clocks = <&clk IMX93_CLK_ENET_TIMER1>, - <&clk IMX93_CLK_ENET_REF>, - <&clk IMX93_CLK_ENET_REF_PHY>; - assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>, - <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>, - <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; - assigned-clock-rates = <100000000>, <50000000>, <50000000>; - status = "okay"; - - mdio: mdio { - clock-frequency = <5000000>; - #address-cells = <1>; - #size-cells = <0>; - - ethphy1: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <1>; - }; - }; -}; - -/* eMMC */ -&usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1>; - bus-width = <8>; - non-removable; - status = "okay"; -}; - -/* Watchdog */ -&wdog3 { - status = "okay"; -}; - -&iomuxc { - pinctrl_fec: fecgrp { - fsl,pins = < - MX93_PAD_ENET2_MDC__ENET1_MDC 0x50e - MX93_PAD_ENET2_MDIO__ENET1_MDIO 0x502 - MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x57e - MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 0x57e - MX93_PAD_ENET2_RXC__ENET1_RX_ER 0x5fe - MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL 0x57e - MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0 0x50e - MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1 0x50e - MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL 0x50e - MX93_PAD_ENET2_TD2__ENET1_TX_CLK 0x4000050e - >; - }; - - pinctrl_leds: ledsgrp { - fsl,pins = < - MX93_PAD_I2C1_SDA__GPIO1_IO01 0x31e - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX93_PAD_SD1_CLK__USDHC1_CLK 0x179e - MX93_PAD_SD1_CMD__USDHC1_CMD 0x1386 - MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x138e - MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x1386 - MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x138e - MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x1386 - MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x1386 - MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x1386 - MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x1386 - MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x1386 - MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x179e - >; - }; -}; diff --git a/arch/arm/dts/imxrt1170-evk.dts b/arch/arm/dts/imxrt1170-evk.dts index 0d8e7016860..354352477c7 100644 --- a/arch/arm/dts/imxrt1170-evk.dts +++ b/arch/arm/dts/imxrt1170-evk.dts @@ -234,6 +234,34 @@ (IMX_PAD_SION | 8) /* SEMC_DQS */ >; }; + + pinctrl_flexspi1: flexspi1grp { + fsl,pins = < + IOMUXC_GPIO_SD_B2_05_FLEXSPI1_A_DQS 0xa + IOMUXC_GPIO_SD_B2_06_FLEXSPI1_A_SS0_B 0xa + IOMUXC_GPIO_SD_B2_07_FLEXSPI1_A_SCLK 0xa + IOMUXC_GPIO_SD_B2_08_FLEXSPI1_A_DATA00 0xa + IOMUXC_GPIO_SD_B2_09_FLEXSPI1_A_DATA01 0xa + IOMUXC_GPIO_SD_B2_10_FLEXSPI1_A_DATA02 0xa + IOMUXC_GPIO_SD_B2_11_FLEXSPI1_A_DATA03 0xa + >; + }; + }; +}; + +&flexspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi1>; + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <250000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; }; }; diff --git a/arch/arm/dts/imxrt1170.dtsi b/arch/arm/dts/imxrt1170.dtsi index 2de775f043f..08665eaf06a 100644 --- a/arch/arm/dts/imxrt1170.dtsi +++ b/arch/arm/dts/imxrt1170.dtsi @@ -246,6 +246,19 @@ #interrupt-cells = <2>; }; + flexspi1: spi@400cc000 { + compatible = "nxp,imxrt1170-fspi"; + reg = <0x400cc000 0x800>, <0x30000000 0x10000000>; + reg-names = "fspi_base", "fspi_mmap"; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <130>; + clocks = <&clks IMXRT1170_CLK_DUMMY>, + <&clks IMXRT1170_CLK_FLEXSPI1>; + clock-names = "fspi_en", "fspi"; + status = "disabled"; + }; + gpt1: gpt1@400ec000 { compatible = "fsl,imxrt-gpt"; reg = <0x400ec000 0x4000>; diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c index 567e8e9e81a..3cdb71a2528 100644 --- a/arch/arm/mach-imx/imx8m/soc.c +++ b/arch/arm/mach-imx/imx8m/soc.c @@ -38,7 +38,7 @@ DECLARE_GLOBAL_DATA_PTR; -#if defined(CONFIG_IMX_HAB) +#if IS_ENABLED(CONFIG_IMX_HAB) struct imx_fuse const imx_sec_config_fuse = { .bank = 1, .word = 3, @@ -52,7 +52,7 @@ struct imx_fuse const imx_field_return_fuse = { int timer_init(void) { -#ifdef CONFIG_XPL_BUILD +#if IS_ENABLED(CONFIG_XPL_BUILD) struct sctr_regs *sctr = (struct sctr_regs *)SYSCNT_CTRL_BASE_ADDR; unsigned long freq = readl(&sctr->cntfid0); @@ -110,7 +110,7 @@ void set_wdog_reset(struct wdog_regs *wdog) setbits_le16(&wdog->wcr, WDOG_WDT_MASK | WDOG_WDZST_MASK); } -#ifdef CONFIG_ARMV8_PSCI +#if IS_ENABLED(CONFIG_ARMV8_PSCI) #define PTE_MAP_NS PTE_BLOCK_NS #else #define PTE_MAP_NS 0 @@ -700,11 +700,11 @@ int arch_cpu_init(void) return 0; } -#if defined(CONFIG_IMX8MN) || defined(CONFIG_IMX8MP) +#if IS_ENABLED(CONFIG_IMX8MN) || IS_ENABLED(CONFIG_IMX8MP) struct rom_api *g_rom_api = (struct rom_api *)0x980; #endif -#if defined(CONFIG_IMX8M) +#if IS_ENABLED(CONFIG_IMX8M) #include <spl.h> int imx8m_detect_secondary_image_boot(void) { @@ -790,8 +790,8 @@ int boot_mode_getprisec(void) } #endif -#if defined(CONFIG_IMX8MN) || defined(CONFIG_IMX8MP) -#ifdef SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION +#if IS_ENABLED(CONFIG_IMX8MN) || IS_ENABLED(CONFIG_IMX8MP) +#if IS_ENABLED(CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION) #define IMG_CNTN_SET1_OFFSET GENMASK(22, 19) unsigned long arch_spl_mmc_get_uboot_raw_sector(struct mmc *mmc, unsigned long raw_sect) @@ -826,7 +826,7 @@ unsigned long arch_spl_mmc_get_uboot_raw_sector(struct mmc *mmc, return raw_sect; } -#endif /* SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION */ +#endif /* CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION */ #endif bool is_usb_boot(void) @@ -834,7 +834,7 @@ bool is_usb_boot(void) return get_boot_device() == USB_BOOT; } -#ifdef CONFIG_OF_SYSTEM_SETUP +#if IS_ENABLED(CONFIG_OF_SYSTEM_SETUP) bool check_fdt_new_path(void *blob) { const char *soc_path = "/soc@0"; @@ -880,7 +880,7 @@ add_status: return 0; } -#ifdef CONFIG_IMX8MQ +#if IS_ENABLED(CONFIG_IMX8MQ) bool check_dcss_fused(void) { struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; @@ -1026,7 +1026,7 @@ int disable_vpu_nodes(void *blob) return -EPERM; } -#ifdef CONFIG_IMX8MN_LOW_DRIVE_MODE +#if IS_ENABLED(CONFIG_IMX8MN_LOW_DRIVE_MODE) static int low_drive_gpu_freq(void *blob) { static const char *nodes_path_8mn[] = { @@ -1311,7 +1311,7 @@ int ft_system_setup(void *blob, struct bd_info *bd) "/cpus/cpu@3", }; -#ifdef CONFIG_IMX8MQ +#if IS_ENABLED(CONFIG_IMX8MQ) int i = 0; int rc; int nodeoff; @@ -1387,7 +1387,7 @@ usb_modify_speed: if (is_imx8md()) disable_cpu_nodes(blob, nodes_path, 2, 4); -#elif defined(CONFIG_IMX8MM) +#elif IS_ENABLED(CONFIG_IMX8MM) if (is_imx8mml() || is_imx8mmdl() || is_imx8mmsl()) disable_vpu_nodes(blob); @@ -1396,10 +1396,10 @@ usb_modify_speed: else if (is_imx8mms() || is_imx8mmsl()) disable_cpu_nodes(blob, nodes_path, 3, 4); -#elif defined(CONFIG_IMX8MN) +#elif IS_ENABLED(CONFIG_IMX8MN) if (is_imx8mnl() || is_imx8mndl() || is_imx8mnsl()) disable_gpu_nodes(blob); -#ifdef CONFIG_IMX8MN_LOW_DRIVE_MODE +#if IS_ENABLED(CONFIG_IMX8MN_LOW_DRIVE_MODE) else { int ldm_gpu = low_drive_gpu_freq(blob); @@ -1415,7 +1415,7 @@ usb_modify_speed: else if (is_imx8mns() || is_imx8mnsl() || is_imx8mnus()) disable_cpu_nodes(blob, nodes_path, 3, 4); -#elif defined(CONFIG_IMX8MP) +#elif IS_ENABLED(CONFIG_IMX8MP) if (is_imx8mpul()) { /* Disable GPU */ disable_gpu_nodes(blob); @@ -1471,7 +1471,7 @@ void reset_cpu(void) } #endif -#if defined(CONFIG_ARCH_MISC_INIT) +#if IS_ENABLED(CONFIG_ARCH_MISC_INIT) int arch_misc_init(void) { if (IS_ENABLED(CONFIG_FSL_CAAM)) { @@ -1487,8 +1487,8 @@ int arch_misc_init(void) } #endif -#if defined(CONFIG_XPL_BUILD) -#if defined(CONFIG_IMX8MQ) || defined(CONFIG_IMX8MM) || defined(CONFIG_IMX8MN) +#if IS_ENABLED(CONFIG_XPL_BUILD) +#if IS_ENABLED(CONFIG_IMX8MQ) || IS_ENABLED(CONFIG_IMX8MM) || IS_ENABLED(CONFIG_IMX8MN) bool serror_need_skip = true; void do_error(struct pt_regs *pt_regs) @@ -1523,7 +1523,7 @@ void do_error(struct pt_regs *pt_regs) #endif #endif -#if defined(CONFIG_IMX8MN) || defined(CONFIG_IMX8MP) +#if IS_ENABLED(CONFIG_IMX8MN) || IS_ENABLED(CONFIG_IMX8MP) enum env_location arch_env_get_location(enum env_operation op, int prio) { enum boot_device dev = get_boot_device(); @@ -1571,7 +1571,7 @@ enum env_location arch_env_get_location(enum env_operation op, int prio) #endif -#ifdef CONFIG_IMX_BOOTAUX +#if IS_ENABLED(CONFIG_IMX_BOOTAUX) const struct rproc_att hostmap[] = { /* aux core , host core, size */ { 0x00000000, 0x007e0000, 0x00020000 }, diff --git a/arch/arm/mach-imx/imx9/Kconfig b/arch/arm/mach-imx/imx9/Kconfig index 0fd82dc0811..e6cafdcd813 100644 --- a/arch/arm/mach-imx/imx9/Kconfig +++ b/arch/arm/mach-imx/imx9/Kconfig @@ -73,6 +73,7 @@ config TARGET_PHYCORE_IMX93 bool "phycore_imx93" select IMX93 select IMX9_LPDDR4X + imply OF_UPSTREAM select OF_BOARD_FIXUP select OF_BOARD_SETUP diff --git a/arch/arm/mach-imx/spl_imx_romapi.c b/arch/arm/mach-imx/spl_imx_romapi.c index 3982f4cca18..b7008df8e35 100644 --- a/arch/arm/mach-imx/spl_imx_romapi.c +++ b/arch/arm/mach-imx/spl_imx_romapi.c @@ -35,12 +35,10 @@ ulong __weak spl_romapi_get_uboot_base(u32 image_offset, u32 rom_bt_dev) { u32 sector = 0; - /* - * Some boards use this value even though MMC is not enabled in SPL, for - * example imx8mn_bsh_smm_s2 - */ -#ifdef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR +#if IS_ENABLED(CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR) sector = CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR; +#elif IS_ENABLED(CONFIG_SPL_NAND_RAW_U_BOOT_USE_SECTOR) + sector = CONFIG_SPL_NAND_RAW_U_BOOT_SECTOR; #endif return image_offset + sector * 512 - 0x8000; diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig index 6761a9cb393..f1ccedba5d7 100644 --- a/arch/arm/mach-kirkwood/Kconfig +++ b/arch/arm/mach-kirkwood/Kconfig @@ -50,11 +50,13 @@ config TARGET_DS109 bool "Synology DS109" select KW88F6281 select SHEEVA_88SV131 + select KIRKWOOD_COMMON config TARGET_GURUPLUG bool "GuruPlug Board" select KW88F6281 select SHEEVA_88SV131 + select KIRKWOOD_COMMON config TARGET_SHEEVAPLUG bool "SheevaPlug Board" @@ -86,6 +88,7 @@ config TARGET_DNS325 bool "dns325 Board" select FEROCEON_88FR131 select KW88F6281 + select KIRKWOOD_COMMON config TARGET_ICONNECT bool "iconnect Board" @@ -103,15 +106,18 @@ config TARGET_NET2BIG_V2 bool "LaCie 2Big Network v2 NAS Board" select FEROCEON_88FR131 select KW88F6281 + select KIRKWOOD_COMMON config TARGET_NETSPACE_V2 bool "LaCie netspace_v2 Board" select FEROCEON_88FR131 + select KIRKWOOD_COMMON config TARGET_IB62X0 bool "ib62x0 Board" select FEROCEON_88FR131 select KW88F6281 + select KIRKWOOD_COMMON config TARGET_DOCKSTAR bool "Dockstar Board" @@ -129,6 +135,7 @@ config TARGET_NAS220 bool "BlackArmor NAS220" select FEROCEON_88FR131 select KW88F6192 + select KIRKWOOD_COMMON config TARGET_NSA310S bool "Zyxel NSA310S" @@ -146,11 +153,13 @@ config TARGET_SBx81LIFKW bool "Allied Telesis SBx81GS24/SBx81GT40/SBx81XS6/SBx81XS16" select FEROCEON_88FR131 select KW88F6281 + select KIRKWOOD_COMMON config TARGET_SBx81LIFXCAT bool "Allied Telesis SBx81GP24/SBx81GT24" select FEROCEON_88FR131 select KW88F6281 + select KIRKWOOD_COMMON endchoice diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index b24623590f2..8c6feae5735 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -77,6 +77,14 @@ config SYS_DCACHE_OFF help Do not enable data cache in U-Boot. +config SYS_CACHE_THEAD_CMO + bool "THEAD non-standard cache operations" + depends on !SYS_DCACHE_OFF + default n + help + Support for non-standard cache management operations on SoCs based on + T-Head C906/C910 cores. + config SPL_SYS_DCACHE_OFF bool "Do not enable dcache in SPL" depends on SPL @@ -118,6 +126,7 @@ source "arch/riscv/cpu/generic/Kconfig" source "arch/riscv/cpu/jh7110/Kconfig" source "arch/riscv/cpu/k1/Kconfig" source "arch/riscv/cpu/k230/Kconfig" +source "arch/riscv/cpu/th1520/Kconfig" # architecture-specific options below diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c index 5b31da64cbd..15c4e14599d 100644 --- a/arch/riscv/cpu/cpu.c +++ b/arch/riscv/cpu/cpu.c @@ -18,6 +18,7 @@ #include <asm/hwcap.h> #include <asm/cpufeature.h> #include <asm/cache.h> +#include <asm/global_data.h> #include <dm/uclass-internal.h> #include <linux/bitops.h> #include <linux/log2.h> @@ -746,3 +747,8 @@ __weak int cleanup_before_linux(void) return 0; } + +void arch_setup_gd(gd_t *new_gd) +{ + set_gd(new_gd); +} diff --git a/arch/riscv/cpu/cv1800b/Kconfig b/arch/riscv/cpu/cv1800b/Kconfig index 7225b1210c5..57f724ae043 100644 --- a/arch/riscv/cpu/cv1800b/Kconfig +++ b/arch/riscv/cpu/cv1800b/Kconfig @@ -6,6 +6,7 @@ config SOPHGO_CV1800B bool select ARCH_EARLY_INIT_R select SYS_CACHE_SHIFT_6 + select SYS_CACHE_THEAD_CMO imply CPU imply CPU_RISCV imply RISCV_TIMER diff --git a/arch/riscv/cpu/cv1800b/Makefile b/arch/riscv/cpu/cv1800b/Makefile index 95beb34b51a..da12e0f64e1 100644 --- a/arch/riscv/cpu/cv1800b/Makefile +++ b/arch/riscv/cpu/cv1800b/Makefile @@ -4,4 +4,3 @@ obj-y += dram.o obj-y += cpu.o -obj-y += cache.o diff --git a/arch/riscv/cpu/th1520/Kconfig b/arch/riscv/cpu/th1520/Kconfig new file mode 100644 index 00000000000..4d44191bd22 --- /dev/null +++ b/arch/riscv/cpu/th1520/Kconfig @@ -0,0 +1,22 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com> +# Copyright (C) 2025, Yao Zi <ziyao@disroot.org> + +config THEAD_TH1520 + bool + select ARCH_EARLY_INIT_R + select SYS_CACHE_SHIFT_6 + select SUPPORT_SPL + select BINMAN if SPL + select SYS_CACHE_THEAD_CMO + select CLK_THEAD + imply CPU + imply CPU_RISCV + imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE) + imply RISCV_ACLINT if RISCV_MMODE + imply SPL_RISCV_ACLINT if SPL_RISCV_MMODE + imply CMD_CPU + imply SPL_CPU + imply SPL_OPENSBI + imply SPL_LOAD_FIT diff --git a/arch/riscv/cpu/th1520/Makefile b/arch/riscv/cpu/th1520/Makefile new file mode 100644 index 00000000000..5d806c06e2e --- /dev/null +++ b/arch/riscv/cpu/th1520/Makefile @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2025, Yao Zi <ziyao@disroot.org> + +obj-y += cache.o +obj-y += cpu.o +obj-y += dram.o +obj-y += spl.o diff --git a/arch/riscv/cpu/th1520/cache.c b/arch/riscv/cpu/th1520/cache.c new file mode 100644 index 00000000000..08aa1f789fd --- /dev/null +++ b/arch/riscv/cpu/th1520/cache.c @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2025 Yao Zi <ziyao@disroot.org> + */ + +#include <asm/io.h> +#include <cpu_func.h> +#include <linux/bitops.h> + +#define CSR_MHCR 0x7c1 +#define CSR_MHCR_IE BIT(0) +#define CSR_MHCR_DE BIT(1) + +void icache_enable(void) +{ + csr_write(CSR_MHCR, csr_read(CSR_MHCR) | CSR_MHCR_IE); +} + +void dcache_enable(void) +{ + csr_write(CSR_MHCR, csr_read(CSR_MHCR) | CSR_MHCR_DE); +} + +int icache_status(void) +{ + return (csr_read(CSR_MHCR) & CSR_MHCR_IE) != 0; +} + +int dcache_status(void) +{ + return (csr_read(CSR_MHCR) & CSR_MHCR_DE) != 0; +} diff --git a/arch/riscv/cpu/th1520/cpu.c b/arch/riscv/cpu/th1520/cpu.c new file mode 100644 index 00000000000..b83f1272c67 --- /dev/null +++ b/arch/riscv/cpu/th1520/cpu.c @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2025 Yao Zi <ziyao@disroot.org> + * + * TH1520 SoC has a set of undocumented customized PMP registers that are + * configured through MMIO operation. It must be disabled before entering + * the DRAM region, or an exception will be raised. + */ + +#include <asm/io.h> +#include <cpu_func.h> + +#define TH1520_PMP_BASE (void *)0xffdc020000 + +void th1520_invalidate_pmp(void) +{ + /* Invalidate the PMP configuration as in vendor U-Boot code */ + writel(0x0, TH1520_PMP_BASE + 0x0); + + invalidate_icache_all(); +} diff --git a/arch/riscv/cpu/th1520/dram.c b/arch/riscv/cpu/th1520/dram.c new file mode 100644 index 00000000000..91007c0a3d3 --- /dev/null +++ b/arch/riscv/cpu/th1520/dram.c @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com> + */ + +#include <fdtdec.h> +#include <init.h> +#include <asm/global_data.h> +#include <linux/sizes.h> + +DECLARE_GLOBAL_DATA_PTR; + +int dram_init(void) +{ + return fdtdec_setup_mem_size_base(); +} + +int dram_init_banksize(void) +{ + return fdtdec_setup_memory_banksize(); +} diff --git a/arch/riscv/cpu/th1520/spl.c b/arch/riscv/cpu/th1520/spl.c new file mode 100644 index 00000000000..362fe895f86 --- /dev/null +++ b/arch/riscv/cpu/th1520/spl.c @@ -0,0 +1,96 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2025 Yao Zi <ziyao@disroot.org> + */ +#include <asm/arch/iopmp.h> +#include <asm/io.h> +#include <dm.h> +#include <linux/sizes.h> +#include <log.h> +#include <init.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define TH1520_SUBSYS_CLK (void __iomem *)(0xffff011000 + 0x220) +#define TH1520_SUBSYS_CLK_VO_EN BIT(2) +#define TH1520_SUBSYS_CLK_VI_EN BIT(1) +#define TH1520_SUBSYS_CLK_DSP_EN BIT(0) +#define TH1520_SUBSYS_RST (void __iomem *)(0xffff015000 + 0x220) +#define TH1520_SUBSYS_RST_VP_N BIT(3) +#define TH1520_SUBSYS_RST_VO_N BIT(2) +#define TH1520_SUBSYS_RST_VI_N BIT(1) +#define TH1520_SUBSYS_RST_DSP_N BIT(0) + +int spl_dram_init(void) +{ + int ret; + struct udevice *dev; + + ret = fdtdec_setup_mem_size_base(); + if (ret) { + printf("failed to setup memory size and base: %d\n", ret); + return ret; + } + + /* DDR init */ + ret = uclass_get_device(UCLASS_RAM, 0, &dev); + if (ret) { + printf("DRAM init failed: %d\n", ret); + return ret; + } + + return 0; +} + +static void __iomem *th1520_iopmp_regs[] = { + TH1520_IOPMP_EMMC, + TH1520_IOPMP_SDIO0, + TH1520_IOPMP_SDIO1, + TH1520_IOPMP_USB0, + TH1520_IOPMP_AO, + TH1520_IOPMP_AUD, + TH1520_IOPMP_CHIP_DBG, + TH1520_IOPMP_EIP120I, + TH1520_IOPMP_EIP120II, + TH1520_IOPMP_EIP120III, + TH1520_IOPMP_ISP0, + TH1520_IOPMP_ISP1, + TH1520_IOPMP_DW200, + TH1520_IOPMP_VIPRE, + TH1520_IOPMP_VENC, + TH1520_IOPMP_VDEC, + TH1520_IOPMP_G2D, + TH1520_IOPMP_FCE, + TH1520_IOPMP_NPU, + TH1520_IOPMP_DPU0, + TH1520_IOPMP_DPU1, + TH1520_IOPMP_GPU, + TH1520_IOPMP_GMAC1, + TH1520_IOPMP_GMAC2, + TH1520_IOPMP_DMAC, + TH1520_IOPMP_TEE_DMAC, + TH1520_IOPMP_DSP0, + TH1520_IOPMP_DSP1, +}; + +void harts_early_init(void) +{ + int i; + + /* + * Set IOPMPs to the default attribute, allowing the application + * processor to access various peripherals. Subsystem clocks should be + * enabled and resets should be deasserted ahead of time, or the HART + * will hang when configuring corresponding IOPMP entries. + */ + setbits_le32(TH1520_SUBSYS_CLK, TH1520_SUBSYS_CLK_VO_EN | + TH1520_SUBSYS_CLK_VI_EN | + TH1520_SUBSYS_CLK_DSP_EN); + setbits_le32(TH1520_SUBSYS_RST, TH1520_SUBSYS_RST_VP_N | + TH1520_SUBSYS_RST_VO_N | + TH1520_SUBSYS_RST_VI_N | + TH1520_SUBSYS_RST_DSP_N); + + for (i = 0; i < ARRAY_SIZE(th1520_iopmp_regs); i++) + writel(TH1520_IOPMP_DEFAULT_ATTR, th1520_iopmp_regs[i]); +} diff --git a/arch/riscv/dts/binman.dtsi b/arch/riscv/dts/binman.dtsi index 5aeeeddb59f..c5b0464d6a7 100644 --- a/arch/riscv/dts/binman.dtsi +++ b/arch/riscv/dts/binman.dtsi @@ -5,6 +5,12 @@ #include <config.h> +#ifdef CONFIG_64BIT +#define ARCH "riscv64" +#else +#define ARCH "riscv" + +#endif / { binman: binman { multiple-images; @@ -31,12 +37,11 @@ description = "U-Boot"; type = "standalone"; os = "U-Boot"; - arch = "riscv"; + arch = ARCH; compression = "none"; load = /bits/ 64 <CONFIG_TEXT_BASE>; uboot_blob: u-boot-nodtb { - filename = "u-boot-nodtb.bin"; }; }; #else @@ -44,7 +49,7 @@ description = "Linux"; type = "standalone"; os = "Linux"; - arch = "riscv"; + arch = ARCH; compression = "none"; load = /bits/ 64 <CONFIG_TEXT_BASE>; @@ -57,7 +62,7 @@ tee { description = "OP-TEE"; type = "tee"; - arch = "riscv"; + arch = ARCH; compression = "none"; os = "tee"; load = /bits/ 64 <CONFIG_SPL_OPTEE_LOAD_ADDR>; @@ -71,7 +76,7 @@ description = "OpenSBI fw_dynamic Firmware"; type = "firmware"; os = "opensbi"; - arch = "riscv"; + arch = ARCH; compression = "none"; load = /bits/ 64 <CONFIG_SPL_OPENSBI_LOAD_ADDR>; entry = /bits/ 64 <CONFIG_SPL_OPENSBI_LOAD_ADDR>; diff --git a/arch/riscv/dts/jh7110-common-u-boot.dtsi b/arch/riscv/dts/jh7110-common-u-boot.dtsi index 6d85b2d91a7..049b0a7ce28 100644 --- a/arch/riscv/dts/jh7110-common-u-boot.dtsi +++ b/arch/riscv/dts/jh7110-common-u-boot.dtsi @@ -27,7 +27,6 @@ bootph-pre-ram; reg-offset = <0>; current-speed = <115200>; - clock-frequency = <24000000>; }; &mmc0 { diff --git a/arch/riscv/dts/jh7110-u-boot.dtsi b/arch/riscv/dts/jh7110-u-boot.dtsi index a9e318c4a31..f8d13277d24 100644 --- a/arch/riscv/dts/jh7110-u-boot.dtsi +++ b/arch/riscv/dts/jh7110-u-boot.dtsi @@ -6,46 +6,6 @@ #include <dt-bindings/reset/starfive,jh7110-crg.h> / { - cpus: cpus { - bootph-pre-ram; - - S7_0: cpu@0 { - bootph-pre-ram; - status = "okay"; - cpu0_intc: interrupt-controller { - bootph-pre-ram; - }; - }; - - U74_1: cpu@1 { - bootph-pre-ram; - cpu1_intc: interrupt-controller { - bootph-pre-ram; - }; - }; - - U74_2: cpu@2 { - bootph-pre-ram; - cpu2_intc: interrupt-controller { - bootph-pre-ram; - }; - }; - - U74_3: cpu@3 { - bootph-pre-ram; - cpu3_intc: interrupt-controller { - bootph-pre-ram; - }; - }; - - U74_4: cpu@4 { - bootph-pre-ram; - cpu4_intc: interrupt-controller { - bootph-pre-ram; - }; - }; - }; - timer { compatible = "riscv,timer"; interrupts-extended = <&cpu0_intc 5>, @@ -58,10 +18,6 @@ soc { bootph-pre-ram; - clint: timer@2000000 { - bootph-pre-ram; - }; - dmc: dmc@15700000 { bootph-pre-ram; compatible = "starfive,jh7110-dmc"; @@ -78,6 +34,34 @@ }; }; +&clint { + bootph-pre-ram; +}; + +&cpu0_intc { + bootph-pre-ram; +}; + +&cpu1_intc { + bootph-pre-ram; +}; + +&cpu2_intc { + bootph-pre-ram; +}; + +&cpu3_intc { + bootph-pre-ram; +}; + +&cpu4_intc { + bootph-pre-ram; +}; + +&cpus { + bootph-pre-ram; +}; + &osc { bootph-pre-ram; }; @@ -107,6 +91,7 @@ }; &syscrg { + assigned-clock-rates = <0>; /* cpufreq not implemented, use defaults */ bootph-pre-ram; }; diff --git a/arch/riscv/dts/th1520-lichee-module-4a.dtsi b/arch/riscv/dts/th1520-lichee-module-4a.dtsi index 86a81bdcf77..9b255f8243c 100644 --- a/arch/riscv/dts/th1520-lichee-module-4a.dtsi +++ b/arch/riscv/dts/th1520-lichee-module-4a.dtsi @@ -14,6 +14,7 @@ memory@0 { device_type = "memory"; reg = <0x0 0x00000000 0x2 0x00000000>; + bootph-pre-ram; }; }; @@ -25,14 +26,6 @@ clock-frequency = <32768>; }; -&apb_clk { - clock-frequency = <62500000>; -}; - -&uart_sclk { - clock-frequency = <100000000>; -}; - &emmc { bus-width = <8>; max-frequency = <198000000>; diff --git a/arch/riscv/dts/th1520-lichee-pi-4a.dts b/arch/riscv/dts/th1520-lichee-pi-4a.dts index a1248b2ee3a..49af88b7adf 100644 --- a/arch/riscv/dts/th1520-lichee-pi-4a.dts +++ b/arch/riscv/dts/th1520-lichee-pi-4a.dts @@ -4,6 +4,7 @@ */ #include "th1520-lichee-module-4a.dtsi" +#include "thead-th1520-binman.dtsi" / { model = "Sipeed Lichee Pi 4A"; diff --git a/arch/riscv/dts/th1520.dtsi b/arch/riscv/dts/th1520.dtsi index cbe3481fadd..28107a9f354 100644 --- a/arch/riscv/dts/th1520.dtsi +++ b/arch/riscv/dts/th1520.dtsi @@ -4,6 +4,7 @@ * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org> */ +#include <dt-bindings/clock/thead,th1520-clk-ap.h> #include <dt-bindings/interrupt-controller/irq.h> / { @@ -14,6 +15,7 @@ cpus: cpus { #address-cells = <1>; #size-cells = <0>; + bootph-pre-ram; timebase-frequency = <3000000>; c910_0: cpu@0 { @@ -21,6 +23,7 @@ device_type = "cpu"; riscv,isa = "rv64imafdc"; reg = <0>; + bootph-pre-ram; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -42,6 +45,7 @@ device_type = "cpu"; riscv,isa = "rv64imafdc"; reg = <1>; + bootph-pre-ram; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -63,6 +67,7 @@ device_type = "cpu"; riscv,isa = "rv64imafdc"; reg = <2>; + bootph-pre-ram; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -84,6 +89,7 @@ device_type = "cpu"; riscv,isa = "rv64imafdc"; reg = <3>; + bootph-pre-ram; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -122,25 +128,6 @@ #clock-cells = <0>; }; - apb_clk: apb-clk-clock { - compatible = "fixed-clock"; - clock-output-names = "apb_clk"; - #clock-cells = <0>; - }; - - uart_sclk: uart-sclk-clock { - compatible = "fixed-clock"; - clock-output-names = "uart_sclk"; - #clock-cells = <0>; - }; - - sdhci_clk: sdhci-clock { - compatible = "fixed-clock"; - clock-frequency = <198000000>; - clock-output-names = "sdhci_clk"; - #clock-cells = <0>; - }; - soc { compatible = "simple-bus"; interrupt-parent = <&plic>; @@ -173,8 +160,10 @@ uart0: serial@ffe7014000 { compatible = "snps,dw-apb-uart"; reg = <0xff 0xe7014000 0x0 0x100>; + bootph-pre-ram; interrupts = <36 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&uart_sclk>; + clocks = <&clk CLK_UART_SCLK>, <&clk CLK_UART0_PCLK>; + clock-names = "buadclk", "apb_pclk"; reg-shift = <2>; reg-io-width = <4>; status = "disabled"; @@ -184,7 +173,7 @@ compatible = "thead,th1520-dwcmshc"; reg = <0xff 0xe7080000 0x0 0x10000>; interrupts = <62 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&sdhci_clk>; + clocks = <&clk CLK_EMMC_SDIO>; clock-names = "core"; status = "disabled"; }; @@ -193,7 +182,7 @@ compatible = "thead,th1520-dwcmshc"; reg = <0xff 0xe7090000 0x0 0x10000>; interrupts = <64 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&sdhci_clk>; + clocks = <&clk CLK_EMMC_SDIO>; clock-names = "core"; status = "disabled"; }; @@ -202,7 +191,7 @@ compatible = "thead,th1520-dwcmshc"; reg = <0xff 0xe70a0000 0x0 0x10000>; interrupts = <71 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&sdhci_clk>; + clocks = <&clk CLK_EMMC_SDIO>; clock-names = "core"; status = "disabled"; }; @@ -211,7 +200,8 @@ compatible = "snps,dw-apb-uart"; reg = <0xff 0xe7f00000 0x0 0x100>; interrupts = <37 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&uart_sclk>; + clocks = <&clk CLK_UART_SCLK>, <&clk CLK_UART1_PCLK>; + clock-names = "buadclk", "apb_pclk"; reg-shift = <2>; reg-io-width = <4>; status = "disabled"; @@ -221,7 +211,8 @@ compatible = "snps,dw-apb-uart"; reg = <0xff 0xe7f04000 0x0 0x100>; interrupts = <39 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&uart_sclk>; + clocks = <&clk CLK_UART_SCLK>, <&clk CLK_UART3_PCLK>; + clock-names = "buadclk", "apb_pclk"; reg-shift = <2>; reg-io-width = <4>; status = "disabled"; @@ -230,6 +221,8 @@ gpio2: gpio@ffe7f34000 { compatible = "snps,dw-apb-gpio"; reg = <0xff 0xe7f34000 0x0 0x1000>; + clocks = <&clk CLK_GPIO2>; + clock-names = "bus"; #address-cells = <1>; #size-cells = <0>; @@ -248,6 +241,8 @@ gpio3: gpio@ffe7f38000 { compatible = "snps,dw-apb-gpio"; reg = <0xff 0xe7f38000 0x0 0x1000>; + clocks = <&clk CLK_GPIO3>; + clock-names = "bus"; #address-cells = <1>; #size-cells = <0>; @@ -266,6 +261,8 @@ gpio0: gpio@ffec005000 { compatible = "snps,dw-apb-gpio"; reg = <0xff 0xec005000 0x0 0x1000>; + clocks = <&clk CLK_GPIO0>; + clock-names = "bus"; #address-cells = <1>; #size-cells = <0>; @@ -284,6 +281,8 @@ gpio1: gpio@ffec006000 { compatible = "snps,dw-apb-gpio"; reg = <0xff 0xec006000 0x0 0x1000>; + clocks = <&clk CLK_GPIO1>; + clock-names = "bus"; #address-cells = <1>; #size-cells = <0>; @@ -303,16 +302,24 @@ compatible = "snps,dw-apb-uart"; reg = <0xff 0xec010000 0x0 0x4000>; interrupts = <38 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&uart_sclk>; + clocks = <&clk CLK_UART_SCLK>, <&clk CLK_UART2_PCLK>; + clock-names = "buadclk", "apb_pclk"; reg-shift = <2>; reg-io-width = <4>; status = "disabled"; }; + clk: clock-controller@ffef010000 { + compatible = "thead,th1520-clk-ap"; + reg = <0xff 0xef010000 0x0 0x1000>; + clocks = <&osc>; + #clock-cells = <1>; + }; + timer0: timer@ffefc32000 { compatible = "snps,dw-apb-timer"; reg = <0xff 0xefc32000 0x0 0x14>; - clocks = <&apb_clk>; + clocks = <&clk CLK_PERI_APB_PCLK>; clock-names = "timer"; interrupts = <16 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; @@ -321,7 +328,7 @@ timer1: timer@ffefc32014 { compatible = "snps,dw-apb-timer"; reg = <0xff 0xefc32014 0x0 0x14>; - clocks = <&apb_clk>; + clocks = <&clk CLK_PERI_APB_PCLK>; clock-names = "timer"; interrupts = <17 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; @@ -330,7 +337,7 @@ timer2: timer@ffefc32028 { compatible = "snps,dw-apb-timer"; reg = <0xff 0xefc32028 0x0 0x14>; - clocks = <&apb_clk>; + clocks = <&clk CLK_PERI_APB_PCLK>; clock-names = "timer"; interrupts = <18 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; @@ -339,7 +346,7 @@ timer3: timer@ffefc3203c { compatible = "snps,dw-apb-timer"; reg = <0xff 0xefc3203c 0x0 0x14>; - clocks = <&apb_clk>; + clocks = <&clk CLK_PERI_APB_PCLK>; clock-names = "timer"; interrupts = <19 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; @@ -349,7 +356,8 @@ compatible = "snps,dw-apb-uart"; reg = <0xff 0xf7f08000 0x0 0x4000>; interrupts = <40 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&uart_sclk>; + clocks = <&clk CLK_UART_SCLK>, <&clk CLK_UART4_PCLK>; + clock-names = "buadclk", "apb_pclk"; reg-shift = <2>; reg-io-width = <4>; status = "disabled"; @@ -359,16 +367,27 @@ compatible = "snps,dw-apb-uart"; reg = <0xff 0xf7f0c000 0x0 0x4000>; interrupts = <41 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&uart_sclk>; + clocks = <&clk CLK_UART_SCLK>, <&clk CLK_UART5_PCLK>; + clock-names = "buadclk", "apb_pclk"; reg-shift = <2>; reg-io-width = <4>; status = "disabled"; }; + ddrc: ddrc@fffd000000 { + compatible = "thead,th1520-ddrc"; + reg = <0xff 0xfd000000 0x0 0x1000000>, + <0xff 0xfe000000 0x0 0x1000000>, + <0xff 0xff000000 0x0 0x4000>, + <0xff 0xff005000 0x0 0x1000>; + reg-names = "phy-0", "phy-1", "ctrl", "sys"; + bootph-pre-ram; + }; + timer4: timer@ffffc33000 { compatible = "snps,dw-apb-timer"; reg = <0xff 0xffc33000 0x0 0x14>; - clocks = <&apb_clk>; + clocks = <&clk CLK_PERI_APB_PCLK>; clock-names = "timer"; interrupts = <20 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; @@ -377,7 +396,7 @@ timer5: timer@ffffc33014 { compatible = "snps,dw-apb-timer"; reg = <0xff 0xffc33014 0x0 0x14>; - clocks = <&apb_clk>; + clocks = <&clk CLK_PERI_APB_PCLK>; clock-names = "timer"; interrupts = <21 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; @@ -386,7 +405,7 @@ timer6: timer@ffffc33028 { compatible = "snps,dw-apb-timer"; reg = <0xff 0xffc33028 0x0 0x14>; - clocks = <&apb_clk>; + clocks = <&clk CLK_PERI_APB_PCLK>; clock-names = "timer"; interrupts = <22 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; @@ -395,7 +414,7 @@ timer7: timer@ffffc3303c { compatible = "snps,dw-apb-timer"; reg = <0xff 0xffc3303c 0x0 0x14>; - clocks = <&apb_clk>; + clocks = <&clk CLK_PERI_APB_PCLK>; clock-names = "timer"; interrupts = <23 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; diff --git a/arch/riscv/dts/thead-th1520-binman.dtsi b/arch/riscv/dts/thead-th1520-binman.dtsi new file mode 100644 index 00000000000..f060639e1c6 --- /dev/null +++ b/arch/riscv/dts/thead-th1520-binman.dtsi @@ -0,0 +1,55 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2025 Yao Zi <ziyao@disroot.org> + */ + +#include <config.h> + +/ { + binman: binman { + }; +}; + +&binman { + filename = "u-boot-with-spl.bin"; + + u-boot-spl { + }; + + ddr-fw { + filename = "th1520-ddr-firmware.bin"; + type = "blob-ext"; + }; + + fit { + offset = <CONFIG_SPL_PAD_TO>; + + description = "Configuration to load M-mode U-Boot"; + + #address-cells = <2>; + fit,fdt-list = "of-list"; + + images { + uboot { + description = "U-Boot"; + type = "standalone"; + os = "U-boot"; + arch = "riscv"; + compression = "none"; + load = /bits/ 64 <CONFIG_TEXT_BASE>; + + uboot_blob: u-boot { + }; + }; + }; + + configurations { + default = "conf-th1520-lichee-pi-4a"; + + conf-th1520-lichee-pi-4a { + description = "th1520-lichee-pi-4a"; + loadables = "uboot"; + }; + }; + }; +}; diff --git a/arch/riscv/include/asm/arch-th1520/cpu.h b/arch/riscv/include/asm/arch-th1520/cpu.h new file mode 100644 index 00000000000..837f0b8d06b --- /dev/null +++ b/arch/riscv/include/asm/arch-th1520/cpu.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (c) 2025 Yao Zi <ziyao@disroot.org> + */ + +#ifndef _ASM_TH1520_CPU_H_ +#define _ASM_TH1520_CPU_H_ +void th1520_invalidate_pmp(void); +#endif /* _ASM_TH1520_CPU_H_ */ diff --git a/arch/riscv/include/asm/arch-th1520/iopmp.h b/arch/riscv/include/asm/arch-th1520/iopmp.h new file mode 100644 index 00000000000..3dc766b5bff --- /dev/null +++ b/arch/riscv/include/asm/arch-th1520/iopmp.h @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2025 Yao Zi <ziyao@disroot.org> + */ +#ifndef _ASM_ARCH_TH1520_IOPMP_H_ +#define _ASM_ARCH_TH1520_IOPMP_H_ + +#define TH1520_IOPMP_EMMC (void *)0xfffc0280c0 +#define TH1520_IOPMP_SDIO0 (void *)0xfffc0290c0 +#define TH1520_IOPMP_SDIO1 (void *)0xfffc02a0c0 +#define TH1520_IOPMP_USB0 (void *)0xfffc02e0c0 +#define TH1520_IOPMP_AO (void *)0xffffc210c0 +#define TH1520_IOPMP_AUD (void *)0xffffc220c0 +#define TH1520_IOPMP_CHIP_DBG (void *)0xffffc370c0 +#define TH1520_IOPMP_EIP120I (void *)0xffff2200c0 +#define TH1520_IOPMP_EIP120II (void *)0xffff2300c0 +#define TH1520_IOPMP_EIP120III (void *)0xffff2400c0 +#define TH1520_IOPMP_ISP0 (void *)0xfff40800c0 +#define TH1520_IOPMP_ISP1 (void *)0xfff40810c0 +#define TH1520_IOPMP_DW200 (void *)0xfff40820c0 +#define TH1520_IOPMP_VIPRE (void *)0xfff40830c0 +#define TH1520_IOPMP_VENC (void *)0xfffcc600c0 +#define TH1520_IOPMP_VDEC (void *)0xfffcc610c0 +#define TH1520_IOPMP_G2D (void *)0xfffcc620c0 +#define TH1520_IOPMP_FCE (void *)0xfffcc630c0 +#define TH1520_IOPMP_NPU (void *)0xffff01c0c0 +#define TH1520_IOPMP_DPU0 (void *)0xffff5200c0 +#define TH1520_IOPMP_DPU1 (void *)0xffff5210c0 +#define TH1520_IOPMP_GPU (void *)0xffff5220c0 +#define TH1520_IOPMP_GMAC1 (void *)0xfffc0010c0 +#define TH1520_IOPMP_GMAC2 (void *)0xfffc0020c0 +#define TH1520_IOPMP_DMAC (void *)0xffffc200c0 +#define TH1520_IOPMP_TEE_DMAC (void *)0xffff2500c0 +#define TH1520_IOPMP_DSP0 (void *)0xffff0580c0 +#define TH1520_IOPMP_DSP1 (void *)0xffff0590c0 +#define TH1520_IOPMP_AUDIO (void *)0xffffc220c0 +#define TH1520_IOPMP_AUDIO0 (void *)0xffcb02e0c0 +#define TH1520_IOPMP_AUDIO1 (void *)0xffcb02f0c0 + +#define TH1520_IOPMP_DEFAULT_ATTR 0xffffffff + +#endif // _ASM_ARCH_TH1520_IOPMP_H_ diff --git a/arch/riscv/include/asm/arch-th1520/spl.h b/arch/riscv/include/asm/arch-th1520/spl.h new file mode 100644 index 00000000000..59aed8cad62 --- /dev/null +++ b/arch/riscv/include/asm/arch-th1520/spl.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2025 Yao Zi <ziyao@disroot.org> + */ +#ifndef _ASM_ARCH_TH1520_SPL_H_ +#define _ASM_ARCH_TH1520_SPL_H_ + +void spl_dram_init(void); + +#endif // _ASM_ARCH_TH1520_SPL_H_ diff --git a/arch/riscv/include/asm/global_data.h b/arch/riscv/include/asm/global_data.h index d356752a56a..47b5e2cfc8f 100644 --- a/arch/riscv/include/asm/global_data.h +++ b/arch/riscv/include/asm/global_data.h @@ -14,6 +14,7 @@ #include <asm/smp.h> #include <asm/u-boot.h> #include <compiler.h> +#include <config.h> /* Architecture-specific global data */ struct arch_global_data { @@ -47,8 +48,26 @@ struct arch_global_data { #include <asm-generic/global_data.h> +#if defined(__clang__) || CONFIG_IS_ENABLED(LTO) + +#define DECLARE_GLOBAL_DATA_PTR +#define gd get_gd() + +static inline gd_t *get_gd(void) +{ + gd_t *gd_ptr; + + __asm__ volatile ("mv %0, gp\n" : "=r" (gd_ptr)); + + return gd_ptr; +} + +#else + #define DECLARE_GLOBAL_DATA_PTR register gd_t *gd asm ("gp") +#endif + static inline void set_gd(volatile gd_t *gd_ptr) { #ifdef CONFIG_64BIT diff --git a/arch/riscv/include/asm/insn-def.h b/arch/riscv/include/asm/insn-def.h index 19a10cad84c..1869342b167 100644 --- a/arch/riscv/include/asm/insn-def.h +++ b/arch/riscv/include/asm/insn-def.h @@ -5,8 +5,8 @@ * Ported from linux insn-def.h. */ -#ifndef _ASM_RISCV_BARRIER_H -#define _ASM_RISCV_BARRIER_H +#ifndef _ASM_RISCV_INSN_DEF_H +#define _ASM_RISCV_INSN_DEF_H #define INSN_I_SIMM12_SHIFT 20 #define INSN_I_RS1_SHIFT 15 @@ -36,4 +36,4 @@ __INSN_I(RV_##opcode, RV_##func3, RV_##rd, \ RV_##rs1, RV_##simm12) -#endif /* _ASM_RISCV_BARRIER_H */ +#endif /* _ASM_RISCV_INSN_DEF_H */ diff --git a/arch/riscv/include/asm/u-boot.h b/arch/riscv/include/asm/u-boot.h index d5e1d5f3231..a90cc4c21cf 100644 --- a/arch/riscv/include/asm/u-boot.h +++ b/arch/riscv/include/asm/u-boot.h @@ -23,6 +23,10 @@ #include <asm/u-boot-riscv.h> /* For image.h:image_check_target_arch() */ +#ifdef CONFIG_64BIT +#define IH_ARCH_DEFAULT IH_ARCH_RISCV64 +#else #define IH_ARCH_DEFAULT IH_ARCH_RISCV +#endif #endif /* _U_BOOT_H_ */ diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile index 189b35c24d3..db8d235c699 100644 --- a/arch/riscv/lib/Makefile +++ b/arch/riscv/lib/Makefile @@ -11,6 +11,7 @@ obj-$(CONFIG_CMD_BOOTI) += bootm.o image.o obj-$(CONFIG_CMD_GO) += boot.o obj-y += cache.o obj-$(CONFIG_SIFIVE_CACHE) += sifive_cache.o +obj-$(CONFIG_SYS_CACHE_THEAD_CMO) += thead_cmo.o ifeq ($(CONFIG_$(PHASE_)RISCV_MMODE),y) obj-$(CONFIG_$(PHASE_)RISCV_ACLINT) += aclint_ipi.o obj-$(CONFIG_ANDES_PLICSW) += andes_plicsw.o diff --git a/arch/riscv/lib/bootm.c b/arch/riscv/lib/bootm.c index 9544907ab1e..c98c5e76633 100644 --- a/arch/riscv/lib/bootm.c +++ b/arch/riscv/lib/bootm.c @@ -90,6 +90,10 @@ static void boot_jump_linux(struct bootm_headers *images, int flag) announce_and_cleanup(fake); if (!fake) { + if (images->os.arch != IH_ARCH_DEFAULT) { + printf("Image arch not compatible with host arch.\n"); + hang(); + } if (CONFIG_IS_ENABLED(OF_LIBFDT) && images->ft_len) { #ifdef CONFIG_SMP ret = smp_call_function(images->ep, diff --git a/arch/riscv/cpu/cv1800b/cache.c b/arch/riscv/lib/thead_cmo.c index b8051e29e02..b8051e29e02 100644 --- a/arch/riscv/cpu/cv1800b/cache.c +++ b/arch/riscv/lib/thead_cmo.c diff --git a/arch/x86/lib/tables.c b/arch/x86/lib/tables.c index ec52992209f..d7f183f95dc 100644 --- a/arch/x86/lib/tables.c +++ b/arch/x86/lib/tables.c @@ -126,6 +126,8 @@ int write_tables(void) use_high = true; if (!gd->arch.table_start_high) gd->arch.table_start_high = rom_addr; + if (table->tag == BLOBLISTT_SMBIOS_TABLES) + gd_set_smbios_start(rom_addr); } rom_table_end = table->write(rom_addr); if (!rom_table_end) { |