diff options
Diffstat (limited to 'arch')
24 files changed, 183 insertions, 80 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index f277929c991..6771f14b105 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1124,6 +1124,7 @@ config ARCH_SUNXI select OF_BOARD_SETUP select OF_CONTROL select OF_SEPARATE + select PINCTRL select SPECIFY_CONSOLE_INDEX select SPL_SEPARATE_BSS if SPL select SPL_STACK_R if SPL diff --git a/arch/arm/dts/sun8i-h3-nanopi-neo.dts b/arch/arm/dts/sun8i-h3-nanopi-neo.dts index 9f33f6fae59..df71fab3cf4 100644 --- a/arch/arm/dts/sun8i-h3-nanopi-neo.dts +++ b/arch/arm/dts/sun8i-h3-nanopi-neo.dts @@ -45,6 +45,10 @@ / { model = "FriendlyARM NanoPi NEO"; compatible = "friendlyarm,nanopi-neo", "allwinner,sun8i-h3"; + + aliases { + ethernet0 = &emac; + }; }; &ehci0 { diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h index edd0fbf49fe..437e86479ce 100644 --- a/arch/arm/include/asm/arch-sunxi/gpio.h +++ b/arch/arm/include/asm/arch-sunxi/gpio.h @@ -135,17 +135,13 @@ enum sunxi_gpio_number { #define SUNXI_GPIO_OUTPUT 1 #define SUNXI_GPIO_DISABLE 7 -#define SUNXI_GPA_EMAC 2 -#define SUN6I_GPA_GMAC 2 -#define SUN7I_GPA_GMAC 5 #define SUN8I_H3_GPA_UART0 2 +#define SUN8I_H3_GPA_UART2 2 #define SUN4I_GPB_PWM 2 #define SUN4I_GPB_TWI0 2 #define SUN4I_GPB_TWI1 2 #define SUN5I_GPB_TWI1 2 -#define SUN4I_GPB_TWI2 2 -#define SUN5I_GPB_TWI2 2 #define SUN8I_V3S_GPB_TWI0 2 #define SUN4I_GPB_UART0 2 #define SUN5I_GPB_UART0 2 @@ -164,11 +160,8 @@ enum sunxi_gpio_number { #define SUNXI_GPD_LCD0 2 #define SUNXI_GPD_LVDS0 3 -#define SUNXI_GPD_PWM 2 #define SUNIV_GPE_UART0 5 -#define SUN8I_GPE_TWI2 3 -#define SUN50I_GPE_TWI2 3 #define SUNXI_GPF_SDC0 2 #define SUNXI_GPF_UART0 4 @@ -179,7 +172,6 @@ enum sunxi_gpio_number { #define SUN6I_GPG_SDC1 2 #define SUN8I_GPG_SDC1 2 #define SUN8I_GPG_UART1 2 -#define SUN6I_GPG_TWI3 2 #define SUN5I_GPG_UART1 4 #define SUN6I_GPH_PWM 2 @@ -191,15 +183,12 @@ enum sunxi_gpio_number { #define SUN6I_GPH_TWI1 2 #define SUN8I_GPH_TWI1 2 #define SUN50I_GPH_TWI1 2 -#define SUN6I_GPH_TWI2 2 #define SUN6I_GPH_UART0 2 #define SUN9I_GPH_UART0 2 #define SUN50I_H6_GPH_UART0 2 #define SUN50I_H616_GPH_UART0 2 #define SUNXI_GPI_SDC3 2 -#define SUN7I_GPI_TWI3 3 -#define SUN7I_GPI_TWI4 3 #define SUN6I_GPL0_R_P2WI_SCK 3 #define SUN6I_GPL1_R_P2WI_SDA 3 @@ -224,6 +213,11 @@ enum sunxi_gpio_number { #define SUNXI_GPIO_AXP0_VBUS_ENABLE 5 #define SUNXI_GPIO_AXP0_GPIO_COUNT 6 +struct sunxi_gpio_plat { + struct sunxi_gpio *regs; + char bank_name[3]; +}; + void sunxi_gpio_set_cfgbank(struct sunxi_gpio *pio, int bank_offset, u32 val); void sunxi_gpio_set_cfgpin(u32 pin, u32 val); int sunxi_gpio_get_cfgbank(struct sunxi_gpio *pio, int bank_offset); diff --git a/arch/arm/include/asm/arch-sunxi/i2c.h b/arch/arm/include/asm/arch-sunxi/i2c.h index 1cb2ba6b0ab..3525f22e7df 100644 --- a/arch/arm/include/asm/arch-sunxi/i2c.h +++ b/arch/arm/include/asm/arch-sunxi/i2c.h @@ -13,17 +13,8 @@ #ifdef CONFIG_I2C1_ENABLE #define CONFIG_I2C_MVTWSI_BASE1 SUNXI_TWI1_BASE #endif -#ifdef CONFIG_I2C2_ENABLE -#define CONFIG_I2C_MVTWSI_BASE2 SUNXI_TWI2_BASE -#endif -#ifdef CONFIG_I2C3_ENABLE -#define CONFIG_I2C_MVTWSI_BASE3 SUNXI_TWI3_BASE -#endif -#ifdef CONFIG_I2C4_ENABLE -#define CONFIG_I2C_MVTWSI_BASE4 SUNXI_TWI4_BASE -#endif #ifdef CONFIG_R_I2C_ENABLE -#define CONFIG_I2C_MVTWSI_BASE5 SUNXI_R_TWI_BASE +#define CONFIG_I2C_MVTWSI_BASE2 SUNXI_R_TWI_BASE #endif /* This is abp0-clk on sun4i/5i/7i / abp1-clk on sun6i/sun8i which is 24MHz */ diff --git a/arch/arm/include/asm/arch-sunxi/prcm_sun50i.h b/arch/arm/include/asm/arch-sunxi/prcm_sun50i.h index 5f636e83845..fd63d3aad83 100644 --- a/arch/arm/include/asm/arch-sunxi/prcm_sun50i.h +++ b/arch/arm/include/asm/arch-sunxi/prcm_sun50i.h @@ -37,8 +37,18 @@ struct sunxi_prcm_reg { u32 w1_gate_reset; /* 0x1ec */ u8 res10[0x1c]; /* 0x1f0 */ u32 rtc_gate_reset; /* 0x20c */ + u8 res11[0x34]; /* 0x210 */ + u32 pll_ldo_cfg; /* 0x244 */ + u8 res12[0x8]; /* 0x248 */ + u32 sys_pwroff_gating; /* 0x250 */ + u8 res13[0xbc]; /* 0x254 */ + u32 res_cal_ctrl; /* 0x310 */ + u32 ohms200; /* 0x314 */ + u32 ohms240; /* 0x318 */ + u32 res_cal_status; /* 0x31c */ }; check_member(sunxi_prcm_reg, rtc_gate_reset, 0x20c); +check_member(sunxi_prcm_reg, res_cal_status, 0x31c); #define PRCM_TWI_GATE (1 << 0) #define PRCM_TWI_RESET (1 << 16) diff --git a/arch/arm/include/asm/arch-sunxi/spl.h b/arch/arm/include/asm/arch-sunxi/spl.h index b543d24e5a0..14944a20eac 100644 --- a/arch/arm/include/asm/arch-sunxi/spl.h +++ b/arch/arm/include/asm/arch-sunxi/spl.h @@ -28,8 +28,7 @@ #define SUNIV_BOOTED_FROM_SPI 0xffff4130 #define SUNIV_BOOTED_FROM_MMC1 0xffff4150 -#define is_boot0_magic(addr) (memcmp((void *)(addr), BOOT0_MAGIC, 8) == 0) - uint32_t sunxi_get_boot_device(void); +uint32_t sunxi_get_spl_size(void); #endif diff --git a/arch/arm/mach-imx/spl.c b/arch/arm/mach-imx/spl.c index 2832b735096..64ca2967721 100644 --- a/arch/arm/mach-imx/spl.c +++ b/arch/arm/mach-imx/spl.c @@ -201,7 +201,7 @@ int g_dnl_get_board_bcd_device_number(int gcnum) #if defined(CONFIG_SPL_MMC) /* called from spl_mmc to see type of boot mode for storage (RAW or FAT) */ -u32 spl_mmc_boot_mode(const u32 boot_device) +u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device) { #if defined(CONFIG_MX7) || defined(CONFIG_IMX8M) || defined(CONFIG_IMX8) switch (get_boot_device()) { diff --git a/arch/arm/mach-k3/am642_init.c b/arch/arm/mach-k3/am642_init.c index 543dea02bca..eabfd570a6b 100644 --- a/arch/arm/mach-k3/am642_init.c +++ b/arch/arm/mach-k3/am642_init.c @@ -208,7 +208,7 @@ void board_init_f(ulong dummy) } } -u32 spl_mmc_boot_mode(const u32 boot_device) +u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device) { switch (boot_device) { case BOOT_DEVICE_MMC1: diff --git a/arch/arm/mach-k3/am6_init.c b/arch/arm/mach-k3/am6_init.c index 8a6b1de7641..86c1a349f1f 100644 --- a/arch/arm/mach-k3/am6_init.c +++ b/arch/arm/mach-k3/am6_init.c @@ -269,7 +269,7 @@ void board_init_f(ulong dummy) spl_enable_dcache(); } -u32 spl_mmc_boot_mode(const u32 boot_device) +u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device) { #if defined(CONFIG_SUPPORT_EMMC_BOOT) u32 devstat = readl(CTRLMMR_MAIN_DEVSTAT); diff --git a/arch/arm/mach-k3/j721e_init.c b/arch/arm/mach-k3/j721e_init.c index c4b6b180505..f503f15f192 100644 --- a/arch/arm/mach-k3/j721e_init.c +++ b/arch/arm/mach-k3/j721e_init.c @@ -291,7 +291,7 @@ void board_init_f(ulong dummy) spl_enable_dcache(); } -u32 spl_mmc_boot_mode(const u32 boot_device) +u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device) { switch (boot_device) { case BOOT_DEVICE_MMC1: diff --git a/arch/arm/mach-k3/j721s2_init.c b/arch/arm/mach-k3/j721s2_init.c index 58a86541b79..2e64e44a80e 100644 --- a/arch/arm/mach-k3/j721s2_init.c +++ b/arch/arm/mach-k3/j721s2_init.c @@ -173,7 +173,7 @@ void board_init_f(ulong dummy) spl_enable_dcache(); } -u32 spl_mmc_boot_mode(const u32 boot_device) +u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device) { switch (boot_device) { case BOOT_DEVICE_MMC1: diff --git a/arch/arm/mach-mvebu/spl.c b/arch/arm/mach-mvebu/spl.c index 5ad323f9d9d..fa9a1d7ab65 100644 --- a/arch/arm/mach-mvebu/spl.c +++ b/arch/arm/mach-mvebu/spl.c @@ -96,7 +96,7 @@ struct kwbimage_main_hdr_v1 { } __packed; #ifdef CONFIG_SPL_MMC -u32 spl_mmc_boot_mode(const u32 boot_device) +u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device) { return MMCSD_MODE_RAW; } diff --git a/arch/arm/mach-omap2/boot-common.c b/arch/arm/mach-omap2/boot-common.c index afc35856419..c463c96c74c 100644 --- a/arch/arm/mach-omap2/boot-common.c +++ b/arch/arm/mach-omap2/boot-common.c @@ -196,7 +196,7 @@ u32 spl_boot_device(void) return gd->arch.omap_boot_device; } -u32 spl_mmc_boot_mode(const u32 boot_device) +u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device) { return gd->arch.omap_boot_mode; } diff --git a/arch/arm/mach-rockchip/spl.c b/arch/arm/mach-rockchip/spl.c index 7a8db632b80..d51a0727b47 100644 --- a/arch/arm/mach-rockchip/spl.c +++ b/arch/arm/mach-rockchip/spl.c @@ -66,7 +66,7 @@ u32 spl_boot_device(void) return boot_device; } -u32 spl_mmc_boot_mode(const u32 boot_device) +u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device) { return MMCSD_MODE_RAW; } diff --git a/arch/arm/mach-socfpga/spl_a10.c b/arch/arm/mach-socfpga/spl_a10.c index d2f454cd246..ec67a5b0eb7 100644 --- a/arch/arm/mach-socfpga/spl_a10.c +++ b/arch/arm/mach-socfpga/spl_a10.c @@ -99,7 +99,7 @@ u32 spl_boot_device(void) } #ifdef CONFIG_SPL_MMC -u32 spl_mmc_boot_mode(const u32 boot_device) +u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device) { #if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4) return MMCSD_MODE_FS; diff --git a/arch/arm/mach-socfpga/spl_gen5.c b/arch/arm/mach-socfpga/spl_gen5.c index 441d893333c..287fbd1713c 100644 --- a/arch/arm/mach-socfpga/spl_gen5.c +++ b/arch/arm/mach-socfpga/spl_gen5.c @@ -53,7 +53,7 @@ u32 spl_boot_device(void) } #ifdef CONFIG_SPL_MMC -u32 spl_mmc_boot_mode(const u32 boot_device) +u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device) { #if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4) return MMCSD_MODE_FS; diff --git a/arch/arm/mach-stm32mp/spl.c b/arch/arm/mach-stm32mp/spl.c index 51fe0698fab..78fa9d7edd2 100644 --- a/arch/arm/mach-stm32mp/spl.c +++ b/arch/arm/mach-stm32mp/spl.c @@ -55,7 +55,7 @@ u32 spl_boot_device(void) return BOOT_DEVICE_MMC1; } -u32 spl_mmc_boot_mode(const u32 boot_device) +u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device) { return MMCSD_MODE_RAW; } diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index 73da6b8f615..1f43b253248 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -755,20 +755,6 @@ config I2C1_ENABLE ---help--- See I2C0_ENABLE help text. -config I2C2_ENABLE - bool "Enable I2C/TWI controller 2" - select CMD_I2C - ---help--- - See I2C0_ENABLE help text. - -if MACH_SUN6I || MACH_SUN7I -config I2C3_ENABLE - bool "Enable I2C/TWI controller 3" - select CMD_I2C - ---help--- - See I2C0_ENABLE help text. -endif - if SUNXI_GEN_SUN6I || SUN50I_GEN_H6 config R_I2C_ENABLE bool "Enable the PRCM I2C/TWI controller" @@ -779,14 +765,6 @@ config R_I2C_ENABLE Set this to y to enable the I2C controller which is part of the PRCM. endif -if MACH_SUN7I -config I2C4_ENABLE - bool "Enable I2C/TWI controller 4" - select CMD_I2C - ---help--- - See I2C0_ENABLE help text. -endif - config AXP_GPIO bool "Enable support for gpio-s on axp PMICs" depends on AXP_PMIC_BUS @@ -1069,6 +1047,8 @@ config BLUETOOTH_DT_DEVICE_FIXUP The used address is "bdaddr" if set, and "ethaddr" with the LSB flipped elsewise. +source "board/sunxi/Kconfig" + endif config CHIP_DIP_SCAN diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c index 9a7673d82dc..173e946465d 100644 --- a/arch/arm/mach-sunxi/board.c +++ b/arch/arm/mach-sunxi/board.c @@ -150,6 +150,10 @@ static int gpio_init(void) sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG_UART1); sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG_UART1); sunxi_gpio_set_pull(SUNXI_GPG(4), SUNXI_GPIO_PULL_UP); +#elif CONFIG_CONS_INDEX == 3 && defined(CONFIG_MACH_SUN8I_H3) + sunxi_gpio_set_cfgpin(SUNXI_GPA(0), SUN8I_H3_GPA_UART2); + sunxi_gpio_set_cfgpin(SUNXI_GPA(1), SUN8I_H3_GPA_UART2); + sunxi_gpio_set_pull(SUNXI_GPA(1), SUNXI_GPIO_PULL_UP); #elif CONFIG_CONS_INDEX == 3 && defined(CONFIG_MACH_SUN8I) sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN8I_GPB_UART2); sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_GPB_UART2); @@ -213,8 +217,21 @@ static int suniv_get_boot_source(void) return SUNXI_INVALID_BOOT_SOURCE; } +static int sunxi_egon_valid(struct boot_file_head *egon_head) +{ + return !memcmp(egon_head->magic, BOOT0_MAGIC, 8); /* eGON.BT0 */ +} + +static int sunxi_toc0_valid(struct toc0_main_info *toc0_info) +{ + return !memcmp(toc0_info->name, TOC0_MAIN_INFO_NAME, 8); /* TOC0.GLH */ +} + static int sunxi_get_boot_source(void) { + struct boot_file_head *egon_head = (void *)SPL_ADDR; + struct toc0_main_info *toc0_info = (void *)SPL_ADDR; + /* * On the ARMv5 SoCs, the SPL header in SRAM is overwritten by the * exception vectors in U-Boot proper, so we won't find any @@ -226,13 +243,15 @@ static int sunxi_get_boot_source(void) !IS_ENABLED(CONFIG_SPL_BUILD)) return SUNXI_BOOTED_FROM_MMC0; - if (!is_boot0_magic(SPL_ADDR + 4)) /* eGON.BT0 */ - return SUNXI_INVALID_BOOT_SOURCE; - if (IS_ENABLED(CONFIG_MACH_SUNIV)) return suniv_get_boot_source(); - else - return readb(SPL_ADDR + 0x28); + if (sunxi_egon_valid(egon_head)) + return readb(&egon_head->boot_media); + if (sunxi_toc0_valid(toc0_info)) + return readb(&toc0_info->platform[0]); + + /* Not a valid image, so we must have been booted via FEL. */ + return SUNXI_INVALID_BOOT_SOURCE; } /* The sunxi internal brom will try to loader external bootloader @@ -278,12 +297,18 @@ uint32_t sunxi_get_boot_device(void) } #ifdef CONFIG_SPL_BUILD -static u32 sunxi_get_spl_size(void) +uint32_t sunxi_get_spl_size(void) { - if (!is_boot0_magic(SPL_ADDR + 4)) /* eGON.BT0 */ - return 0; + struct boot_file_head *egon_head = (void *)SPL_ADDR; + struct toc0_main_info *toc0_info = (void *)SPL_ADDR; + + if (sunxi_egon_valid(egon_head)) + return readl(&egon_head->length); + if (sunxi_toc0_valid(toc0_info)) + return readl(&toc0_info->length); - return readl(SPL_ADDR + 0x10); + /* Not a valid image, so use the default U-Boot offset. */ + return 0; } /* @@ -321,6 +346,89 @@ __weak void sunxi_sram_init(void) { } +/* + * When booting from an eMMC boot partition, the SPL puts the same boot + * source code into SRAM A1 as when loading the SPL from the normal + * eMMC user data partition: 0x2. So to know where we have been loaded + * from, we repeat the BROM algorithm here: checking for a valid eGON boot + * image at offset 0 of a (potentially) selected boot partition. + * If any of the conditions is not met, it must have been the eMMC user + * data partition. + */ +static bool sunxi_valid_emmc_boot(struct mmc *mmc) +{ + struct blk_desc *bd = mmc_get_blk_desc(mmc); + uint32_t *buffer = (void *)(uintptr_t)CONFIG_SYS_TEXT_BASE; + struct boot_file_head *egon_head = (void *)buffer; + int bootpart = EXT_CSD_EXTRACT_BOOT_PART(mmc->part_config); + uint32_t spl_size, emmc_checksum, chksum = 0; + ulong count; + + /* The BROM requires BOOT_ACK to be enabled. */ + if (!EXT_CSD_EXTRACT_BOOT_ACK(mmc->part_config)) + return false; + + /* + * The BOOT_BUS_CONDITION register must be 4-bit SDR, with (0x09) + * or without (0x01) high speed timings. + */ + if ((mmc->ext_csd[EXT_CSD_BOOT_BUS_WIDTH] & 0x1b) != 0x01 && + (mmc->ext_csd[EXT_CSD_BOOT_BUS_WIDTH] & 0x1b) != 0x09) + return false; + + /* Partition 0 is the user data partition, bootpart must be 1 or 2. */ + if (bootpart != 1 && bootpart != 2) + return false; + + /* Failure to switch to the boot partition is fatal. */ + if (mmc_switch_part(mmc, bootpart)) + return false; + + /* Read the first block to do some sanity checks on the eGON header. */ + count = blk_dread(bd, 0, 1, buffer); + if (count != 1 || !sunxi_egon_valid(egon_head)) + return false; + + /* Read the rest of the SPL now we know it's halfway sane. */ + spl_size = buffer[4]; + count = blk_dread(bd, 1, DIV_ROUND_UP(spl_size, bd->blksz) - 1, + buffer + bd->blksz / 4); + + /* Save the checksum and replace it with the "stamp value". */ + emmc_checksum = buffer[3]; + buffer[3] = 0x5f0a6c39; + + /* The checksum is a simple ignore-carry addition of all words. */ + for (count = 0; count < spl_size / 4; count++) + chksum += buffer[count]; + + debug("eMMC boot part SPL checksum: stored: 0x%08x, computed: 0x%08x\n", + emmc_checksum, chksum); + + return emmc_checksum == chksum; +} + +u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device) +{ + static u32 result = ~0; + + if (result != ~0) + return result; + + result = MMCSD_MODE_RAW; + if (!IS_SD(mmc) && IS_ENABLED(CONFIG_SUPPORT_EMMC_BOOT)) { + if (sunxi_valid_emmc_boot(mmc)) + result = MMCSD_MODE_EMMCBOOT; + else + mmc_switch_part(mmc, 0); + } + + debug("%s(): %s part\n", __func__, + result == MMCSD_MODE_RAW ? "user" : "boot"); + + return result; +} + void board_init_f(ulong dummy) { sunxi_sram_init(); diff --git a/arch/arm/mach-sunxi/clock_sun50i_h6.c b/arch/arm/mach-sunxi/clock_sun50i_h6.c index a947463e0a5..7926394cf76 100644 --- a/arch/arm/mach-sunxi/clock_sun50i_h6.c +++ b/arch/arm/mach-sunxi/clock_sun50i_h6.c @@ -9,10 +9,24 @@ void clock_init_safe(void) { struct sunxi_ccm_reg *const ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + struct sunxi_prcm_reg *const prcm = + (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE; + + if (IS_ENABLED(CONFIG_MACH_SUN50I_H616)) { + /* this seems to enable PLLs on H616 */ + setbits_le32(&prcm->sys_pwroff_gating, 0x10); + setbits_le32(&prcm->res_cal_ctrl, 2); + } + + clrbits_le32(&prcm->res_cal_ctrl, 1); + setbits_le32(&prcm->res_cal_ctrl, 1); - /* this seems to enable PLLs on H616 */ - if (IS_ENABLED(CONFIG_MACH_SUN50I_H616)) - setbits_le32(SUNXI_PRCM_BASE + 0x250, 0x10); + if (IS_ENABLED(CONFIG_MACH_SUN50I_H6)) { + /* set key field for ldo enable */ + setbits_le32(&prcm->pll_ldo_cfg, 0xA7000000); + /* set PLL VDD LDO output to 1.14 V */ + setbits_le32(&prcm->pll_ldo_cfg, 0x60000); + } clock_set_pll1(408000000); diff --git a/arch/arm/mach-sunxi/dram_sun50i_h6.c b/arch/arm/mach-sunxi/dram_sun50i_h6.c index d05375c9027..b332f3a3e4a 100644 --- a/arch/arm/mach-sunxi/dram_sun50i_h6.c +++ b/arch/arm/mach-sunxi/dram_sun50i_h6.c @@ -12,6 +12,7 @@ #include <asm/arch/clock.h> #include <asm/arch/dram.h> #include <asm/arch/cpu.h> +#include <asm/arch/prcm.h> #include <linux/bitops.h> #include <linux/delay.h> #include <linux/kconfig.h> @@ -665,6 +666,8 @@ unsigned long sunxi_dram_init(void) { struct sunxi_mctl_com_reg * const mctl_com = (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; + struct sunxi_prcm_reg *const prcm = + (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE; struct dram_para para = { .clk = CONFIG_DRAM_CLK, #ifdef CONFIG_SUNXI_DRAM_H6_LPDDR3 @@ -680,9 +683,8 @@ unsigned long sunxi_dram_init(void) unsigned long size; - /* RES_CAL_CTRL_REG in BSP U-boot*/ - setbits_le32(0x7010310, BIT(8)); - clrbits_le32(0x7010318, 0x3f); + setbits_le32(&prcm->res_cal_ctrl, BIT(8)); + clrbits_le32(&prcm->ohms240, 0x3f); mctl_auto_detect_rank_width(¶); mctl_auto_detect_dram_size(¶); diff --git a/arch/arm/mach-sunxi/dram_sun50i_h616.c b/arch/arm/mach-sunxi/dram_sun50i_h616.c index 83e8abc2f8d..454c845a001 100644 --- a/arch/arm/mach-sunxi/dram_sun50i_h616.c +++ b/arch/arm/mach-sunxi/dram_sun50i_h616.c @@ -19,6 +19,7 @@ #include <asm/arch/clock.h> #include <asm/arch/dram.h> #include <asm/arch/cpu.h> +#include <asm/arch/prcm.h> #include <linux/bitops.h> #include <linux/delay.h> #include <linux/kconfig.h> @@ -1001,14 +1002,16 @@ static unsigned long mctl_calc_size(struct dram_para *para) unsigned long sunxi_dram_init(void) { + struct sunxi_prcm_reg *const prcm = + (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE; struct dram_para para = { .clk = CONFIG_DRAM_CLK, .type = SUNXI_DRAM_TYPE_DDR3, }; unsigned long size; - setbits_le32(0x7010310, BIT(8)); - clrbits_le32(0x7010318, 0x3f); + setbits_le32(&prcm->res_cal_ctrl, BIT(8)); + clrbits_le32(&prcm->ohms240, 0x3f); mctl_auto_detect_rank_width(¶); mctl_auto_detect_dram_size(¶); diff --git a/arch/arm/mach-sunxi/spl_spi_sunxi.c b/arch/arm/mach-sunxi/spl_spi_sunxi.c index 734c165e5d2..de9aa68c4ac 100644 --- a/arch/arm/mach-sunxi/spl_spi_sunxi.c +++ b/arch/arm/mach-sunxi/spl_spi_sunxi.c @@ -337,9 +337,9 @@ static int spl_spi_load_image(struct spl_image_info *spl_image, int ret = 0; struct image_header *header; header = (struct image_header *)(CONFIG_SYS_TEXT_BASE); - int load_offset = readl(SPL_ADDR + 0x10); + uint32_t load_offset = sunxi_get_spl_size(); - load_offset = max(load_offset, CONFIG_SYS_SPI_U_BOOT_OFFS); + load_offset = max_t(uint32_t, load_offset, CONFIG_SYS_SPI_U_BOOT_OFFS); spi0_init(); diff --git a/arch/arm/mach-uniphier/mmc-boot-mode.c b/arch/arm/mach-uniphier/mmc-boot-mode.c index e47e5df6480..09cad743c55 100644 --- a/arch/arm/mach-uniphier/mmc-boot-mode.c +++ b/arch/arm/mach-uniphier/mmc-boot-mode.c @@ -7,10 +7,8 @@ #include <mmc.h> #include <spl.h> -u32 spl_mmc_boot_mode(const u32 boot_device) +u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device) { - struct mmc *mmc; - /* * work around a bug in the Boot ROM of LD4, Pro4, and sLD8: * @@ -24,7 +22,6 @@ u32 spl_mmc_boot_mode(const u32 boot_device) * Fixup mmc->part_config here because it is used to determine the * partition which the U-Boot image is read from. */ - mmc = find_mmc_device(0); mmc->part_config &= ~EXT_CSD_BOOT_PART_NUM(PART_ACCESS_MASK); mmc->part_config |= EXT_CSD_BOOT_PARTITION_ENABLE; |