diff options
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/Kconfig | 1 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/Kconfig | 10 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/nonsec_virt.S | 4 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/virt-v7.c | 4 | ||||
| -rw-r--r-- | arch/arm/dts/imx8mm-cl-iot-gate-ied-adc0.dtso (renamed from arch/arm/dts/imx8mm-cl-iot-gate-ied-adc0.dts) | 0 | ||||
| -rw-r--r-- | arch/arm/dts/imx8mm-cl-iot-gate-ied-adc1.dtso (renamed from arch/arm/dts/imx8mm-cl-iot-gate-ied-adc1.dts) | 0 | ||||
| -rw-r--r-- | arch/arm/dts/imx8mm-cl-iot-gate-ied-can0.dtso (renamed from arch/arm/dts/imx8mm-cl-iot-gate-ied-can0.dts) | 0 | ||||
| -rw-r--r-- | arch/arm/dts/imx8mm-cl-iot-gate-ied-can1.dtso (renamed from arch/arm/dts/imx8mm-cl-iot-gate-ied-can1.dts) | 0 | ||||
| -rw-r--r-- | arch/arm/dts/imx8mm-cl-iot-gate-ied-tpm0.dtso (renamed from arch/arm/dts/imx8mm-cl-iot-gate-ied-tpm0.dts) | 0 | ||||
| -rw-r--r-- | arch/arm/dts/imx8mm-cl-iot-gate-ied-tpm1.dtso (renamed from arch/arm/dts/imx8mm-cl-iot-gate-ied-tpm1.dts) | 0 | ||||
| -rw-r--r-- | arch/arm/dts/imx8mm-cl-iot-gate-ied.dtso (renamed from arch/arm/dts/imx8mm-cl-iot-gate-ied.dts) | 0 | ||||
| -rw-r--r-- | arch/arm/dts/k3-am625-verdin-wifi-dev-u-boot.dtsi | 72 | ||||
| -rw-r--r-- | arch/arm/dts/k3-am65-iot2050-common-u-boot.dtsi | 44 | ||||
| -rw-r--r-- | arch/arm/dts/k3-am6548-iot2050-advanced-m2-bkey-ekey-pcie-overlay.dtso (renamed from arch/arm/dts/k3-am6548-iot2050-advanced-m2-bkey-ekey-pcie-overlay.dts) | 0 | ||||
| -rw-r--r-- | arch/arm/dts/k3-am6548-iot2050-advanced-m2-bkey-usb3-overlay.dtso (renamed from arch/arm/dts/k3-am6548-iot2050-advanced-m2-bkey-usb3-overlay.dts) | 0 | ||||
| -rw-r--r-- | arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi | 82 | ||||
| -rw-r--r-- | arch/arm/dts/k3-j721e-sk-u-boot.dtsi | 70 | ||||
| -rw-r--r-- | arch/arm/dts/zynqmp-sck-kr-g-revA.dtso (renamed from arch/arm/dts/zynqmp-sck-kr-g-revA.dts) | 0 | ||||
| -rw-r--r-- | arch/arm/dts/zynqmp-sck-kr-g-revB.dtso (renamed from arch/arm/dts/zynqmp-sck-kr-g-revB.dts) | 0 | ||||
| -rw-r--r-- | arch/arm/dts/zynqmp-sck-kv-g-revA.dtso (renamed from arch/arm/dts/zynqmp-sck-kv-g-revA.dts) | 0 | ||||
| -rw-r--r-- | arch/arm/dts/zynqmp-sck-kv-g-revB.dtso (renamed from arch/arm/dts/zynqmp-sck-kv-g-revB.dts) | 0 | ||||
| -rw-r--r-- | arch/arm/include/asm/system.h | 1 | ||||
| -rw-r--r-- | arch/arm/mach-apple/board.c | 183 | ||||
| -rw-r--r-- | arch/arm/mach-k3/config_secure.mk | 44 | ||||
| -rw-r--r-- | arch/sandbox/dts/overlay0.dtso (renamed from arch/sandbox/dts/overlay0.dts) | 0 | ||||
| -rw-r--r-- | arch/sandbox/dts/overlay1.dtso (renamed from arch/sandbox/dts/overlay1.dts) | 0 |
26 files changed, 333 insertions, 182 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 7b0978447f1..531b081de99 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -787,6 +787,7 @@ config ARCH_K3 select FIT select REGEX select FIT_SIGNATURE if ARM64 + imply TI_SECURE_DEVICE config ARCH_OMAP2PLUS bool "TI OMAP2+" diff --git a/arch/arm/cpu/armv7/Kconfig b/arch/arm/cpu/armv7/Kconfig index ccc2f208677..f015d133cb0 100644 --- a/arch/arm/cpu/armv7/Kconfig +++ b/arch/arm/cpu/armv7/Kconfig @@ -58,6 +58,16 @@ config ARMV7_SECURE_MAX_SIZE default 0x3c00 if MACH_SUN8I && MACH_SUN8I_H3 default 0x10000 +config ARM_GIC_BASE_ADDRESS + hex + depends on ARMV7_NONSEC + depends on ARCH_EXYNOS5 + default 0x10480000 if ARCH_EXYNOS5 + help + Override the GIC base address if the Arm Cortex defined + CBAR/PERIPHBASE system register holds the wrong value. + Used by the PSCI code to configure the secure side of the GIC. + config ARMV7_VIRT bool "Enable support for hardware virtualization" if EXPERT depends on CPU_V7_HAS_VIRT && ARMV7_NONSEC diff --git a/arch/arm/cpu/armv7/nonsec_virt.S b/arch/arm/cpu/armv7/nonsec_virt.S index 9004074da2c..bed40fa3d99 100644 --- a/arch/arm/cpu/armv7/nonsec_virt.S +++ b/arch/arm/cpu/armv7/nonsec_virt.S @@ -112,8 +112,8 @@ ENTRY(_do_nonsec_entry) ENDPROC(_do_nonsec_entry) .macro get_cbar_addr addr -#ifdef CFG_ARM_GIC_BASE_ADDRESS - ldr \addr, =CFG_ARM_GIC_BASE_ADDRESS +#ifdef CONFIG_ARM_GIC_BASE_ADDRESS + ldr \addr, =CONFIG_ARM_GIC_BASE_ADDRESS #else mrc p15, 4, \addr, c15, c0, 0 @ read CBAR bfc \addr, #0, #15 @ clear reserved bits diff --git a/arch/arm/cpu/armv7/virt-v7.c b/arch/arm/cpu/armv7/virt-v7.c index c82b215b6f9..5ffeca13d91 100644 --- a/arch/arm/cpu/armv7/virt-v7.c +++ b/arch/arm/cpu/armv7/virt-v7.c @@ -26,8 +26,8 @@ static unsigned int read_id_pfr1(void) static unsigned long get_gicd_base_address(void) { -#ifdef CFG_ARM_GIC_BASE_ADDRESS - return CFG_ARM_GIC_BASE_ADDRESS + GIC_DIST_OFFSET; +#ifdef CONFIG_ARM_GIC_BASE_ADDRESS + return CONFIG_ARM_GIC_BASE_ADDRESS + GIC_DIST_OFFSET; #else unsigned periphbase; diff --git a/arch/arm/dts/imx8mm-cl-iot-gate-ied-adc0.dts b/arch/arm/dts/imx8mm-cl-iot-gate-ied-adc0.dtso index 3f2201e4eef..3f2201e4eef 100644 --- a/arch/arm/dts/imx8mm-cl-iot-gate-ied-adc0.dts +++ b/arch/arm/dts/imx8mm-cl-iot-gate-ied-adc0.dtso diff --git a/arch/arm/dts/imx8mm-cl-iot-gate-ied-adc1.dts b/arch/arm/dts/imx8mm-cl-iot-gate-ied-adc1.dtso index bb0f848718f..bb0f848718f 100644 --- a/arch/arm/dts/imx8mm-cl-iot-gate-ied-adc1.dts +++ b/arch/arm/dts/imx8mm-cl-iot-gate-ied-adc1.dtso diff --git a/arch/arm/dts/imx8mm-cl-iot-gate-ied-can0.dts b/arch/arm/dts/imx8mm-cl-iot-gate-ied-can0.dtso index 0e46300142e..0e46300142e 100644 --- a/arch/arm/dts/imx8mm-cl-iot-gate-ied-can0.dts +++ b/arch/arm/dts/imx8mm-cl-iot-gate-ied-can0.dtso diff --git a/arch/arm/dts/imx8mm-cl-iot-gate-ied-can1.dts b/arch/arm/dts/imx8mm-cl-iot-gate-ied-can1.dtso index fd7274eb7aa..fd7274eb7aa 100644 --- a/arch/arm/dts/imx8mm-cl-iot-gate-ied-can1.dts +++ b/arch/arm/dts/imx8mm-cl-iot-gate-ied-can1.dtso diff --git a/arch/arm/dts/imx8mm-cl-iot-gate-ied-tpm0.dts b/arch/arm/dts/imx8mm-cl-iot-gate-ied-tpm0.dtso index 06fa77c0e8d..06fa77c0e8d 100644 --- a/arch/arm/dts/imx8mm-cl-iot-gate-ied-tpm0.dts +++ b/arch/arm/dts/imx8mm-cl-iot-gate-ied-tpm0.dtso diff --git a/arch/arm/dts/imx8mm-cl-iot-gate-ied-tpm1.dts b/arch/arm/dts/imx8mm-cl-iot-gate-ied-tpm1.dtso index c9676a3a000..c9676a3a000 100644 --- a/arch/arm/dts/imx8mm-cl-iot-gate-ied-tpm1.dts +++ b/arch/arm/dts/imx8mm-cl-iot-gate-ied-tpm1.dtso diff --git a/arch/arm/dts/imx8mm-cl-iot-gate-ied.dts b/arch/arm/dts/imx8mm-cl-iot-gate-ied.dtso index b85485126e3..b85485126e3 100644 --- a/arch/arm/dts/imx8mm-cl-iot-gate-ied.dts +++ b/arch/arm/dts/imx8mm-cl-iot-gate-ied.dtso diff --git a/arch/arm/dts/k3-am625-verdin-wifi-dev-u-boot.dtsi b/arch/arm/dts/k3-am625-verdin-wifi-dev-u-boot.dtsi index 5d564603eb2..afa24d07a4c 100644 --- a/arch/arm/dts/k3-am625-verdin-wifi-dev-u-boot.dtsi +++ b/arch/arm/dts/k3-am625-verdin-wifi-dev-u-boot.dtsi @@ -17,49 +17,49 @@ }; memory@80000000 { - bootph-pre-ram; + bootph-all; }; }; &cbass_main { - bootph-pre-ram; + bootph-all; timer@2400000 { clock-frequency = <25000000>; - bootph-pre-ram; + bootph-all; }; }; &cbass_mcu { - bootph-pre-ram; + bootph-all; }; &cbass_wakeup { - bootph-pre-ram; + bootph-all; }; &chipid { - bootph-pre-ram; + bootph-all; }; &cpsw3g { - bootph-pre-ram; + bootph-all; }; &cpsw3g_phy0 { - bootph-pre-ram; + bootph-all; }; &cpsw3g_phy1 { - bootph-pre-ram; + bootph-all; }; &cpsw_port1 { - bootph-pre-ram; + bootph-all; }; &cpsw_port2 { - bootph-pre-ram; + bootph-all; }; /* MDIO, shared by Verdin ETH_1 (On-module PHY) and Verdin ETH_2_RGMII */ @@ -67,40 +67,40 @@ /delete-property/ assigned-clocks; /delete-property/ assigned-clock-parents; /delete-property/ assigned-clock-rates; - bootph-pre-ram; + bootph-all; }; &dmsc { - bootph-pre-ram; + bootph-all; k3_sysreset: sysreset-controller { compatible = "ti,sci-sysreset"; - bootph-pre-ram; + bootph-all; }; }; &dmss { - bootph-pre-ram; + bootph-all; }; &fss { - bootph-pre-ram; + bootph-all; }; &k3_clks { - bootph-pre-ram; + bootph-all; }; &k3_pds { - bootph-pre-ram; + bootph-all; }; &k3_reset { - bootph-pre-ram; + bootph-all; }; &main_gpio0 { - bootph-pre-ram; + bootph-all; }; /* On-module I2C - PMIC_I2C */ @@ -130,53 +130,53 @@ }; &main_pmx0 { - bootph-pre-ram; + bootph-all; }; /* Verdin UART_3, used as the Linux console */ &main_uart0 { - bootph-pre-ram; + bootph-all; }; /* Verdin UART_1 */ &main_uart1 { - bootph-pre-ram; + bootph-all; }; &mcu_pmx0 { - bootph-pre-ram; + bootph-all; }; &pinctrl_ctrl_sleep_moci { - bootph-pre-ram; + bootph-all; }; &pinctrl_i2c0 { - bootph-pre-ram; + bootph-all; }; &pinctrl_i2c1 { - bootph-pre-ram; + bootph-all; }; &pinctrl_sdhci0 { - bootph-pre-ram; + bootph-all; }; &pinctrl_uart0 { - bootph-pre-ram; + bootph-all; }; &pinctrl_uart1 { - bootph-pre-ram; + bootph-all; }; &pinctrl_wkup_uart0 { - bootph-pre-ram; + bootph-all; }; &sdhci0 { - bootph-pre-ram; + bootph-all; }; &sdhci2 { @@ -184,18 +184,18 @@ }; &secure_proxy_main { - bootph-pre-ram; + bootph-all; }; &verdin_ctrl_sleep_moci { - bootph-pre-ram; + bootph-all; }; &wkup_conf { - bootph-pre-ram; + bootph-all; }; /* Verdin UART_2 */ &wkup_uart0 { - bootph-pre-ram; + bootph-all; }; diff --git a/arch/arm/dts/k3-am65-iot2050-common-u-boot.dtsi b/arch/arm/dts/k3-am65-iot2050-common-u-boot.dtsi index 082a3c89d0f..d53f133cd63 100644 --- a/arch/arm/dts/k3-am65-iot2050-common-u-boot.dtsi +++ b/arch/arm/dts/k3-am65-iot2050-common-u-boot.dtsi @@ -15,18 +15,18 @@ }; leds { - bootph-pre-ram; + bootph-all; status-led-red { - bootph-pre-ram; + bootph-all; }; status-led-green { - bootph-pre-ram; + bootph-all; }; }; }; &cbass_mcu { - bootph-pre-ram; + bootph-all; mcu_navss: bus@28380000 { ringacc@2b800000 { @@ -53,70 +53,70 @@ }; &cbass_wakeup { - bootph-pre-ram; + bootph-all; }; &cbass_main { - bootph-pre-ram; + bootph-all; main_navss: bus@30800000 { - bootph-pre-ram; + bootph-all; }; }; &wkup_pmx0 { - bootph-pre-ram; + bootph-all; mcu-fss0-ospi0-pins-default { - bootph-pre-ram; + bootph-all; }; }; &main_pmx0 { - bootph-pre-ram; + bootph-all; main-uart1-pins-default { - bootph-pre-ram; + bootph-all; }; }; &main_uart1 { - bootph-pre-ram; + bootph-all; current-speed = <115200>; }; &wkup_gpio0 { - bootph-pre-ram; + bootph-all; }; &ospi0 { - bootph-pre-ram; + bootph-all; flash@0 { - bootph-pre-ram; + bootph-all; }; }; &secure_proxy_main { - bootph-pre-ram; + bootph-all; }; &dmsc { - bootph-pre-ram; + bootph-all; k3_sysreset: sysreset-controller { compatible = "ti,sci-sysreset"; - bootph-pre-ram; + bootph-all; }; }; &k3_pds { - bootph-pre-ram; + bootph-all; }; &k3_clks { - bootph-pre-ram; + bootph-all; }; &k3_reset { - bootph-pre-ram; + bootph-all; }; &fss { - bootph-pre-ram; + bootph-all; }; diff --git a/arch/arm/dts/k3-am6548-iot2050-advanced-m2-bkey-ekey-pcie-overlay.dts b/arch/arm/dts/k3-am6548-iot2050-advanced-m2-bkey-ekey-pcie-overlay.dtso index c9e736098f9..c9e736098f9 100644 --- a/arch/arm/dts/k3-am6548-iot2050-advanced-m2-bkey-ekey-pcie-overlay.dts +++ b/arch/arm/dts/k3-am6548-iot2050-advanced-m2-bkey-ekey-pcie-overlay.dtso diff --git a/arch/arm/dts/k3-am6548-iot2050-advanced-m2-bkey-usb3-overlay.dts b/arch/arm/dts/k3-am6548-iot2050-advanced-m2-bkey-usb3-overlay.dtso index 72fc011bd54..72fc011bd54 100644 --- a/arch/arm/dts/k3-am6548-iot2050-advanced-m2-bkey-usb3-overlay.dts +++ b/arch/arm/dts/k3-am6548-iot2050-advanced-m2-bkey-usb3-overlay.dtso diff --git a/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi b/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi index c638af63c18..cd95907b981 100644 --- a/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi +++ b/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi @@ -6,27 +6,27 @@ #include "k3-j721e-binman.dtsi" &cbass_main { - bootph-pre-ram; + bootph-all; }; &main_navss { - bootph-pre-ram; + bootph-all; }; &cbass_mcu_wakeup { - bootph-pre-ram; + bootph-all; chipid@43000014 { - bootph-pre-ram; + bootph-all; }; }; &mcu_navss { - bootph-pre-ram; + bootph-all; }; &mcu_ringacc { - bootph-pre-ram; + bootph-all; }; &mcu_udmap { @@ -38,144 +38,144 @@ <0x0 0x28400000 0x0 0x2000>; reg-names = "gcfg", "rchan", "rchanrt", "tchan", "tchanrt", "rflow"; - bootph-pre-ram; + bootph-all; }; &secure_proxy_main { - bootph-pre-ram; + bootph-all; }; &dmsc { - bootph-pre-ram; + bootph-all; k3_sysreset: sysreset-controller { compatible = "ti,sci-sysreset"; - bootph-pre-ram; + bootph-all; }; }; &k3_pds { - bootph-pre-ram; + bootph-all; }; &k3_clks { - bootph-pre-ram; + bootph-all; }; &k3_reset { - bootph-pre-ram; + bootph-all; }; &wkup_pmx0 { - bootph-pre-ram; + bootph-all; }; &main_pmx0 { - bootph-pre-ram; + bootph-all; }; &main_uart0 { - bootph-pre-ram; + bootph-all; }; &mcu_uart0 { - bootph-pre-ram; + bootph-all; }; &main_sdhci0 { - bootph-pre-ram; + bootph-all; }; &main_sdhci1 { - bootph-pre-ram; + bootph-all; }; &main_uart0_pins_default { - bootph-pre-ram; + bootph-all; }; &main_usbss0_pins_default { - bootph-pre-ram; + bootph-all; }; &usbss0 { - bootph-pre-ram; + bootph-all; }; &usb0 { dr_mode = "peripheral"; - bootph-pre-ram; + bootph-all; }; &main_mmc1_pins_default { - bootph-pre-ram; + bootph-all; }; &wkup_i2c0_pins_default { - bootph-pre-ram; + bootph-all; }; &wkup_uart0 { - bootph-pre-ram; + bootph-all; status = "okay"; }; &wkup_i2c0 { - bootph-pre-ram; + bootph-all; status = "okay"; }; &main_i2c0 { - bootph-pre-ram; + bootph-all; }; &main_i2c0_pins_default { - bootph-pre-ram; + bootph-all; }; &main_esm { - bootph-pre-ram; + bootph-all; }; &exp2 { - bootph-pre-ram; + bootph-all; }; &mcu_fss0_ospi0_pins_default { - bootph-pre-ram; + bootph-all; }; &fss { - bootph-pre-ram; + bootph-all; }; &wkup_gpio0 { - bootph-pre-ram; + bootph-all; }; &ospi0 { - bootph-pre-ram; + bootph-all; flash@0 { - bootph-pre-ram; + bootph-all; }; }; &ospi1 { - bootph-pre-ram; + bootph-all; flash@0 { - bootph-pre-ram; + bootph-all; }; }; &mcu_fss0_hpb0_pins_default { - bootph-pre-ram; + bootph-all; }; &wkup_gpio_pins_default { - bootph-pre-ram; + bootph-all; }; &mcu_fss0_ospi1_pins_default { - bootph-pre-ram; + bootph-all; }; diff --git a/arch/arm/dts/k3-j721e-sk-u-boot.dtsi b/arch/arm/dts/k3-j721e-sk-u-boot.dtsi index 57da7c210a8..370fe5190b2 100644 --- a/arch/arm/dts/k3-j721e-sk-u-boot.dtsi +++ b/arch/arm/dts/k3-j721e-sk-u-boot.dtsi @@ -6,27 +6,27 @@ #include "k3-j721e-binman.dtsi" &cbass_main { - bootph-pre-ram; + bootph-all; }; &main_navss { - bootph-pre-ram; + bootph-all; }; &cbass_mcu_wakeup { - bootph-pre-ram; + bootph-all; chipid@43000014 { - bootph-pre-ram; + bootph-all; }; }; &mcu_navss { - bootph-pre-ram; + bootph-all; }; &mcu_ringacc { - bootph-pre-ram; + bootph-all; }; &mcu_udmap { @@ -38,120 +38,120 @@ <0x0 0x28400000 0x0 0x2000>; reg-names = "gcfg", "rchan", "rchanrt", "tchan", "tchanrt", "rflow"; - bootph-pre-ram; + bootph-all; }; &secure_proxy_main { - bootph-pre-ram; + bootph-all; }; &dmsc { - bootph-pre-ram; + bootph-all; k3_sysreset: sysreset-controller { compatible = "ti,sci-sysreset"; - bootph-pre-ram; + bootph-all; }; }; &k3_pds { - bootph-pre-ram; + bootph-all; }; &k3_clks { - bootph-pre-ram; + bootph-all; }; &k3_reset { - bootph-pre-ram; + bootph-all; }; &wkup_pmx0 { - bootph-pre-ram; + bootph-all; }; &main_pmx0 { - bootph-pre-ram; + bootph-all; }; &main_uart0 { - bootph-pre-ram; + bootph-all; }; &mcu_uart0 { - bootph-pre-ram; + bootph-all; }; &main_sdhci1 { - bootph-pre-ram; + bootph-all; }; &main_uart0_pins_default { - bootph-pre-ram; + bootph-all; }; &main_usbss0_pins_default { - bootph-pre-ram; + bootph-all; }; &usbss0 { - bootph-pre-ram; + bootph-all; }; &usb0 { dr_mode = "host"; - bootph-pre-ram; + bootph-all; }; &main_usbss1_pins_default { - bootph-pre-ram; + bootph-all; }; &usbss1 { - bootph-pre-ram; + bootph-all; }; &usb1 { dr_mode = "host"; - bootph-pre-ram; + bootph-all; }; &main_mmc1_pins_default { - bootph-pre-ram; + bootph-all; }; &wkup_i2c0_pins_default { - bootph-pre-ram; + bootph-all; }; &wkup_i2c0 { - bootph-pre-ram; + bootph-all; }; &wkup_uart0 { - bootph-pre-ram; + bootph-all; status = "okay"; }; &mcu_fss0_ospi0_pins_default { - bootph-pre-ram; + bootph-all; }; &fss { - bootph-pre-ram; + bootph-all; }; &main_esm { - bootph-pre-ram; + bootph-all; }; &ospi0 { - bootph-pre-ram; + bootph-all; flash@0 { - bootph-pre-ram; + bootph-all; partition@3fc0000 { - bootph-pre-ram; + bootph-all; }; }; }; diff --git a/arch/arm/dts/zynqmp-sck-kr-g-revA.dts b/arch/arm/dts/zynqmp-sck-kr-g-revA.dtso index 30a0230d476..30a0230d476 100644 --- a/arch/arm/dts/zynqmp-sck-kr-g-revA.dts +++ b/arch/arm/dts/zynqmp-sck-kr-g-revA.dtso diff --git a/arch/arm/dts/zynqmp-sck-kr-g-revB.dts b/arch/arm/dts/zynqmp-sck-kr-g-revB.dtso index 8f4c52d6d64..8f4c52d6d64 100644 --- a/arch/arm/dts/zynqmp-sck-kr-g-revB.dts +++ b/arch/arm/dts/zynqmp-sck-kr-g-revB.dtso diff --git a/arch/arm/dts/zynqmp-sck-kv-g-revA.dts b/arch/arm/dts/zynqmp-sck-kv-g-revA.dtso index 55bef1df75d..55bef1df75d 100644 --- a/arch/arm/dts/zynqmp-sck-kv-g-revA.dts +++ b/arch/arm/dts/zynqmp-sck-kv-g-revA.dtso diff --git a/arch/arm/dts/zynqmp-sck-kv-g-revB.dts b/arch/arm/dts/zynqmp-sck-kv-g-revB.dtso index 1b1d9e772f5..1b1d9e772f5 100644 --- a/arch/arm/dts/zynqmp-sck-kv-g-revB.dts +++ b/arch/arm/dts/zynqmp-sck-kv-g-revB.dtso diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index 87d1c77e8b1..0eae857e73a 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -84,6 +84,7 @@ #define HCR_EL2_HCD_DIS (1 << 29) /* Hypervisor Call disabled */ #define HCR_EL2_AMO_EL2 (1 << 5) /* Route SErrors to EL2 */ +#define ID_AA64ISAR0_EL1_RNDR (0xFUL << 60) /* RNDR random registers */ /* * ID_AA64ISAR1_EL1 bits definitions */ diff --git a/arch/arm/mach-apple/board.c b/arch/arm/mach-apple/board.c index d5019481184..47393babbc6 100644 --- a/arch/arm/mach-apple/board.c +++ b/arch/arm/mach-apple/board.c @@ -444,6 +444,187 @@ static struct mm_region t6020_mem_map[] = { } }; +/* Apple M2 Ultra */ + +static struct mm_region t6022_mem_map[] = { + { + /* I/O */ + .virt = 0x280000000, + .phys = 0x280000000, + .size = SZ_1G, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* I/O */ + .virt = 0x340000000, + .phys = 0x340000000, + .size = SZ_1G, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* I/O */ + .virt = 0x380000000, + .phys = 0x380000000, + .size = SZ_1G, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* I/O */ + .virt = 0x580000000, + .phys = 0x580000000, + .size = SZ_512M, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* PCIE */ + .virt = 0x5a0000000, + .phys = 0x5a0000000, + .size = SZ_512M, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRE) | + PTE_BLOCK_INNER_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* PCIE */ + .virt = 0x5c0000000, + .phys = 0x5c0000000, + .size = SZ_1G, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRE) | + PTE_BLOCK_INNER_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* I/O */ + .virt = 0x700000000, + .phys = 0x700000000, + .size = SZ_1G, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* I/O */ + .virt = 0xb00000000, + .phys = 0xb00000000, + .size = SZ_1G, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* I/O */ + .virt = 0xf00000000, + .phys = 0xf00000000, + .size = SZ_1G, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* I/O */ + .virt = 0x1300000000, + .phys = 0x1300000000, + .size = SZ_1G, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* I/O */ + .virt = 0x2280000000, + .phys = 0x2280000000, + .size = SZ_1G, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* I/O */ + .virt = 0x2340000000, + .phys = 0x2340000000, + .size = SZ_1G, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* I/O */ + .virt = 0x2380000000, + .phys = 0x2380000000, + .size = SZ_1G, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* I/O */ + .virt = 0x2580000000, + .phys = 0x2580000000, + .size = SZ_512M, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* PCIE */ + .virt = 0x25a0000000, + .phys = 0x25a0000000, + .size = SZ_512M, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRE) | + PTE_BLOCK_INNER_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* PCIE */ + .virt = 0x25c0000000, + .phys = 0x25c0000000, + .size = SZ_1G, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRE) | + PTE_BLOCK_INNER_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* I/O */ + .virt = 0x2700000000, + .phys = 0x2700000000, + .size = SZ_1G, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* I/O */ + .virt = 0x2b00000000, + .phys = 0x2b00000000, + .size = SZ_1G, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* I/O */ + .virt = 0x2f00000000, + .phys = 0x2f00000000, + .size = SZ_1G, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* I/O */ + .virt = 0x3300000000, + .phys = 0x3300000000, + .size = SZ_1G, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* RAM */ + .virt = 0x10000000000, + .phys = 0x10000000000, + .size = 16UL * SZ_1G, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + /* Framebuffer */ + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) | + PTE_BLOCK_INNER_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* List terminator */ + 0, + } +}; + struct mm_region *mem_map; int board_init(void) @@ -488,6 +669,8 @@ void build_mem_map(void) else if (of_machine_is_compatible("apple,t6020") || of_machine_is_compatible("apple,t6021")) mem_map = t6020_mem_map; + else if (of_machine_is_compatible("apple,t6022")) + mem_map = t6022_mem_map; else panic("Unsupported SoC\n"); diff --git a/arch/arm/mach-k3/config_secure.mk b/arch/arm/mach-k3/config_secure.mk deleted file mode 100644 index 9cc1f9eb24f..00000000000 --- a/arch/arm/mach-k3/config_secure.mk +++ /dev/null @@ -1,44 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -# -# Copyright (C) 2018 Texas Instruments, Incorporated - http://www.ti.com/ -# Andrew F. Davis <afd@ti.com> - -quiet_cmd_k3secureimg = SECURE $@ -ifneq ($(TI_SECURE_DEV_PKG),) -ifneq ($(wildcard $(TI_SECURE_DEV_PKG)/scripts/secure-binary-image.sh),) -cmd_k3secureimg = $(TI_SECURE_DEV_PKG)/scripts/secure-binary-image.sh \ - $< $@ \ - $(if $(KBUILD_VERBOSE:1=), >/dev/null) -else -cmd_k3secureimg = echo "WARNING:" \ - "$(TI_SECURE_DEV_PKG)/scripts/secure-binary-image.sh not found." \ - "$@ was NOT secured!"; cp $< $@ -endif -else -cmd_k3secureimg = echo "WARNING: TI_SECURE_DEV_PKG environment" \ - "variable must be defined for TI secure devices." \ - "$@ was NOT secured!"; cp $< $@ -endif - -%.dtb_HS: %.dtb FORCE - $(call if_changed,k3secureimg) - -$(obj)/u-boot-spl-nodtb.bin_HS: $(obj)/u-boot-spl-nodtb.bin FORCE - $(call if_changed,k3secureimg) - -tispl.bin_HS: $(obj)/u-boot-spl-nodtb.bin_HS $(patsubst %,$(obj)/dts/%.dtb_HS,$(subst ",,$(CONFIG_SPL_OF_LIST))) $(SPL_ITS) FORCE - $(call if_changed,mkfitimage) - -MKIMAGEFLAGS_u-boot.img_HS = -f auto -A $(ARCH) -T firmware -C none -O u-boot \ - -a $(CONFIG_TEXT_BASE) -e $(CONFIG_SYS_UBOOT_START) \ - -n "U-Boot $(UBOOTRELEASE) for $(BOARD) board" -E \ - $(patsubst %,-b arch/$(ARCH)/dts/%.dtb_HS,$(subst ",,$(CONFIG_OF_LIST))) - -OF_LIST_TARGETS = $(patsubst %,arch/$(ARCH)/dts/%.dtb,$(subst ",,$(CONFIG_OF_LIST))) -$(OF_LIST_TARGETS): dtbs - -u-boot-nodtb.bin_HS: u-boot-nodtb.bin FORCE - $(call if_changed,k3secureimg) - -u-boot.img_HS: u-boot-nodtb.bin_HS u-boot.img $(patsubst %.dtb,%.dtb_HS,$(OF_LIST_TARGETS)) FORCE - $(call if_changed,mkimage) diff --git a/arch/sandbox/dts/overlay0.dts b/arch/sandbox/dts/overlay0.dtso index 9e5f38962bc..9e5f38962bc 100644 --- a/arch/sandbox/dts/overlay0.dts +++ b/arch/sandbox/dts/overlay0.dtso diff --git a/arch/sandbox/dts/overlay1.dts b/arch/sandbox/dts/overlay1.dtso index 303e713f336..303e713f336 100644 --- a/arch/sandbox/dts/overlay1.dts +++ b/arch/sandbox/dts/overlay1.dtso |