diff options
Diffstat (limited to 'arch')
67 files changed, 3157 insertions, 470 deletions
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index df7b4addf99..2a0efd8edad 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -90,6 +90,9 @@ dtb-$(CONFIG_ROCKCHIP_PX30) += \ dtb-$(CONFIG_ROCKCHIP_RK3036) += \ rk3036-sdk.dtb +dtb-$(CONFIG_ROCKCHIP_RK3066) += \ + rk3066a-mk808.dtb + dtb-$(CONFIG_ROCKCHIP_RK3128) += \ rk3128-evb.dtb diff --git a/arch/arm/dts/rk3066a-mk808-u-boot.dtsi b/arch/arm/dts/rk3066a-mk808-u-boot.dtsi new file mode 100644 index 00000000000..e0aa929fcef --- /dev/null +++ b/arch/arm/dts/rk3066a-mk808-u-boot.dtsi @@ -0,0 +1,49 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +#include "rk3066a-u-boot.dtsi" + +/ { + config { + u-boot,boot-led = "mk808:blue:power"; + }; +}; + +&cru { + u-boot,dm-pre-reloc; +}; + +&dmc { + compatible = "rockchip,rk3066-dmc", "syscon"; + rockchip,pctl-timing = <0x12c 0xc8 0x1f4 0x1e 0x4e 0x4 0x69 0x6 + 0x3 0x0 0x6 0x5 0xc 0x10 0x6 0x4 + 0x4 0x5 0x4 0x200 0x3 0xa 0x40 0x0 + 0x1 0x5 0x5 0x3 0xc 0x1e 0x100 0x0 + 0x4 0x0>; + rockchip,phy-timing = <0x208c6690 0x690878 0x10022a00 + 0x220 0x40 0x0 0x0>; + rockchip,sdram-params = <0x24716310 0 2 300000000 3 9 0>; +}; + +&mmc0 { + fifo-mode; + max-frequency = <4000000>; + u-boot,dm-spl; + u-boot,spl-fifo-mode; +}; + +&mmc1 { + status = "disabled"; +}; + +&noc { + compatible = "rockchip,rk3066-noc", "syscon"; +}; + +&timer2 { + clock-frequency = <24000000>; + u-boot,dm-pre-reloc; +}; + +&uart2 { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/rk3066a-mk808.dts b/arch/arm/dts/rk3066a-mk808.dts new file mode 100644 index 00000000000..667d57a4ff4 --- /dev/null +++ b/arch/arm/dts/rk3066a-mk808.dts @@ -0,0 +1,216 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2016 Paweł Jarosz <paweljarosz3691@gmail.com> + */ + +/dts-v1/; +#include <dt-bindings/input/input.h> +#include "rk3066a.dtsi" + +/ { + model = "Rikomagic MK808"; + compatible = "rikomagic,mk808", "rockchip,rk3066a"; + + aliases { + mmc0 = &mmc0; + mmc1 = &mmc1; + }; + + chosen { + stdout-path = "serial2:115200n8"; + }; + + memory@60000000 { + reg = <0x60000000 0x40000000>; + device_type = "memory"; + }; + + adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 1>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <2500000>; + poll-interval = <100>; + + recovery { + label = "recovery"; + linux,code = <KEY_VENDOR>; + press-threshold-microvolt = <0>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + blue_led: led-0 { + label = "mk808:blue:power"; + gpios = <&gpio0 RK_PA3 GPIO_ACTIVE_HIGH>; + default-state = "off"; + linux,default-trigger = "default-on"; + }; + }; + + hdmi_con { + compatible = "hdmi-connector"; + type = "c"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + + vcc_2v5: vcc-2v5 { + compatible = "regulator-fixed"; + regulator-name = "vcc_2v5"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + }; + + vcc_io: vcc-io { + compatible = "regulator-fixed"; + regulator-name = "vcc_io"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vcc_host: usb-host-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&host_drv>; + pinctrl-names = "default"; + regulator-always-on; + regulator-name = "host-pwr"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + startup-delay-us = <100000>; + vin-supply = <&vcc_io>; + }; + + vcc_otg: usb-otg-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&otg_drv>; + pinctrl-names = "default"; + regulator-always-on; + regulator-name = "vcc_otg"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + startup-delay-us = <100000>; + vin-supply = <&vcc_io>; + }; + + vcc_sd: sdmmc-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio3 RK_PA7 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&sdmmc_pwr>; + pinctrl-names = "default"; + regulator-name = "vcc_sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <100000>; + vin-supply = <&vcc_io>; + }; + + vcc_wifi: sdio-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio3 RK_PD0 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&wifi_pwr>; + pinctrl-names = "default"; + regulator-name = "vcc_wifi"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <100000>; + vin-supply = <&vcc_io>; + }; +}; + +&hdmi { + status = "okay"; +}; + +&hdmi_in_vop1 { + status = "disabled"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&mmc0 { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + vmmc-supply = <&vcc_sd>; + status = "okay"; +}; + +&mmc1 { + bus-width = <4>; + non-removable; + pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_bus4>; + pinctrl-names = "default"; + vmmc-supply = <&vcc_wifi>; + status = "okay"; +}; + +&pinctrl { + usb-host { + host_drv: host-drv { + rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_default>; + }; + }; + + usb-otg { + otg_drv: otg-drv { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_default>; + }; + }; + + sdmmc { + sdmmc_pwr: sdmmc-pwr { + rockchip,pins = <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_default>; + }; + }; + + sdio { + wifi_pwr: wifi-pwr { + rockchip,pins = <3 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&saradc { + vref-supply = <&vcc_2v5>; + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&usb_host { + status = "okay"; +}; + +&usb_otg { + status = "okay"; +}; + +&usbphy { + status = "okay"; +}; + +&vop0 { + status = "okay"; +}; + +&wdt { + status = "okay"; +}; diff --git a/arch/arm/dts/rk3066a-u-boot.dtsi b/arch/arm/dts/rk3066a-u-boot.dtsi new file mode 100644 index 00000000000..bc6e609d02b --- /dev/null +++ b/arch/arm/dts/rk3066a-u-boot.dtsi @@ -0,0 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include "rockchip-u-boot.dtsi" +#include "rk3xxx-u-boot.dtsi" diff --git a/arch/arm/dts/rk3066a.dtsi b/arch/arm/dts/rk3066a.dtsi new file mode 100644 index 00000000000..c25b9695db4 --- /dev/null +++ b/arch/arm/dts/rk3066a.dtsi @@ -0,0 +1,879 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2013 MundoReader S.L. + * Author: Heiko Stuebner <heiko@sntech.de> + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/pinctrl/rockchip.h> +#include <dt-bindings/clock/rk3066a-cru.h> +#include <dt-bindings/power/rk3066-power.h> +#include "rk3xxx.dtsi" + +/ { + compatible = "rockchip,rk3066a"; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + enable-method = "rockchip,rk3066-smp"; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + next-level-cache = <&L2>; + reg = <0x0>; + operating-points = + /* kHz uV */ + <1416000 1300000>, + <1200000 1175000>, + <1008000 1125000>, + <816000 1125000>, + <600000 1100000>, + <504000 1100000>, + <312000 1075000>; + clock-latency = <40000>; + clocks = <&cru ARMCLK>; + }; + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + next-level-cache = <&L2>; + reg = <0x1>; + }; + }; + + display-subsystem { + compatible = "rockchip,display-subsystem"; + ports = <&vop0_out>, <&vop1_out>; + }; + + sram: sram@10080000 { + compatible = "mmio-sram"; + reg = <0x10080000 0x10000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x10080000 0x10000>; + + smp-sram@0 { + compatible = "rockchip,rk3066-smp-sram"; + reg = <0x0 0x50>; + }; + }; + + vop0: vop@1010c000 { + compatible = "rockchip,rk3066-vop"; + reg = <0x1010c000 0x19c>; + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru ACLK_LCDC0>, + <&cru DCLK_LCDC0>, + <&cru HCLK_LCDC0>; + clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; + power-domains = <&power RK3066_PD_VIO>; + resets = <&cru SRST_LCDC0_AXI>, + <&cru SRST_LCDC0_AHB>, + <&cru SRST_LCDC0_DCLK>; + reset-names = "axi", "ahb", "dclk"; + status = "disabled"; + + vop0_out: port { + #address-cells = <1>; + #size-cells = <0>; + + vop0_out_hdmi: endpoint@0 { + reg = <0>; + remote-endpoint = <&hdmi_in_vop0>; + }; + }; + }; + + vop1: vop@1010e000 { + compatible = "rockchip,rk3066-vop"; + reg = <0x1010e000 0x19c>; + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru ACLK_LCDC1>, + <&cru DCLK_LCDC1>, + <&cru HCLK_LCDC1>; + clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; + power-domains = <&power RK3066_PD_VIO>; + resets = <&cru SRST_LCDC1_AXI>, + <&cru SRST_LCDC1_AHB>, + <&cru SRST_LCDC1_DCLK>; + reset-names = "axi", "ahb", "dclk"; + status = "disabled"; + + vop1_out: port { + #address-cells = <1>; + #size-cells = <0>; + + vop1_out_hdmi: endpoint@0 { + reg = <0>; + remote-endpoint = <&hdmi_in_vop1>; + }; + }; + }; + + hdmi: hdmi@10116000 { + compatible = "rockchip,rk3066-hdmi"; + reg = <0x10116000 0x2000>; + interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru HCLK_HDMI>; + clock-names = "hclk"; + pinctrl-names = "default"; + pinctrl-0 = <&hdmii2c_xfer>, <&hdmi_hpd>; + power-domains = <&power RK3066_PD_VIO>; + rockchip,grf = <&grf>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + hdmi_in: port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + hdmi_in_vop0: endpoint@0 { + reg = <0>; + remote-endpoint = <&vop0_out_hdmi>; + }; + + hdmi_in_vop1: endpoint@1 { + reg = <1>; + remote-endpoint = <&vop1_out_hdmi>; + }; + }; + + hdmi_out: port@1 { + reg = <1>; + }; + }; + }; + + i2s0: i2s@10118000 { + compatible = "rockchip,rk3066-i2s"; + reg = <0x10118000 0x2000>; + interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_bus>; + clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0>; + clock-names = "i2s_clk", "i2s_hclk"; + dmas = <&dmac1_s 4>, <&dmac1_s 5>; + dma-names = "tx", "rx"; + rockchip,playback-channels = <8>; + rockchip,capture-channels = <2>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + i2s1: i2s@1011a000 { + compatible = "rockchip,rk3066-i2s"; + reg = <0x1011a000 0x2000>; + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1_bus>; + clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1>; + clock-names = "i2s_clk", "i2s_hclk"; + dmas = <&dmac1_s 6>, <&dmac1_s 7>; + dma-names = "tx", "rx"; + rockchip,playback-channels = <2>; + rockchip,capture-channels = <2>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + i2s2: i2s@1011c000 { + compatible = "rockchip,rk3066-i2s"; + reg = <0x1011c000 0x2000>; + interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s2_bus>; + clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2>; + clock-names = "i2s_clk", "i2s_hclk"; + dmas = <&dmac1_s 9>, <&dmac1_s 10>; + dma-names = "tx", "rx"; + rockchip,playback-channels = <2>; + rockchip,capture-channels = <2>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + cru: clock-controller@20000000 { + compatible = "rockchip,rk3066a-cru"; + reg = <0x20000000 0x1000>; + rockchip,grf = <&grf>; + + #clock-cells = <1>; + #reset-cells = <1>; + assigned-clocks = <&cru PLL_CPLL>, <&cru PLL_GPLL>, + <&cru ACLK_CPU>, <&cru HCLK_CPU>, + <&cru PCLK_CPU>, <&cru ACLK_PERI>, + <&cru HCLK_PERI>, <&cru PCLK_PERI>; + assigned-clock-rates = <400000000>, <594000000>, + <300000000>, <150000000>, + <75000000>, <300000000>, + <150000000>, <75000000>; + }; + + timer2: timer@2000e000 { + compatible = "snps,dw-apb-timer"; + reg = <0x2000e000 0x100>; + interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru SCLK_TIMER2>, <&cru PCLK_TIMER2>; + clock-names = "timer", "pclk"; + }; + + efuse: efuse@20010000 { + compatible = "rockchip,rk3066a-efuse"; + reg = <0x20010000 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cru PCLK_EFUSE>; + clock-names = "pclk_efuse"; + + cpu_leakage: cpu_leakage@17 { + reg = <0x17 0x1>; + }; + }; + + timer0: timer@20038000 { + compatible = "snps,dw-apb-timer"; + reg = <0x20038000 0x100>; + interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru SCLK_TIMER0>, <&cru PCLK_TIMER0>; + clock-names = "timer", "pclk"; + }; + + timer1: timer@2003a000 { + compatible = "snps,dw-apb-timer"; + reg = <0x2003a000 0x100>; + interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru SCLK_TIMER1>, <&cru PCLK_TIMER1>; + clock-names = "timer", "pclk"; + }; + + tsadc: tsadc@20060000 { + compatible = "rockchip,rk3066-tsadc"; + reg = <0x20060000 0x100>; + clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; + clock-names = "saradc", "apb_pclk"; + interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; + #io-channel-cells = <1>; + resets = <&cru SRST_TSADC>; + reset-names = "saradc-apb"; + status = "disabled"; + }; + + pinctrl: pinctrl { + compatible = "rockchip,rk3066a-pinctrl"; + rockchip,grf = <&grf>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + gpio0: gpio@20034000 { + compatible = "rockchip,gpio-bank"; + reg = <0x20034000 0x100>; + interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru PCLK_GPIO0>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio1: gpio@2003c000 { + compatible = "rockchip,gpio-bank"; + reg = <0x2003c000 0x100>; + interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru PCLK_GPIO1>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio@2003e000 { + compatible = "rockchip,gpio-bank"; + reg = <0x2003e000 0x100>; + interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru PCLK_GPIO2>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio@20080000 { + compatible = "rockchip,gpio-bank"; + reg = <0x20080000 0x100>; + interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru PCLK_GPIO3>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio4: gpio@20084000 { + compatible = "rockchip,gpio-bank"; + reg = <0x20084000 0x100>; + interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru PCLK_GPIO4>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio6: gpio@2000a000 { + compatible = "rockchip,gpio-bank"; + reg = <0x2000a000 0x100>; + interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru PCLK_GPIO6>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + pcfg_pull_default: pcfg-pull-default { + bias-pull-pin-default; + }; + + pcfg_pull_none: pcfg-pull-none { + bias-disable; + }; + + emac { + emac_xfer: emac-xfer { + rockchip,pins = <1 RK_PC0 2 &pcfg_pull_none>, /* mac_clk */ + <1 RK_PC1 2 &pcfg_pull_none>, /* tx_en */ + <1 RK_PC2 2 &pcfg_pull_none>, /* txd1 */ + <1 RK_PC3 2 &pcfg_pull_none>, /* txd0 */ + <1 RK_PC4 2 &pcfg_pull_none>, /* rx_err */ + <1 RK_PC5 2 &pcfg_pull_none>, /* crs_dvalid */ + <1 RK_PC6 2 &pcfg_pull_none>, /* rxd1 */ + <1 RK_PC7 2 &pcfg_pull_none>; /* rxd0 */ + }; + + emac_mdio: emac-mdio { + rockchip,pins = <1 RK_PD0 2 &pcfg_pull_none>, /* mac_md */ + <1 RK_PD1 2 &pcfg_pull_none>; /* mac_mdclk */ + }; + }; + + emmc { + emmc_clk: emmc-clk { + rockchip,pins = <3 RK_PD7 2 &pcfg_pull_default>; + }; + + emmc_cmd: emmc-cmd { + rockchip,pins = <4 RK_PB1 2 &pcfg_pull_default>; + }; + + emmc_rst: emmc-rst { + rockchip,pins = <4 RK_PB2 2 &pcfg_pull_default>; + }; + + /* + * The data pins are shared between nandc and emmc and + * not accessible through pinctrl. Also they should've + * been already set correctly by firmware, as + * flash/emmc is the boot-device. + */ + }; + + hdmi { + hdmi_hpd: hdmi-hpd { + rockchip,pins = <0 RK_PA0 1 &pcfg_pull_default>; + }; + + hdmii2c_xfer: hdmii2c-xfer { + rockchip,pins = <0 RK_PA1 1 &pcfg_pull_none>, + <0 RK_PA2 1 &pcfg_pull_none>; + }; + }; + + i2c0 { + i2c0_xfer: i2c0-xfer { + rockchip,pins = <2 RK_PD4 1 &pcfg_pull_none>, + <2 RK_PD5 1 &pcfg_pull_none>; + }; + }; + + i2c1 { + i2c1_xfer: i2c1-xfer { + rockchip,pins = <2 RK_PD6 1 &pcfg_pull_none>, + <2 RK_PD7 1 &pcfg_pull_none>; + }; + }; + + i2c2 { + i2c2_xfer: i2c2-xfer { + rockchip,pins = <3 RK_PA0 1 &pcfg_pull_none>, + <3 RK_PA1 1 &pcfg_pull_none>; + }; + }; + + i2c3 { + i2c3_xfer: i2c3-xfer { + rockchip,pins = <3 RK_PA2 2 &pcfg_pull_none>, + <3 RK_PA3 2 &pcfg_pull_none>; + }; + }; + + i2c4 { + i2c4_xfer: i2c4-xfer { + rockchip,pins = <3 RK_PA4 1 &pcfg_pull_none>, + <3 RK_PA5 1 &pcfg_pull_none>; + }; + }; + + pwm0 { + pwm0_out: pwm0-out { + rockchip,pins = <0 RK_PA3 1 &pcfg_pull_none>; + }; + }; + + pwm1 { + pwm1_out: pwm1-out { + rockchip,pins = <0 RK_PA4 1 &pcfg_pull_none>; + }; + }; + + pwm2 { + pwm2_out: pwm2-out { + rockchip,pins = <0 RK_PD6 1 &pcfg_pull_none>; + }; + }; + + pwm3 { + pwm3_out: pwm3-out { + rockchip,pins = <0 RK_PD7 1 &pcfg_pull_none>; + }; + }; + + spi0 { + spi0_clk: spi0-clk { + rockchip,pins = <1 RK_PA5 2 &pcfg_pull_default>; + }; + spi0_cs0: spi0-cs0 { + rockchip,pins = <1 RK_PA4 2 &pcfg_pull_default>; + }; + spi0_tx: spi0-tx { + rockchip,pins = <1 RK_PA7 2 &pcfg_pull_default>; + }; + spi0_rx: spi0-rx { + rockchip,pins = <1 RK_PA6 2 &pcfg_pull_default>; + }; + spi0_cs1: spi0-cs1 { + rockchip,pins = <4 RK_PB7 1 &pcfg_pull_default>; + }; + }; + + spi1 { + spi1_clk: spi1-clk { + rockchip,pins = <2 RK_PC3 2 &pcfg_pull_default>; + }; + spi1_cs0: spi1-cs0 { + rockchip,pins = <2 RK_PC4 2 &pcfg_pull_default>; + }; + spi1_rx: spi1-rx { + rockchip,pins = <2 RK_PC6 2 &pcfg_pull_default>; + }; + spi1_tx: spi1-tx { + rockchip,pins = <2 RK_PC5 2 &pcfg_pull_default>; + }; + spi1_cs1: spi1-cs1 { + rockchip,pins = <2 RK_PC7 2 &pcfg_pull_default>; + }; + }; + + uart0 { + uart0_xfer: uart0-xfer { + rockchip,pins = <1 RK_PA0 1 &pcfg_pull_default>, + <1 RK_PA1 1 &pcfg_pull_default>; + }; + + uart0_cts: uart0-cts { + rockchip,pins = <1 RK_PA2 1 &pcfg_pull_default>; + }; + + uart0_rts: uart0-rts { + rockchip,pins = <1 RK_PA3 1 &pcfg_pull_default>; + }; + }; + + uart1 { + uart1_xfer: uart1-xfer { + rockchip,pins = <1 RK_PA4 1 &pcfg_pull_default>, + <1 RK_PA5 1 &pcfg_pull_default>; + }; + + uart1_cts: uart1-cts { + rockchip,pins = <1 RK_PA6 1 &pcfg_pull_default>; + }; + + uart1_rts: uart1-rts { + rockchip,pins = <1 RK_PA7 1 &pcfg_pull_default>; + }; + }; + + uart2 { + uart2_xfer: uart2-xfer { + rockchip,pins = <1 RK_PB0 1 &pcfg_pull_default>, + <1 RK_PB1 1 &pcfg_pull_default>; + }; + /* no rts / cts for uart2 */ + }; + + uart3 { + uart3_xfer: uart3-xfer { + rockchip,pins = <3 RK_PD3 1 &pcfg_pull_default>, + <3 RK_PD4 1 &pcfg_pull_default>; + }; + + uart3_cts: uart3-cts { + rockchip,pins = <3 RK_PD5 1 &pcfg_pull_default>; + }; + + uart3_rts: uart3-rts { + rockchip,pins = <3 RK_PD6 1 &pcfg_pull_default>; + }; + }; + + sd0 { + sd0_clk: sd0-clk { + rockchip,pins = <3 RK_PB0 1 &pcfg_pull_default>; + }; + + sd0_cmd: sd0-cmd { + rockchip,pins = <3 RK_PB1 1 &pcfg_pull_default>; + }; + + sd0_cd: sd0-cd { + rockchip,pins = <3 RK_PB6 1 &pcfg_pull_default>; + }; + + sd0_wp: sd0-wp { + rockchip,pins = <3 RK_PB7 1 &pcfg_pull_default>; + }; + + sd0_bus1: sd0-bus-width1 { + rockchip,pins = <3 RK_PB2 1 &pcfg_pull_default>; + }; + + sd0_bus4: sd0-bus-width4 { + rockchip,pins = <3 RK_PB2 1 &pcfg_pull_default>, + <3 RK_PB3 1 &pcfg_pull_default>, + <3 RK_PB4 1 &pcfg_pull_default>, + <3 RK_PB5 1 &pcfg_pull_default>; + }; + }; + + sd1 { + sd1_clk: sd1-clk { + rockchip,pins = <3 RK_PC5 1 &pcfg_pull_default>; + }; + + sd1_cmd: sd1-cmd { + rockchip,pins = <3 RK_PC0 1 &pcfg_pull_default>; + }; + + sd1_cd: sd1-cd { + rockchip,pins = <3 RK_PC6 1 &pcfg_pull_default>; + }; + + sd1_wp: sd1-wp { + rockchip,pins = <3 RK_PC7 1 &pcfg_pull_default>; + }; + + sd1_bus1: sd1-bus-width1 { + rockchip,pins = <3 RK_PC1 1 &pcfg_pull_default>; + }; + + sd1_bus4: sd1-bus-width4 { + rockchip,pins = <3 RK_PC1 1 &pcfg_pull_default>, + <3 RK_PC2 1 &pcfg_pull_default>, + <3 RK_PC3 1 &pcfg_pull_default>, + <3 RK_PC4 1 &pcfg_pull_default>; + }; + }; + + i2s0 { + i2s0_bus: i2s0-bus { + rockchip,pins = <0 RK_PA7 1 &pcfg_pull_default>, + <0 RK_PB0 1 &pcfg_pull_default>, + <0 RK_PB1 1 &pcfg_pull_default>, + <0 RK_PB2 1 &pcfg_pull_default>, + <0 RK_PB3 1 &pcfg_pull_default>, + <0 RK_PB4 1 &pcfg_pull_default>, + <0 RK_PB5 1 &pcfg_pull_default>, + <0 RK_PB6 1 &pcfg_pull_default>, + <0 RK_PB7 1 &pcfg_pull_default>; + }; + }; + + i2s1 { + i2s1_bus: i2s1-bus { + rockchip,pins = <0 RK_PC0 1 &pcfg_pull_default>, + <0 RK_PC1 1 &pcfg_pull_default>, + <0 RK_PC2 1 &pcfg_pull_default>, + <0 RK_PC3 1 &pcfg_pull_default>, + <0 RK_PC4 1 &pcfg_pull_default>, + <0 RK_PC5 1 &pcfg_pull_default>; + }; + }; + + i2s2 { + i2s2_bus: i2s2-bus { + rockchip,pins = <0 RK_PD0 1 &pcfg_pull_default>, + <0 RK_PD1 1 &pcfg_pull_default>, + <0 RK_PD2 1 &pcfg_pull_default>, + <0 RK_PD3 1 &pcfg_pull_default>, + <0 RK_PD4 1 &pcfg_pull_default>, + <0 RK_PD5 1 &pcfg_pull_default>; + }; + }; + }; +}; + +&gpu { + compatible = "rockchip,rk3066-mali", "arm,mali-400"; + interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "gp", + "gpmmu", + "pp0", + "ppmmu0", + "pp1", + "ppmmu1", + "pp2", + "ppmmu2", + "pp3", + "ppmmu3"; + power-domains = <&power RK3066_PD_GPU>; +}; + +&grf { + compatible = "rockchip,rk3066-grf", "syscon", "simple-mfd"; + + usbphy: usbphy { + compatible = "rockchip,rk3066a-usb-phy"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + usbphy0: usb-phy@17c { + reg = <0x17c>; + clocks = <&cru SCLK_OTGPHY0>; + clock-names = "phyclk"; + #clock-cells = <0>; + #phy-cells = <0>; + }; + + usbphy1: usb-phy@188 { + reg = <0x188>; + clocks = <&cru SCLK_OTGPHY1>; + clock-names = "phyclk"; + #clock-cells = <0>; + #phy-cells = <0>; + }; + }; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_xfer>; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_xfer>; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_xfer>; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_xfer>; +}; + +&i2c4 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c4_xfer>; +}; + +&mmc0 { + clock-frequency = <50000000>; + dmas = <&dmac2 1>; + dma-names = "rx-tx"; + max-frequency = <50000000>; + pinctrl-names = "default"; + pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus4>; +}; + +&mmc1 { + dmas = <&dmac2 3>; + dma-names = "rx-tx"; + pinctrl-names = "default"; + pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_bus4>; +}; + +&emmc { + dmas = <&dmac2 4>; + dma-names = "rx-tx"; +}; + +&pmu { + power: power-controller { + compatible = "rockchip,rk3066-power-controller"; + #power-domain-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + + power-domain@RK3066_PD_VIO { + reg = <RK3066_PD_VIO>; + clocks = <&cru ACLK_LCDC0>, + <&cru ACLK_LCDC1>, + <&cru DCLK_LCDC0>, + <&cru DCLK_LCDC1>, + <&cru HCLK_LCDC0>, + <&cru HCLK_LCDC1>, + <&cru SCLK_CIF1>, + <&cru ACLK_CIF1>, + <&cru HCLK_CIF1>, + <&cru SCLK_CIF0>, + <&cru ACLK_CIF0>, + <&cru HCLK_CIF0>, + <&cru HCLK_HDMI>, + <&cru ACLK_IPP>, + <&cru HCLK_IPP>, + <&cru ACLK_RGA>, + <&cru HCLK_RGA>; + pm_qos = <&qos_lcdc0>, + <&qos_lcdc1>, + <&qos_cif0>, + <&qos_cif1>, + <&qos_ipp>, + <&qos_rga>; + #power-domain-cells = <0>; + }; + + power-domain@RK3066_PD_VIDEO { + reg = <RK3066_PD_VIDEO>; + clocks = <&cru ACLK_VDPU>, + <&cru ACLK_VEPU>, + <&cru HCLK_VDPU>, + <&cru HCLK_VEPU>; + pm_qos = <&qos_vpu>; + #power-domain-cells = <0>; + }; + + power-domain@RK3066_PD_GPU { + reg = <RK3066_PD_GPU>; + clocks = <&cru ACLK_GPU>; + pm_qos = <&qos_gpu>; + #power-domain-cells = <0>; + }; + }; +}; + +&pwm0 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm0_out>; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm1_out>; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm2_out>; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm3_out>; +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>; +}; + +&spi1 { + pinctrl-names = "default"; + pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>; +}; + +&uart0 { + compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart"; + dmas = <&dmac1_s 0>, <&dmac1_s 1>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer>; +}; + +&uart1 { + compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart"; + dmas = <&dmac1_s 2>, <&dmac1_s 3>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&uart1_xfer>; +}; + +&uart2 { + compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart"; + dmas = <&dmac2 6>, <&dmac2 7>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&uart2_xfer>; +}; + +&uart3 { + compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart"; + dmas = <&dmac2 8>, <&dmac2 9>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&uart3_xfer>; +}; + +&vpu { + power-domains = <&power RK3066_PD_VIDEO>; +}; + +&wdt { + compatible = "rockchip,rk3066-wdt", "snps,dw-wdt"; +}; + +&emac { + compatible = "rockchip,rk3066-emac"; +}; diff --git a/arch/arm/dts/rk3188-u-boot.dtsi b/arch/arm/dts/rk3188-u-boot.dtsi index 43f05b9876d..735776c16b8 100644 --- a/arch/arm/dts/rk3188-u-boot.dtsi +++ b/arch/arm/dts/rk3188-u-boot.dtsi @@ -4,6 +4,7 @@ */ #include "rockchip-u-boot.dtsi" +#include "rk3xxx-u-boot.dtsi" &global_timer { status = "okay"; diff --git a/arch/arm/dts/rk3188.dtsi b/arch/arm/dts/rk3188.dtsi index 6c1c2ff5339..6764776cce1 100644 --- a/arch/arm/dts/rk3188.dtsi +++ b/arch/arm/dts/rk3188.dtsi @@ -9,7 +9,6 @@ #include <dt-bindings/clock/rk3188-cru.h> #include <dt-bindings/power/rk3188-power.h> #include "rk3xxx.dtsi" -#include "rk3xxx-u-boot.dtsi" / { compatible = "rockchip,rk3188"; diff --git a/arch/arm/dts/rk3229-evb-u-boot.dtsi b/arch/arm/dts/rk3229-evb-u-boot.dtsi new file mode 100644 index 00000000000..b65149c2491 --- /dev/null +++ b/arch/arm/dts/rk3229-evb-u-boot.dtsi @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +#include "rk322x-u-boot.dtsi" + +/ { + chosen { + stdout-path = &uart2; + }; +}; + +&dmc { + rockchip,pctl-timing = <0x96 0xC8 0x1F3 0xF 0x8000004D 0x4 0x4E 0x6 0x3 + 0x0 0x6 0x5 0xC 0x10 0x6 0x4 0x4 + 0x5 0x4 0x200 0x3 0xA 0x40 0x0 0x1 + 0x5 0x5 0x3 0xC 0x1E 0x100 0x0 0x4 + 0x0 0x924>; + rockchip,phy-timing = <0x220 0x1 0x0 0x0 0x0 0x4 0x60>; + rockchip,sdram-params = <0x428B188 0x0 0x21 0x472 0x15 + 0 300 3 0 120>; +}; + +&emmc { + u-boot,dm-pre-reloc; +}; + +&uart2 { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/rk3229-evb.dts b/arch/arm/dts/rk3229-evb.dts index 632cdc9bc3d..797476e8bef 100644 --- a/arch/arm/dts/rk3229-evb.dts +++ b/arch/arm/dts/rk3229-evb.dts @@ -1,18 +1,16 @@ -// SPDX-License-Identifier: GPL-2.0+ OR X11 -/* - * (C) Copyright 2017 Rockchip Electronics Co., Ltd. - */ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /dts-v1/; -#include "rk322x.dtsi" +#include <dt-bindings/input/input.h> +#include "rk3229.dtsi" / { model = "Rockchip RK3229 Evaluation board"; compatible = "rockchip,rk3229-evb", "rockchip,rk3229"; - chosen { - stdout-path = &uart2; + aliases { + mmc0 = &emmc; }; memory@60000000 { @@ -20,6 +18,15 @@ reg = <0x60000000 0x40000000>; }; + dc_12v: dc-12v-regulator { + compatible = "regulator-fixed"; + regulator-name = "dc_12v"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + ext_gmac: ext_gmac { compatible = "fixed-clock"; clock-frequency = <125000000>; @@ -27,6 +34,18 @@ #clock-cells = <0>; }; + vcc_host: vcc-host-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio3 RK_PC4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&host_vbus_drv>; + regulator-name = "vcc_host"; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc_sys>; + }; + vcc_phy: vcc-phy-regulator { compatible = "regulator-fixed"; enable-active-high; @@ -35,18 +54,95 @@ regulator-max-microvolt = <1800000>; regulator-always-on; regulator-boot-on; + vin-supply = <&vccio_1v8>; + }; + + vcc_sys: vcc-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&dc_12v>; + }; + + vccio_1v8: vccio-1v8-regulator { + compatible = "regulator-fixed"; + regulator-name = "vccio_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + vin-supply = <&vcc_sys>; + }; + + vccio_3v3: vccio-3v3-regulator { + compatible = "regulator-fixed"; + regulator-name = "vccio_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + vin-supply = <&vcc_sys>; + }; + + vdd_arm: vdd-arm-regulator { + compatible = "pwm-regulator"; + pwms = <&pwm1 0 25000 1>; + pwm-supply = <&vcc_sys>; + regulator-name = "vdd_arm"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1400000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_log: vdd-log-regulator { + compatible = "pwm-regulator"; + pwms = <&pwm2 0 25000 1>; + pwm-supply = <&vcc_sys>; + regulator-name = "vdd_log"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + regulator-boot-on; + }; + + gpio_keys { + compatible = "gpio-keys"; + autorepeat; + pinctrl-names = "default"; + pinctrl-0 = <&pwr_key>; + + power_key: power-key { + label = "GPIO Key Power"; + gpios = <&gpio3 23 GPIO_ACTIVE_LOW>; + linux,code = <KEY_POWER>; + debounce-interval = <100>; + wakeup-source; + }; }; }; -&dmc { - rockchip,pctl-timing = <0x96 0xC8 0x1F3 0xF 0x8000004D 0x4 0x4E 0x6 0x3 - 0x0 0x6 0x5 0xC 0x10 0x6 0x4 0x4 - 0x5 0x4 0x200 0x3 0xA 0x40 0x0 0x1 - 0x5 0x5 0x3 0xC 0x1E 0x100 0x0 0x4 - 0x0 0x924>; - rockchip,phy-timing = <0x220 0x1 0x0 0x0 0x0 0x4 0x60>; - rockchip,sdram-params = <0x428B188 0x0 0x21 0x472 0x15 - 0 300 3 0 120>; +&cpu0 { + cpu-supply = <&vdd_arm>; +}; + +&cpu1 { + cpu-supply = <&vdd_arm>; +}; + +&cpu2 { + cpu-supply = <&vdd_arm>; +}; + +&cpu3 { + cpu-supply = <&vdd_arm>; +}; + +&emmc { + cap-mmc-highspeed; + non-removable; + status = "okay"; }; &gmac { @@ -65,27 +161,96 @@ status = "okay"; }; -&emmc { - u-boot,dm-pre-reloc; +&io_domains { + status = "okay"; + + vccio1-supply = <&vccio_3v3>; + vccio2-supply = <&vccio_1v8>; + vccio4-supply = <&vccio_3v3>; +}; + +&pinctrl { + keys { + pwr_key: pwr-key { + rockchip,pins = <3 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb { + host_vbus_drv: host-vbus-drv { + rockchip,pins = <3 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pwm1 { status = "okay"; }; -&sdmmc { +&pwm2 { + status = "okay"; +}; + +&tsadc { + rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */ status = "okay"; - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - card-detect-delay = <200>; - disable-wp; - num-slots = <1>; - supports-sd; }; &uart2 { - u-boot,dm-pre-reloc; status = "okay"; }; -&usb20_otg { - status = "okay"; +&u2phy0 { + status = "okay"; + + u2phy0_otg: otg-port { + status = "okay"; + }; + + u2phy0_host: host-port { + phy-supply = <&vcc_host>; + status = "okay"; + }; +}; + +&u2phy1 { + status = "okay"; + + u2phy1_otg: otg-port { + phy-supply = <&vcc_host>; + status = "okay"; + }; + + u2phy1_host: host-port { + phy-supply = <&vcc_host>; + status = "okay"; + }; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usb_host2_ehci { + status = "okay"; +}; + +&usb_host2_ohci { + status = "okay"; +}; + +&usb_otg { + status = "okay"; }; diff --git a/arch/arm/dts/rk3229.dtsi b/arch/arm/dts/rk3229.dtsi new file mode 100644 index 00000000000..c340fb30e77 --- /dev/null +++ b/arch/arm/dts/rk3229.dtsi @@ -0,0 +1,52 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd + */ + +#include "rk322x.dtsi" + +/ { + compatible = "rockchip,rk3229"; + + /delete-node/ opp-table0; + + cpu0_opp_table: opp-table-0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-408000000 { + opp-hz = /bits/ 64 <408000000>; + opp-microvolt = <950000>; + clock-latency-ns = <40000>; + opp-suspend; + }; + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <975000>; + }; + opp-816000000 { + opp-hz = /bits/ 64 <816000000>; + opp-microvolt = <1000000>; + }; + opp-1008000000 { + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <1175000>; + }; + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <1275000>; + }; + opp-1296000000 { + opp-hz = /bits/ 64 <1296000000>; + opp-microvolt = <1325000>; + }; + opp-1392000000 { + opp-hz = /bits/ 64 <1392000000>; + opp-microvolt = <1375000>; + }; + opp-1464000000 { + opp-hz = /bits/ 64 <1464000000>; + opp-microvolt = <1400000>; + }; + }; +}; diff --git a/arch/arm/dts/rk322x-u-boot.dtsi b/arch/arm/dts/rk322x-u-boot.dtsi new file mode 100644 index 00000000000..79c41e481be --- /dev/null +++ b/arch/arm/dts/rk322x-u-boot.dtsi @@ -0,0 +1,56 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include "rockchip-u-boot.dtsi" + +/ { + bus_intmem@10080000 { + compatible = "mmio-sram"; + reg = <0x10080000 0x9000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x10080000 0x9000>; + + smp-sram@0 { + compatible = "rockchip,rk322x-smp-sram"; + reg = <0x00 0x10>; + }; + + ddr_sram: ddr-sram@1000 { + compatible = "rockchip,rk322x-ddr-sram"; + reg = <0x1000 0x8000>; + }; + }; + + dmc: dmc@11200000 { + compatible = "rockchip,rk3228-dmc", "syscon"; + reg = <0x11200000 0x3fc + 0x12000000 0x400>; + rockchip,cru = <&cru>; + rockchip,grf = <&grf>; + rockchip,msch = <&service_msch>; + rockchip,sram = <&ddr_sram>; + u-boot,dm-pre-reloc; + }; + + service_msch: syscon@31090000 { + compatible = "rockchip,rk3228-msch", "syscon"; + reg = <0x31090000 0x2000>; + u-boot,dm-pre-reloc; + }; +}; + +&cru { + u-boot,dm-pre-reloc; +}; + +&emmc { + max-frequency = <150000000>; +}; + +&grf { + u-boot,dm-pre-reloc; +}; + +&sdmmc { + max-frequency = <150000000>; +}; diff --git a/arch/arm/dts/rk322x.dtsi b/arch/arm/dts/rk322x.dtsi index 4a8be5dabbd..8eed9e3a92e 100644 --- a/arch/arm/dts/rk322x.dtsi +++ b/arch/arm/dts/rk322x.dtsi @@ -1,7 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd. - */ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/interrupt-controller/irq.h> @@ -9,6 +6,7 @@ #include <dt-bindings/pinctrl/rockchip.h> #include <dt-bindings/clock/rk3228-cru.h> #include <dt-bindings/thermal/thermal.h> +#include <dt-bindings/power/rk3228-power.h> / { #address-cells = <1>; @@ -20,8 +18,7 @@ serial0 = &uart0; serial1 = &uart1; serial2 = &uart2; - mmc0 = &emmc; - mmc1 = &sdmmc; + spi0 = &spi0; }; cpus { @@ -33,13 +30,11 @@ compatible = "arm,cortex-a7"; reg = <0xf00>; resets = <&cru SRST_CORE0>; - operating-points = < - /* KHz uV */ - 816000 1000000 - >; + operating-points-v2 = <&cpu0_opp_table>; #cooling-cells = <2>; /* min followed by max */ clock-latency = <40000>; clocks = <&cru ARMCLK>; + enable-method = "psci"; }; cpu1: cpu@f01 { @@ -47,6 +42,9 @@ compatible = "arm,cortex-a7"; reg = <0xf01>; resets = <&cru SRST_CORE1>; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; /* min followed by max */ + enable-method = "psci"; }; cpu2: cpu@f02 { @@ -54,6 +52,9 @@ compatible = "arm,cortex-a7"; reg = <0xf02>; resets = <&cru SRST_CORE2>; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; /* min followed by max */ + enable-method = "psci"; }; cpu3: cpu@f03 { @@ -61,23 +62,37 @@ compatible = "arm,cortex-a7"; reg = <0xf03>; resets = <&cru SRST_CORE3>; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; /* min followed by max */ + enable-method = "psci"; }; }; - amba { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; + cpu0_opp_table: opp-table-0 { + compatible = "operating-points-v2"; + opp-shared; - pdma: pdma@110f0000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x110f0000 0x4000>; - interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; - #dma-cells = <1>; - clocks = <&cru ACLK_DMAC>; - clock-names = "apb_pclk"; + opp-408000000 { + opp-hz = /bits/ 64 <408000000>; + opp-microvolt = <950000>; + clock-latency-ns = <40000>; + opp-suspend; + }; + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <975000>; + }; + opp-816000000 { + opp-hz = /bits/ 64 <816000000>; + opp-microvolt = <1000000>; + }; + opp-1008000000 { + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <1175000>; + }; + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <1275000>; }; }; @@ -90,6 +105,11 @@ interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; }; + psci { + compatible = "arm,psci-1.0", "arm,psci-0.2"; + method = "smc"; + }; + timer { compatible = "arm,armv7-timer"; arm,cpu-registers-not-fw-configured; @@ -107,28 +127,15 @@ #clock-cells = <0>; }; - bus_intmem@10080000 { - compatible = "mmio-sram"; - reg = <0x10080000 0x9000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x10080000 0x9000>; - smp-sram@0 { - compatible = "rockchip,rk322x-smp-sram"; - reg = <0x00 0x10>; - }; - ddr_sram: ddr-sram@1000 { - compatible = "rockchip,rk322x-ddr-sram"; - reg = <0x1000 0x8000>; - }; + display_subsystem: display-subsystem { + compatible = "rockchip,display-subsystem"; + ports = <&vop_out>; }; i2s1: i2s1@100b0000 { compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s"; reg = <0x100b0000 0x4000>; interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; clock-names = "i2s_clk", "i2s_hclk"; clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>; dmas = <&pdma 14>, <&pdma 15>; @@ -142,8 +149,6 @@ compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s"; reg = <0x100c0000 0x4000>; interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; clock-names = "i2s_clk", "i2s_hclk"; clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>; dmas = <&pdma 11>, <&pdma 12>; @@ -151,12 +156,23 @@ status = "disabled"; }; + spdif: spdif@100d0000 { + compatible = "rockchip,rk3228-spdif"; + reg = <0x100d0000 0x1000>; + interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>; + clock-names = "mclk", "hclk"; + dmas = <&pdma 10>; + dma-names = "tx"; + pinctrl-names = "default"; + pinctrl-0 = <&spdif_tx>; + status = "disabled"; + }; + i2s2: i2s2@100e0000 { compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s"; reg = <0x100e0000 0x4000>; interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; clock-names = "i2s_clk", "i2s_hclk"; clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>; dmas = <&pdma 0>, <&pdma 1>; @@ -165,9 +181,124 @@ }; grf: syscon@11000000 { - u-boot,dm-pre-reloc; - compatible = "rockchip,rk3228-grf", "syscon"; + compatible = "rockchip,rk3228-grf", "syscon", "simple-mfd"; reg = <0x11000000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + io_domains: io-domains { + compatible = "rockchip,rk3228-io-voltage-domain"; + status = "disabled"; + }; + + power: power-controller { + compatible = "rockchip,rk3228-power-controller"; + #power-domain-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + + power-domain@RK3228_PD_VIO { + reg = <RK3228_PD_VIO>; + clocks = <&cru ACLK_HDCP>, + <&cru SCLK_HDCP>, + <&cru ACLK_IEP>, + <&cru HCLK_IEP>, + <&cru ACLK_RGA>, + <&cru HCLK_RGA>, + <&cru SCLK_RGA>; + pm_qos = <&qos_hdcp>, + <&qos_iep>, + <&qos_rga_r>, + <&qos_rga_w>; + #power-domain-cells = <0>; + }; + + power-domain@RK3228_PD_VOP { + reg = <RK3228_PD_VOP>; + clocks =<&cru ACLK_VOP>, + <&cru DCLK_VOP>, + <&cru HCLK_VOP>; + pm_qos = <&qos_vop>; + #power-domain-cells = <0>; + }; + + power-domain@RK3228_PD_VPU { + reg = <RK3228_PD_VPU>; + clocks = <&cru ACLK_VPU>, + <&cru HCLK_VPU>; + pm_qos = <&qos_vpu>; + #power-domain-cells = <0>; + }; + + power-domain@RK3228_PD_RKVDEC { + reg = <RK3228_PD_RKVDEC>; + clocks = <&cru ACLK_RKVDEC>, + <&cru HCLK_RKVDEC>, + <&cru SCLK_VDEC_CABAC>, + <&cru SCLK_VDEC_CORE>; + pm_qos = <&qos_rkvdec_r>, + <&qos_rkvdec_w>; + #power-domain-cells = <0>; + }; + + power-domain@RK3228_PD_GPU { + reg = <RK3228_PD_GPU>; + clocks = <&cru ACLK_GPU>; + pm_qos = <&qos_gpu>; + #power-domain-cells = <0>; + }; + }; + + u2phy0: usb2phy@760 { + compatible = "rockchip,rk3228-usb2phy"; + reg = <0x0760 0x0c>; + clocks = <&cru SCLK_OTGPHY0>; + clock-names = "phyclk"; + clock-output-names = "usb480m_phy0"; + #clock-cells = <0>; + status = "disabled"; + + u2phy0_otg: otg-port { + interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "otg-bvalid", "otg-id", + "linestate"; + #phy-cells = <0>; + status = "disabled"; + }; + + u2phy0_host: host-port { + interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "linestate"; + #phy-cells = <0>; + status = "disabled"; + }; + }; + + u2phy1: usb2phy@800 { + compatible = "rockchip,rk3228-usb2phy"; + reg = <0x0800 0x0c>; + clocks = <&cru SCLK_OTGPHY1>; + clock-names = "phyclk"; + clock-output-names = "usb480m_phy1"; + #clock-cells = <0>; + status = "disabled"; + + u2phy1_otg: otg-port { + interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "linestate"; + #phy-cells = <0>; + status = "disabled"; + }; + + u2phy1_host: host-port { + interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "linestate"; + #phy-cells = <0>; + status = "disabled"; + }; + }; }; uart0: serial@11010000 { @@ -206,12 +337,29 @@ clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; clock-names = "baudclk", "apb_pclk"; pinctrl-names = "default"; - pinctrl-0 = <&uart21_xfer>; + pinctrl-0 = <&uart2_xfer>; reg-shift = <2>; reg-io-width = <4>; status = "disabled"; }; + efuse: efuse@11040000 { + compatible = "rockchip,rk3228-efuse"; + reg = <0x11040000 0x20>; + clocks = <&cru PCLK_EFUSE_256>; + clock-names = "pclk_efuse"; + #address-cells = <1>; + #size-cells = <1>; + + /* Data cells */ + efuse_id: id@7 { + reg = <0x7 0x10>; + }; + cpu_leakage: cpu_leakage@17 { + reg = <0x17 0x1>; + }; + }; + i2c0: i2c@11050000 { compatible = "rockchip,rk3228-i2c"; reg = <0x11050000 0x1000>; @@ -264,12 +412,32 @@ status = "disabled"; }; + spi0: spi@11090000 { + compatible = "rockchip,rk3228-spi"; + reg = <0x11090000 0x1000>; + interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; + clock-names = "spiclk", "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0 &spi0_cs1>; + status = "disabled"; + }; + + wdt: watchdog@110a0000 { + compatible = "rockchip,rk3228-wdt", "snps,dw-wdt"; + reg = <0x110a0000 0x100>; + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru PCLK_CPU>; + status = "disabled"; + }; + pwm0: pwm@110b0000 { compatible = "rockchip,rk3288-pwm"; reg = <0x110b0000 0x10>; #pwm-cells = <3>; clocks = <&cru PCLK_PWM>; - clock-names = "pwm"; pinctrl-names = "default"; pinctrl-0 = <&pwm0_pin>; status = "disabled"; @@ -280,7 +448,6 @@ reg = <0x110b0010 0x10>; #pwm-cells = <3>; clocks = <&cru PCLK_PWM>; - clock-names = "pwm"; pinctrl-names = "default"; pinctrl-0 = <&pwm1_pin>; status = "disabled"; @@ -291,7 +458,6 @@ reg = <0x110b0020 0x10>; #pwm-cells = <3>; clocks = <&cru PCLK_PWM>; - clock-names = "pwm"; pinctrl-names = "default"; pinctrl-0 = <&pwm2_pin>; status = "disabled"; @@ -302,29 +468,48 @@ reg = <0x110b0030 0x10>; #pwm-cells = <2>; clocks = <&cru PCLK_PWM>; - clock-names = "pwm"; pinctrl-names = "default"; pinctrl-0 = <&pwm3_pin>; status = "disabled"; }; timer: timer@110c0000 { - compatible = "rockchip,rk3288-timer"; + compatible = "rockchip,rk3228-timer", "rockchip,rk3288-timer"; reg = <0x110c0000 0x20>; interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&xin24m>, <&cru PCLK_TIMER>; - clock-names = "timer", "pclk"; + clocks = <&cru PCLK_TIMER>, <&xin24m>; + clock-names = "pclk", "timer"; }; cru: clock-controller@110e0000 { - u-boot,dm-pre-reloc; compatible = "rockchip,rk3228-cru"; reg = <0x110e0000 0x1000>; rockchip,grf = <&grf>; #clock-cells = <1>; #reset-cells = <1>; - assigned-clocks = <&cru PLL_GPLL>; - assigned-clock-rates = <594000000>; + assigned-clocks = + <&cru PLL_GPLL>, <&cru ARMCLK>, + <&cru PLL_CPLL>, <&cru ACLK_PERI>, + <&cru HCLK_PERI>, <&cru PCLK_PERI>, + <&cru ACLK_CPU>, <&cru HCLK_CPU>, + <&cru PCLK_CPU>; + assigned-clock-rates = + <594000000>, <816000000>, + <500000000>, <150000000>, + <150000000>, <75000000>, + <150000000>, <150000000>, + <75000000>; + }; + + pdma: pdma@110f0000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x110f0000 0x4000>; + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; + #dma-cells = <1>; + arm,pl330-periph-burst; + clocks = <&cru ACLK_DMAC>; + clock-names = "apb_pclk"; }; thermal-zones { @@ -356,12 +541,18 @@ map0 { trip = <&cpu_alert0>; cooling-device = - <&cpu0 THERMAL_NO_LIMIT 6>; + <&cpu0 THERMAL_NO_LIMIT 6>, + <&cpu1 THERMAL_NO_LIMIT 6>, + <&cpu2 THERMAL_NO_LIMIT 6>, + <&cpu3 THERMAL_NO_LIMIT 6>; }; map1 { trip = <&cpu_alert1>; cooling-device = - <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -373,55 +564,220 @@ interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; clock-names = "tsadc", "apb_pclk"; + assigned-clocks = <&cru SCLK_TSADC>; + assigned-clock-rates = <32768>; resets = <&cru SRST_TSADC>; reset-names = "tsadc-apb"; pinctrl-names = "init", "default", "sleep"; - pinctrl-0 = <&otp_gpio>; + pinctrl-0 = <&otp_pin>; pinctrl-1 = <&otp_out>; - pinctrl-2 = <&otp_gpio>; - #thermal-sensor-cells = <0>; + pinctrl-2 = <&otp_pin>; + #thermal-sensor-cells = <1>; rockchip,hw-tshut-temp = <95000>; status = "disabled"; }; - sdmmc: dwmmc@30000000 { + hdmi_phy: hdmi-phy@12030000 { + compatible = "rockchip,rk3228-hdmi-phy"; + reg = <0x12030000 0x10000>; + clocks = <&cru PCLK_HDMI_PHY>, <&xin24m>, <&cru DCLK_HDMI_PHY>; + clock-names = "sysclk", "refoclk", "refpclk"; + #clock-cells = <0>; + clock-output-names = "hdmiphy_phy"; + #phy-cells = <0>; + status = "disabled"; + }; + + gpu: gpu@20000000 { + compatible = "rockchip,rk3228-mali", "arm,mali-400"; + reg = <0x20000000 0x10000>; + interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "gp", + "gpmmu", + "pp0", + "ppmmu0", + "pp1", + "ppmmu1"; + clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>; + clock-names = "bus", "core"; + power-domains = <&power RK3228_PD_GPU>; + resets = <&cru SRST_GPU_A>; + status = "disabled"; + }; + + vpu: video-codec@20020000 { + compatible = "rockchip,rk3228-vpu", "rockchip,rk3399-vpu"; + reg = <0x20020000 0x800>; + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "vepu", "vdpu"; + clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; + clock-names = "aclk", "hclk"; + iommus = <&vpu_mmu>; + power-domains = <&power RK3228_PD_VPU>; + }; + + vpu_mmu: iommu@20020800 { + compatible = "rockchip,iommu"; + reg = <0x20020800 0x100>; + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; + clock-names = "aclk", "iface"; + power-domains = <&power RK3228_PD_VPU>; + #iommu-cells = <0>; + }; + + vdec: video-codec@20030000 { + compatible = "rockchip,rk3228-vdec", "rockchip,rk3399-vdec"; + reg = <0x20030000 0x480>; + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>, + <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>; + clock-names = "axi", "ahb", "cabac", "core"; + assigned-clocks = <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>; + assigned-clock-rates = <300000000>, <300000000>; + iommus = <&vdec_mmu>; + power-domains = <&power RK3228_PD_RKVDEC>; + }; + + vdec_mmu: iommu@20030480 { + compatible = "rockchip,iommu"; + reg = <0x20030480 0x40>, <0x200304c0 0x40>; + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>; + clock-names = "aclk", "iface"; + power-domains = <&power RK3228_PD_RKVDEC>; + #iommu-cells = <0>; + }; + + vop: vop@20050000 { + compatible = "rockchip,rk3228-vop"; + reg = <0x20050000 0x1ffc>; + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>; + clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; + resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru SRST_VOP_D>; + reset-names = "axi", "ahb", "dclk"; + iommus = <&vop_mmu>; + power-domains = <&power RK3228_PD_VOP>; + status = "disabled"; + + vop_out: port { + #address-cells = <1>; + #size-cells = <0>; + + vop_out_hdmi: endpoint@0 { + reg = <0>; + remote-endpoint = <&hdmi_in_vop>; + }; + }; + }; + + vop_mmu: iommu@20053f00 { + compatible = "rockchip,iommu"; + reg = <0x20053f00 0x100>; + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; + clock-names = "aclk", "iface"; + power-domains = <&power RK3228_PD_VOP>; + #iommu-cells = <0>; + status = "disabled"; + }; + + rga: rga@20060000 { + compatible = "rockchip,rk3228-rga", "rockchip,rk3288-rga"; + reg = <0x20060000 0x1000>; + interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>; + clock-names = "aclk", "hclk", "sclk"; + power-domains = <&power RK3228_PD_VIO>; + resets = <&cru SRST_RGA>, <&cru SRST_RGA_A>, <&cru SRST_RGA_H>; + reset-names = "core", "axi", "ahb"; + }; + + iep_mmu: iommu@20070800 { + compatible = "rockchip,iommu"; + reg = <0x20070800 0x100>; + interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; + clock-names = "aclk", "iface"; + power-domains = <&power RK3228_PD_VIO>; + #iommu-cells = <0>; + status = "disabled"; + }; + + hdmi: hdmi@200a0000 { + compatible = "rockchip,rk3228-dw-hdmi"; + reg = <0x200a0000 0x20000>; + reg-io-width = <4>; + interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; + assigned-clocks = <&cru SCLK_HDMI_PHY>; + assigned-clock-parents = <&hdmi_phy>; + clocks = <&cru SCLK_HDMI_HDCP>, <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_CEC>; + clock-names = "isfr", "iahb", "cec"; + pinctrl-names = "default"; + pinctrl-0 = <&hdmii2c_xfer &hdmi_hpd &hdmi_cec>; + resets = <&cru SRST_HDMI_P>; + reset-names = "hdmi"; + phys = <&hdmi_phy>; + phy-names = "hdmi"; + rockchip,grf = <&grf>; + status = "disabled"; + + ports { + hdmi_in: port { + #address-cells = <1>; + #size-cells = <0>; + hdmi_in_vop: endpoint@0 { + reg = <0>; + remote-endpoint = <&vop_out_hdmi>; + }; + }; + }; + }; + + sdmmc: mmc@30000000 { compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc"; reg = <0x30000000 0x4000>; - max-frequency = <150000000>; interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; - clock-names = "biu", "ciu", "ciu_drv", "ciu_sample"; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; fifo-depth = <0x100>; pinctrl-names = "default"; pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>; status = "disabled"; }; - sdio: dwmmc@30010000 { + sdio: mmc@30010000 { compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc"; reg = <0x30010000 0x4000>; interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; - clock-names = "biu", "ciu", "ciu_drv", "ciu_sample"; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; fifo-depth = <0x100>; pinctrl-names = "default"; pinctrl-0 = <&sdio_clk &sdio_cmd &sdio_bus4>; status = "disabled"; }; - emmc: dwmmc@30020000 { - compatible = "rockchip,rk3288-dw-mshc"; + emmc: mmc@30020000 { + compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc"; reg = <0x30020000 0x4000>; - max-frequency = <150000000>; interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <37500000>; + max-frequency = <37500000>; clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; - clock-names = "biu", "ciu", "ciu_drv", "ciu_sample"; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; bus-width = <8>; - default-sample-phase = <158>; - num-slots = <1>; + rockchip,default-sample-phase = <158>; fifo-depth = <0x100>; pinctrl-names = "default"; pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; @@ -430,13 +786,79 @@ status = "disabled"; }; - usb20_otg: usb@30040000 { - compatible = "rockchip,rk3229-usb", "rockchip,rk3288-usb", + usb_otg: usb@30040000 { + compatible = "rockchip,rk3228-usb", "rockchip,rk3066-usb", "snps,dwc2"; reg = <0x30040000 0x40000>; interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; - hnp-srp-disable; + clocks = <&cru HCLK_OTG>; + clock-names = "otg"; dr_mode = "otg"; + g-np-tx-fifo-size = <16>; + g-rx-fifo-size = <280>; + g-tx-fifo-size = <256 128 128 64 32 16>; + phys = <&u2phy0_otg>; + phy-names = "usb2-phy"; + status = "disabled"; + }; + + usb_host0_ehci: usb@30080000 { + compatible = "generic-ehci"; + reg = <0x30080000 0x20000>; + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru HCLK_HOST0>, <&u2phy0>; + phys = <&u2phy0_host>; + phy-names = "usb"; + status = "disabled"; + }; + + usb_host0_ohci: usb@300a0000 { + compatible = "generic-ohci"; + reg = <0x300a0000 0x20000>; + interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru HCLK_HOST0>, <&u2phy0>; + phys = <&u2phy0_host>; + phy-names = "usb"; + status = "disabled"; + }; + + usb_host1_ehci: usb@300c0000 { + compatible = "generic-ehci"; + reg = <0x300c0000 0x20000>; + interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru HCLK_HOST1>, <&u2phy1>; + phys = <&u2phy1_otg>; + phy-names = "usb"; + status = "disabled"; + }; + + usb_host1_ohci: usb@300e0000 { + compatible = "generic-ohci"; + reg = <0x300e0000 0x20000>; + interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru HCLK_HOST1>, <&u2phy1>; + phys = <&u2phy1_otg>; + phy-names = "usb"; + status = "disabled"; + }; + + usb_host2_ehci: usb@30100000 { + compatible = "generic-ehci"; + reg = <0x30100000 0x20000>; + interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru HCLK_HOST2>, <&u2phy1>; + phys = <&u2phy1_host>; + phy-names = "usb"; + status = "disabled"; + }; + + usb_host2_ohci: usb@30120000 { + compatible = "generic-ohci"; + reg = <0x30120000 0x20000>; + interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru HCLK_HOST2>, <&u2phy1>; + phys = <&u2phy1_host>; + phy-names = "usb"; status = "disabled"; }; @@ -459,6 +881,51 @@ status = "disabled"; }; + qos_iep: qos@31030080 { + compatible = "rockchip,rk3228-qos", "syscon"; + reg = <0x31030080 0x20>; + }; + + qos_rga_w: qos@31030100 { + compatible = "rockchip,rk3228-qos", "syscon"; + reg = <0x31030100 0x20>; + }; + + qos_hdcp: qos@31030180 { + compatible = "rockchip,rk3228-qos", "syscon"; + reg = <0x31030180 0x20>; + }; + + qos_rga_r: qos@31030200 { + compatible = "rockchip,rk3228-qos", "syscon"; + reg = <0x31030200 0x20>; + }; + + qos_vpu: qos@31040000 { + compatible = "rockchip,rk3228-qos", "syscon"; + reg = <0x31040000 0x20>; + }; + + qos_gpu: qos@31050000 { + compatible = "rockchip,rk3228-qos", "syscon"; + reg = <0x31050000 0x20>; + }; + + qos_vop: qos@31060000 { + compatible = "rockchip,rk3228-qos", "syscon"; + reg = <0x31060000 0x20>; + }; + + qos_rkvdec_r: qos@31070000 { + compatible = "rockchip,rk3228-qos", "syscon"; + reg = <0x31070000 0x20>; + }; + + qos_rkvdec_w: qos@31070080 { + compatible = "rockchip,rk3228-qos", "syscon"; + reg = <0x31070080 0x20>; + }; + gic: interrupt-controller@32010000 { compatible = "arm,gic-400"; interrupt-controller; @@ -479,7 +946,7 @@ #size-cells = <1>; ranges; - gpio0: gpio0@11110000 { + gpio0: gpio@11110000 { compatible = "rockchip,gpio-bank"; reg = <0x11110000 0x100>; interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; @@ -492,7 +959,7 @@ #interrupt-cells = <2>; }; - gpio1: gpio1@11120000 { + gpio1: gpio@11120000 { compatible = "rockchip,gpio-bank"; reg = <0x11120000 0x100>; interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; @@ -505,7 +972,7 @@ #interrupt-cells = <2>; }; - gpio2: gpio2@11130000 { + gpio2: gpio@11130000 { compatible = "rockchip,gpio-bank"; reg = <0x11130000 0x100>; interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; @@ -518,7 +985,7 @@ #interrupt-cells = <2>; }; - gpio3: gpio3@11140000 { + gpio3: gpio@11140000 { compatible = "rockchip,gpio-bank"; reg = <0x11140000 0x100>; interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; @@ -549,240 +1016,278 @@ sdmmc { sdmmc_clk: sdmmc-clk { - rockchip,pins = <1 16 RK_FUNC_1 &pcfg_pull_none_drv_12ma>; + rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none_drv_12ma>; }; sdmmc_cmd: sdmmc-cmd { - rockchip,pins = <1 15 RK_FUNC_1 &pcfg_pull_none_drv_12ma>; + rockchip,pins = <1 RK_PB7 1 &pcfg_pull_none_drv_12ma>; }; sdmmc_bus4: sdmmc-bus4 { - rockchip,pins = <1 18 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, - <1 19 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, - <1 20 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, - <1 21 RK_FUNC_1 &pcfg_pull_none_drv_12ma>; + rockchip,pins = <1 RK_PC2 1 &pcfg_pull_none_drv_12ma>, + <1 RK_PC3 1 &pcfg_pull_none_drv_12ma>, + <1 RK_PC4 1 &pcfg_pull_none_drv_12ma>, + <1 RK_PC5 1 &pcfg_pull_none_drv_12ma>; }; }; sdio { sdio_clk: sdio-clk { - rockchip,pins = <3 0 RK_FUNC_1 &pcfg_pull_none_drv_12ma>; + rockchip,pins = <3 RK_PA0 1 &pcfg_pull_none_drv_12ma>; }; sdio_cmd: sdio-cmd { - rockchip,pins = <3 1 RK_FUNC_1 &pcfg_pull_none_drv_12ma>; + rockchip,pins = <3 RK_PA1 1 &pcfg_pull_none_drv_12ma>; }; sdio_bus4: sdio-bus4 { - rockchip,pins = <3 2 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, - <3 3 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, - <3 4 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, - <3 5 RK_FUNC_1 &pcfg_pull_none_drv_12ma>; + rockchip,pins = <3 RK_PA2 1 &pcfg_pull_none_drv_12ma>, + <3 RK_PA3 1 &pcfg_pull_none_drv_12ma>, + <3 RK_PA4 1 &pcfg_pull_none_drv_12ma>, + <3 RK_PA5 1 &pcfg_pull_none_drv_12ma>; }; }; emmc { emmc_clk: emmc-clk { - rockchip,pins = <2 RK_PA7 RK_FUNC_2 &pcfg_pull_none>; + rockchip,pins = <2 RK_PA7 2 &pcfg_pull_none>; }; emmc_cmd: emmc-cmd { - rockchip,pins = <1 RK_PC6 RK_FUNC_2 &pcfg_pull_none>; + rockchip,pins = <1 RK_PC6 2 &pcfg_pull_none>; }; emmc_bus8: emmc-bus8 { - rockchip,pins = <1 RK_PD0 RK_FUNC_2 &pcfg_pull_none>, - <1 RK_PD1 RK_FUNC_2 &pcfg_pull_none>, - <1 RK_PD2 RK_FUNC_2 &pcfg_pull_none>, - <1 RK_PD3 RK_FUNC_2 &pcfg_pull_none>, - <1 RK_PD4 RK_FUNC_2 &pcfg_pull_none>, - <1 RK_PD5 RK_FUNC_2 &pcfg_pull_none>, - <1 RK_PD6 RK_FUNC_2 &pcfg_pull_none>, - <1 RK_PD7 RK_FUNC_2 &pcfg_pull_none>; + rockchip,pins = <1 RK_PD0 2 &pcfg_pull_none>, + <1 RK_PD1 2 &pcfg_pull_none>, + <1 RK_PD2 2 &pcfg_pull_none>, + <1 RK_PD3 2 &pcfg_pull_none>, + <1 RK_PD4 2 &pcfg_pull_none>, + <1 RK_PD5 2 &pcfg_pull_none>, + <1 RK_PD6 2 &pcfg_pull_none>, + <1 RK_PD7 2 &pcfg_pull_none>; }; }; gmac { rgmii_pins: rgmii-pins { - rockchip,pins = <2 RK_PB6 RK_FUNC_1 &pcfg_pull_none>, - <2 RK_PB4 RK_FUNC_1 &pcfg_pull_none>, - <2 RK_PD1 RK_FUNC_1 &pcfg_pull_none>, - <2 RK_PC3 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, - <2 RK_PC2 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, - <2 RK_PC6 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, - <2 RK_PC7 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, - <2 RK_PB1 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, - <2 RK_PB5 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, - <2 RK_PC1 RK_FUNC_1 &pcfg_pull_none>, - <2 RK_PC0 RK_FUNC_1 &pcfg_pull_none>, - <2 RK_PC5 RK_FUNC_2 &pcfg_pull_none>, - <2 RK_PC4 RK_FUNC_2 &pcfg_pull_none>, - <2 RK_PB3 RK_FUNC_1 &pcfg_pull_none>, - <2 RK_PB0 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <2 RK_PB6 1 &pcfg_pull_none>, + <2 RK_PB4 1 &pcfg_pull_none>, + <2 RK_PD1 1 &pcfg_pull_none>, + <2 RK_PC3 1 &pcfg_pull_none_drv_12ma>, + <2 RK_PC2 1 &pcfg_pull_none_drv_12ma>, + <2 RK_PC6 1 &pcfg_pull_none_drv_12ma>, + <2 RK_PC7 1 &pcfg_pull_none_drv_12ma>, + <2 RK_PB1 1 &pcfg_pull_none_drv_12ma>, + <2 RK_PB5 1 &pcfg_pull_none_drv_12ma>, + <2 RK_PC1 1 &pcfg_pull_none>, + <2 RK_PC0 1 &pcfg_pull_none>, + <2 RK_PC5 2 &pcfg_pull_none>, + <2 RK_PC4 2 &pcfg_pull_none>, + <2 RK_PB3 1 &pcfg_pull_none>, + <2 RK_PB0 1 &pcfg_pull_none>; }; rmii_pins: rmii-pins { - rockchip,pins = <2 RK_PB6 RK_FUNC_1 &pcfg_pull_none>, - <2 RK_PB4 RK_FUNC_1 &pcfg_pull_none>, - <2 RK_PD1 RK_FUNC_1 &pcfg_pull_none>, - <2 RK_PC3 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, - <2 RK_PC2 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, - <2 RK_PB5 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, - <2 RK_PC1 RK_FUNC_1 &pcfg_pull_none>, - <2 RK_PC0 RK_FUNC_1 &pcfg_pull_none>, - <2 RK_PB0 RK_FUNC_1 &pcfg_pull_none>, - <2 RK_PB7 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <2 RK_PB6 1 &pcfg_pull_none>, + <2 RK_PB4 1 &pcfg_pull_none>, + <2 RK_PD1 1 &pcfg_pull_none>, + <2 RK_PC3 1 &pcfg_pull_none_drv_12ma>, + <2 RK_PC2 1 &pcfg_pull_none_drv_12ma>, + <2 RK_PB5 1 &pcfg_pull_none_drv_12ma>, + <2 RK_PC1 1 &pcfg_pull_none>, + <2 RK_PC0 1 &pcfg_pull_none>, + <2 RK_PB0 1 &pcfg_pull_none>, + <2 RK_PB7 1 &pcfg_pull_none>; }; phy_pins: phy-pins { - rockchip,pins = <2 RK_PB6 RK_FUNC_2 &pcfg_pull_none>, - <2 RK_PB0 RK_FUNC_2 &pcfg_pull_none>; + rockchip,pins = <2 RK_PB6 2 &pcfg_pull_none>, + <2 RK_PB0 2 &pcfg_pull_none>; + }; + }; + + hdmi { + hdmi_hpd: hdmi-hpd { + rockchip,pins = <0 RK_PB7 1 &pcfg_pull_down>; + }; + + hdmii2c_xfer: hdmii2c-xfer { + rockchip,pins = <0 RK_PA6 2 &pcfg_pull_none>, + <0 RK_PA7 2 &pcfg_pull_none>; + }; + + hdmi_cec: hdmi-cec { + rockchip,pins = <0 RK_PC4 1 &pcfg_pull_none>; }; }; i2c0 { i2c0_xfer: i2c0-xfer { - rockchip,pins = <0 RK_PA0 RK_FUNC_1 &pcfg_pull_none>, - <0 RK_PA1 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>, + <0 RK_PA1 1 &pcfg_pull_none>; }; }; i2c1 { i2c1_xfer: i2c1-xfer { - rockchip,pins = <0 RK_PA2 RK_FUNC_1 &pcfg_pull_none>, - <0 RK_PA3 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <0 RK_PA2 1 &pcfg_pull_none>, + <0 RK_PA3 1 &pcfg_pull_none>; }; }; i2c2 { i2c2_xfer: i2c2-xfer { - rockchip,pins = <2 RK_PC4 RK_FUNC_1 &pcfg_pull_none>, - <2 RK_PC5 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <2 RK_PC4 1 &pcfg_pull_none>, + <2 RK_PC5 1 &pcfg_pull_none>; }; }; i2c3 { i2c3_xfer: i2c3-xfer { - rockchip,pins = <0 RK_PA6 RK_FUNC_1 &pcfg_pull_none>, - <0 RK_PA7 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <0 RK_PA6 1 &pcfg_pull_none>, + <0 RK_PA7 1 &pcfg_pull_none>; + }; + }; + + spi0 { + spi0_clk: spi0-clk { + rockchip,pins = <0 RK_PB1 2 &pcfg_pull_up>; + }; + spi0_cs0: spi0-cs0 { + rockchip,pins = <0 RK_PB6 2 &pcfg_pull_up>; + }; + spi0_tx: spi0-tx { + rockchip,pins = <0 RK_PB3 2 &pcfg_pull_up>; + }; + spi0_rx: spi0-rx { + rockchip,pins = <0 RK_PB5 2 &pcfg_pull_up>; + }; + spi0_cs1: spi0-cs1 { + rockchip,pins = <1 RK_PB4 1 &pcfg_pull_up>; + }; + }; + + spi1 { + spi1_clk: spi1-clk { + rockchip,pins = <0 RK_PC7 2 &pcfg_pull_up>; + }; + spi1_cs0: spi1-cs0 { + rockchip,pins = <2 RK_PA2 2 &pcfg_pull_up>; + }; + spi1_rx: spi1-rx { + rockchip,pins = <2 RK_PA0 2 &pcfg_pull_up>; + }; + spi1_tx: spi1-tx { + rockchip,pins = <2 RK_PA1 2 &pcfg_pull_up>; + }; + spi1_cs1: spi1-cs1 { + rockchip,pins = <2 RK_PA3 2 &pcfg_pull_up>; }; }; i2s1 { i2s1_bus: i2s1-bus { - rockchip,pins = <0 RK_PB0 RK_FUNC_1 &pcfg_pull_none>, - <0 RK_PB1 RK_FUNC_1 &pcfg_pull_none>, - <0 RK_PB3 RK_FUNC_1 &pcfg_pull_none>, - <0 RK_PB4 RK_FUNC_1 &pcfg_pull_none>, - <0 RK_PB5 RK_FUNC_1 &pcfg_pull_none>, - <0 RK_PB6 RK_FUNC_1 &pcfg_pull_none>, - <1 RK_PA2 RK_FUNC_1 &pcfg_pull_none>, - <1 RK_PA4 RK_FUNC_1 &pcfg_pull_none>, - <1 RK_PA5 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <0 RK_PB0 1 &pcfg_pull_none>, + <0 RK_PB1 1 &pcfg_pull_none>, + <0 RK_PB3 1 &pcfg_pull_none>, + <0 RK_PB4 1 &pcfg_pull_none>, + <0 RK_PB5 1 &pcfg_pull_none>, + <0 RK_PB6 1 &pcfg_pull_none>, + <1 RK_PA2 2 &pcfg_pull_none>, + <1 RK_PA4 2 &pcfg_pull_none>, + <1 RK_PA5 2 &pcfg_pull_none>; }; }; pwm0 { pwm0_pin: pwm0-pin { - rockchip,pins = <3 RK_PC5 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <3 RK_PC5 1 &pcfg_pull_none>; }; }; pwm1 { pwm1_pin: pwm1-pin { - rockchip,pins = <0 RK_PD6 RK_FUNC_2 &pcfg_pull_none>; + rockchip,pins = <0 RK_PD6 2 &pcfg_pull_none>; }; }; pwm2 { pwm2_pin: pwm2-pin { - rockchip,pins = <1 RK_PB4 RK_FUNC_2 &pcfg_pull_none>; + rockchip,pins = <1 RK_PB4 2 &pcfg_pull_none>; }; }; pwm3 { pwm3_pin: pwm3-pin { - rockchip,pins = <1 RK_PB3 RK_FUNC_2 &pcfg_pull_none>; + rockchip,pins = <1 RK_PB3 2 &pcfg_pull_none>; + }; + }; + + spdif { + spdif_tx: spdif-tx { + rockchip,pins = <3 RK_PD7 2 &pcfg_pull_none>; }; }; tsadc { - otp_gpio: otp-gpio { + otp_pin: otp-pin { rockchip,pins = <0 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; }; otp_out: otp-out { - rockchip,pins = <0 RK_PD0 RK_FUNC_2 &pcfg_pull_none>; + rockchip,pins = <0 RK_PD0 2 &pcfg_pull_none>; }; }; uart0 { uart0_xfer: uart0-xfer { - rockchip,pins = <2 RK_PD2 RK_FUNC_1 &pcfg_pull_none>, - <2 RK_PD3 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <2 RK_PD2 1 &pcfg_pull_none>, + <2 RK_PD3 1 &pcfg_pull_none>; }; uart0_cts: uart0-cts { - rockchip,pins = <2 RK_PD5 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <2 RK_PD5 1 &pcfg_pull_none>; }; uart0_rts: uart0-rts { - rockchip,pins = <0 RK_PC1 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <0 RK_PC1 1 &pcfg_pull_none>; }; }; uart1 { uart1_xfer: uart1-xfer { - rockchip,pins = <1 RK_PB1 RK_FUNC_1 &pcfg_pull_none>, - <1 RK_PB2 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <1 RK_PB1 1 &pcfg_pull_none>, + <1 RK_PB2 1 &pcfg_pull_none>; }; uart1_cts: uart1-cts { - rockchip,pins = <1 RK_PB0 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <1 RK_PB0 1 &pcfg_pull_none>; }; uart1_rts: uart1-rts { - rockchip,pins = <1 RK_PB3 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <1 RK_PB3 1 &pcfg_pull_none>; }; }; uart2 { uart2_xfer: uart2-xfer { - rockchip,pins = <1 RK_PC2 RK_FUNC_2 &pcfg_pull_up>, - <1 RK_PC3 RK_FUNC_2 &pcfg_pull_none>; + rockchip,pins = <1 RK_PC2 2 &pcfg_pull_up>, + <1 RK_PC3 2 &pcfg_pull_none>; }; - uart2_cts: uart2-cts { - rockchip,pins = <0 RK_PD1 RK_FUNC_1 &pcfg_pull_none>; + uart21_xfer: uart21-xfer { + rockchip,pins = <1 RK_PB2 2 &pcfg_pull_up>, + <1 RK_PB1 2 &pcfg_pull_none>; }; - uart2_rts: uart2-rts { - rockchip,pins = <0 RK_PD0 RK_FUNC_1 &pcfg_pull_none>; + uart2_cts: uart2-cts { + rockchip,pins = <0 RK_PD1 1 &pcfg_pull_none>; }; - }; - uart2-1 { - uart21_xfer: uart21-xfer { - rockchip,pins = <1 10 RK_FUNC_2 &pcfg_pull_up>, - <1 9 RK_FUNC_2 &pcfg_pull_none>; + uart2_rts: uart2-rts { + rockchip,pins = <0 RK_PD0 1 &pcfg_pull_none>; }; }; }; - - dmc: dmc@11200000 { - u-boot,dm-pre-reloc; - compatible = "rockchip,rk3228-dmc", "syscon"; - rockchip,cru = <&cru>; - rockchip,grf = <&grf>; - rockchip,msch = <&service_msch>; - reg = <0x11200000 0x3fc - 0x12000000 0x400>; - rockchip,sram = <&ddr_sram>; - }; - - service_msch: syscon@31090000 { - u-boot,dm-pre-reloc; - compatible = "rockchip,rk3228-msch", "syscon"; - reg = <0x31090000 0x2000>; - }; }; diff --git a/arch/arm/dts/rk3288-evb-u-boot.dtsi b/arch/arm/dts/rk3288-evb-u-boot.dtsi index 8ac7840f8f9..c8f51207116 100644 --- a/arch/arm/dts/rk3288-evb-u-boot.dtsi +++ b/arch/arm/dts/rk3288-evb-u-boot.dtsi @@ -5,6 +5,17 @@ #include "rk3288-u-boot.dtsi" +&dmc { + rockchip,pctl-timing = <0x215 0xc8 0x0 0x35 0x26 0x2 0x70 0x2000d + 0x6 0x0 0x8 0x4 0x17 0x24 0xd 0x6 + 0x4 0x8 0x4 0x76 0x4 0x0 0x30 0x0 + 0x1 0x2 0x2 0x4 0x0 0x0 0xc0 0x4 + 0x8 0x1f4>; + rockchip,phy-timing = <0x48d7dd93 0x187008d8 0x121076 + 0x0 0xc3 0x6 0x2>; + rockchip,sdram-params = <0x20d266a4 0x5b6 2 533000000 6 9 0>; +}; + &pinctrl { u-boot,dm-pre-reloc; }; diff --git a/arch/arm/dts/rk3288-evb.dts b/arch/arm/dts/rk3288-evb.dts index eac91a873f2..bb24a96cddf 100644 --- a/arch/arm/dts/rk3288-evb.dts +++ b/arch/arm/dts/rk3288-evb.dts @@ -15,17 +15,6 @@ }; }; -&dmc { - rockchip,pctl-timing = <0x215 0xc8 0x0 0x35 0x26 0x2 0x70 0x2000d - 0x6 0x0 0x8 0x4 0x17 0x24 0xd 0x6 - 0x4 0x8 0x4 0x76 0x4 0x0 0x30 0x0 - 0x1 0x2 0x2 0x4 0x0 0x0 0xc0 0x4 - 0x8 0x1f4>; - rockchip,phy-timing = <0x48d7dd93 0x187008d8 0x121076 - 0x0 0xc3 0x6 0x2>; - rockchip,sdram-params = <0x20d266a4 0x5b6 2 533000000 6 9 0>; -}; - &pwm1 { status = "okay"; }; diff --git a/arch/arm/dts/rk3288-firefly-u-boot.dtsi b/arch/arm/dts/rk3288-firefly-u-boot.dtsi index 8b9c38310fb..cc84d7c4ae1 100644 --- a/arch/arm/dts/rk3288-firefly-u-boot.dtsi +++ b/arch/arm/dts/rk3288-firefly-u-boot.dtsi @@ -5,6 +5,37 @@ #include "rk3288-u-boot.dtsi" +/ { + config { + u-boot,dm-pre-reloc; + u-boot,boot-led = "firefly:green:power"; + }; + + leds { + u-boot,dm-pre-reloc; + + work { + u-boot,dm-pre-reloc; + }; + + power { + u-boot,dm-pre-reloc; + }; + }; +}; + +&dmc { + rockchip,pctl-timing = <0x29a 0xc8 0x1f8 0x42 0x4e 0x4 0xea 0xa + 0x5 0x0 0xa 0x7 0x19 0x24 0xa 0x7 + 0x5 0xa 0x5 0x200 0x5 0x10 0x40 0x0 + 0x1 0x7 0x7 0x4 0xc 0x43 0x100 0x0 + 0x5 0x0>; + rockchip,phy-timing = <0x48f9aab4 0xea0910 0x1002c200 + 0xa60 0x40 0x10 0x0>; + /* Add a dummy value to cause of-platdata think this is bytes */ + rockchip,sdram-params = <0x30B25564 0x627 3 666000000 3 9 1>; +}; + &pinctrl { u-boot,dm-pre-reloc; }; diff --git a/arch/arm/dts/rk3288-firefly.dts b/arch/arm/dts/rk3288-firefly.dts index 1cff04e7c7b..72982efdf6d 100644 --- a/arch/arm/dts/rk3288-firefly.dts +++ b/arch/arm/dts/rk3288-firefly.dts @@ -13,23 +13,6 @@ chosen { stdout-path = &uart2; }; - - config { - u-boot,dm-pre-reloc; - u-boot,boot-led = "firefly:green:power"; - }; -}; - -&dmc { - rockchip,pctl-timing = <0x29a 0xc8 0x1f8 0x42 0x4e 0x4 0xea 0xa - 0x5 0x0 0xa 0x7 0x19 0x24 0xa 0x7 - 0x5 0xa 0x5 0x200 0x5 0x10 0x40 0x0 - 0x1 0x7 0x7 0x4 0xc 0x43 0x100 0x0 - 0x5 0x0>; - rockchip,phy-timing = <0x48f9aab4 0xea0910 0x1002c200 - 0xa60 0x40 0x10 0x0>; - /* Add a dummy value to cause of-platdata think this is bytes */ - rockchip,sdram-params = <0x30B25564 0x627 3 666000000 3 9 1>; }; &ir { diff --git a/arch/arm/dts/rk3288-firefly.dtsi b/arch/arm/dts/rk3288-firefly.dtsi index b7f279f706f..1117d3913ed 100644 --- a/arch/arm/dts/rk3288-firefly.dtsi +++ b/arch/arm/dts/rk3288-firefly.dtsi @@ -37,11 +37,9 @@ }; leds { - u-boot,dm-pre-reloc; compatible = "gpio-leds"; work { - u-boot,dm-pre-reloc; gpios = <&gpio8 1 GPIO_ACTIVE_LOW>; label = "firefly:blue:user"; linux,default-trigger = "rc-feedback"; @@ -50,7 +48,6 @@ }; power { - u-boot,dm-pre-reloc; gpios = <&gpio8 2 GPIO_ACTIVE_LOW>; label = "firefly:green:power"; linux,default-trigger = "default-on"; diff --git a/arch/arm/dts/rk3288-miqi-u-boot.dtsi b/arch/arm/dts/rk3288-miqi-u-boot.dtsi index 4f63fc9f131..2a74fdd15fb 100644 --- a/arch/arm/dts/rk3288-miqi-u-boot.dtsi +++ b/arch/arm/dts/rk3288-miqi-u-boot.dtsi @@ -4,6 +4,26 @@ */ #include "rk3288-u-boot.dtsi" +/ { + leds { + u-boot,dm-pre-reloc; + + work { + u-boot,dm-pre-reloc; + }; + }; +}; + +&dmc { + rockchip,pctl-timing = <0x29a 0xc8 0x1f8 0x42 0x4e 0x4 0xea 0xa + 0x5 0x0 0xa 0x7 0x19 0x24 0xa 0x7 + 0x5 0xa 0x5 0x200 0x5 0x10 0x40 0x0 + 0x1 0x7 0x7 0x4 0xc 0x43 0x100 0x0 + 0x5 0x0>; + rockchip,phy-timing = <0x48f9aab4 0xea0910 0x1002c200 + 0xa60 0x40 0x10 0x0>; + rockchip,sdram-params = <0x30B25564 0x627 3 666000000 3 9 1>; +}; &pinctrl { u-boot,dm-pre-reloc; diff --git a/arch/arm/dts/rk3288-miqi.dts b/arch/arm/dts/rk3288-miqi.dts index e47170c6530..4a2f249e1b1 100644 --- a/arch/arm/dts/rk3288-miqi.dts +++ b/arch/arm/dts/rk3288-miqi.dts @@ -14,14 +14,3 @@ stdout-path = "serial2:115200n8"; }; }; - -&dmc { - rockchip,pctl-timing = <0x29a 0xc8 0x1f8 0x42 0x4e 0x4 0xea 0xa - 0x5 0x0 0xa 0x7 0x19 0x24 0xa 0x7 - 0x5 0xa 0x5 0x200 0x5 0x10 0x40 0x0 - 0x1 0x7 0x7 0x4 0xc 0x43 0x100 0x0 - 0x5 0x0>; - rockchip,phy-timing = <0x48f9aab4 0xea0910 0x1002c200 - 0xa60 0x40 0x10 0x0>; - rockchip,sdram-params = <0x30B25564 0x627 3 666000000 3 9 1>; -}; diff --git a/arch/arm/dts/rk3288-miqi.dtsi b/arch/arm/dts/rk3288-miqi.dtsi index 432f744bebc..cb80cbf27df 100644 --- a/arch/arm/dts/rk3288-miqi.dtsi +++ b/arch/arm/dts/rk3288-miqi.dtsi @@ -34,11 +34,9 @@ leds { - u-boot,dm-pre-reloc; compatible = "gpio-leds"; work { - u-boot,dm-pre-reloc; gpios = <&gpio7 4 GPIO_ACTIVE_LOW>; label = "miqi:green:user"; linux,default-trigger = "default-on"; diff --git a/arch/arm/dts/rk3288-phycore-rdk-u-boot.dtsi b/arch/arm/dts/rk3288-phycore-rdk-u-boot.dtsi new file mode 100644 index 00000000000..30f4cb106e2 --- /dev/null +++ b/arch/arm/dts/rk3288-phycore-rdk-u-boot.dtsi @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include "rk3288-u-boot.dtsi" + +&dmc { + rockchip,num-channels = <2>; + rockchip,pctl-timing = <0x29a 0xc8 0x1f8 0x42 0x4e 0x4 0xea 0xa + 0x5 0x0 0xa 0x7 0x19 0x24 0xa 0x7 + 0x5 0xa 0x5 0x200 0x5 0x10 0x40 0x0 + 0x1 0x7 0x7 0x4 0xc 0x43 0x100 0x0 + 0x5 0x0>; + rockchip,phy-timing = <0x48f9aab4 0xea0910 0x1002c200 + 0xa60 0x40 0x10 0x0>; + rockchip,sdram-channel = /bits/ 8 <0x1 0xa 0x3 0x2 0x1 0x0 0xe 0xe>; + rockchip,sdram-params = <0x30B25564 0x627 3 666000000 3 5 1>; +}; + +&emmc { + u-boot,dm-pre-reloc; +}; + +&i2c0 { + u-boot,dm-pre-reloc; + + rk818: pmic@1c { + u-boot,dm-pre-reloc; + + regulators { + u-boot,dm-pre-reloc; + }; + }; +}; + +&pinctrl { + u-boot,dm-pre-reloc; +}; + +&sdmmc { + u-boot,dm-pre-reloc; +}; + +&uart2 { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/rk3288-phycore-rdk.dts b/arch/arm/dts/rk3288-phycore-rdk.dts index cc3921095c3..ebea8e67ead 100644 --- a/arch/arm/dts/rk3288-phycore-rdk.dts +++ b/arch/arm/dts/rk3288-phycore-rdk.dts @@ -112,19 +112,6 @@ }; }; -&dmc { - rockchip,num-channels = <2>; - rockchip,pctl-timing = <0x29a 0xc8 0x1f8 0x42 0x4e 0x4 0xea 0xa - 0x5 0x0 0xa 0x7 0x19 0x24 0xa 0x7 - 0x5 0xa 0x5 0x200 0x5 0x10 0x40 0x0 - 0x1 0x7 0x7 0x4 0xc 0x43 0x100 0x0 - 0x5 0x0>; - rockchip,phy-timing = <0x48f9aab4 0xea0910 0x1002c200 - 0xa60 0x40 0x10 0x0>; - rockchip,sdram-channel = /bits/ 8 <0x1 0xa 0x3 0x2 0x1 0x0 0xe 0xe>; - rockchip,sdram-params = <0x30B25564 0x627 3 666000000 3 5 1>; -}; - &gmac { status = "okay"; }; @@ -175,8 +162,6 @@ }; &pinctrl { - u-boot,dm-pre-reloc; - pcfg_pull_up_drv_12ma: pcfg-pull-up-drv-12ma { bias-pull-up; drive-strength = <12>; @@ -246,8 +231,6 @@ }; &sdmmc { - u-boot,dm-pre-reloc; - bus-width = <4>; cap-mmc-highspeed; cap-sd-highspeed; @@ -268,7 +251,6 @@ }; &uart2 { - u-boot,dm-pre-reloc; status = "okay"; }; diff --git a/arch/arm/dts/rk3288-phycore-som.dtsi b/arch/arm/dts/rk3288-phycore-som.dtsi index 02d11968cb3..821525f7148 100644 --- a/arch/arm/dts/rk3288-phycore-som.dtsi +++ b/arch/arm/dts/rk3288-phycore-som.dtsi @@ -149,8 +149,6 @@ &emmc { status = "okay"; - u-boot,dm-pre-reloc; - bus-width = <8>; cap-mmc-highspeed; disable-wp; @@ -201,8 +199,6 @@ &i2c0 { status = "okay"; - u-boot,dm-pre-reloc; - clock-frequency = <400000>; rk818: pmic@1c { @@ -216,7 +212,6 @@ rockchip,system-power-controller; wakeup-source; #clock-cells = <1>; - u-boot,dm-pre-reloc; vcc1-supply = <&vdd_sys>; vcc2-supply = <&vdd_sys>; @@ -230,7 +225,6 @@ vddio-supply = <&vdd_3v3_io>; regulators { - u-boot,dm-pre-reloc; vdd_log: DCDC_REG1 { regulator-name = "vdd_log"; regulator-always-on; diff --git a/arch/arm/dts/rk3288-popmetal-u-boot.dtsi b/arch/arm/dts/rk3288-popmetal-u-boot.dtsi index 8ac7840f8f9..3782253c8aa 100644 --- a/arch/arm/dts/rk3288-popmetal-u-boot.dtsi +++ b/arch/arm/dts/rk3288-popmetal-u-boot.dtsi @@ -5,6 +5,17 @@ #include "rk3288-u-boot.dtsi" +&dmc { + rockchip,pctl-timing = <0x29a 0xc8 0x1f8 0x42 0x4e 0x4 0xea 0xa + 0x5 0x0 0xa 0x7 0x19 0x24 0xa 0x7 + 0x5 0xa 0x5 0x200 0x5 0x10 0x40 0x0 + 0x1 0x7 0x7 0x4 0xc 0x43 0x100 0x0 + 0x5 0x0>; + rockchip,phy-timing = <0x48f9aab4 0xea0910 0x1002c200 + 0xa60 0x40 0x10 0x0>; + rockchip,sdram-params = <0x30B25564 0x627 3 666000000 3 9 1>; +}; + &pinctrl { u-boot,dm-pre-reloc; }; diff --git a/arch/arm/dts/rk3288-popmetal.dts b/arch/arm/dts/rk3288-popmetal.dts index 5c6d06f2fdb..736dc51e261 100644 --- a/arch/arm/dts/rk3288-popmetal.dts +++ b/arch/arm/dts/rk3288-popmetal.dts @@ -15,17 +15,6 @@ }; }; -&dmc { - rockchip,pctl-timing = <0x29a 0xc8 0x1f8 0x42 0x4e 0x4 0xea 0xa - 0x5 0x0 0xa 0x7 0x19 0x24 0xa 0x7 - 0x5 0xa 0x5 0x200 0x5 0x10 0x40 0x0 - 0x1 0x7 0x7 0x4 0xc 0x43 0x100 0x0 - 0x5 0x0>; - rockchip,phy-timing = <0x48f9aab4 0xea0910 0x1002c200 - 0xa60 0x40 0x10 0x0>; - rockchip,sdram-params = <0x30B25564 0x627 3 666000000 3 9 1>; -}; - &pwm1 { status = "okay"; }; diff --git a/arch/arm/dts/rk3288-rock2-square-u-boot.dtsi b/arch/arm/dts/rk3288-rock2-square-u-boot.dtsi new file mode 100644 index 00000000000..509f789b98b --- /dev/null +++ b/arch/arm/dts/rk3288-rock2-square-u-boot.dtsi @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include "rk3288-u-boot.dtsi" + +&dmc { + rockchip,pctl-timing = <0x29a 0xc8 0x1f8 0x42 0x4e 0x4 0xea 0xa + 0x5 0x0 0xa 0x7 0x19 0x24 0xa 0x7 + 0x5 0xa 0x5 0x200 0x5 0x10 0x40 0x0 + 0x1 0x7 0x7 0x4 0xc 0x43 0x100 0x0 + 0x5 0x0>; + rockchip,phy-timing = <0x48f9aab4 0xea0910 0x1002c200 + 0xa60 0x40 0x10 0x0>; + rockchip,sdram-params = <0x30B25564 0x627 3 666000000 3 9 1>; +}; + +&gpio7 { + u-boot,dm-pre-reloc; +}; + +&pinctrl { + u-boot,dm-pre-reloc; +}; + +&sdmmc { + u-boot,dm-pre-reloc; +}; + +&uart2 { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/rk3288-rock2-square.dts b/arch/arm/dts/rk3288-rock2-square.dts index 11c580a0b56..41676696ba3 100644 --- a/arch/arm/dts/rk3288-rock2-square.dts +++ b/arch/arm/dts/rk3288-rock2-square.dts @@ -96,7 +96,6 @@ }; &sdmmc { - u-boot,dm-pre-reloc; bus-width = <4>; cap-mmc-highspeed; cap-sd-highspeed; @@ -139,7 +138,6 @@ }; &pinctrl { - u-boot,dm-pre-reloc; ir { ir_int: ir-int { rockchip,pins = <8 1 RK_FUNC_GPIO &pcfg_pull_up>; @@ -171,7 +169,6 @@ &uart2 { status = "okay"; - u-boot,dm-pre-reloc; reg-shift = <2>; }; @@ -182,18 +179,3 @@ &usb_host0_ehci { status = "okay"; }; - -&dmc { - rockchip,pctl-timing = <0x29a 0xc8 0x1f8 0x42 0x4e 0x4 0xea 0xa - 0x5 0x0 0xa 0x7 0x19 0x24 0xa 0x7 - 0x5 0xa 0x5 0x200 0x5 0x10 0x40 0x0 - 0x1 0x7 0x7 0x4 0xc 0x43 0x100 0x0 - 0x5 0x0>; - rockchip,phy-timing = <0x48f9aab4 0xea0910 0x1002c200 - 0xa60 0x40 0x10 0x0>; - rockchip,sdram-params = <0x30B25564 0x627 3 666000000 3 9 1>; -}; - -&gpio7 { - u-boot,dm-pre-reloc; -}; diff --git a/arch/arm/dts/rk3288-u-boot.dtsi b/arch/arm/dts/rk3288-u-boot.dtsi index e3c6c10f130..9eb696b1411 100644 --- a/arch/arm/dts/rk3288-u-boot.dtsi +++ b/arch/arm/dts/rk3288-u-boot.dtsi @@ -7,10 +7,53 @@ #include "rockchip-optee.dtsi" / { + aliases { + gpio0 = &gpio0; + gpio1 = &gpio1; + gpio2 = &gpio2; + gpio3 = &gpio3; + gpio4 = &gpio4; + gpio5 = &gpio5; + gpio6 = &gpio6; + gpio7 = &gpio7; + gpio8 = &gpio8; + mmc0 = &emmc; + mmc1 = &sdmmc; + mmc2 = &sdio0; + mmc3 = &sdio1; + }; + chosen { u-boot,spl-boot-order = \ "same-as-spl", &emmc, &sdmmc; }; + + dmc: dmc@ff610000 { + compatible = "rockchip,rk3288-dmc", "syscon"; + reg = <0xff610000 0x3fc + 0xff620000 0x294 + 0xff630000 0x3fc + 0xff640000 0x294>; + clocks = <&cru PCLK_DDRUPCTL0>, <&cru PCLK_PUBL0>, + <&cru PCLK_DDRUPCTL1>, <&cru PCLK_PUBL1>, + <&cru ARMCLK>; + clock-names = "pclk_ddrupctl0", "pclk_publ0", + "pclk_ddrupctl1", "pclk_publ1", + "arm_clk"; + rockchip,cru = <&cru>; + rockchip,grf = <&grf>; + rockchip,noc = <&noc>; + rockchip,pmu = <&pmu>; + rockchip,sgrf = <&sgrf>; + rockchip,sram = <&ddr_sram>; + u-boot,dm-pre-reloc; + }; + + noc: syscon@ffac0000 { + compatible = "rockchip,rk3288-noc", "syscon"; + reg = <0xffac0000 0x2000>; + u-boot,dm-pre-reloc; + }; }; #ifdef CONFIG_ROCKCHIP_SPI_IMAGE @@ -37,38 +80,53 @@ }; #endif -&dmc { - u-boot,dm-pre-reloc; +&bus_intmem { + ddr_sram: ddr-sram@1000 { + compatible = "rockchip,rk3288-ddr-sram"; + reg = <0x1000 0x4000>; + }; }; -&pmu { +&cru { u-boot,dm-pre-reloc; }; -&sgrf { +&gpio7 { u-boot,dm-pre-reloc; }; -&cru { +&grf { u-boot,dm-pre-reloc; }; -&grf { +&pmu { u-boot,dm-pre-reloc; }; -&vopb { +&sgrf { u-boot,dm-pre-reloc; }; -&vopl { - u-boot,dm-pre-reloc; +&uart0 { + clock-frequency = <24000000>; +}; + +&uart1 { + clock-frequency = <24000000>; }; -&noc { +&uart2 { + clock-frequency = <24000000>; +}; + +&uart3 { + clock-frequency = <24000000>; +}; + +&vopb { u-boot,dm-pre-reloc; }; -&gpio7 { +&vopl { u-boot,dm-pre-reloc; }; diff --git a/arch/arm/dts/rk3288-veyron-jerry-u-boot.dtsi b/arch/arm/dts/rk3288-veyron-jerry-u-boot.dtsi new file mode 100644 index 00000000000..2cc6b090acb --- /dev/null +++ b/arch/arm/dts/rk3288-veyron-jerry-u-boot.dtsi @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include "rk3288-veyron-u-boot.dtsi" + +&dmc { + rockchip,pctl-timing = <0x29a 0xc8 0x1f4 0x42 0x4e 0x4 0xea 0xa + 0x5 0x0 0xa 0x7 0x19 0x24 0xa 0x7 + 0x5 0xa 0x5 0x200 0x5 0x10 0x40 0x0 + 0x1 0x7 0x7 0x4 0xc 0x43 0x100 0x0 + 0x5 0x0>; + rockchip,phy-timing = <0x48f9aab4 0xea0910 0x1002c200 + 0xa60 0x40 0x10 0x0>; + rockchip,sdram-params = <0x30B25564 0x627 3 666000000 3 9 1>; +}; diff --git a/arch/arm/dts/rk3288-veyron-jerry.dts b/arch/arm/dts/rk3288-veyron-jerry.dts index c251d9d5942..ff7669eba4d 100644 --- a/arch/arm/dts/rk3288-veyron-jerry.dts +++ b/arch/arm/dts/rk3288-veyron-jerry.dts @@ -66,17 +66,6 @@ }; }; -&dmc { - rockchip,pctl-timing = <0x29a 0xc8 0x1f4 0x42 0x4e 0x4 0xea 0xa - 0x5 0x0 0xa 0x7 0x19 0x24 0xa 0x7 - 0x5 0xa 0x5 0x200 0x5 0x10 0x40 0x0 - 0x1 0x7 0x7 0x4 0xc 0x43 0x100 0x0 - 0x5 0x0>; - rockchip,phy-timing = <0x48f9aab4 0xea0910 0x1002c200 - 0xa60 0x40 0x10 0x0>; - rockchip,sdram-params = <0x30B25564 0x627 3 666000000 3 9 1>; -}; - &gpio_keys { power { gpios = <&gpio0 5 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/dts/rk3288-veyron-mickey-u-boot.dtsi b/arch/arm/dts/rk3288-veyron-mickey-u-boot.dtsi new file mode 100644 index 00000000000..213a46babf0 --- /dev/null +++ b/arch/arm/dts/rk3288-veyron-mickey-u-boot.dtsi @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include "rk3288-veyron-u-boot.dtsi" + +&dmc { + rockchip,pctl-timing = <0x215 0xc8 0x0 0x35 0x26 0x2 0x70 0x2000d + 0x6 0x0 0x8 0x4 0x17 0x24 0xd 0x6 + 0x4 0x8 0x4 0x76 0x4 0x0 0x30 0x0 + 0x1 0x2 0x2 0x4 0x0 0x0 0xc0 0x4 + 0x8 0x1f4>; + rockchip,phy-timing = <0x48d7dd93 0x187008d8 0x121076 + 0x0 0xc3 0x6 0x2>; + rockchip,sdram-params = <0x20d266a4 0x5b6 2 533000000 6 9 1>; +}; diff --git a/arch/arm/dts/rk3288-veyron-mickey.dts b/arch/arm/dts/rk3288-veyron-mickey.dts index e0dc3620618..0521d9e0e9a 100644 --- a/arch/arm/dts/rk3288-veyron-mickey.dts +++ b/arch/arm/dts/rk3288-veyron-mickey.dts @@ -161,17 +161,6 @@ }; }; -&dmc { - rockchip,pctl-timing = <0x215 0xc8 0x0 0x35 0x26 0x2 0x70 0x2000d - 0x6 0x0 0x8 0x4 0x17 0x24 0xd 0x6 - 0x4 0x8 0x4 0x76 0x4 0x0 0x30 0x0 - 0x1 0x2 0x2 0x4 0x0 0x0 0xc0 0x4 - 0x8 0x1f4>; - rockchip,phy-timing = <0x48d7dd93 0x187008d8 0x121076 - 0x0 0xc3 0x6 0x2>; - rockchip,sdram-params = <0x20d266a4 0x5b6 2 533000000 6 9 1>; -}; - &emmc { /delete-property/mmc-hs200-1_8v; }; diff --git a/arch/arm/dts/rk3288-veyron-minnie-u-boot.dtsi b/arch/arm/dts/rk3288-veyron-minnie-u-boot.dtsi new file mode 100644 index 00000000000..8211da41fcc --- /dev/null +++ b/arch/arm/dts/rk3288-veyron-minnie-u-boot.dtsi @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include "rk3288-veyron-u-boot.dtsi" + +&dmc { + rockchip,pctl-timing = <0x215 0xc8 0x0 0x35 0x26 0x2 0x70 0x2000d + 0x6 0x0 0x8 0x4 0x17 0x24 0xd 0x6 + 0x4 0x8 0x4 0x76 0x4 0x0 0x30 0x0 + 0x1 0x2 0x2 0x4 0x0 0x0 0xc0 0x4 + 0x8 0x1f4>; + rockchip,phy-timing = <0x48d7dd93 0x187008d8 0x121076 + 0x0 0xc3 0x6 0x1>; + rockchip,sdram-params = <0x20d266a4 0x5b6 6 533000000 6 13 0>; +}; diff --git a/arch/arm/dts/rk3288-veyron-minnie.dts b/arch/arm/dts/rk3288-veyron-minnie.dts index 646f6ae7424..b56a3f4f51a 100644 --- a/arch/arm/dts/rk3288-veyron-minnie.dts +++ b/arch/arm/dts/rk3288-veyron-minnie.dts @@ -137,17 +137,6 @@ power-supply = <&backlight_regulator>; }; -&dmc { - rockchip,pctl-timing = <0x215 0xc8 0x0 0x35 0x26 0x2 0x70 0x2000d - 0x6 0x0 0x8 0x4 0x17 0x24 0xd 0x6 - 0x4 0x8 0x4 0x76 0x4 0x0 0x30 0x0 - 0x1 0x2 0x2 0x4 0x0 0x0 0xc0 0x4 - 0x8 0x1f4>; - rockchip,phy-timing = <0x48d7dd93 0x187008d8 0x121076 - 0x0 0xc3 0x6 0x1>; - rockchip,sdram-params = <0x20d266a4 0x5b6 6 533000000 6 13 0>; -}; - &emmc { /delete-property/mmc-hs200-1_8v; }; diff --git a/arch/arm/dts/rk3288-veyron-u-boot.dtsi b/arch/arm/dts/rk3288-veyron-u-boot.dtsi index 899fe6e7a04..21e1aec2911 100644 --- a/arch/arm/dts/rk3288-veyron-u-boot.dtsi +++ b/arch/arm/dts/rk3288-veyron-u-boot.dtsi @@ -5,7 +5,68 @@ #include "rk3288-u-boot.dtsi" +/ { + chosen { + u-boot,spl-boot-order = &spi_flash; + }; +}; + +&dmc { + logic-supply = <&vdd_logic>; + rockchip,odt-disable-freq = <333000000>; + rockchip,dll-disable-freq = <333000000>; + rockchip,sr-enable-freq = <333000000>; + rockchip,pd-enable-freq = <666000000>; + rockchip,auto-self-refresh-cnt = <0>; + rockchip,auto-power-down-cnt = <64>; + rockchip,ddr-speed-bin = <21>; + rockchip,trcd = <10>; + rockchip,trp = <10>; + operating-points = < + /* KHz uV */ + 200000 1050000 + 333000 1100000 + 533000 1150000 + 666000 1200000 + >; +}; + +&gpio3 { + u-boot,dm-pre-reloc; +}; + &gpio7 { u-boot,dm-pre-reloc; }; +&gpio8 { + u-boot,dm-pre-reloc; +}; + +&i2c0 { + u-boot,dm-pre-reloc; +}; + +&pinctrl { + u-boot,dm-pre-reloc; +}; + +&rk808 { + u-boot,dm-pre-reloc; +}; + +&sdmmc { + u-boot,dm-pre-reloc; +}; + +&spi2 { + u-boot,dm-pre-reloc; +}; + +&spi_flash { + u-boot,dm-pre-reloc; +}; + +&uart2 { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/rk3288-veyron.dtsi b/arch/arm/dts/rk3288-veyron.dtsi index 8754043b9b3..4a9c27a49e2 100644 --- a/arch/arm/dts/rk3288-veyron.dtsi +++ b/arch/arm/dts/rk3288-veyron.dtsi @@ -16,7 +16,6 @@ chosen { stdout-path = &uart2; - u-boot,spl-boot-order = &spi_flash; }; firmware { @@ -220,26 +219,6 @@ cpu0-supply = <&vdd_cpu>; }; -&dmc { - logic-supply = <&vdd_logic>; - rockchip,odt-disable-freq = <333000000>; - rockchip,dll-disable-freq = <333000000>; - rockchip,sr-enable-freq = <333000000>; - rockchip,pd-enable-freq = <666000000>; - rockchip,auto-self-refresh-cnt = <0>; - rockchip,auto-power-down-cnt = <64>; - rockchip,ddr-speed-bin = <21>; - rockchip,trcd = <10>; - rockchip,trp = <10>; - operating-points = < - /* KHz uV */ - 200000 1050000 - 333000 1100000 - 533000 1150000 - 666000 1200000 - >; -}; - &efuse { status = "okay"; }; @@ -299,10 +278,8 @@ &spi2 { status = "okay"; - u-boot,dm-pre-reloc; spi_flash: spiflash@0 { - u-boot,dm-pre-reloc; compatible = "spidev", "jedec,spi-nor"; spi-max-frequency = <20000000>; /* Reduce for Dediprog em100 pro */ reg = <0>; @@ -315,7 +292,6 @@ clock-frequency = <400000>; i2c-scl-falling-time-ns = <50>; /* 2.5ns measured */ i2c-scl-rising-time-ns = <100>; /* 45ns measured */ - u-boot,dm-pre-reloc; rk808: pmic@1b { compatible = "rockchip,rk808"; @@ -328,7 +304,6 @@ rockchip,system-power-controller; wakeup-source; #clock-cells = <1>; - u-boot,dm-pre-reloc; vcc1-supply = <&vcc33_sys>; vcc2-supply = <&vcc33_sys>; @@ -557,7 +532,6 @@ &uart2 { status = "okay"; - u-boot,dm-pre-reloc; reg-shift = <2>; }; @@ -601,7 +575,6 @@ }; &pinctrl { - u-boot,dm-pre-reloc; pinctrl-names = "default", "sleep"; pinctrl-0 = < /* Common for sleep and wake, but no owners */ @@ -826,15 +799,3 @@ assigned-clocks = <&cru SCLK_USBPHY480M_SRC>; assigned-clock-parents = <&cru SCLK_OTGPHY0>; }; - -&sdmmc { - u-boot,dm-pre-reloc; -}; - -&gpio3 { - u-boot,dm-pre-reloc; -}; - -&gpio8 { - u-boot,dm-pre-reloc; -}; diff --git a/arch/arm/dts/rk3288.dtsi b/arch/arm/dts/rk3288.dtsi index 22bb06cec5b..c4abfa3702c 100644 --- a/arch/arm/dts/rk3288.dtsi +++ b/arch/arm/dts/rk3288.dtsi @@ -5,7 +5,7 @@ #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/pinctrl/rockchip.h> #include <dt-bindings/clock/rk3288-cru.h> -#include <dt-bindings/power-domain/rk3288.h> +#include <dt-bindings/power/rk3288-power.h> #include <dt-bindings/thermal/thermal.h> #include <dt-bindings/video/rk3288.h> #include "skeleton.dtsi" @@ -15,25 +15,12 @@ interrupt-parent = <&gic>; aliases { - gpio0 = &gpio0; - gpio1 = &gpio1; - gpio2 = &gpio2; - gpio3 = &gpio3; - gpio4 = &gpio4; - gpio5 = &gpio5; - gpio6 = &gpio6; - gpio7 = &gpio7; - gpio8 = &gpio8; i2c0 = &i2c0; i2c1 = &i2c1; i2c2 = &i2c2; i2c3 = &i2c3; i2c4 = &i2c4; i2c5 = &i2c5; - mmc0 = &emmc; - mmc1 = &sdmmc; - mmc2 = &sdio0; - mmc3 = &sdio1; mshc0 = &emmc; mshc1 = &sdmmc; mshc2 = &sdio0; @@ -323,7 +310,6 @@ interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; reg-shift = <2>; reg-io-width = <4>; - clock-frequency = <24000000>; clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; clock-names = "baudclk", "apb_pclk"; pinctrl-names = "default"; @@ -337,7 +323,6 @@ interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; reg-shift = <2>; reg-io-width = <4>; - clock-frequency = <24000000>; clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; clock-names = "baudclk", "apb_pclk"; pinctrl-names = "default"; @@ -351,7 +336,6 @@ interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; reg-shift = <2>; reg-io-width = <4>; - clock-frequency = <24000000>; clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; clock-names = "baudclk", "apb_pclk"; pinctrl-names = "default"; @@ -364,7 +348,6 @@ interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; reg-shift = <2>; reg-io-width = <4>; - clock-frequency = <24000000>; clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; clock-names = "baudclk", "apb_pclk"; pinctrl-names = "default"; @@ -378,7 +361,6 @@ interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; reg-shift = <2>; reg-io-width = <4>; - clock-frequency = <24000000>; clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; clock-names = "baudclk", "apb_pclk"; pinctrl-names = "default"; @@ -476,26 +458,6 @@ status = "disabled"; }; - dmc: dmc@ff610000 { - compatible = "rockchip,rk3288-dmc", "syscon"; - rockchip,cru = <&cru>; - rockchip,grf = <&grf>; - rockchip,pmu = <&pmu>; - rockchip,sgrf = <&sgrf>; - rockchip,noc = <&noc>; - reg = <0xff610000 0x3fc - 0xff620000 0x294 - 0xff630000 0x3fc - 0xff640000 0x294>; - rockchip,sram = <&ddr_sram>; - clocks = <&cru PCLK_DDRUPCTL0>, <&cru PCLK_PUBL0>, - <&cru PCLK_DDRUPCTL1>, <&cru PCLK_PUBL1>, - <&cru ARMCLK>; - clock-names = "pclk_ddrupctl0", "pclk_publ0", - "pclk_ddrupctl1", "pclk_publ1", - "arm_clk"; - }; - i2c0: i2c@ff650000 { compatible = "rockchip,rk3288-i2c"; reg = <0xff650000 0x1000>; @@ -570,7 +532,7 @@ status = "disabled"; }; - bus_intmem@ff700000 { + bus_intmem: bus_intmem@ff700000 { compatible = "mmio-sram"; reg = <0xff700000 0x18000>; #address-cells = <1>; @@ -580,10 +542,6 @@ compatible = "rockchip,rk3066-smp-sram"; reg = <0x00 0x10>; }; - ddr_sram: ddr-sram@1000 { - compatible = "rockchip,rk3288-ddr-sram"; - reg = <0x1000 0x4000>; - }; }; sram@ff720000 { @@ -912,11 +870,6 @@ status = "disabled"; }; - noc: syscon@ffac0000 { - compatible = "rockchip,rk3288-noc", "syscon"; - reg = <0xffac0000 0x2000>; - }; - efuse: efuse@ffb40000 { compatible = "rockchip,rk3288-efuse"; reg = <0xffb40000 0x10000>; diff --git a/arch/arm/dts/rk3xxx-u-boot.dtsi b/arch/arm/dts/rk3xxx-u-boot.dtsi index 581594c35d3..e67432fb392 100644 --- a/arch/arm/dts/rk3xxx-u-boot.dtsi +++ b/arch/arm/dts/rk3xxx-u-boot.dtsi @@ -4,7 +4,7 @@ noc: syscon@10128000 { compatible = "rockchip,rk3188-noc", "syscon"; reg = <0x10128000 0x2000>; - u-boot,dm-spl; + u-boot,dm-pre-reloc; }; dmc: dmc@20020000 { @@ -18,16 +18,16 @@ rockchip,grf = <&grf>; rockchip,pmu = <&pmu>; rockchip,noc = <&noc>; - u-boot,dm-spl; + u-boot,dm-pre-reloc; }; }; &grf { - u-boot,dm-spl; + u-boot,dm-pre-reloc; }; &pmu { - u-boot,dm-spl; + u-boot,dm-pre-reloc; }; &uart2 { diff --git a/arch/arm/include/asm/arch-rk3066/boot0.h b/arch/arm/include/asm/arch-rk3066/boot0.h new file mode 100644 index 00000000000..28c0fb9a4c6 --- /dev/null +++ b/arch/arm/include/asm/arch-rk3066/boot0.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#ifndef __ASM_ARCH_BOOT0_H__ +#define __ASM_ARCH_BOOT0_H__ + +#include <asm/arch-rockchip/boot0.h> + +#endif diff --git a/arch/arm/include/asm/arch-rk3066/gpio.h b/arch/arm/include/asm/arch-rk3066/gpio.h new file mode 100644 index 00000000000..a4a3b3289c2 --- /dev/null +++ b/arch/arm/include/asm/arch-rk3066/gpio.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#ifndef __ASM_ARCH_GPIO_H__ +#define __ASM_ARCH_GPIO_H__ + +#include <asm/arch-rockchip/gpio.h> + +#endif diff --git a/arch/arm/include/asm/arch-rk3066/timer.h b/arch/arm/include/asm/arch-rk3066/timer.h new file mode 100644 index 00000000000..3bb39428cd6 --- /dev/null +++ b/arch/arm/include/asm/arch-rk3066/timer.h @@ -0,0 +1,6 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#ifndef __ASM_ARCH_TIMER_H__ +#define __ASM_ARCH_TIMER_H__ + +#endif diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3066.h b/arch/arm/include/asm/arch-rockchip/cru_rk3066.h new file mode 100644 index 00000000000..76a715a8e6a --- /dev/null +++ b/arch/arm/include/asm/arch-rockchip/cru_rk3066.h @@ -0,0 +1,157 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2021 Paweł Jarosz <paweljarosz3691@gmail.com> + */ + +#ifndef _ASM_ARCH_CRU_RK3066_H +#define _ASM_ARCH_CRU_RK3066_H + +#include <linux/bitops.h> +#include <linux/bitfield.h> + +#define REG(name, h, l) \ + name##_MASK = GENMASK(h, l), \ + name##_SHIFT = __bf_shf(name##_MASK) + +#define OSC_HZ (24 * 1000 * 1000) + +#define APLL_HZ (1416 * 1000000) +#define APLL_SAFE_HZ (600 * 1000000) +#define GPLL_HZ (594 * 1000000) +#define CPLL_HZ (384 * 1000000) + +/* The SRAM is clocked off aclk_cpu, so we want to max it out for boot speed */ +#define CPU_ACLK_HZ 297000000 +#define CPU_HCLK_HZ 148500000 +#define CPU_PCLK_HZ 74250000 +#define CPU_H2P_HZ 74250000 + +#define PERI_ACLK_HZ 148500000 +#define PERI_HCLK_HZ 148500000 +#define PERI_PCLK_HZ 74250000 + +/* Private data for the clock driver - used by rockchip_get_cru() */ +struct rk3066_clk_priv { + struct rk3066_grf *grf; + struct rk3066_cru *cru; + ulong rate; + bool has_bwadj; +}; + +struct rk3066_cru { + struct rk3066_pll { + u32 con0; + u32 con1; + u32 con2; + u32 con3; + } pll[4]; + u32 cru_mode_con; + u32 cru_clksel_con[35]; + u32 cru_clkgate_con[10]; + u32 reserved1[2]; + u32 cru_glb_srst_fst_value; + u32 cru_glb_srst_snd_value; + u32 reserved2[2]; + u32 cru_softrst_con[9]; + u32 cru_misc_con; + u32 reserved3[2]; + u32 cru_glb_cnt_th; +}; + +check_member(rk3066_cru, cru_glb_cnt_th, 0x0140); + +/* CRU_CLKSEL0_CON */ +enum { + REG(CPU_ACLK_PLL, 8, 8), + CPU_ACLK_PLL_SELECT_APLL = 0, + CPU_ACLK_PLL_SELECT_GPLL, + + REG(CORE_PERI_DIV, 7, 6), + + REG(A9_CORE_DIV, 4, 0), +}; + +/* CRU_CLKSEL1_CON */ +enum { + REG(AHB2APB_DIV, 15, 14), + + REG(CPU_PCLK_DIV, 13, 12), + + REG(CPU_HCLK_DIV, 9, 8), + + REG(CPU_ACLK_DIV, 2, 0), +}; + +/* CRU_CLKSEL10_CON */ +enum { + REG(PERI_SEL_PLL, 15, 15), + PERI_SEL_CPLL = 0, + PERI_SEL_GPLL, + + REG(PERI_PCLK_DIV, 13, 12), + + REG(PERI_HCLK_DIV, 9, 8), + + REG(PERI_ACLK_DIV, 4, 0), +}; + +/* CRU_CLKSEL11_CON */ +enum { + REG(MMC0_DIV, 5, 0), +}; + +/* CRU_CLKSEL12_CON */ +enum { + REG(UART_PLL, 15, 15), + UART_PLL_SELECT_GENERAL = 0, + UART_PLL_SELECT_CODEC, + + REG(EMMC_DIV, 13, 8), + + REG(SDIO_DIV, 5, 0), +}; + +/* CRU_CLKSEL24_CON */ +enum { + REG(SARADC_DIV, 15, 8), +}; + +/* CRU_CLKSEL25_CON */ +enum { + REG(SPI1_DIV, 14, 8), + + REG(SPI0_DIV, 6, 0), +}; + +/* CRU_CLKSEL34_CON */ +enum { + REG(TSADC_DIV, 15, 0), +}; + +/* CRU_MODE_CON */ +enum { + REG(GPLL_MODE, 13, 12), + + REG(CPLL_MODE, 9, 8), + + REG(DPLL_MODE, 5, 4), + + REG(APLL_MODE, 1, 0), + PLL_MODE_SLOW = 0, + PLL_MODE_NORMAL, + PLL_MODE_DEEP, +}; + +/* CRU_APLL_CON0 */ +enum { + REG(CLKR, 13, 8), + + REG(CLKOD, 3, 0), +}; + +/* CRU_APLL_CON1 */ +enum { + REG(CLKF, 12, 0), +}; + +#endif diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3066.h b/arch/arm/include/asm/arch-rockchip/grf_rk3066.h new file mode 100644 index 00000000000..d8e0812ceea --- /dev/null +++ b/arch/arm/include/asm/arch-rockchip/grf_rk3066.h @@ -0,0 +1,210 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2021 Paweł Jarosz <paweljarosz3691@gmail.com> + */ + +#ifndef _ASM_ARCH_GRF_RK3066_H +#define _ASM_ARCH_GRF_RK3066_H + +#include <linux/bitops.h> +#include <linux/bitfield.h> + +#define REG(name, h, l) \ + name##_MASK = GENMASK(h, l), \ + name##_SHIFT = __bf_shf(name##_MASK) + +struct rk3066_grf_gpio_lh { + u32 l; + u32 h; +}; + +struct rk3066_grf { + struct rk3066_grf_gpio_lh gpio_dir[7]; + struct rk3066_grf_gpio_lh gpio_do[7]; + struct rk3066_grf_gpio_lh gpio_en[7]; + + u32 gpio0a_iomux; + u32 gpio0b_iomux; + u32 gpio0c_iomux; + u32 gpio0d_iomux; + + u32 gpio1a_iomux; + u32 gpio1b_iomux; + u32 gpio1c_iomux; + u32 gpio1d_iomux; + + u32 gpio2a_iomux; + u32 gpio2b_iomux; + u32 gpio2c_iomux; + u32 gpio2d_iomux; + + u32 gpio3a_iomux; + u32 gpio3b_iomux; + u32 gpio3c_iomux; + u32 gpio3d_iomux; + + u32 gpio4a_iomux; + u32 gpio4b_iomux; + u32 gpio4c_iomux; + u32 gpio4d_iomux; + + u32 reserved0[5]; + + u32 gpio6b_iomux; + + u32 reserved1[2]; + + struct rk3066_grf_gpio_lh gpio_pull[7]; + + u32 soc_con0; + u32 soc_con1; + u32 soc_con2; + + u32 soc_status0; + + u32 dmac1_con[3]; + u32 dmac2_con[4]; + + u32 uoc0_con[3]; + u32 uoc1_con[4]; + u32 ddrc_con; + u32 ddrc_stat; + + u32 reserved2[10]; + + u32 os_reg[4]; +}; + +check_member(rk3066_grf, os_reg[3], 0x01d4); + +/* GRF_GPIO1B_IOMUX */ +enum { + REG(GPIO1B1, 2, 2), + GPIO1B1_GPIO = 0, + GPIO1B1_UART2_SOUT, + + REG(GPIO1B0, 0, 0), + GPIO1B0_GPIO = 0, + GPIO1B0_UART2_SIN +}; + +/* GRF_GPIO3B_IOMUX */ +enum { + REG(GPIO3B6, 12, 12), + GPIO3B6_GPIO = 0, + GPIO3B6_SDMMC0_DECTN, + + REG(GPIO3B5, 10, 10), + GPIO3B5_GPIO = 0, + GPIO3B5_SDMMC0_DATA3, + + REG(GPIO3B4, 8, 8), + GPIO3B4_GPIO = 0, + GPIO3B4_SDMMC0_DATA2, + + REG(GPIO3B3, 6, 6), + GPIO3B3_GPIO = 0, + GPIO3B3_SDMMC0_DATA1, + + REG(GPIO3B2, 4, 4), + GPIO3B2_GPIO = 0, + GPIO3B2_SDMMC0_DATA0, + + REG(GPIO3B1, 2, 2), + GPIO3B1_GPIO = 0, + GPIO3B1_SDMMC0_CMD, + + REG(GPIO3B0, 0, 0), + GPIO3B0_GPIO = 0, + GPIO3B0_SDMMC0_CLKOUT, +}; + +/* GRF_SOC_CON0 */ +enum { + REG(SMC_MUX_CON, 13, 13), + + REG(NOC_REMAP, 12, 12), + + REG(EMMC_FLASH_SEL, 11, 11), + + REG(TZPC_REVISION, 10, 7), + + REG(L2CACHE_ACC, 6, 5), + + REG(L2RD_WAIT, 4, 3), + + REG(IMEMRD_WAIT, 2, 1), + + REG(SOC_REMAP, 0, 0), +}; + +/* GRF_SOC_CON1 */ +enum { + REG(RKI2C4_SEL, 15, 15), + + REG(RKI2C3_SEL, 14, 14), + + REG(RKI2C2_SEL, 13, 13), + + REG(RKI2C1_SEL, 12, 12), + + REG(RKI2C0_SEL, 11, 11), + + REG(VCODEC_SEL, 10, 10), + + REG(PERI_EMEM_PAUSE, 9, 9), + + REG(PERI_USB_PAUSE, 8, 8), + + REG(SMC_MUX_MODE_0, 6, 6), + + REG(SMC_SRAM_MW_0, 5, 4), + + REG(SMC_REMAP_0, 3, 3), + + REG(SMC_A_GT_M0_SYNC, 2, 2), + + REG(EMAC_SPEED, 1, 1), + + REG(EMAC_MODE, 0, 0), +}; + +/* GRF_SOC_CON2 */ +enum { + REG(MSCH4_MAINDDR3, 7, 7), + MSCH4_MAINDDR3_DDR3 = 1, + + REG(EMAC_NEWRCV_EN, 6, 6), + + REG(SW_ADDR15_EN, 5, 5), + + REG(SW_ADDR16_EN, 4, 4), + + REG(SW_ADDR17_EN, 3, 3), + + REG(BANK2_TO_RANK_EN, 2, 2), + + REG(RANK_TO_ROW15_EN, 1, 1), + + REG(UPCTL_C_ACTIVE_IN, 0, 0), + UPCTL_C_ACTIVE_IN_MAY = 0, + UPCTL_C_ACTIVE_IN_WILL, +}; + +/* GRF_DDRC_CON0 */ +enum { + REG(DTO_LB, 12, 11), + + REG(DTO_TE, 10, 9), + + REG(DTO_PDR, 8, 7), + + REG(DTO_PDD, 6, 5), + + REG(DTO_IOM, 4, 3), + + REG(DTO_OE, 2, 1), + + REG(ATO_AE, 0, 0), +}; +#endif diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index 308dc09b038..18aff5480ba 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -35,6 +35,28 @@ config ROCKCHIP_RK3036 and video codec support. Peripherals include Gigabit Ethernet, USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs. +config ROCKCHIP_RK3066 + bool "Support Rockchip RK3066" + select CPU_V7A + select SPL_BOARD_INIT if SPL + select SUPPORT_SPL + select SUPPORT_TPL + select SPL + select TPL + select TPL_ROCKCHIP_BACK_TO_BROM + select TPL_ROCKCHIP_EARLYRETURN_TO_BROM + imply ROCKCHIP_COMMON_BOARD + imply SPL_ROCKCHIP_COMMON_BOARD + imply SPL_SERIAL + imply TPL_ROCKCHIP_COMMON_BOARD + imply TPL_SERIAL + help + The Rockchip RK3066 is a ARM-based SoC with a dual-core Cortex-A9 + including NEON and GPU, 512KB L2 cache, Mali-400 graphics, two + video interfaces, several memory options and video codec support. + Peripherals include Fast Ethernet, USB2 host and OTG, SDIO, I2S, + UART, SPI, I2C and PWMs. + config ROCKCHIP_RK3128 bool "Support Rockchip RK3128" select CPU_V7A @@ -339,6 +361,16 @@ config ROCKCHIP_BOOT_MODE_REG The Soc will enter to different boot mode(defined in asm/arch-rockchip/boot_mode.h) according to the value from this register. +config ROCKCHIP_STIMER + bool "Rockchip STIMER support" + default y + help + Enable Rockchip STIMER support. + +config ROCKCHIP_STIMER_BASE + hex + depends on ROCKCHIP_STIMER + config ROCKCHIP_SPL_RESERVE_IRAM hex "Size of IRAM reserved in SPL" default 0 @@ -395,6 +427,7 @@ config LNX_KRNL_IMG_TEXT_OFFSET_BASE source "arch/arm/mach-rockchip/px30/Kconfig" source "arch/arm/mach-rockchip/rk3036/Kconfig" +source "arch/arm/mach-rockchip/rk3066/Kconfig" source "arch/arm/mach-rockchip/rk3128/Kconfig" source "arch/arm/mach-rockchip/rk3188/Kconfig" source "arch/arm/mach-rockchip/rk322x/Kconfig" diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile index 00aef0ecee6..6c1c7b8a108 100644 --- a/arch/arm/mach-rockchip/Makefile +++ b/arch/arm/mach-rockchip/Makefile @@ -34,6 +34,7 @@ obj-$(CONFIG_$(SPL_TPL_)RAM) += sdram.o obj-$(CONFIG_ROCKCHIP_PX30) += px30/ obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036/ +obj-$(CONFIG_ROCKCHIP_RK3066) += rk3066/ obj-$(CONFIG_ROCKCHIP_RK3128) += rk3128/ obj-$(CONFIG_ROCKCHIP_RK3188) += rk3188/ obj-$(CONFIG_ROCKCHIP_RK322X) += rk322x/ diff --git a/arch/arm/mach-rockchip/px30/Kconfig b/arch/arm/mach-rockchip/px30/Kconfig index 145bf3591ff..4886fe946e3 100644 --- a/arch/arm/mach-rockchip/px30/Kconfig +++ b/arch/arm/mach-rockchip/px30/Kconfig @@ -38,6 +38,9 @@ config TARGET_PX30_CORE config ROCKCHIP_BOOT_MODE_REG default 0xff010200 +config ROCKCHIP_STIMER_BASE + default 0xff220020 + config SYS_SOC default "px30" diff --git a/arch/arm/mach-rockchip/rk3036/Kconfig b/arch/arm/mach-rockchip/rk3036/Kconfig index b746795d813..111531be1ef 100644 --- a/arch/arm/mach-rockchip/rk3036/Kconfig +++ b/arch/arm/mach-rockchip/rk3036/Kconfig @@ -16,6 +16,9 @@ endchoice config ROCKCHIP_BOOT_MODE_REG default 0x200081c8 +config ROCKCHIP_STIMER_BASE + default 0x200440a0 + config SYS_SOC default "rk3036" diff --git a/arch/arm/mach-rockchip/rk3066/Kconfig b/arch/arm/mach-rockchip/rk3066/Kconfig new file mode 100644 index 00000000000..95d7fc8a291 --- /dev/null +++ b/arch/arm/mach-rockchip/rk3066/Kconfig @@ -0,0 +1,39 @@ +if ROCKCHIP_RK3066 + +config TARGET_MK808 + bool "MK808" + help + MK808 is a RK3066-based board with 1 USB host and 1 USB OTG port, + HDMI and a micro-SD card slot. It also includes on-board NAND + and 1GB of SDRAM. + +config ROCKCHIP_BOOT_MODE_REG + default 0x20004040 + +config SYS_SOC + default "rk3066" + +config SYS_MALLOC_F_LEN + default 0x0800 + +config SPL_LIBCOMMON_SUPPORT + default y + +config SPL_LIBGENERIC_SUPPORT + default y + +config SPL_SERIAL + default y + +config TPL_LIBCOMMON_SUPPORT + default y + +config TPL_LIBGENERIC_SUPPORT + default y + +config TPL_SERIAL + default y + +source "board/rikomagic/mk808/Kconfig" + +endif diff --git a/arch/arm/mach-rockchip/rk3066/Makefile b/arch/arm/mach-rockchip/rk3066/Makefile new file mode 100644 index 00000000000..9e2a9d4b0aa --- /dev/null +++ b/arch/arm/mach-rockchip/rk3066/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0+ + +obj-y += clk_rk3066.o +obj-y += rk3066.o +obj-y += syscon_rk3066.o diff --git a/arch/arm/mach-rockchip/rk3066/clk_rk3066.c b/arch/arm/mach-rockchip/rk3066/clk_rk3066.c new file mode 100644 index 00000000000..c47526dca5d --- /dev/null +++ b/arch/arm/mach-rockchip/rk3066/clk_rk3066.c @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2015 Google, Inc + * Written by Simon Glass <sjg@chromium.org> + */ + +#include <common.h> +#include <dm.h> +#include <syscon.h> +#include <asm/arch-rockchip/clock.h> +#include <asm/arch-rockchip/cru_rk3066.h> +#include <linux/err.h> + +int rockchip_get_clk(struct udevice **devp) +{ + return uclass_get_device_by_driver(UCLASS_CLK, + DM_DRIVER_GET(rockchip_rk3066a_cru), devp); +} + +void *rockchip_get_cru(void) +{ + struct rk3066_clk_priv *priv; + struct udevice *dev; + int ret; + + ret = rockchip_get_clk(&dev); + if (ret) + return ERR_PTR(ret); + + priv = dev_get_priv(dev); + + return priv->cru; +} diff --git a/arch/arm/mach-rockchip/rk3066/rk3066.c b/arch/arm/mach-rockchip/rk3066/rk3066.c new file mode 100644 index 00000000000..78c7d894f90 --- /dev/null +++ b/arch/arm/mach-rockchip/rk3066/rk3066.c @@ -0,0 +1,49 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2016 Rockchip Electronics Co., Ltd + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch-rockchip/bootrom.h> +#include <asm/arch-rockchip/grf_rk3066.h> + +#define GRF_BASE 0x20008000 + +const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = { + [BROM_BOOTSOURCE_EMMC] = "/mmc@1021c000", + [BROM_BOOTSOURCE_SD] = "/mmc@10214000", +}; + +void board_debug_uart_init(void) +{ + struct rk3066_grf * const grf = (void *)GRF_BASE; + + /* Enable early UART on the RK3066 */ + rk_clrsetreg(&grf->gpio1b_iomux, + GPIO1B1_MASK | GPIO1B0_MASK, + GPIO1B1_UART2_SOUT << GPIO1B1_SHIFT | + GPIO1B0_UART2_SIN << GPIO1B0_SHIFT); +} + +void spl_board_init(void) +{ + if (!IS_ENABLED(CONFIG_SPL_BUILD)) + return; + + if (IS_ENABLED(CONFIG_SPL_DM_MMC)) { + struct rk3066_grf * const grf = (void *)GRF_BASE; + + rk_clrsetreg(&grf->gpio3b_iomux, + GPIO3B0_MASK | GPIO3B1_MASK | GPIO3B2_MASK | + GPIO3B3_MASK | GPIO3B4_MASK | GPIO3B5_MASK | + GPIO3B6_MASK, + GPIO3B0_SDMMC0_CLKOUT << GPIO3B0_SHIFT | + GPIO3B1_SDMMC0_CMD << GPIO3B1_SHIFT | + GPIO3B2_SDMMC0_DATA0 << GPIO3B2_SHIFT | + GPIO3B3_SDMMC0_DATA1 << GPIO3B3_SHIFT | + GPIO3B4_SDMMC0_DATA2 << GPIO3B4_SHIFT | + GPIO3B5_SDMMC0_DATA3 << GPIO3B5_SHIFT | + GPIO3B6_SDMMC0_DECTN << GPIO3B6_SHIFT); + } +} diff --git a/arch/arm/mach-rockchip/rk3066/syscon_rk3066.c b/arch/arm/mach-rockchip/rk3066/syscon_rk3066.c new file mode 100644 index 00000000000..a598f6400de --- /dev/null +++ b/arch/arm/mach-rockchip/rk3066/syscon_rk3066.c @@ -0,0 +1,55 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2015 Google, Inc + * Written by Simon Glass <sjg@chromium.org> + */ + +#include <common.h> +#include <dm.h> +#include <log.h> +#include <syscon.h> +#include <asm/arch-rockchip/clock.h> + +static const struct udevice_id rk3066_syscon_ids[] = { + { .compatible = "rockchip,rk3066-noc", .data = ROCKCHIP_SYSCON_NOC }, + { .compatible = "rockchip,rk3066-grf", .data = ROCKCHIP_SYSCON_GRF }, + { .compatible = "rockchip,rk3066-pmu", .data = ROCKCHIP_SYSCON_PMU }, + { } +}; + +U_BOOT_DRIVER(syscon_rk3066) = { + .name = "rk3066_syscon", + .id = UCLASS_SYSCON, + .of_match = rk3066_syscon_ids, +}; + +#if CONFIG_IS_ENABLED(OF_PLATDATA) +static int rk3066_syscon_bind_of_plat(struct udevice *dev) +{ + dev->driver_data = dev->driver->of_match->data; + debug("syscon: %s %d\n", dev->name, (uint)dev->driver_data); + + return 0; +} + +U_BOOT_DRIVER(rockchip_rk3066_noc) = { + .name = "rockchip_rk3066_noc", + .id = UCLASS_SYSCON, + .of_match = rk3066_syscon_ids, + .bind = rk3066_syscon_bind_of_plat, +}; + +U_BOOT_DRIVER(rockchip_rk3066_grf) = { + .name = "rockchip_rk3066_grf", + .id = UCLASS_SYSCON, + .of_match = rk3066_syscon_ids + 1, + .bind = rk3066_syscon_bind_of_plat, +}; + +U_BOOT_DRIVER(rockchip_rk3066_pmu) = { + .name = "rockchip_rk3066_pmu", + .id = UCLASS_SYSCON, + .of_match = rk3066_syscon_ids + 2, + .bind = rk3066_syscon_bind_of_plat, +}; +#endif diff --git a/arch/arm/mach-rockchip/rk3128/Kconfig b/arch/arm/mach-rockchip/rk3128/Kconfig index b867401c7f5..9cc494eb409 100644 --- a/arch/arm/mach-rockchip/rk3128/Kconfig +++ b/arch/arm/mach-rockchip/rk3128/Kconfig @@ -16,6 +16,9 @@ endchoice config ROCKCHIP_BOOT_MODE_REG default 0x100a0038 +config ROCKCHIP_STIMER_BASE + default 0x200440a0 + config SYS_SOC default "rk3128" diff --git a/arch/arm/mach-rockchip/rk3188/rk3188.c b/arch/arm/mach-rockchip/rk3188/rk3188.c index 5a02914e1b0..df8fa1566f0 100644 --- a/arch/arm/mach-rockchip/rk3188/rk3188.c +++ b/arch/arm/mach-rockchip/rk3188/rk3188.c @@ -21,8 +21,8 @@ #define GRF_BASE 0x20008000 const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = { - [BROM_BOOTSOURCE_EMMC] = "/dwmmc@1021c000", - [BROM_BOOTSOURCE_SD] = "/dwmmc@10214000", + [BROM_BOOTSOURCE_EMMC] = "/mmc@1021c000", + [BROM_BOOTSOURCE_SD] = "/mmc@10214000", }; #ifdef CONFIG_DEBUG_UART_BOARD_INIT diff --git a/arch/arm/mach-rockchip/rk322x/Kconfig b/arch/arm/mach-rockchip/rk322x/Kconfig index 6458cd55814..058f848ddc7 100644 --- a/arch/arm/mach-rockchip/rk322x/Kconfig +++ b/arch/arm/mach-rockchip/rk322x/Kconfig @@ -8,6 +8,9 @@ config TARGET_EVB_RK3229 config ROCKCHIP_BOOT_MODE_REG default 0x110005c8 +config ROCKCHIP_STIMER_BASE + default 0x110d0020 + config SYS_SOC default "rk322x" diff --git a/arch/arm/mach-rockchip/rk322x/rk322x.c b/arch/arm/mach-rockchip/rk322x/rk322x.c index ad4ac62e514..a304795fec6 100644 --- a/arch/arm/mach-rockchip/rk322x/rk322x.c +++ b/arch/arm/mach-rockchip/rk322x/rk322x.c @@ -9,8 +9,8 @@ #include <asm/arch-rockchip/hardware.h> const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = { - [BROM_BOOTSOURCE_EMMC] = "/dwmmc@30020000", - [BROM_BOOTSOURCE_SD] = "/dwmmc@30000000", + [BROM_BOOTSOURCE_EMMC] = "/mmc@30020000", + [BROM_BOOTSOURCE_SD] = "/mmc@30000000", }; #ifdef CONFIG_DEBUG_UART_BOARD_INIT diff --git a/arch/arm/mach-rockchip/rk3288/Kconfig b/arch/arm/mach-rockchip/rk3288/Kconfig index f37b1bdfd50..dd8c7826fc1 100644 --- a/arch/arm/mach-rockchip/rk3288/Kconfig +++ b/arch/arm/mach-rockchip/rk3288/Kconfig @@ -148,6 +148,9 @@ config ROCKCHIP_FAST_SPL config ROCKCHIP_BOOT_MODE_REG default 0xff730094 +config ROCKCHIP_STIMER_BASE + default 0xff810020 + config SYS_SOC default "rk3288" diff --git a/arch/arm/mach-rockchip/rk3288/rk3288.c b/arch/arm/mach-rockchip/rk3288/rk3288.c index bc20bc5ab90..3ad2887575d 100644 --- a/arch/arm/mach-rockchip/rk3288/rk3288.c +++ b/arch/arm/mach-rockchip/rk3288/rk3288.c @@ -28,8 +28,8 @@ DECLARE_GLOBAL_DATA_PTR; #define GRF_BASE 0xff770000 const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = { - [BROM_BOOTSOURCE_EMMC] = "/dwmmc@ff0f0000", - [BROM_BOOTSOURCE_SD] = "/dwmmc@ff0c0000", + [BROM_BOOTSOURCE_EMMC] = "/mmc@ff0f0000", + [BROM_BOOTSOURCE_SD] = "/mmc@ff0c0000", }; #ifdef CONFIG_SPL_BUILD diff --git a/arch/arm/mach-rockchip/rk3308/Kconfig b/arch/arm/mach-rockchip/rk3308/Kconfig index 8fa536e15dc..194353e4cd9 100644 --- a/arch/arm/mach-rockchip/rk3308/Kconfig +++ b/arch/arm/mach-rockchip/rk3308/Kconfig @@ -8,6 +8,12 @@ config TARGET_ROC_RK3308_CC bool "Firefly roc-rk3308-cc" select BOARD_LATE_INIT +config ROCKCHIP_BOOT_MODE_REG + default 0xff000500 + +config ROCKCHIP_STIMER_BASE + default 0xff1b00a0 + config SYS_SOC default "rk3308" @@ -17,10 +23,6 @@ config SYS_MALLOC_F_LEN config SPL_SERIAL default y -config ROCKCHIP_BOOT_MODE_REG - default 0xff000500 - - source "board/rockchip/evb_rk3308/Kconfig" source "board/firefly/firefly-rk3308/Kconfig" diff --git a/arch/arm/mach-rockchip/rk3328/Kconfig b/arch/arm/mach-rockchip/rk3328/Kconfig index d13a1690226..f6f1e06a83f 100644 --- a/arch/arm/mach-rockchip/rk3328/Kconfig +++ b/arch/arm/mach-rockchip/rk3328/Kconfig @@ -15,6 +15,9 @@ endchoice config ROCKCHIP_BOOT_MODE_REG default 0xff1005c8 +config ROCKCHIP_STIMER_BASE + default 0xff1d0020 + config SYS_SOC default "rk3328" diff --git a/arch/arm/mach-rockchip/rk3328/rk3328.c b/arch/arm/mach-rockchip/rk3328/rk3328.c index ec3336cb49a..de17b886827 100644 --- a/arch/arm/mach-rockchip/rk3328/rk3328.c +++ b/arch/arm/mach-rockchip/rk3328/rk3328.c @@ -21,8 +21,8 @@ DECLARE_GLOBAL_DATA_PTR; #define FW_DDR_CON_REG 0xFF7C0040 const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = { - [BROM_BOOTSOURCE_EMMC] = "/rksdmmc@ff520000", - [BROM_BOOTSOURCE_SD] = "/rksdmmc@ff500000", + [BROM_BOOTSOURCE_EMMC] = "/mmc@ff520000", + [BROM_BOOTSOURCE_SD] = "/mmc@ff500000", }; static struct mm_region rk3328_mem_map[] = { diff --git a/arch/arm/mach-rockchip/rk3368/Kconfig b/arch/arm/mach-rockchip/rk3368/Kconfig index 78eb96df3d1..104db36737b 100644 --- a/arch/arm/mach-rockchip/rk3368/Kconfig +++ b/arch/arm/mach-rockchip/rk3368/Kconfig @@ -45,6 +45,9 @@ endchoice config ROCKCHIP_BOOT_MODE_REG default 0xff738200 +config ROCKCHIP_STIMER_BASE + default 0xff830020 + config SYS_SOC default "rk3368" diff --git a/arch/arm/mach-rockchip/rk3368/rk3368.c b/arch/arm/mach-rockchip/rk3368/rk3368.c index 9b7132d471c..d0a6107e5e0 100644 --- a/arch/arm/mach-rockchip/rk3368/rk3368.c +++ b/arch/arm/mach-rockchip/rk3368/rk3368.c @@ -58,8 +58,8 @@ static struct mm_region rk3368_mem_map[] = { struct mm_region *mem_map = rk3368_mem_map; const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = { - [BROM_BOOTSOURCE_EMMC] = "/dwmmc@ff0f0000", - [BROM_BOOTSOURCE_SD] = "/dwmmc@ff0c0000", + [BROM_BOOTSOURCE_EMMC] = "/mmc@ff0f0000", + [BROM_BOOTSOURCE_SD] = "/mmc@ff0c0000", }; #ifdef CONFIG_ARCH_EARLY_INIT_R diff --git a/arch/arm/mach-rockchip/rk3399/Kconfig b/arch/arm/mach-rockchip/rk3399/Kconfig index 0833e083d9e..c1f251316cb 100644 --- a/arch/arm/mach-rockchip/rk3399/Kconfig +++ b/arch/arm/mach-rockchip/rk3399/Kconfig @@ -125,6 +125,9 @@ endchoice config ROCKCHIP_BOOT_MODE_REG default 0xff320300 +config ROCKCHIP_STIMER_BASE + default 0xff8680a0 + config SYS_SOC default "rk3399" diff --git a/arch/arm/mach-rockchip/rk3568/Kconfig b/arch/arm/mach-rockchip/rk3568/Kconfig index 201c63c2a9c..4e7c02cce06 100644 --- a/arch/arm/mach-rockchip/rk3568/Kconfig +++ b/arch/arm/mach-rockchip/rk3568/Kconfig @@ -9,6 +9,9 @@ config TARGET_EVB_RK3568 config ROCKCHIP_BOOT_MODE_REG default 0xfdc20200 +config ROCKCHIP_STIMER_BASE + default 0xfdd1c020 + config SYS_SOC default "rk3568" diff --git a/arch/arm/mach-rockchip/spl.c b/arch/arm/mach-rockchip/spl.c index d51a0727b47..eda2248029d 100644 --- a/arch/arm/mach-rockchip/spl.c +++ b/arch/arm/mach-rockchip/spl.c @@ -71,7 +71,6 @@ u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device) return MMCSD_MODE_RAW; } -#if !defined(CONFIG_ROCKCHIP_RK3188) #define TIMER_LOAD_COUNT_L 0x00 #define TIMER_LOAD_COUNT_H 0x04 #define TIMER_CONTROL_REG 0x10 @@ -81,6 +80,7 @@ u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device) __weak void rockchip_stimer_init(void) { +#if defined(CONFIG_ROCKCHIP_STIMER_BASE) /* If Timer already enabled, don't re-init it */ u32 reg = readl(CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG); @@ -95,8 +95,8 @@ __weak void rockchip_stimer_init(void) writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 4); writel(TIMER_EN | TIMER_FMODE, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG); -} #endif +} __weak int board_early_init_f(void) { @@ -133,9 +133,9 @@ void board_init_f(ulong dummy) hang(); } arch_cpu_init(); -#if !defined(CONFIG_ROCKCHIP_RK3188) + rockchip_stimer_init(); -#endif + #ifdef CONFIG_SYS_ARCH_TIMER /* Init ARM arch timer in arch/arm/cpu/armv7/arch_timer.c */ timer_init(); diff --git a/arch/arm/mach-rockchip/tpl.c b/arch/arm/mach-rockchip/tpl.c index 3c007bb4508..8126587060f 100644 --- a/arch/arm/mach-rockchip/tpl.c +++ b/arch/arm/mach-rockchip/tpl.c @@ -15,6 +15,7 @@ #include <asm/io.h> #include <asm/arch-rockchip/bootrom.h> #include <linux/bitops.h> +#include <linux/kconfig.h> #if CONFIG_IS_ENABLED(BANNER_PRINT) #include <timestamp.h> @@ -29,6 +30,7 @@ __weak void rockchip_stimer_init(void) { +#if defined(CONFIG_ROCKCHIP_STIMER_BASE) /* If Timer already enabled, don't re-init it */ u32 reg = readl(CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG); @@ -45,6 +47,7 @@ __weak void rockchip_stimer_init(void) writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 4); writel(TIMER_EN | TIMER_FMODE, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG); +#endif } void board_init_f(ulong dummy) @@ -75,8 +78,10 @@ void board_init_f(ulong dummy) /* Init secure timer */ rockchip_stimer_init(); - /* Init ARM arch timer in arch/arm/cpu/ */ - timer_init(); + + /* Init ARM arch timer */ + if (IS_ENABLED(CONFIG_SYS_ARCH_TIMER)) + timer_init(); ret = uclass_get_device(UCLASS_RAM, 0, &dev); if (ret) { |