diff options
Diffstat (limited to 'board/renesas')
| -rw-r--r-- | board/renesas/common/Makefile | 8 | ||||
| -rw-r--r-- | board/renesas/common/rza1-common.c | 27 | ||||
| -rw-r--r-- | board/renesas/common/rza1-lowlevel_init.S (renamed from board/renesas/grpeach/lowlevel_init.S) | 0 | ||||
| -rw-r--r-- | board/renesas/genmai/Kconfig | 12 | ||||
| -rw-r--r-- | board/renesas/genmai/MAINTAINERS | 5 | ||||
| -rw-r--r-- | board/renesas/genmai/Makefile | 7 | ||||
| -rw-r--r-- | board/renesas/genmai/genmai.c | 49 | ||||
| -rw-r--r-- | board/renesas/grpeach/Makefile | 1 | ||||
| -rw-r--r-- | board/renesas/grpeach/grpeach.c | 22 |
9 files changed, 108 insertions, 23 deletions
diff --git a/board/renesas/common/Makefile b/board/renesas/common/Makefile index 5e51b691178..1849c995aee 100644 --- a/board/renesas/common/Makefile +++ b/board/renesas/common/Makefile @@ -5,6 +5,7 @@ # # R-Car SoCs +ifndef CONFIG_RZA1 ifndef CONFIG_RZG2L # 32 bit SoCs @@ -45,3 +46,10 @@ endif endif endif +endif + +# RZ/A1 SoCs +ifdef CONFIG_RZA1 +obj-y += rza1-common.o +obj-y += rza1-lowlevel_init.o +endif diff --git a/board/renesas/common/rza1-common.c b/board/renesas/common/rza1-common.c new file mode 100644 index 00000000000..5027319a58a --- /dev/null +++ b/board/renesas/common/rza1-common.c @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2017 Renesas Electronics + * Copyright (C) Chris Brandt + */ + +#include <init.h> +#include <asm/io.h> + +#define RZA1_WDT_BASE 0xfcfe0000 +#define WTCSR 0x00 +#define WTCNT 0x02 +#define WRCSR 0x04 + +void __weak reset_cpu(void) +{ + /* Dummy read (must read WRCSR:WOVF at least once before clearing) */ + readb(RZA1_WDT_BASE + WRCSR); + + writew(0xa500, RZA1_WDT_BASE + WRCSR); + writew(0x5a5f, RZA1_WDT_BASE + WRCSR); + writew(0x5a00, RZA1_WDT_BASE + WTCNT); + writew(0xa578, RZA1_WDT_BASE + WTCSR); + + for (;;) + asm volatile("wfi"); +} diff --git a/board/renesas/grpeach/lowlevel_init.S b/board/renesas/common/rza1-lowlevel_init.S index b83c4e86867..b83c4e86867 100644 --- a/board/renesas/grpeach/lowlevel_init.S +++ b/board/renesas/common/rza1-lowlevel_init.S diff --git a/board/renesas/genmai/Kconfig b/board/renesas/genmai/Kconfig new file mode 100644 index 00000000000..4e67a9b325a --- /dev/null +++ b/board/renesas/genmai/Kconfig @@ -0,0 +1,12 @@ +if TARGET_GENMAI + +config SYS_BOARD + default "genmai" + +config SYS_VENDOR + default "renesas" + +config SYS_CONFIG_NAME + default "genmai" + +endif diff --git a/board/renesas/genmai/MAINTAINERS b/board/renesas/genmai/MAINTAINERS new file mode 100644 index 00000000000..1f1c2944632 --- /dev/null +++ b/board/renesas/genmai/MAINTAINERS @@ -0,0 +1,5 @@ +GENMAI BOARD +M: Magnus Damm <damm@opensource.se> +S: Maintained +F: arch/arm/dts/r7s72100* +N: genmai diff --git a/board/renesas/genmai/Makefile b/board/renesas/genmai/Makefile new file mode 100644 index 00000000000..73f5e45affd --- /dev/null +++ b/board/renesas/genmai/Makefile @@ -0,0 +1,7 @@ +# +# Copyright (C) 2025 Magnus Damm <damm@opensource.se> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := genmai.o diff --git a/board/renesas/genmai/genmai.c b/board/renesas/genmai/genmai.c new file mode 100644 index 00000000000..8153aed15e3 --- /dev/null +++ b/board/renesas/genmai/genmai.c @@ -0,0 +1,49 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2025 Magnus Damm <damm@opensource.se> + */ + +#include <init.h> +#include <asm/global_data.h> +#include <asm/io.h> + +#define RZA1_BCR_BASE 0x3FFFC000 +#define CS0BCR (RZA1_BCR_BASE + 0x04) +#define CS0WCR (RZA1_BCR_BASE + 0x28) +#define CS1BCR (RZA1_BCR_BASE + 0x08) +#define CS1WCR (RZA1_BCR_BASE + 0x2c) + +DECLARE_GLOBAL_DATA_PTR; + +int board_init(void) +{ + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; + + /* setup NOR Flash on CS0 and CS1 */ + writel(0x00000b40, CS0WCR); + writel(0x10000c00, CS0BCR); + writel(0x00000b40, CS1WCR); + writel(0x10000c00, CS1BCR); + return 0; +} + +/* + * The Genmai DT will most likely contain memory nodes describing the external + * SDRAM memory connected to CS2 and CS3, however we do not yet have any code + * in U-Boot to setup the memory controller. For now ignore DT and make use of + * the RZ/A1H on-chip memory which is 10 MiB at CFG_SYS_SDRAM_BASE. + */ + +int dram_init(void) +{ + gd->ram_base = CFG_SYS_SDRAM_BASE; + gd->ram_size = 10 << 20; + return 0; +} + +int dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = gd->ram_base; + gd->bd->bi_dram[0].size = gd->ram_size; + return 0; +} diff --git a/board/renesas/grpeach/Makefile b/board/renesas/grpeach/Makefile index 48e185ce3e8..89f8e0e8544 100644 --- a/board/renesas/grpeach/Makefile +++ b/board/renesas/grpeach/Makefile @@ -5,4 +5,3 @@ # SPDX-License-Identifier: GPL-2.0+ obj-y := grpeach.o -obj-y += lowlevel_init.o diff --git a/board/renesas/grpeach/grpeach.c b/board/renesas/grpeach/grpeach.c index 88f65c3b6a0..3a6393fdce1 100644 --- a/board/renesas/grpeach/grpeach.c +++ b/board/renesas/grpeach/grpeach.c @@ -4,17 +4,9 @@ * Copyright (C) Chris Brandt */ -#include <cpu_func.h> #include <errno.h> #include <init.h> #include <asm/global_data.h> -#include <asm/io.h> -#include <asm/arch/sys_proto.h> - -#define RZA1_WDT_BASE 0xfcfe0000 -#define WTCSR 0x00 -#define WTCNT 0x02 -#define WRCSR 0x04 DECLARE_GLOBAL_DATA_PTR; @@ -39,17 +31,3 @@ int dram_init_banksize(void) return 0; } - -void reset_cpu(void) -{ - /* Dummy read (must read WRCSR:WOVF at least once before clearing) */ - readb(RZA1_WDT_BASE + WRCSR); - - writew(0xa500, RZA1_WDT_BASE + WRCSR); - writew(0x5a5f, RZA1_WDT_BASE + WRCSR); - writew(0x5a00, RZA1_WDT_BASE + WTCNT); - writew(0xa578, RZA1_WDT_BASE + WTCSR); - - for (;;) - asm volatile("wfi"); -} |