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-rw-r--r--board/udoo/udoo.c8
-rw-r--r--board/udoo/udoo_spl.c35
2 files changed, 43 insertions, 0 deletions
diff --git a/board/udoo/udoo.c b/board/udoo/udoo.c
index 5c49388cbfb..9e0365615d6 100644
--- a/board/udoo/udoo.c
+++ b/board/udoo/udoo.c
@@ -90,6 +90,14 @@ int mx6_rgmii_rework(struct phy_device *phydev)
static void setup_iomux_enet(void)
{
+ gpio_request(IMX_GPIO_NR(2, 31), "eth_power");
+ gpio_request(IMX_GPIO_NR(3, 23), "eth_phy_reset");
+ gpio_request(IMX_GPIO_NR(6, 24), "strap1");
+ gpio_request(IMX_GPIO_NR(6, 25), "strap2");
+ gpio_request(IMX_GPIO_NR(6, 27), "strap3");
+ gpio_request(IMX_GPIO_NR(6, 28), "strap4");
+ gpio_request(IMX_GPIO_NR(6, 29), "strap5");
+
gpio_direction_output(IMX_GPIO_NR(2, 31), 1); /* Power supply on */
gpio_direction_output(IMX_GPIO_NR(3, 23), 0); /* assert PHY rst */
diff --git a/board/udoo/udoo_spl.c b/board/udoo/udoo_spl.c
index d9afbbb7419..647380e1db6 100644
--- a/board/udoo/udoo_spl.c
+++ b/board/udoo/udoo_spl.c
@@ -254,4 +254,39 @@ void board_init_f(ulong dummy)
/* DDR initialization */
spl_dram_init();
}
+
+#define USDHC3_CD_GPIO IMX_GPIO_NR(7, 0)
+
+#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
+ PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
+ PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+static struct fsl_esdhc_cfg usdhc_cfg[2] = {
+ {USDHC3_BASE_ADDR},
+};
+
+static const iomux_v3_cfg_t usdhc3_pads[] = {
+ IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+ return !gpio_get_value(USDHC3_CD_GPIO);
+}
+
+int board_mmc_init(struct bd_info *bis)
+{
+ SETUP_IOMUX_PADS(usdhc3_pads);
+ usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+ usdhc_cfg[0].max_bus_width = 4;
+ gpio_direction_input(USDHC3_CD_GPIO);
+
+ return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
+}
#endif