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-rw-r--r--board/atmel/sama7d65_curiosity/Kconfig15
-rw-r--r--board/atmel/sama7d65_curiosity/MAINTAINERS6
-rw-r--r--board/atmel/sama7d65_curiosity/Makefile7
-rw-r--r--board/atmel/sama7d65_curiosity/sama7d65_curiosity.c75
-rw-r--r--board/samsung/e850-96/e850-96.c77
-rw-r--r--board/samsung/e850-96/e850-96.env44
-rw-r--r--board/st/common/Kconfig2
-rw-r--r--board/st/common/stpmic1.c51
-rw-r--r--board/st/stm32mp1/debug_uart.c21
-rw-r--r--board/st/stm32mp2/Kconfig14
-rw-r--r--board/sunxi/MAINTAINERS15
-rw-r--r--board/sunxi/board.c7
12 files changed, 312 insertions, 22 deletions
diff --git a/board/atmel/sama7d65_curiosity/Kconfig b/board/atmel/sama7d65_curiosity/Kconfig
new file mode 100644
index 00000000000..21ff432f2c1
--- /dev/null
+++ b/board/atmel/sama7d65_curiosity/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_SAMA7D65_CURIOSITY
+
+config SYS_BOARD
+ default "sama7d65_curiosity"
+
+config SYS_VENDOR
+ default "atmel"
+
+config SYS_SOC
+ default "at91"
+
+config SYS_CONFIG_NAME
+ default "sama7d65_curiosity"
+
+endif
diff --git a/board/atmel/sama7d65_curiosity/MAINTAINERS b/board/atmel/sama7d65_curiosity/MAINTAINERS
new file mode 100644
index 00000000000..054af3c6541
--- /dev/null
+++ b/board/atmel/sama7d65_curiosity/MAINTAINERS
@@ -0,0 +1,6 @@
+SAMA7D65 CURIOSITY BOARD
+M: Ryan Wanner <ryan.wanner@microchip.com>
+S: Maintained
+F: board/atmel/sama7d65_curiosity.c
+F: include/configs/sama7d65_curiosity.h
+F: configs/sama7d65_curiosity_mmc1_defconfig
diff --git a/board/atmel/sama7d65_curiosity/Makefile b/board/atmel/sama7d65_curiosity/Makefile
new file mode 100644
index 00000000000..56d011d1d81
--- /dev/null
+++ b/board/atmel/sama7d65_curiosity/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
+#
+# Author: Ryan Wanner <ryan.wanner@microchip.com>
+
+obj-y += sama7d65_curiosity.o
diff --git a/board/atmel/sama7d65_curiosity/sama7d65_curiosity.c b/board/atmel/sama7d65_curiosity/sama7d65_curiosity.c
new file mode 100644
index 00000000000..713b1b9d959
--- /dev/null
+++ b/board/atmel/sama7d65_curiosity/sama7d65_curiosity.c
@@ -0,0 +1,75 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2024 Microchip Technology, Inc. and its subsidiaries
+ *
+ * Author: Ryan Wanner <ryan.wanner@microchip.com>
+ *
+ */
+
+#include <debug_uart.h>
+#include <init.h>
+#include <fdtdec.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/atmel_pio4.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/sama7d65.h>
+#include <asm/mach-types.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void board_leds_init(void)
+{
+ atmel_pio4_set_pio_output(AT91_PIO_PORTA, 21, 0); /* LED BLUE */
+ atmel_pio4_set_pio_output(AT91_PIO_PORTB, 17, 0); /* LED RED */
+ atmel_pio4_set_pio_output(AT91_PIO_PORTB, 15, 1); /* LED GREEN */
+}
+
+int board_late_init(void)
+{
+ return 0;
+}
+
+#if (IS_ENABLED(CONFIG_DEBUG_UART_BOARD_INIT))
+static void board_uart0_hw_init(void)
+{
+ /* FLEXCOM6 IO0 */
+ atmel_pio4_set_b_periph(AT91_PIO_PORTD, 18, 0);
+ /* FLEXCOM6 IO1 */
+ atmel_pio4_set_b_periph(AT91_PIO_PORTD, 19, 0);
+
+ at91_periph_clk_enable(ATMEL_ID_FLEXCOM6);
+}
+
+void board_debug_uart_init(void)
+{
+ board_uart0_hw_init();
+}
+#endif
+
+int board_early_init_f(void)
+{
+ return 0;
+}
+
+int board_init(void)
+{
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100;
+
+ board_leds_init();
+
+ return 0;
+}
+
+int dram_init_banksize(void)
+{
+ return fdtdec_setup_memory_banksize();
+}
+
+int dram_init(void)
+{
+ return fdtdec_setup_mem_size_base();
+}
diff --git a/board/samsung/e850-96/e850-96.c b/board/samsung/e850-96/e850-96.c
index 4d4f8d14c6d..a6c264d1248 100644
--- a/board/samsung/e850-96/e850-96.c
+++ b/board/samsung/e850-96/e850-96.c
@@ -4,9 +4,57 @@
* Author: Sam Protsenko <semen.protsenko@linaro.org>
*/
+#include <efi_loader.h>
+#include <env.h>
#include <init.h>
+#include <mapmem.h>
+#include <asm/io.h>
#include "fw.h"
+/* OTP Controller base address and register offsets */
+#define EXYNOS850_OTP_BASE 0x10000000
+#define OTP_CHIPID0 0x4
+#define OTP_CHIPID1 0x8
+
+struct efi_fw_image fw_images[] = {
+ {
+ .image_type_id = E850_96_FWBL1_IMAGE_GUID,
+ .fw_name = u"E850-96-FWBL1",
+ .image_index = 1,
+ },
+ {
+ .image_type_id = E850_96_EPBL_IMAGE_GUID,
+ .fw_name = u"E850-96-EPBL",
+ .image_index = 2,
+ },
+ {
+ .image_type_id = E850_96_BL2_IMAGE_GUID,
+ .fw_name = u"E850-96-BL2",
+ .image_index = 3,
+ },
+ {
+ .image_type_id = E850_96_BOOTLOADER_IMAGE_GUID,
+ .fw_name = u"E850-96-BOOTLOADER",
+ .image_index = 4,
+ },
+ {
+ .image_type_id = E850_96_EL3_MON_IMAGE_GUID,
+ .fw_name = u"E850-96-EL3-MON",
+ .image_index = 5,
+ },
+};
+
+struct efi_capsule_update_info update_info = {
+ .dfu_string = "mmc 0="
+ "fwbl1.img raw 0x0 0x18 mmcpart 1;"
+ "epbl.img raw 0x18 0x98 mmcpart 1;"
+ "bl2.img raw 0xb0 0x200 mmcpart 1;"
+ "bootloader.img raw 0x438 0x1000 mmcpart 1;"
+ "el3_mon.img raw 0x1438 0x200 mmcpart 1",
+ .num_images = ARRAY_SIZE(fw_images),
+ .images = fw_images,
+};
+
int dram_init(void)
{
return fdtdec_setup_mem_size_base();
@@ -17,10 +65,39 @@ int dram_init_banksize(void)
return fdtdec_setup_memory_banksize();
}
+/* Read the unique SoC ID from OTP registers */
+static u64 get_chip_id(void)
+{
+ void __iomem *otp_base;
+ u64 val;
+
+ otp_base = map_sysmem(EXYNOS850_OTP_BASE, 12);
+ val = readl(otp_base + OTP_CHIPID0);
+ val |= (u64)readl(otp_base + OTP_CHIPID1) << 32UL;
+ unmap_sysmem(otp_base);
+
+ return val;
+}
+
+static void setup_serial(void)
+{
+ char serial_str[17] = { 0 };
+ u64 serial_num;
+
+ if (env_get("serial#"))
+ return;
+
+ serial_num = get_chip_id();
+ snprintf(serial_str, sizeof(serial_str), "%016llx", serial_num);
+ env_set("serial#", serial_str);
+}
+
int board_late_init(void)
{
int err;
+ setup_serial();
+
/*
* Do this in board_late_init() to make sure MMC is not probed before
* efi_init_early().
diff --git a/board/samsung/e850-96/e850-96.env b/board/samsung/e850-96/e850-96.env
index 5ac76bcef02..aed7a71046d 100644
--- a/board/samsung/e850-96/e850-96.env
+++ b/board/samsung/e850-96/e850-96.env
@@ -7,5 +7,49 @@ pxefile_addr_r=0x8c200000
ramdisk_addr_r=0x8c300000
fdtfile=CONFIG_DEFAULT_FDT_FILE
+dfu_alt_info=
+ rawemmc raw 0 0x747c000 mmcpart 1;
+ esp part 0 1;
+ rootfs part 0 2;
+ fwbl1 raw 0x0 0x18 mmcpart 1;
+ epbl raw 0x18 0x98 mmcpart 1;
+ bl2 raw 0xb0 0x200 mmcpart 1;
+ dram_train raw 0x2b0 0x20 mmcpart 1;
+ ect_test raw 0x2d0 0x64 mmcpart 1;
+ acpm_test raw 0x334 0x104 mmcpart 1;
+ bootloader raw 0x438 0x1000 mmcpart 1;
+ el3_mon raw 0x1438 0x200 mmcpart 1
+
partitions=name=esp,start=512K,size=128M,bootable,type=system;
partitions+=name=rootfs,size=-,bootable,type=linux
+
+partitions_android=name=esp,start=512K,size=128M,bootable,type=system;
+partitions_android+=name=efs,size=20M,uuid=${uuid_gpt_efs};
+partitions_android+=name=env,size=16K,uuid=${uuid_gpt_env};
+partitions_android+=name=kernel,size=30M,uuid=${uuid_gpt_kernel};
+partitions_android+=name=ramdisk,size=26M,uuid=${uuid_gpt_ramdisk};
+partitions_android+=name=dtbo_a,size=1M,uuid=${uuid_gpt_dtbo};
+partitions_android+=name=dtbo_b,size=1M,uuid=${uuid_gpt_dtbo};
+partitions_android+=name=ldfw,size=4016K,uuid=${uuid_gpt_ldfw};
+partitions_android+=name=keystorage,size=8K,uuid=${uuid_gpt_keystorage};
+partitions_android+=name=tzsw,size=1M,uuid=${uuid_gpt_tzsw};
+partitions_android+=name=harx,size=2M,uuid=${uuid_gpt_harx};
+partitions_android+=name=harx_rkp,size=2M,uuid=${uuid_gpt_harx_rkp};
+partitions_android+=name=logo,size=40M,uuid=${uuid_gpt_logo};
+partitions_android+=name=super,size=3600M,uuid=${uuid_gpt_super};
+partitions_android+=name=cache,size=300M,uuid=${uuid_gpt_cache};
+partitions_android+=name=modem,size=100M,uuid=${uuid_gpt_modem};
+partitions_android+=name=boot_a,size=100M,uuid=${uuid_gpt_boot};
+partitions_android+=name=boot_b,size=100M,uuid=${uuid_gpt_boot};
+partitions_android+=name=persist,size=30M,uuid=${uuid_gpt_persist};
+partitions_android+=name=recovery_a,size=40M,uuid=${uuid_gpt_recovery};
+partitions_android+=name=recovery_b,size=40M,uuid=${uuid_gpt_recovery};
+partitions_android+=name=misc,size=40M,uuid=${uuid_gpt_misc};
+partitions_android+=name=mnv,size=20M,uuid=${uuid_gpt_mnv};
+partitions_android+=name=frp,size=512K,uuid=${uuid_gpt_frp};
+partitions_android+=name=vbmeta_a,size=64K,uuid=${uuid_gpt_vbmeta};
+partitions_android+=name=vbmeta_b,size=64K,uuid=${uuid_gpt_vbmeta};
+partitions_android+=name=metadata,size=16M,uuid=${uuid_gpt_metadata};
+partitions_android+=name=dtb_a,size=1M,uuid=${uuid_gpt_dtb};
+partitions_android+=name=dtb_b,size=1M,uuid=${uuid_gpt_dtb};
+partitions_android+=name=userdata,size=-,uuid=${uuid_gpt_userdata}
diff --git a/board/st/common/Kconfig b/board/st/common/Kconfig
index 5efac658cf4..94ec806949b 100644
--- a/board/st/common/Kconfig
+++ b/board/st/common/Kconfig
@@ -1,7 +1,7 @@
config CMD_STBOARD
bool "stboard - command for OTP board information"
depends on ARCH_STM32MP
- default y if TARGET_ST_STM32MP25X || TARGET_ST_STM32MP15X || TARGET_ST_STM32MP13X
+ default y if TARGET_ST_STM32MP13X || TARGET_ST_STM32MP15X || TARGET_ST_STM32MP23X || TARGET_ST_STM32MP25X
help
This compile the stboard command to
read and write the board in the OTP.
diff --git a/board/st/common/stpmic1.c b/board/st/common/stpmic1.c
index 45c2bb5bcea..b46f89dacb9 100644
--- a/board/st/common/stpmic1.c
+++ b/board/st/common/stpmic1.c
@@ -14,8 +14,19 @@
#include <power/pmic.h>
#include <power/stpmic1.h>
+static bool is_stm32mp13xx(void)
+{
+ if (!IS_ENABLED(CONFIG_STM32MP13X))
+ return false;
+
+ return of_machine_is_compatible("st,stm32mp131") ||
+ of_machine_is_compatible("st,stm32mp133") ||
+ of_machine_is_compatible("st,stm32mp135");
+}
+
int board_ddr_power_init(enum ddr_type ddr_type)
{
+ bool is_mp13 = is_stm32mp13xx();
struct udevice *dev;
bool buck3_at_1800000v = false;
int ret;
@@ -30,18 +41,21 @@ int board_ddr_power_init(enum ddr_type ddr_type)
switch (ddr_type) {
case STM32MP_DDR3:
/* VTT = Set LDO3 to sync mode */
- ret = pmic_reg_read(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3));
- if (ret < 0)
- return ret;
-
- ret &= ~STPMIC1_LDO3_MODE;
- ret &= ~STPMIC1_LDO12356_VOUT_MASK;
- ret |= STPMIC1_LDO_VOUT(STPMIC1_LDO3_DDR_SEL);
-
- ret = pmic_reg_write(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3),
- ret);
- if (ret < 0)
- return ret;
+ if (!is_mp13) {
+ /* Enable VTT only on STM32MP15xx */
+ ret = pmic_reg_read(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3));
+ if (ret < 0)
+ return ret;
+
+ ret &= ~STPMIC1_LDO3_MODE;
+ ret &= ~STPMIC1_LDO12356_VOUT_MASK;
+ ret |= STPMIC1_LDO_VOUT(STPMIC1_LDO3_DDR_SEL);
+
+ ret = pmic_reg_write(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3),
+ ret);
+ if (ret < 0)
+ return ret;
+ }
/* VDD_DDR = Set BUCK2 to 1.35V */
ret = pmic_clrsetbits(dev,
@@ -69,11 +83,14 @@ int board_ddr_power_init(enum ddr_type ddr_type)
mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);
/* Enable VTT = LDO3 */
- ret = pmic_clrsetbits(dev,
- STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3),
- STPMIC1_LDO_ENA, STPMIC1_LDO_ENA);
- if (ret < 0)
- return ret;
+ if (!is_mp13) {
+ /* Enable VTT only on STM32MP15xx */
+ ret = pmic_clrsetbits(dev,
+ STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3),
+ STPMIC1_LDO_ENA, STPMIC1_LDO_ENA);
+ if (ret < 0)
+ return ret;
+ }
mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);
diff --git a/board/st/stm32mp1/debug_uart.c b/board/st/stm32mp1/debug_uart.c
index 24e3f9f2201..4c2149e0480 100644
--- a/board/st/stm32mp1/debug_uart.c
+++ b/board/st/stm32mp1/debug_uart.c
@@ -9,17 +9,32 @@
#include <asm/arch/stm32.h>
#include <linux/bitops.h>
+#if IS_ENABLED(CONFIG_STM32MP13X)
+#define RCC_MP_APB1ENSETR (STM32_RCC_BASE + 0x0700)
+#define RCC_MP_AHB4ENSETR (STM32_RCC_BASE + 0x0768)
+#elif IS_ENABLED(CONFIG_STM32MP15X)
#define RCC_MP_APB1ENSETR (STM32_RCC_BASE + 0x0A00)
#define RCC_MP_AHB4ENSETR (STM32_RCC_BASE + 0x0A28)
+#endif
+#define GPIOA_BASE 0x50002000
#define GPIOG_BASE 0x50008000
void board_debug_uart_init(void)
{
- if (CONFIG_DEBUG_UART_BASE == STM32_UART4_BASE) {
- /* UART4 clock enable */
- setbits_le32(RCC_MP_APB1ENSETR, BIT(16));
+ if (CONFIG_DEBUG_UART_BASE != STM32_UART4_BASE)
+ return;
+ /* UART4 clock enable */
+ setbits_le32(RCC_MP_APB1ENSETR, BIT(16));
+
+ if (IS_ENABLED(CONFIG_STM32MP13X)) {
+ /* GPIOA clock enable */
+ writel(BIT(0), RCC_MP_AHB4ENSETR);
+ /* GPIO configuration for DH boards: Uart4 TX = A9 */
+ writel(0xfffbffff, GPIOA_BASE + 0x00);
+ writel(0x00000080, GPIOA_BASE + 0x24);
+ } else if (IS_ENABLED(CONFIG_STM32MP15X)) {
/* GPIOG clock enable */
writel(BIT(6), RCC_MP_AHB4ENSETR);
/* GPIO configuration for ST boards: Uart4 TX = G11 */
diff --git a/board/st/stm32mp2/Kconfig b/board/st/stm32mp2/Kconfig
index f91e25f1f9a..e88c71a278e 100644
--- a/board/st/stm32mp2/Kconfig
+++ b/board/st/stm32mp2/Kconfig
@@ -1,3 +1,17 @@
+if TARGET_ST_STM32MP23X
+
+config SYS_BOARD
+ default "stm32mp2"
+
+config SYS_VENDOR
+ default "st"
+
+config SYS_CONFIG_NAME
+ default "stm32mp23_st_common"
+
+source "board/st/common/Kconfig"
+endif
+
if TARGET_ST_STM32MP25X
config SYS_BOARD
diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS
index 1b4b7d87163..e00b54f4535 100644
--- a/board/sunxi/MAINTAINERS
+++ b/board/sunxi/MAINTAINERS
@@ -137,6 +137,11 @@ M: Chris Morgan <macromorgan@hotmail.com>
S: Maintained
F: configs/anbernic_rg35xx_h700_defconfig
+AVAOTA A1 BOARD
+M: Andre Przywara <andre.przywara@arm.com>
+S: Maintained
+F: configs/avaota-a1_defconfig
+
BANANAPI M1 PLUS
M: Jagan Teki <jagan@amarulasolutions.com>
S: Maintained
@@ -531,6 +536,11 @@ M: Quentin Schulz <quentin.schulz@free-electrons.com>
S: Maintained
F: configs/parrot_r16_defconfig
+RADXA CUBIE A5E BOARD
+M: Andre Przywara <andre.przywara@arm.com>
+S: Maintained
+F: configs/radxa-cubie-a5e_defconfig
+
SINLINX SINA31s BOARD
M: Chen-Yu Tsai <wens@csie.org>
S: Maintained
@@ -591,6 +601,11 @@ M: Andre Przywara <andre.przywara@arm.com>
S: Maintained
F: configs/x96_mate_defconfig
+X96Q PRO+ TV BOX
+M: Andre Przywara <andre.przywara@arm.com>
+S: Maintained
+F: configs/x96q_pro_plus_defconfig
+
YONES TOPTECH BD1078 BOARD
M: Paul Kocialkowski <contact@paulk.fr>
S: Maintained
diff --git a/board/sunxi/board.c b/board/sunxi/board.c
index 943b6221b8a..2929bc17f08 100644
--- a/board/sunxi/board.c
+++ b/board/sunxi/board.c
@@ -118,6 +118,10 @@ void i2c_init_board(void)
clock_twi_onoff(5, 1);
sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN50I_H616_GPL_R_TWI);
sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN50I_H616_GPL_R_TWI);
+#elif CONFIG_MACH_SUN55I_A523
+ clock_twi_onoff(5, 1);
+ sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN50I_GPL_R_TWI);
+ sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN50I_GPL_R_TWI);
#else
clock_twi_onoff(5, 1);
sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_H3_GPL_R_TWI);
@@ -435,7 +439,8 @@ static void mmc_pinmux_setup(int sdc)
sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
sunxi_gpio_set_drv(pin, 2);
}
-#elif defined(CONFIG_MACH_SUN50I_H616) || defined(CONFIG_MACH_SUN50I_A133)
+#elif defined(CONFIG_MACH_SUN50I_H616) || defined(CONFIG_MACH_SUN50I_A133) || \
+ defined(CONFIG_MACH_SUN55I_A523)
/* SDC2: PC0-PC1, PC5-PC6, PC8-PC11, PC13-PC16 */
for (pin = SUNXI_GPC(0); pin <= SUNXI_GPC(16); pin++) {
if (pin > SUNXI_GPC(1) && pin < SUNXI_GPC(5))
generated by cgit v1.2.3 (git 2.0.4) at 2025-08-04 08:51:24 +0000