diff options
Diffstat (limited to 'board')
81 files changed, 1774 insertions, 167 deletions
diff --git a/board/andestech/voyager/Kconfig b/board/andestech/voyager/Kconfig new file mode 100644 index 00000000000..b2e212c3fee --- /dev/null +++ b/board/andestech/voyager/Kconfig @@ -0,0 +1,44 @@ +if TARGET_ANDES_VOYAGER + +config SYS_CPU + default "andes" + +config SYS_BOARD + default "voyager" + +config SYS_VENDOR + default "andestech" + +config SYS_SOC + default "qilai" + +config SYS_CONFIG_NAME + default "voyager" + +config ENV_SIZE + default 0x2000 if ENV_IS_IN_SPI_FLASH + +config ENV_OFFSET + default 0x1F0000 if ENV_IS_IN_SPI_FLASH + +config SPL_TEXT_BASE + default 0x400800000 + +config SPL_OPENSBI_LOAD_ADDR + default 0x400000000 + +config SYS_FDT_BASE + hex + default 0x81E0000 if OF_SEPARATE + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select RISCV_ANDES + select SUPPORT_SPL + select BINMAN if SPL + imply SMP + imply SPL_RAM_SUPPORT + imply SPL_RAM_DEVICE + imply OF_HAS_PRIOR_STAGE + +endif diff --git a/board/andestech/voyager/MAINTAINERS b/board/andestech/voyager/MAINTAINERS new file mode 100644 index 00000000000..b87026ee383 --- /dev/null +++ b/board/andestech/voyager/MAINTAINERS @@ -0,0 +1,8 @@ +Andestech Voyager BOARD +M: Randolph <randolph@andestech.com> +S: Maintained +F: board/andestech/voyager/ +F: configs/voyager_spl_defconfig +F: doc/board/andestech/voyager.rst +F: include/configs/qilai.h + diff --git a/board/andestech/voyager/Makefile b/board/andestech/voyager/Makefile new file mode 100644 index 00000000000..d293e3e2d89 --- /dev/null +++ b/board/andestech/voyager/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2025 Andes Technology Corporation. +# Randolph Lin, Andes Technology Corporation <randolph@andestech.com> + +obj-y := voyager.o diff --git a/board/andestech/voyager/voyager.c b/board/andestech/voyager/voyager.c new file mode 100644 index 00000000000..dc8f1347775 --- /dev/null +++ b/board/andestech/voyager/voyager.c @@ -0,0 +1,70 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2025 Andes Technology Corporation + * Randolph Lin, Andes Technology Corporation <randolph@andestech.com> + */ + +#include <asm/csr.h> +#include <asm/global_data.h> +#include <asm/sbi.h> +#include <config.h> +#include <cpu_func.h> +#include <dm.h> +#include <env.h> +#include <fdtdec.h> +#include <flash.h> +#include <image.h> +#include <init.h> +#include <linux/io.h> +#include <net.h> +#include <spl.h> + +DECLARE_GLOBAL_DATA_PTR; + +int dram_init(void) +{ + return fdtdec_setup_mem_size_base(); +} + +int dram_init_banksize(void) +{ + return fdtdec_setup_memory_banksize(); +} + +#ifdef CONFIG_SPL_BOARD_INIT +void spl_board_init(void) +{ + /* enable andes-l2 cache */ + if (!CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) + enable_caches(); +} +#endif + +#ifdef CONFIG_BOARD_EARLY_INIT_R +int board_early_init_r(void) +{ + /* enable andes-l2 cache */ + if (!CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) + enable_caches(); + + return 0; +} +#endif + +#ifdef CONFIG_SPL +void board_boot_order(u32 *spl_boot_list) +{ + u8 i; + u32 boot_devices[] = { +#ifdef CONFIG_SPL_RAM_SUPPORT + BOOT_DEVICE_RAM, +#endif +#ifdef CONFIG_SPL_MMC + BOOT_DEVICE_MMC1, +#endif + }; + + for (i = 0; i < ARRAY_SIZE(boot_devices); i++) + spl_boot_list[i] = boot_devices[i]; +} +#endif diff --git a/board/aristainetos/MAINTAINERS b/board/aristainetos/MAINTAINERS index c81bef9cb7c..77d7b1614c8 100644 --- a/board/aristainetos/MAINTAINERS +++ b/board/aristainetos/MAINTAINERS @@ -1,5 +1,5 @@ ARISTAINETOS BOARD -M: Heiko Schocher <hs@denx.de> +M: Heiko Schocher <hs@nabladev.com> S: Maintained F: board/aristainetos/ F: include/configs/aristainetos2.h diff --git a/board/asus/transformer-t20/configs/sl101.config b/board/asus/transformer-t20/configs/sl101.config index 4f639e1b412..87c6f7a216d 100644 --- a/board/asus/transformer-t20/configs/sl101.config +++ b/board/asus/transformer-t20/configs/sl101.config @@ -1 +1,2 @@ +CONFIG_ENV_SOURCE_FILE="sl101" CONFIG_DEFAULT_DEVICE_TREE="tegra20-asus-sl101" diff --git a/board/asus/transformer-t20/sl101.env b/board/asus/transformer-t20/sl101.env new file mode 100644 index 00000000000..f2bf298a997 --- /dev/null +++ b/board/asus/transformer-t20/sl101.env @@ -0,0 +1,15 @@ +#include <env/nvidia/prod_upd.env> + +button_cmd_0_name=Volume Down +button_cmd_0=bootmenu +partitions=name=emmc,start=0,size=-,uuid=${uuid_gpt_rootfs} +boot_dev=1 + +bootmenu_0=mount internal storage=usb start && ums 0 mmc 0; bootmenu +bootmenu_1=mount external storage=usb start && ums 0 mmc 1; bootmenu +bootmenu_2=fastboot=echo Starting Fastboot protocol ...; fastboot usb 0; bootmenu +bootmenu_3=update bootloader=run flash_uboot +bootmenu_4=reboot RCM=enterrcm +bootmenu_5=reboot=reset +bootmenu_6=power off=poweroff +bootmenu_delay=-1 diff --git a/board/atmel/sama7d65_curiosity/Kconfig b/board/atmel/sama7d65_curiosity/Kconfig new file mode 100644 index 00000000000..21ff432f2c1 --- /dev/null +++ b/board/atmel/sama7d65_curiosity/Kconfig @@ -0,0 +1,15 @@ +if TARGET_SAMA7D65_CURIOSITY + +config SYS_BOARD + default "sama7d65_curiosity" + +config SYS_VENDOR + default "atmel" + +config SYS_SOC + default "at91" + +config SYS_CONFIG_NAME + default "sama7d65_curiosity" + +endif diff --git a/board/atmel/sama7d65_curiosity/MAINTAINERS b/board/atmel/sama7d65_curiosity/MAINTAINERS new file mode 100644 index 00000000000..054af3c6541 --- /dev/null +++ b/board/atmel/sama7d65_curiosity/MAINTAINERS @@ -0,0 +1,6 @@ +SAMA7D65 CURIOSITY BOARD +M: Ryan Wanner <ryan.wanner@microchip.com> +S: Maintained +F: board/atmel/sama7d65_curiosity.c +F: include/configs/sama7d65_curiosity.h +F: configs/sama7d65_curiosity_mmc1_defconfig diff --git a/board/atmel/sama7d65_curiosity/Makefile b/board/atmel/sama7d65_curiosity/Makefile new file mode 100644 index 00000000000..56d011d1d81 --- /dev/null +++ b/board/atmel/sama7d65_curiosity/Makefile @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries +# +# Author: Ryan Wanner <ryan.wanner@microchip.com> + +obj-y += sama7d65_curiosity.o diff --git a/board/atmel/sama7d65_curiosity/sama7d65_curiosity.c b/board/atmel/sama7d65_curiosity/sama7d65_curiosity.c new file mode 100644 index 00000000000..713b1b9d959 --- /dev/null +++ b/board/atmel/sama7d65_curiosity/sama7d65_curiosity.c @@ -0,0 +1,75 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2024 Microchip Technology, Inc. and its subsidiaries + * + * Author: Ryan Wanner <ryan.wanner@microchip.com> + * + */ + +#include <debug_uart.h> +#include <init.h> +#include <fdtdec.h> +#include <asm/global_data.h> +#include <asm/io.h> +#include <asm/arch/at91_common.h> +#include <asm/arch/atmel_pio4.h> +#include <asm/arch/clk.h> +#include <asm/arch/gpio.h> +#include <asm/arch/sama7d65.h> +#include <asm/mach-types.h> + +DECLARE_GLOBAL_DATA_PTR; + +static void board_leds_init(void) +{ + atmel_pio4_set_pio_output(AT91_PIO_PORTA, 21, 0); /* LED BLUE */ + atmel_pio4_set_pio_output(AT91_PIO_PORTB, 17, 0); /* LED RED */ + atmel_pio4_set_pio_output(AT91_PIO_PORTB, 15, 1); /* LED GREEN */ +} + +int board_late_init(void) +{ + return 0; +} + +#if (IS_ENABLED(CONFIG_DEBUG_UART_BOARD_INIT)) +static void board_uart0_hw_init(void) +{ + /* FLEXCOM6 IO0 */ + atmel_pio4_set_b_periph(AT91_PIO_PORTD, 18, 0); + /* FLEXCOM6 IO1 */ + atmel_pio4_set_b_periph(AT91_PIO_PORTD, 19, 0); + + at91_periph_clk_enable(ATMEL_ID_FLEXCOM6); +} + +void board_debug_uart_init(void) +{ + board_uart0_hw_init(); +} +#endif + +int board_early_init_f(void) +{ + return 0; +} + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100; + + board_leds_init(); + + return 0; +} + +int dram_init_banksize(void) +{ + return fdtdec_setup_memory_banksize(); +} + +int dram_init(void) +{ + return fdtdec_setup_mem_size_base(); +} diff --git a/board/bosch/shc/MAINTAINERS b/board/bosch/shc/MAINTAINERS index 58104cc1318..a30c672e1d6 100644 --- a/board/bosch/shc/MAINTAINERS +++ b/board/bosch/shc/MAINTAINERS @@ -1,5 +1,5 @@ SHC BOARD -M: Heiko Schocher <hs@denx.de> +M: Heiko Schocher <hs@nabladev.com> S: Maintained F: board/bosch/shc F: include/configs/am335x_shc.h diff --git a/board/dhelectronics/common/dh_common.c b/board/dhelectronics/common/dh_common.c index 8c052c45007..6101ecc7ebc 100644 --- a/board/dhelectronics/common/dh_common.c +++ b/board/dhelectronics/common/dh_common.c @@ -88,9 +88,9 @@ int dh_read_eeprom_id_page(u8 *eeprom_buffer, const char *alias) /* Validate header ID */ if (eip->hdr.id[0] != 'D' || eip->hdr.id[1] != 'H' || eip->hdr.id[2] != 'E') { printf("%s: Error validating header ID! (got %c%c%c (0x%02x 0x%02x 0x%02x) != expected DHE)\n", - __func__, isprint(eip->hdr.id[0]) ? eip->hdr.id[0] : '.', - isprint(eip->hdr.id[1]) ? eip->hdr.id[1] : '.', - isprint(eip->hdr.id[2]) ? eip->hdr.id[2] : '.', + __func__, (isascii(eip->hdr.id[0]) && isprint(eip->hdr.id[0])) ? eip->hdr.id[0] : '.', + (isascii(eip->hdr.id[1]) && isprint(eip->hdr.id[1])) ? eip->hdr.id[1] : '.', + (isascii(eip->hdr.id[2]) && isprint(eip->hdr.id[2])) ? eip->hdr.id[2] : '.', eip->hdr.id[0], eip->hdr.id[1], eip->hdr.id[2]); return -EINVAL; } @@ -131,14 +131,17 @@ int dh_read_eeprom_id_page(u8 *eeprom_buffer, const char *alias) int dh_get_value_from_eeprom_buffer(enum eip_request_values request, u8 *data, int data_len, struct eeprom_id_page *eip) { - const char fin_chr = (eip->pl.item_prefix & DH_ITEM_PREFIX_FIN_BIT) ? - DH_ITEM_PREFIX_FIN_FLASHED_CHR : DH_ITEM_PREFIX_FIN_HALF_CHR; - const u8 soc_coded = eip->pl.item_prefix & 0xf; + char fin_chr; + u8 soc_coded; char soc_chr; if (!eip) return -EINVAL; + fin_chr = (eip->pl.item_prefix & DH_ITEM_PREFIX_FIN_BIT) ? + DH_ITEM_PREFIX_FIN_FLASHED_CHR : DH_ITEM_PREFIX_FIN_HALF_CHR; + soc_coded = eip->pl.item_prefix & 0xf; + /* Copy requested data */ switch (request) { case DH_MAC0: diff --git a/board/dhelectronics/dh_imx6/dh_imx6_spl.c b/board/dhelectronics/dh_imx6/dh_imx6_spl.c index a50763e1926..eb9bc93d973 100644 --- a/board/dhelectronics/dh_imx6/dh_imx6_spl.c +++ b/board/dhelectronics/dh_imx6/dh_imx6_spl.c @@ -49,6 +49,10 @@ (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ PAD_CTL_SRE_FAST | PAD_CTL_HYS) +#define OTG_PAD_CTRL \ + (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ + PAD_CTL_SRE_SLOW | PAD_CTL_HYS) + static const struct mx6dq_iomux_ddr_regs dhcom6dq_ddr_ioregs = { .dram_sdclk_0 = 0x00020030, .dram_sdclk_1 = 0x00020030, @@ -509,7 +513,7 @@ int board_mmc_init(struct bd_info *bis) /* USB */ static iomux_v3_cfg_t const usb_pads[] = { - IOMUX_PADS(PAD_GPIO_1__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_GPIO_1__USB_OTG_ID | MUX_PAD_CTRL(OTG_PAD_CTRL)), IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL)), }; diff --git a/board/dhelectronics/dh_stm32mp1/board.c b/board/dhelectronics/dh_stm32mp1/board.c index f7347bbb826..bd9326d6b1b 100644 --- a/board/dhelectronics/dh_stm32mp1/board.c +++ b/board/dhelectronics/dh_stm32mp1/board.c @@ -85,6 +85,9 @@ static bool dh_stm32_mac_is_in_ks8851(void) if (!ofnode_valid(node)) return false; + if (!ofnode_device_is_compatible(node, "micrel,ks8851-mll")) + return false; + ret = ofnode_get_path(node, path, sizeof(path)); if (ret) return false; @@ -93,9 +96,6 @@ static bool dh_stm32_mac_is_in_ks8851(void) if (ret) return false; - if (!ofnode_device_is_compatible(node, "micrel,ks8851-mll")) - return false; - /* * KS8851 with EEPROM may use custom MAC from EEPROM, read * out the KS8851 CCR register to determine whether EEPROM diff --git a/board/freescale/imx95_evk/MAINTAINERS b/board/freescale/imx95_evk/MAINTAINERS index 5caf763e0cc..9d5c4e41b65 100644 --- a/board/freescale/imx95_evk/MAINTAINERS +++ b/board/freescale/imx95_evk/MAINTAINERS @@ -3,4 +3,5 @@ M: Alice Guo <alice.guo@nxp.com> S: Maintained F: board/freescale/imx95_evk/ F: include/configs/imx95_evk.h +F: configs/imx95_a0_19x19_evk_defconfig F: configs/imx95_19x19_evk_defconfig diff --git a/board/gameforce/ace-rk3588s/Kconfig b/board/gameforce/ace-rk3588s/Kconfig new file mode 100644 index 00000000000..52f98ccf897 --- /dev/null +++ b/board/gameforce/ace-rk3588s/Kconfig @@ -0,0 +1,9 @@ +if TARGET_GAMEFORCE_ACE_RK3588S + +config SYS_BOARD + default "gameforce-ace-rk3588s" + +config SYS_VENDOR + default "GameForce" + +endif diff --git a/board/gameforce/ace-rk3588s/MAINTAINERS b/board/gameforce/ace-rk3588s/MAINTAINERS new file mode 100644 index 00000000000..dc18e7c8849 --- /dev/null +++ b/board/gameforce/ace-rk3588s/MAINTAINERS @@ -0,0 +1,5 @@ +GAMEFORCE-ACE-RK3588S +M: Chris Morgan <macromorgan@hotmail.com> +S: Maintained +F: board/gameforce/ace-rk3588s/ +F: configs/gameforce-ace-rk3588s_defconfig diff --git a/board/intel/agilex-socdk/Makefile b/board/intel/agilex-socdk/Makefile new file mode 100644 index 00000000000..306a8cf5f0b --- /dev/null +++ b/board/intel/agilex-socdk/Makefile @@ -0,0 +1,7 @@ +# +# Copyright (C) 2025 Altera Corporation <www.altera.com> +# +# SPDX-License-Identifier: GPL-2.0 +# + +obj-y := socfpga.o diff --git a/board/intel/agilex-socdk/socfpga.c b/board/intel/agilex-socdk/socfpga.c new file mode 100644 index 00000000000..60c8704b391 --- /dev/null +++ b/board/intel/agilex-socdk/socfpga.c @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2025 Altera Corporation <www.altera.com> + */ + +#include <asm/arch/misc.h> + +int board_early_init_f(void) +{ + socfpga_get_sys_mgr_addr(); + return 0; +} diff --git a/board/intel/agilex5-socdk/socfpga.c b/board/intel/agilex5-socdk/socfpga.c index d6628cfc696..60c8704b391 100644 --- a/board/intel/agilex5-socdk/socfpga.c +++ b/board/intel/agilex5-socdk/socfpga.c @@ -7,6 +7,6 @@ int board_early_init_f(void) { - socfpga_get_sys_mgr_addr("sysmgr@10d12000"); + socfpga_get_sys_mgr_addr(); return 0; } diff --git a/board/intel/agilex7m-socdk/MAINTAINERS b/board/intel/agilex7m-socdk/MAINTAINERS new file mode 100644 index 00000000000..9a5b80ae4df --- /dev/null +++ b/board/intel/agilex7m-socdk/MAINTAINERS @@ -0,0 +1,10 @@ +SOCFPGA BOARD +M: Tien Fong Chee <tien.fong.chee@altera.com> +M: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com> +S: Maintained +F: arch/arm/dts/socfpga_soc64_u-boot.dtsi +F: arch/arm/dts/socfpga_agilex7m* +F: arch/arm/mach-socfpga/spl_agilex7m.c +F: board/intel/agilex7m-socdk/ +F: include/configs/socfpga_agilex7m_socdk.h +F: configs/socfpga_agilex7m_sdmmc_defconfig diff --git a/board/intel/agilex7m-socdk/Makefile b/board/intel/agilex7m-socdk/Makefile new file mode 100644 index 00000000000..306a8cf5f0b --- /dev/null +++ b/board/intel/agilex7m-socdk/Makefile @@ -0,0 +1,7 @@ +# +# Copyright (C) 2025 Altera Corporation <www.altera.com> +# +# SPDX-License-Identifier: GPL-2.0 +# + +obj-y := socfpga.o diff --git a/board/intel/agilex7m-socdk/socfpga.c b/board/intel/agilex7m-socdk/socfpga.c new file mode 100644 index 00000000000..60c8704b391 --- /dev/null +++ b/board/intel/agilex7m-socdk/socfpga.c @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2025 Altera Corporation <www.altera.com> + */ + +#include <asm/arch/misc.h> + +int board_early_init_f(void) +{ + socfpga_get_sys_mgr_addr(); + return 0; +} diff --git a/board/keymile/km83xx/MAINTAINERS b/board/keymile/km83xx/MAINTAINERS index 8822e5d9155..af0d6afb2b4 100644 --- a/board/keymile/km83xx/MAINTAINERS +++ b/board/keymile/km83xx/MAINTAINERS @@ -1,6 +1,6 @@ KM83XX BOARD M: Holger Brunck <holger.brunck@hitachienergy.com> -M: Heiko Schocher <hs@denx.de> +M: Heiko Schocher <hs@nabladev.com> S: Maintained F: board/keymile/km83xx/ F: board/keymile/common/ diff --git a/board/microchip/mpfs_icicle/Kconfig b/board/microchip/mpfs_icicle/Kconfig index 6e8c479e955..760dffc488b 100644 --- a/board/microchip/mpfs_icicle/Kconfig +++ b/board/microchip/mpfs_icicle/Kconfig @@ -59,5 +59,9 @@ config BOARD_SPECIFIC_OPTIONS # dummy imply MTD_SPI_NAND imply CMD_MTD imply CMD_MTDPARTS + imply DM_MAILBOX + imply MPFS_MBOX + imply MISC + imply MPFS_SYSCONTROLLER endif diff --git a/board/microchip/mpfs_icicle/mpfs_icicle.c b/board/microchip/mpfs_icicle/mpfs_icicle.c index ba622e38ee5..739a9b6cd76 100644 --- a/board/microchip/mpfs_icicle/mpfs_icicle.c +++ b/board/microchip/mpfs_icicle/mpfs_icicle.c @@ -4,52 +4,21 @@ * Padmarao Begari <padmarao.begari@microchip.com> */ -#include <dm.h> -#include <env.h> -#include <init.h> #include <asm/global_data.h> #include <asm/io.h> #include <asm/sections.h> +#include <dm.h> +#include <dm/devres.h> +#include <env.h> +#include <linux/compat.h> +#include <mpfs-mailbox.h> DECLARE_GLOBAL_DATA_PTR; -#define MPFS_SYSREG_SOFT_RESET ((unsigned int *)0x20002088) -#define MPFS_SYS_SERVICE_CR ((unsigned int *)0x37020050) -#define MPFS_SYS_SERVICE_SR ((unsigned int *)0x37020054) -#define MPFS_SYS_SERVICE_MAILBOX ((unsigned char *)0x37020800) - +#define MPFS_SYSREG_SOFT_RESET ((unsigned int *)0x20002088) #define PERIPH_RESET_VALUE 0x1e8u -#define SERVICE_CR_REQ 0x1u -#define SERVICE_SR_BUSY 0x2u -static void read_device_serial_number(u8 *response, u8 response_size) -{ - u8 idx; - u8 *response_buf; - unsigned int val; - - response_buf = (u8 *)response; - - writel(SERVICE_CR_REQ, MPFS_SYS_SERVICE_CR); - /* - * REQ bit will remain set till the system controller starts - * processing. - */ - do { - val = readl(MPFS_SYS_SERVICE_CR); - } while (SERVICE_CR_REQ == (val & SERVICE_CR_REQ)); - - /* - * Once system controller starts processing the busy bit will - * go high and service is completed when busy bit is gone low - */ - do { - val = readl(MPFS_SYS_SERVICE_SR); - } while (SERVICE_SR_BUSY == (val & SERVICE_SR_BUSY)); - - for (idx = 0; idx < response_size; idx++) - response_buf[idx] = readb(MPFS_SYS_SERVICE_MAILBOX + idx); -} +static unsigned char mac_addr[6]; #if defined(CONFIG_MULTI_DTB_FIT) int board_fit_config_name_match(const char *name) @@ -145,13 +114,35 @@ int board_late_init(void) { u32 ret; int node; - u8 idx; - u8 device_serial_number[16] = { 0 }; - unsigned char mac_addr[6]; - char icicle_mac_addr[20]; + u8 device_serial_number[16] = {0}; void *blob = (void *)gd->fdt_blob; + struct udevice *dev; + struct mpfs_sys_serv *sys_serv_priv; + + ret = uclass_get_device_by_name(UCLASS_MISC, "syscontroller", &dev); + if (ret) { + debug("%s: system controller setup failed\n", __func__); + return ret; + } + + sys_serv_priv = kzalloc(sizeof(*sys_serv_priv), GFP_KERNEL); + if (!sys_serv_priv) + return -ENOMEM; - read_device_serial_number(device_serial_number, 16); + sys_serv_priv->dev = dev; + + sys_serv_priv->sys_controller = mpfs_syscontroller_get(dev); + ret = IS_ERR(sys_serv_priv->sys_controller); + if (ret) { + debug("%s: Failed to register system controller sub device ret=%d\n", __func__, ret); + return -ENODEV; + } + + ret = mpfs_syscontroller_read_sernum(sys_serv_priv, device_serial_number); + if (ret) { + printf("Cannot read device serial number\n"); + return -EINVAL; + } /* Update MAC address with device serial number */ mac_addr[0] = 0x00; @@ -170,19 +161,6 @@ int board_late_init(void) } } - icicle_mac_addr[0] = '['; - - sprintf(&icicle_mac_addr[1], "%pM", mac_addr); - - icicle_mac_addr[18] = ']'; - icicle_mac_addr[19] = '\0'; - - for (idx = 0; idx < 20; idx++) { - if (icicle_mac_addr[idx] == ':') - icicle_mac_addr[idx] = ' '; - } - env_set("icicle_mac_addr0", icicle_mac_addr); - mac_addr[5] = device_serial_number[0] + 1; node = fdt_path_offset(blob, "/soc/ethernet@20110000"); @@ -194,18 +172,33 @@ int board_late_init(void) } } - icicle_mac_addr[0] = '['; + return 0; +} - sprintf(&icicle_mac_addr[1], "%pM", mac_addr); +int ft_board_setup(void *blob, struct bd_info *bd) +{ + u32 ret; + int node; - icicle_mac_addr[18] = ']'; - icicle_mac_addr[19] = '\0'; + node = fdt_path_offset(blob, "/soc/ethernet@20110000"); + if (node >= 0) { + ret = fdt_setprop(blob, node, "local-mac-address", mac_addr, 6); + if (ret) { + printf("Error setting local-mac-address property for ethernet@20110000\n"); + return -ENODEV; + } + } + + mac_addr[5] -= 1; - for (idx = 0; idx < 20; idx++) { - if (icicle_mac_addr[idx] == ':') - icicle_mac_addr[idx] = ' '; + node = fdt_path_offset(blob, "/soc/ethernet@20112000"); + if (node >= 0) { + ret = fdt_setprop(blob, node, "local-mac-address", mac_addr, 6); + if (ret) { + printf("Error setting local-mac-address property for ethernet@20112000\n"); + return -ENODEV; + } } - env_set("icicle_mac_addr1", icicle_mac_addr); return 0; } diff --git a/board/microsoft/surface-2/Kconfig b/board/microsoft/surface-2/Kconfig new file mode 100644 index 00000000000..8573666dc92 --- /dev/null +++ b/board/microsoft/surface-2/Kconfig @@ -0,0 +1,13 @@ +if TARGET_SURFACE_2 + +config SYS_BOARD + default "surface-2" + +config SYS_VENDOR + default "microsoft" + +config TEGRA_BOARD_STRING + string "Default Tegra board name" + default "Microsoft Surface 2" + +endif diff --git a/board/microsoft/surface-2/MAINTAINERS b/board/microsoft/surface-2/MAINTAINERS new file mode 100644 index 00000000000..57747d304cd --- /dev/null +++ b/board/microsoft/surface-2/MAINTAINERS @@ -0,0 +1,7 @@ +SURFACE_2 BOARD +M: Jonas Schwöbel <jonasschwoebel@yahoo.de> +S: Maintained +F: arch/arm/dts/tegra114-microsoft-surface-2* +F: board/microsoft/surface-2/ +F: configs/surface-2_defconfig +F: doc/board/microsoft/surface-2.rst diff --git a/board/microsoft/surface-2/Makefile b/board/microsoft/surface-2/Makefile new file mode 100644 index 00000000000..43bf6c66db2 --- /dev/null +++ b/board/microsoft/surface-2/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0 +# +# Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. + +obj-$(CONFIG_XPL_BUILD) += surface-2-spl.o +obj-$(CONFIG_MULTI_DTB_FIT) += board-info.o diff --git a/board/microsoft/surface-2/board-info.c b/board/microsoft/surface-2/board-info.c new file mode 100644 index 00000000000..95a4accdc90 --- /dev/null +++ b/board/microsoft/surface-2/board-info.c @@ -0,0 +1,71 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2025 + * Svyatoslav Ryhel <clamor95@gmail.com> + */ + +#include <stdio.h> +#include <env.h> +#include <spl_gpio.h> + +#include <asm/gpio.h> +#include <asm/arch/pinmux.h> +#include <linux/string.h> + +static int id_gpio_get_value(u32 pingrp, u32 pin) +{ + /* Configure pinmux */ + pinmux_set_func(pingrp, PMUX_FUNC_KBC); + pinmux_set_pullupdown(pingrp, PMUX_PULL_DOWN); + pinmux_tristate_enable(pingrp); + pinmux_set_io(pingrp, PMUX_PIN_INPUT); + + /* + * Since this function may be called + * during DM reload we should use SPL + * GPIO functions which do not depend + * on DM. + */ + spl_gpio_input(NULL, pin); + return spl_gpio_get_value(NULL, pin); +} + +static int get_board_id(void) +{ + u32 pcb_id0, pcb_id1, pcb_id2, pcb_id3, pcb_id4, board_id; + + pcb_id0 = id_gpio_get_value(PMUX_PINGRP_KB_COL0_PQ0, TEGRA_GPIO(Q, 0)); + pcb_id1 = id_gpio_get_value(PMUX_PINGRP_KB_COL1_PQ1, TEGRA_GPIO(Q, 1)); + pcb_id2 = id_gpio_get_value(PMUX_PINGRP_KB_COL2_PQ2, TEGRA_GPIO(Q, 2)); + pcb_id3 = id_gpio_get_value(PMUX_PINGRP_KB_COL3_PQ3, TEGRA_GPIO(Q, 3)); + pcb_id4 = id_gpio_get_value(PMUX_PINGRP_KB_COL4_PQ4, TEGRA_GPIO(Q, 4)); + + /* Construct board ID */ + board_id = pcb_id4 << 4 | pcb_id3 << 3 | pcb_id2 << 2 | pcb_id1 << 1 | pcb_id0; + + log_debug("[SURFACE-2]: Board ID %02x\n", board_id); + + return board_id & 0x1f; +} + +int board_fit_config_name_match(const char *name) +{ + char dt_name[64] = { 0 }; + + snprintf(dt_name, sizeof(dt_name), "tegra114-microsoft-surface-2-%02x.dtb", + get_board_id()); + + if (!strcmp(name, dt_name)) + return 0; + + return -1; +} + +void nvidia_board_late_init(void) +{ + char dt_path[64] = { 0 }; + + snprintf(dt_path, sizeof(dt_path), "tegra114-microsoft-surface-2-%02x.dtb", + get_board_id()); + env_set("fdtfile", dt_path); +} diff --git a/board/microsoft/surface-2/surface-2-spl.c b/board/microsoft/surface-2/surface-2-spl.c new file mode 100644 index 00000000000..16f4373c7f0 --- /dev/null +++ b/board/microsoft/surface-2/surface-2-spl.c @@ -0,0 +1,42 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Surface 2 SPL stage configuration + * + * (C) Copyright 2010-2013 + * NVIDIA Corporation <www.nvidia.com> + * + * (C) Copyright 2023 + * Svyatoslav Ryhel <clamor95@gmail.com> + */ + +#include <asm/arch/tegra.h> +#include <asm/arch-tegra/tegra_i2c.h> +#include <linux/delay.h> + +#define TPS65913_I2C_ADDR (0x58 << 1) + +#define TPS65913_SMPS12_CTRL 0x20 +#define TPS65913_SMPS12_VOLTAGE 0x23 +#define TPS65913_SMPS45_CTRL 0x28 +#define TPS65913_SMPS45_VOLTAGE 0x2B + +#define TPS65913_SMPS12_CTRL_DATA (0x5100 | TPS65913_SMPS12_CTRL) +#define TPS65913_SMPS12_VOLTAGE_DATA (0x3900 | TPS65913_SMPS12_VOLTAGE) +#define TPS65913_SMPS45_CTRL_DATA (0x5100 | TPS65913_SMPS45_CTRL) +#define TPS65913_SMPS45_VOLTAGE_DATA (0x4c00 | TPS65913_SMPS45_VOLTAGE) + +void pmic_enable_cpu_vdd(void) +{ + /* Set CORE VDD to 1.200V. */ + tegra_i2c_ll_write(TPS65913_I2C_ADDR, TPS65913_SMPS45_VOLTAGE_DATA); + udelay(1000); + tegra_i2c_ll_write(TPS65913_I2C_ADDR, TPS65913_SMPS45_CTRL_DATA); + + udelay(1000); + + /* Set CPU VDD to 1.0125V. */ + tegra_i2c_ll_write(TPS65913_I2C_ADDR, TPS65913_SMPS12_VOLTAGE_DATA); + udelay(1000); + tegra_i2c_ll_write(TPS65913_I2C_ADDR, TPS65913_SMPS12_CTRL_DATA); + udelay(10 * 1000); +} diff --git a/board/microsoft/surface-2/surface-2.env b/board/microsoft/surface-2/surface-2.env new file mode 100644 index 00000000000..a77885a7c6d --- /dev/null +++ b/board/microsoft/surface-2/surface-2.env @@ -0,0 +1,8 @@ +button_cmd_0_name=Volume Down +button_cmd_0=bootmenu + +bootmenu_0=mount internal storage=usb start && ums 0 mmc 0; bootmenu +bootmenu_1=mount external storage=usb start && ums 0 mmc 1; bootmenu +bootmenu_2=fastboot=echo Starting Fastboot protocol ...; fastboot usb 0; bootmenu +bootmenu_4=power off=reset +bootmenu_delay=-1 diff --git a/board/pegatron/chagall/Kconfig b/board/pegatron/chagall/Kconfig new file mode 100644 index 00000000000..8c229d0e333 --- /dev/null +++ b/board/pegatron/chagall/Kconfig @@ -0,0 +1,13 @@ +if TARGET_CHAGALL + +config SYS_BOARD + default "chagall" + +config SYS_VENDOR + default "pegatron" + +config TEGRA_BOARD_STRING + string "Default Tegra board name" + default "Pegatron Chagall" + +endif diff --git a/board/pegatron/chagall/MAINTAINERS b/board/pegatron/chagall/MAINTAINERS new file mode 100644 index 00000000000..5ebd5940f42 --- /dev/null +++ b/board/pegatron/chagall/MAINTAINERS @@ -0,0 +1,7 @@ +CHAGALL BOARD +M: Svyatoslav Ryhel <clamor95@gmail.com> +S: Maintained +F: arch/arm/dts/tegra30-pegatron-chagall.dts +F: board/pegatron/chagall/ +F: configs/chagall_defconfig +F: doc/board/pegatron/chagall.rst diff --git a/board/pegatron/chagall/Makefile b/board/pegatron/chagall/Makefile new file mode 100644 index 00000000000..17cfef50987 --- /dev/null +++ b/board/pegatron/chagall/Makefile @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2010-2012 +# NVIDIA Corporation <www.nvidia.com> +# +# (C) Copyright 2021 +# Svyatoslav Ryhel <clamor95@gmail.com> + +obj-$(CONFIG_XPL_BUILD) += chagall-spl.o + +obj-y += chagall.o diff --git a/board/pegatron/chagall/chagall-spl.c b/board/pegatron/chagall/chagall-spl.c new file mode 100644 index 00000000000..6c271973ada --- /dev/null +++ b/board/pegatron/chagall/chagall-spl.c @@ -0,0 +1,41 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Chagall SPL stage configuration + * + * (C) Copyright 2010-2013 + * NVIDIA Corporation <www.nvidia.com> + * + * (C) Copyright 2021 + * Svyatoslav Ryhel <clamor95@gmail.com> + */ + +#include <asm/arch/tegra.h> +#include <asm/arch-tegra/tegra_i2c.h> +#include <linux/delay.h> + +#define TPS65911_I2C_ADDR (0x2D << 1) +#define TPS65911_VDDCTRL_OP_REG 0x28 +#define TPS65911_VDDCTRL_SR_REG 0x27 +#define TPS65911_VDDCTRL_OP_DATA (0x2400 | TPS65911_VDDCTRL_OP_REG) +#define TPS65911_VDDCTRL_SR_DATA (0x0100 | TPS65911_VDDCTRL_SR_REG) + +#define TPS62361B_I2C_ADDR (0x60 << 1) +#define TPS62361B_SET3_REG 0x03 +#define TPS62361B_SET3_DATA (0x4600 | TPS62361B_SET3_REG) + +void pmic_enable_cpu_vdd(void) +{ + /* Set VDD_CORE to 1.200V. */ + tegra_i2c_ll_write(TPS62361B_I2C_ADDR, TPS62361B_SET3_DATA); + + udelay(1000); + + /* + * Bring up CPU VDD via the TPS65911x PMIC on the DVC I2C bus. + * First set VDD to 1.0125V, then enable the VDD regulator. + */ + tegra_i2c_ll_write(TPS65911_I2C_ADDR, TPS65911_VDDCTRL_OP_DATA); + udelay(1000); + tegra_i2c_ll_write(TPS65911_I2C_ADDR, TPS65911_VDDCTRL_SR_DATA); + udelay(10 * 1000); +} diff --git a/board/pegatron/chagall/chagall.c b/board/pegatron/chagall/chagall.c new file mode 100644 index 00000000000..1412c4f9b60 --- /dev/null +++ b/board/pegatron/chagall/chagall.c @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2010-2013 + * NVIDIA Corporation <www.nvidia.com> + * + * (C) Copyright 2021 + * Svyatoslav Ryhel <clamor95@gmail.com> + */ + +/* Chagall derives from Cardhu board */ + +#include <fdt_support.h> + +#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) +int ft_board_setup(void *blob, struct bd_info *bd) +{ + /* Remove TrustZone nodes */ + fdt_del_node_and_alias(blob, "/firmware"); + fdt_del_node_and_alias(blob, "/reserved-memory/trustzone@bfe00000"); + + return 0; +} +#endif diff --git a/board/pegatron/chagall/chagall.env b/board/pegatron/chagall/chagall.env new file mode 100644 index 00000000000..68bf51bdc3c --- /dev/null +++ b/board/pegatron/chagall/chagall.env @@ -0,0 +1,9 @@ +button_cmd_0_name=Volume Down +button_cmd_0=bootmenu + +bootmenu_0=mount external storage=usb start && ums 0 mmc 1; bootmenu +bootmenu_1=fastboot=echo Starting Fastboot protocol ...; fastboot usb 0; bootmenu +bootmenu_2=reboot RCM=enterrcm +bootmenu_3=reboot=reset +bootmenu_4=power off=poweroff +bootmenu_delay=-1 diff --git a/board/phytec/phycore_am62ax/phycore_am62ax.env b/board/phytec/phycore_am62ax/phycore_am62ax.env index 797904013dc..ff4ab8c87b8 100644 --- a/board/phytec/phycore_am62ax/phycore_am62ax.env +++ b/board/phytec/phycore_am62ax/phycore_am62ax.env @@ -25,5 +25,9 @@ spi_fdt_addr=0x700000 spi_image_addr=0x800000 spi_ramdisk_addr=0x2200000 +#ifdef CONFIG_BOOTMETH_RAUC +bootmeths=rauc script efi extlinux pxe +#else bootmeths=script efi extlinux pxe +#endif boot_targets=mmc1 mmc0 spi_flash dhcp diff --git a/board/phytec/phycore_am62x/phycore_am62x.env b/board/phytec/phycore_am62x/phycore_am62x.env index 797904013dc..ff4ab8c87b8 100644 --- a/board/phytec/phycore_am62x/phycore_am62x.env +++ b/board/phytec/phycore_am62x/phycore_am62x.env @@ -25,5 +25,9 @@ spi_fdt_addr=0x700000 spi_image_addr=0x800000 spi_ramdisk_addr=0x2200000 +#ifdef CONFIG_BOOTMETH_RAUC +bootmeths=rauc script efi extlinux pxe +#else bootmeths=script efi extlinux pxe +#endif boot_targets=mmc1 mmc0 spi_flash dhcp diff --git a/board/phytec/phycore_am64x/phycore_am64x.env b/board/phytec/phycore_am64x/phycore_am64x.env index 36ab16e2f7a..cbaf45b3ace 100644 --- a/board/phytec/phycore_am64x/phycore_am64x.env +++ b/board/phytec/phycore_am64x/phycore_am64x.env @@ -24,5 +24,9 @@ spi_fdt_addr=0x700000 spi_image_addr=0x800000 spi_ramdisk_addr=0x2200000 +#ifdef CONFIG_BOOTMETH_RAUC +bootmeths=rauc script efi extlinux pxe +#else bootmeths=script efi extlinux pxe +#endif boot_targets=mmc1 mmc0 spi_flash dhcp diff --git a/board/phytec/phycore_imx93/phycore-imx93.c b/board/phytec/phycore_imx93/phycore-imx93.c index 8d2caf8bbef..fab66caf2a1 100644 --- a/board/phytec/phycore_imx93/phycore-imx93.c +++ b/board/phytec/phycore_imx93/phycore-imx93.c @@ -79,6 +79,10 @@ int board_fix_fdt(void *blob) emmc_fixup(blob, &data); + /* Update dtb clocks for low drive mode */ + if (is_voltage_mode(VOLT_LOW_DRIVE)) + low_drive_freq_update(blob); + return 0; } @@ -86,5 +90,10 @@ int ft_board_setup(void *blob, struct bd_info *bd) { emmc_fixup(blob, NULL); + /** + * NOTE: VOLT_LOW_DRIVE fixup is done by the ft_system_setup() + * in arch/arm/mach-imx/imx9/soc.c for Linux device-tree. + */ + return 0; } diff --git a/board/phytec/phycore_imx93/spl.c b/board/phytec/phycore_imx93/spl.c index 7b5d38d438f..beaa536c600 100644 --- a/board/phytec/phycore_imx93/spl.c +++ b/board/phytec/phycore_imx93/spl.c @@ -52,8 +52,7 @@ void spl_dram_init(void) int ret; enum phytec_imx93_ddr_eeprom_code ddr_opt = PHYTEC_IMX93_DDR_INVALID; - /* NOTE: In SPL lpi2c3 is mapped to bus 0 */ - ret = phytec_eeprom_data_setup(NULL, 0, EEPROM_ADDR); + ret = phytec_eeprom_data_setup(NULL, 2, EEPROM_ADDR); if (ret && !IS_ENABLED(CONFIG_PHYCORE_IMX93_RAM_TYPE_FIX)) goto out; diff --git a/board/renesas/sparrowhawk/sparrowhawk.c b/board/renesas/sparrowhawk/sparrowhawk.c index 8e72b5424d1..58de7f25cbd 100644 --- a/board/renesas/sparrowhawk/sparrowhawk.c +++ b/board/renesas/sparrowhawk/sparrowhawk.c @@ -6,8 +6,12 @@ #include <asm/io.h> #include <compiler.h> #include <dbsc5.h> +#include <spi.h> +#include <spi_flash.h> #include <spl.h> +#include "../../../drivers/mtd/spi/sf_internal.h" + #if defined(CONFIG_XPL_BUILD) static const struct renesas_dbsc5_board_config @@ -112,12 +116,134 @@ dbsc5_get_board_data(struct udevice *dev, const u32 modemr0) * Use MD[19] setting to discern 8 GiB and 16 GiB DRAM Sparrow Hawk * board variants from each other automatically. */ - if (modemr0 & BIT(19)) + if ((renesas_get_cpu_rev_integer() >= 3) && (modemr0 & BIT(19))) return &renesas_v4h_sparrowhawk_16g_5500_dbsc5_board_config; else return &renesas_v4h_sparrowhawk_8g_6400_dbsc5_board_config; } +static bool renesas_v4h_sparrowhawk_is_evta1 = false; + +unsigned int spl_spi_get_uboot_offs(struct spi_flash *flash) +{ + const u8 sf_ids_evta1[6] = { 0x01, 0x02, 0x20, 0x4d, 0x00, 0x81 }; + + renesas_v4h_sparrowhawk_is_evta1 = !memcmp(sf_ids_evta1, flash->info->id, + sizeof(sf_ids_evta1)); + + return CONFIG_SYS_SPI_U_BOOT_OFFS; +} + +void spl_perform_fixups(struct spl_image_info *spl_image) +{ + void *blob = spl_image_fdt_addr(spl_image); + int err, offs; + u32 size; + + if (!renesas_v4h_sparrowhawk_is_evta1) + return; + + printf("EVTA1 board detected\n"); + + /* + * MicroSD voltage switch is not populated on Sparrow Hawk EVTA1, + * rewrite MicroSD slot regulator to only support 3V3 and disable + * UHS modes in MicroSD slot node. + */ + if (!blob) + return; + + err = fdt_check_header(blob); + if (err < 0) { + printf("Invalid FDT header: %s\n", fdt_strerror(err)); + return; + } + + size = fdt_totalsize(blob); + err = fdt_open_into(blob, blob, size + 64); + if (err < 0) { + printf("Failed to expand DT\n"); + return; + } + + offs = fdt_path_offset(blob, "/regulator-vcc-sdhi"); + if (offs < 0) { + printf("Failed to locate MicroSD regulator node: %d\n", offs); + return; + } + + err = fdt_setprop_string(blob, offs, "compatible", "regulator-fixed"); + if (err < 0) { + printf("Failed to set fixed MicroSD regulator: %d\n", err); + return; + } + + err = fdt_setprop_u32(blob, offs, "regulator-min-microvolt", 3300000); + if (err < 0) { + printf("Failed to set MicroSD regulator minimum voltage: %d\n", err); + return; + } + + err = fdt_nop_property(blob, offs, "gpios"); + if (err < 0) { + printf("Failed to remove MicroSD regulator gpios: %d\n", err); + return; + } + + err = fdt_nop_property(blob, offs, "gpios-states"); + if (err < 0) { + printf("Failed to remove MicroSD regulator gpio states: %d\n", err); + return; + } + + err = fdt_nop_property(blob, offs, "states"); + if (err < 0) { + printf("Failed to remove MicroSD regulator states: %d\n", err); + return; + } + + offs = fdt_path_offset(blob, "/soc/mmc@ee140000"); + if (offs < 0) { + printf("Failed to locate MicroSD device node: %d\n", offs); + return; + } + + err = fdt_nop_property(blob, offs, "sd-uhs-sdr50"); + if (err < 0) { + printf("Failed to disable SDR50 mode in MicroSD node: %d\n", err); + return; + } + + err = fdt_nop_property(blob, offs, "sd-uhs-sdr104"); + if (err < 0) { + printf("Failed to disable SDR104 mode in MicroSD node: %d\n", err); + return; + } + + err = fdt_setprop_string(blob, offs, "pinctrl-names", "default"); + if (err < 0) { + printf("Failed to set fixed MicroSD pin names: %d\n", err); + return; + } + + err = fdt_nop_property(blob, offs, "pinctrl-1"); + if (err < 0) { + printf("Failed to disable UHS pins in MicroSD node: %d\n", err); + return; + } + + offs = fdt_path_offset(blob, "/soc/pinctrl@e6050000/avb0/pins-vddq18-25-avb"); + if (offs < 0) { + printf("Failed to locate AVB pinctrl node: %d\n", offs); + return; + } + + err = fdt_setprop_u32(blob, offs, "power-source", 2500); + if (err < 0) { + printf("Failed to set AVB IO voltage: %d\n", err); + return; + } +} #endif #define RST_MODEMR0 0xe6160000 @@ -130,7 +256,7 @@ void renesas_dram_init_banksize(void) int bank; /* 8 GiB device, do nothing. */ - if (!(modemr0 & BIT(19))) + if (!((renesas_get_cpu_rev_integer() >= 3) && (modemr0 & BIT(19)))) return; /* 16 GiB device, adjust memory map. */ diff --git a/board/rockchip/evb_rk3588/MAINTAINERS b/board/rockchip/evb_rk3588/MAINTAINERS index 1232f05a387..379c85f48a4 100644 --- a/board/rockchip/evb_rk3588/MAINTAINERS +++ b/board/rockchip/evb_rk3588/MAINTAINERS @@ -48,3 +48,9 @@ S: Maintained F: configs/orangepi-5-plus-rk3588_defconfig F: arch/arm/dts/rk3588-orangepi-5-plus.dts F: arch/arm/dts/rk3588-orangepi-5-plus-u-boot.dtsi + +ORANGEPI-5-RK3588-ULTRA +M: Niu Zhihong <zhihong@nzhnb.com> +S: Maintained +F: configs/orangepi-5-ultra-rk3588_defconfig +F: arch/arm/dts/rk3588-orangepi-5-ultra-u-boot.dtsi diff --git a/board/samsung/e850-96/Makefile b/board/samsung/e850-96/Makefile index 71d46ea3d2b..76b8d47994e 100644 --- a/board/samsung/e850-96/Makefile +++ b/board/samsung/e850-96/Makefile @@ -3,4 +3,4 @@ # Copyright (C) 2024, Linaro Limited # Sam Protsenko <semen.protsenko@linaro.org> -obj-y := e850-96.o fw.o +obj-y := e850-96.o fw.o acpm.o pmic.o diff --git a/board/samsung/e850-96/acpm.c b/board/samsung/e850-96/acpm.c new file mode 100644 index 00000000000..1cc5c6d0e4a --- /dev/null +++ b/board/samsung/e850-96/acpm.c @@ -0,0 +1,169 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2025 Linaro Ltd. + * Author: Sam Protsenko <semen.protsenko@linaro.org> + * + * ACPM (Active Clock and Power Management) is an IPC protocol for communicating + * with APM (Active Power Management) core. The message exchange between AP + * (Application Processor) and APM is happening by using shared memory in SRAM + * (iRAM) and generating interrupts using Mailbox block. By using this IPC + * interface it's possible to offload power management tasks to APM core, which + * acts as a supervisor for CPU. One of the main tasks of APM is controlling + * PMIC chip over I3C bus. So in order to access PMIC chip registers it's + * recommended to do so by sending corresponding commands to APM via ACPM IPC + * protocol. The IPC interaction sequence looks like this: + * + * AP (CPU) <-> ACPM IPC (Mailbox + SRAM) <-> APM <-> I3C <-> PMIC + * + * This file contains functions for accessing I3C bus via APM block using + * ACPM IPC. + */ + +#include <linux/iopoll.h> +#include <linux/time.h> +#include <asm/io.h> +#include "acpm.h" + +/* Mailbox registers */ +#define MBOX_INTGR0 0x8 /* Interrupt Generation */ +#define MBOX_INTCR1 0x20 /* Interrupt Clear */ +#define MBOX_INTSR1 0x28 /* Interrupt Status */ +#define MBOX_INTGR_OFFSET 16 +#define MBOX_TIMEOUT (1 * USEC_PER_SEC) + +/* APM shared memory registers */ +#define SHMEM_SR0 0x0 +#define SHMEM_SR1 0x4 +#define SHMEM_SR2 0x8 +#define SHMEM_SR3 0xc + +/* IPC functions */ +#define IPC_FUNC_READ 0x0 +#define IPC_FUNC_WRITE 0x1 +/* Command 0 shifts and masks */ +#define IPC_REG_SHIFT 0 +#define IPC_REG_MASK 0xff +#define IPC_TYPE_SHIFT 8 +#define IPC_TYPE_MASK 0xf +#define IPC_CHANNEL_SHIFT 12 +#define IPC_CHANNEL_MASK 0xf +/* Command 1 shifts and masks */ +#define IPC_FUNC_SHIFT 0 +#define IPC_FUNC_MASK 0xff +#define IPC_WRITE_VAL_SHIFT 8 +#define IPC_WRITE_VAL_MASK 0xff +/* Command 3 shifts and masks */ +#define IPC_DEST_SHIFT 8 +#define IPC_DEST_MASK 0xff +#define IPC_RETURN_SHIFT 24 +#define IPC_RETURN_MASK 0xff + +/** + * acpm_ipc_send_data_async() - Send data to I3C block over ACPM IPC + * @acpm: ACPM data + * @cmd0: Command 0 value to send + * @cmd1: Command 1 value to send + */ +static void acpm_ipc_send_data_async(struct acpm *acpm, u32 cmd0, u32 cmd1) +{ + u32 irq_bit = 1 << acpm->ipc_ch; + u32 intgr = irq_bit << MBOX_INTGR_OFFSET; + + /* Write data to the shared memory */ + writel(cmd0, acpm->sram_base + SHMEM_SR0); + writel(cmd1, acpm->sram_base + SHMEM_SR1); + dsb(); + + /* Generate interrupt for I3C block */ + writel(intgr, acpm->mbox_base + MBOX_INTGR0); +} + +/** + * acpm_ipc_wait_resp() - Read response data from I3C block over ACPM IPC + * @acpm: ACPM data + * @cmd2: Will contain read value for command 2 + * @cmd3: Will contain read value for command 3 + * + * Return: 0 on success or negative value on error. + */ +static int acpm_ipc_wait_resp(struct acpm *acpm, u32 *cmd2, u32 *cmd3) +{ + u32 irq_bit = 1 << acpm->ipc_ch; + u32 reg; + int ret; + + /* Wait for the interrupt from I3C block */ + ret = readl_poll_timeout(acpm->mbox_base + MBOX_INTSR1, reg, + reg & irq_bit, MBOX_TIMEOUT); + if (ret < 0) + return ret; + + /* Clear the interrupt */ + writel(irq_bit, acpm->mbox_base + MBOX_INTCR1); + + /* Read data from the shared memory */ + *cmd2 = readl(acpm->sram_base + SHMEM_SR2); + *cmd3 = readl(acpm->sram_base + SHMEM_SR3); + + return 0; +} + +/** + * acpm_i3c_read() - Read an I3C register of some I3C slave device + * @acpm: ACPM data + * @ch: I3C channel (bus) number (0-15) + * @addr: I3C address of slave device (0-15) + * @reg: Address of I3C register in the slave device to read from + * @val: Will contain the read value + * + * Return: 0 on success or non-zero code on error (may be positive). + */ +int acpm_i3c_read(struct acpm *acpm, u8 ch, u8 addr, u8 reg, u8 *val) +{ + u32 cmd[4] = { 0 }; + u8 ret; + + cmd[0] = (ch & IPC_CHANNEL_MASK) << IPC_CHANNEL_SHIFT | + (addr & IPC_TYPE_MASK) << IPC_TYPE_SHIFT | + (reg & IPC_REG_MASK) << IPC_REG_SHIFT; + cmd[1] = IPC_FUNC_READ << IPC_FUNC_SHIFT; + + acpm_ipc_send_data_async(acpm, cmd[0], cmd[1]); + ret = acpm_ipc_wait_resp(acpm, &cmd[2], &cmd[3]); + if (ret) + return ret; + + *val = (cmd[3] >> IPC_DEST_SHIFT) & IPC_DEST_MASK; + ret = (cmd[3] >> IPC_RETURN_SHIFT) & IPC_RETURN_MASK; + return ret; +} + +/** + * acpm_i3c_write() - Write an I3C register of some I3C slave device + * @acpm: ACPM data + * @ch: I3C channel (bus) number (0-15) + * @addr: I3C address of slave device (0-15) + * @reg: Address of I3C register in the slave device to write into + * @val: Value to write + * + * Return: 0 on success or non-zero code on error (may be positive). + */ +int acpm_i3c_write(struct acpm *acpm, u8 ch, u8 addr, u8 reg, u8 val) +{ + u32 cmd[4] = { 0 }; + u8 ret; + + cmd[0] = (ch & IPC_CHANNEL_MASK) << IPC_CHANNEL_SHIFT | + (addr & IPC_TYPE_MASK) << IPC_TYPE_SHIFT | + (reg & IPC_REG_MASK) << IPC_REG_SHIFT; + cmd[1] = IPC_FUNC_WRITE << IPC_FUNC_SHIFT | + (val & IPC_WRITE_VAL_MASK) << IPC_WRITE_VAL_SHIFT; + + acpm_ipc_send_data_async(acpm, cmd[0], cmd[1]); + ret = acpm_ipc_wait_resp(acpm, &cmd[2], &cmd[3]); + if (ret) + return ret; + + ret = (cmd[3] >> IPC_RETURN_SHIFT) & IPC_RETURN_MASK; + return ret; +} diff --git a/board/samsung/e850-96/acpm.h b/board/samsung/e850-96/acpm.h new file mode 100644 index 00000000000..9373969209f --- /dev/null +++ b/board/samsung/e850-96/acpm.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2025 Linaro Ltd. + * Sam Protsenko <semen.protsenko@linaro.org> + */ + +#ifndef __E850_96_ACPM_H +#define __E850_96_ACPM_H + +#include <linux/types.h> + +/** + * struct acpm - Data for I3C communication over ACPM IPC protocol + * @mbox_base: Base address of APM mailbox block + * @sram_base: Base address of shared memory used for APM messages + * @ipc_ch: Mailbox channel number used for communication with I3C block (0-15) + */ +struct acpm { + void __iomem *mbox_base; + void __iomem *sram_base; + u8 ipc_ch; +}; + +int acpm_i3c_read(struct acpm *acpm, u8 ch, u8 addr, u8 reg, u8 *val); +int acpm_i3c_write(struct acpm *acpm, u8 ch, u8 addr, u8 reg, u8 val); + +#endif /* __E850_96_ACPM_H */ diff --git a/board/samsung/e850-96/e850-96.c b/board/samsung/e850-96/e850-96.c index 4d4f8d14c6d..3df241edde2 100644 --- a/board/samsung/e850-96/e850-96.c +++ b/board/samsung/e850-96/e850-96.c @@ -4,8 +4,78 @@ * Author: Sam Protsenko <semen.protsenko@linaro.org> */ +#include <efi_loader.h> +#include <env.h> #include <init.h> +#include <mapmem.h> +#include <net.h> +#include <usb.h> +#include <asm/io.h> #include "fw.h" +#include "pmic.h" + +/* OTP Controller base address and register offsets */ +#define EXYNOS850_OTP_BASE 0x10000000 +#define OTP_CHIPID0 0x4 +#define OTP_CHIPID1 0x8 + +/* ACPM and PMIC definitions */ +#define EXYNOS850_MBOX_APM2AP_BASE 0x11900000 +#define EXYNOS850_APM_SRAM_BASE 0x02039000 /* in iRAM */ +#define EXYNOS850_APM_SHMEM_OFFSET 0x3200 +#define EXYNOS850_IPC_AP_I3C 10 + +/* LDFW firmware definitions */ +#define LDFW_NWD_ADDR 0x88000000 +#define EMMC_IFNAME "mmc" +#define EMMC_DEV_NUM 0 +#define EMMC_ESP_PART 1 + +struct efi_fw_image fw_images[] = { + { + .image_type_id = E850_96_FWBL1_IMAGE_GUID, + .fw_name = u"E850-96-FWBL1", + .image_index = 1, + }, + { + .image_type_id = E850_96_EPBL_IMAGE_GUID, + .fw_name = u"E850-96-EPBL", + .image_index = 2, + }, + { + .image_type_id = E850_96_BL2_IMAGE_GUID, + .fw_name = u"E850-96-BL2", + .image_index = 3, + }, + { + .image_type_id = E850_96_BOOTLOADER_IMAGE_GUID, + .fw_name = u"E850-96-BOOTLOADER", + .image_index = 4, + }, + { + .image_type_id = E850_96_EL3_MON_IMAGE_GUID, + .fw_name = u"E850-96-EL3-MON", + .image_index = 5, + }, +}; + +struct efi_capsule_update_info update_info = { + .dfu_string = "mmc 0=" + "fwbl1.img raw 0x0 0x18 mmcpart 1;" + "epbl.img raw 0x18 0x98 mmcpart 1;" + "bl2.img raw 0xb0 0x200 mmcpart 1;" + "bootloader.img raw 0x438 0x1000 mmcpart 1;" + "el3_mon.img raw 0x1438 0x200 mmcpart 1", + .num_images = ARRAY_SIZE(fw_images), + .images = fw_images, +}; + +static struct acpm acpm = { + .mbox_base = (void __iomem *)EXYNOS850_MBOX_APM2AP_BASE, + .sram_base = (void __iomem *)(EXYNOS850_APM_SRAM_BASE + + EXYNOS850_APM_SHMEM_OFFSET), + .ipc_ch = EXYNOS850_IPC_AP_I3C, +}; int dram_init(void) { @@ -17,17 +87,101 @@ int dram_init_banksize(void) return fdtdec_setup_memory_banksize(); } -int board_late_init(void) +/* Read the unique SoC ID from OTP registers */ +static u64 get_chip_id(void) +{ + void __iomem *otp_base; + u64 val; + + otp_base = map_sysmem(EXYNOS850_OTP_BASE, 12); + val = readl(otp_base + OTP_CHIPID0); + val |= (u64)readl(otp_base + OTP_CHIPID1) << 32UL; + unmap_sysmem(otp_base); + + return val; +} + +static void setup_serial(void) +{ + char serial_str[17] = { 0 }; + u64 serial_num; + + if (env_get("serial#")) + return; + + serial_num = get_chip_id(); + snprintf(serial_str, sizeof(serial_str), "%016llx", serial_num); + env_set("serial#", serial_str); +} + +static void setup_ethaddr(void) +{ + u64 serial_num; + u32 mac_hi, mac_lo; + u8 mac_addr[6]; + + if (env_get("ethaddr")) + return; + + serial_num = get_chip_id(); + mac_lo = (u32)serial_num; /* OTP_CHIPID0 */ + mac_hi = (u32)(serial_num >> 32UL); /* OTP_CHIPID1 */ + mac_addr[0] = (mac_hi >> 8) & 0xff; + mac_addr[1] = mac_hi & 0xff; + mac_addr[2] = (mac_lo >> 24) & 0xff; + mac_addr[3] = (mac_lo >> 16) & 0xff; + mac_addr[4] = (mac_lo >> 8) & 0xff; + mac_addr[5] = mac_lo & 0xff; + mac_addr[0] &= ~0x1; /* make sure it's not a multicast address */ + if (is_valid_ethaddr(mac_addr)) + eth_env_set_enetaddr("ethaddr", mac_addr); +} + +/* + * Call this in board_late_init() to avoid probing block devices before + * efi_init_early(). + */ +void load_firmware(void) { + const char *ifname; + ulong dev, part; int err; - /* - * Do this in board_late_init() to make sure MMC is not probed before - * efi_init_early(). - */ - err = load_ldfw(); + ifname = env_get("bootdev"); + if (!ifname) + ifname = EMMC_IFNAME; + dev = env_get_ulong("bootdevnum", 10, EMMC_DEV_NUM); + part = env_get_ulong("bootdevpart", 10, EMMC_ESP_PART); + + if (!strcmp(ifname, "usb")) { + printf("Starting USB (bootdev=usb)...\n"); + err = usb_init(); + if (err) + return; + } + + printf("Loading LDFW firmware (from %s %ld)...\n", ifname, dev); + err = load_ldfw(ifname, dev, part, LDFW_NWD_ADDR); if (err) printf("ERROR: LDFW loading failed (%d)\n", err); +} + +int board_late_init(void) +{ + setup_serial(); + setup_ethaddr(); + load_firmware(); + + return 0; +} + +int power_init_board(void) +{ + int err; + + err = pmic_init(&acpm); + if (err) + printf("ERROR: Failed to configure PMIC (%d)\n", err); return 0; } diff --git a/board/samsung/e850-96/e850-96.env b/board/samsung/e850-96/e850-96.env index 5ac76bcef02..992318b0ab2 100644 --- a/board/samsung/e850-96/e850-96.env +++ b/board/samsung/e850-96/e850-96.env @@ -5,7 +5,51 @@ fdt_addr_r=0x8c000000 scriptaddr=0x8c100000 pxefile_addr_r=0x8c200000 ramdisk_addr_r=0x8c300000 -fdtfile=CONFIG_DEFAULT_FDT_FILE +fdtfile=exynos/exynos850-e850-96.dtb + +dfu_alt_info= + rawemmc raw 0 0x747c000 mmcpart 1; + esp part 0 1; + rootfs part 0 2; + fwbl1 raw 0x0 0x18 mmcpart 1; + epbl raw 0x18 0x98 mmcpart 1; + bl2 raw 0xb0 0x200 mmcpart 1; + dram_train raw 0x2b0 0x20 mmcpart 1; + ect_test raw 0x2d0 0x64 mmcpart 1; + acpm_test raw 0x334 0x104 mmcpart 1; + bootloader raw 0x438 0x1000 mmcpart 1; + el3_mon raw 0x1438 0x200 mmcpart 1 partitions=name=esp,start=512K,size=128M,bootable,type=system; partitions+=name=rootfs,size=-,bootable,type=linux + +partitions_android=name=esp,start=512K,size=128M,bootable,type=system; +partitions_android+=name=efs,size=20M,uuid=${uuid_gpt_efs}; +partitions_android+=name=env,size=16K,uuid=${uuid_gpt_env}; +partitions_android+=name=kernel,size=30M,uuid=${uuid_gpt_kernel}; +partitions_android+=name=ramdisk,size=26M,uuid=${uuid_gpt_ramdisk}; +partitions_android+=name=dtbo_a,size=1M,uuid=${uuid_gpt_dtbo}; +partitions_android+=name=dtbo_b,size=1M,uuid=${uuid_gpt_dtbo}; +partitions_android+=name=ldfw,size=4016K,uuid=${uuid_gpt_ldfw}; +partitions_android+=name=keystorage,size=8K,uuid=${uuid_gpt_keystorage}; +partitions_android+=name=tzsw,size=1M,uuid=${uuid_gpt_tzsw}; +partitions_android+=name=harx,size=2M,uuid=${uuid_gpt_harx}; +partitions_android+=name=harx_rkp,size=2M,uuid=${uuid_gpt_harx_rkp}; +partitions_android+=name=logo,size=40M,uuid=${uuid_gpt_logo}; +partitions_android+=name=super,size=3600M,uuid=${uuid_gpt_super}; +partitions_android+=name=cache,size=300M,uuid=${uuid_gpt_cache}; +partitions_android+=name=modem,size=100M,uuid=${uuid_gpt_modem}; +partitions_android+=name=boot_a,size=100M,uuid=${uuid_gpt_boot}; +partitions_android+=name=boot_b,size=100M,uuid=${uuid_gpt_boot}; +partitions_android+=name=persist,size=30M,uuid=${uuid_gpt_persist}; +partitions_android+=name=recovery_a,size=40M,uuid=${uuid_gpt_recovery}; +partitions_android+=name=recovery_b,size=40M,uuid=${uuid_gpt_recovery}; +partitions_android+=name=misc,size=40M,uuid=${uuid_gpt_misc}; +partitions_android+=name=mnv,size=20M,uuid=${uuid_gpt_mnv}; +partitions_android+=name=frp,size=512K,uuid=${uuid_gpt_frp}; +partitions_android+=name=vbmeta_a,size=64K,uuid=${uuid_gpt_vbmeta}; +partitions_android+=name=vbmeta_b,size=64K,uuid=${uuid_gpt_vbmeta}; +partitions_android+=name=metadata,size=16M,uuid=${uuid_gpt_metadata}; +partitions_android+=name=dtb_a,size=1M,uuid=${uuid_gpt_dtb}; +partitions_android+=name=dtb_b,size=1M,uuid=${uuid_gpt_dtb}; +partitions_android+=name=userdata,size=-,uuid=${uuid_gpt_userdata} diff --git a/board/samsung/e850-96/fw.c b/board/samsung/e850-96/fw.c index 8f64e759b43..64235c01a25 100644 --- a/board/samsung/e850-96/fw.c +++ b/board/samsung/e850-96/fw.c @@ -11,13 +11,9 @@ #include <linux/arm-smccc.h> #include "fw.h" -#define EMMC_IFACE "mmc" -#define EMMC_DEV_NUM 0 #define LDFW_RAW_PART "ldfw" -#define LDFW_FAT_PART "esp" #define LDFW_FAT_PATH "/EFI/firmware/ldfw.bin" -#define LDFW_NWD_ADDR 0x88000000 #define LDFW_MAGIC 0x10adab1e #define SMC_CMD_LOAD_LDFW -0x500 #define SDM_HW_RESET_STATUS 0x1230 @@ -39,19 +35,23 @@ struct ldfw_header { }; /* Load LDFW binary as a file from FAT partition */ -static int read_fw_from_fat(const char *part_name, const char *path, void *buf) +static int read_fw_from_fat(const char *ifname, int dev, int part, + const char *path, void *buf) { - char dev_part_str[8]; + struct blk_desc *blk_desc; loff_t len_read; int err; - snprintf(dev_part_str, sizeof(dev_part_str), "%d#%s", EMMC_DEV_NUM, - LDFW_FAT_PART); + blk_desc = blk_get_dev(ifname, dev); + if (!blk_desc) { + debug("%s: Can't get block device\n", __func__); + return -ENODEV; + } - err = fs_set_blk_dev(EMMC_IFACE, dev_part_str, FS_TYPE_FAT); + err = fs_set_blk_dev_with_part(blk_desc, part); if (err) { - debug("%s: Can't set block device\n", __func__); - return -ENODEV; + debug("%s: Can't set partition\n", __func__); + return -ENOENT; } err = fs_read(path, (ulong)buf, 0, 0, &len_read); @@ -64,16 +64,17 @@ static int read_fw_from_fat(const char *part_name, const char *path, void *buf) } /* Load LDFW binary from raw partition on block device into RAM buffer */ -static int read_fw_from_raw(const char *part_name, void *buf) +static int read_fw_from_raw(const char *ifname, int dev, const char *part_name, + void *buf) { struct blk_desc *blk_desc; struct disk_partition part; unsigned long cnt; int part_num; - blk_desc = blk_get_dev(EMMC_IFACE, EMMC_DEV_NUM); + blk_desc = blk_get_dev(ifname, dev); if (!blk_desc) { - debug("%s: Can't get eMMC device\n", __func__); + debug("%s: Can't get block device\n", __func__); return -ENODEV; } @@ -92,9 +93,17 @@ static int read_fw_from_raw(const char *part_name, void *buf) return 0; } -int load_ldfw(void) +/** + * load_ldfw - Load the loadable firmware (LDFW) + * @ifname: Interface name of the block device to load the firmware from + * @dev: Device number + * @part: Partition number + * @addr: Temporary memory (Normal World) to use for loading the firmware + * + * Return: 0 on success or a negative value on error. + */ +int load_ldfw(const char *ifname, int dev, int part, phys_addr_t addr) { - const phys_addr_t addr = (phys_addr_t)LDFW_NWD_ADDR; struct ldfw_header *hdr; struct arm_smccc_res res; void *buf = (void *)addr; @@ -102,9 +111,9 @@ int load_ldfw(void) int err, i; /* First try to read LDFW from EFI partition, then from the raw one */ - err = read_fw_from_fat(LDFW_FAT_PART, LDFW_FAT_PATH, buf); + err = read_fw_from_fat(ifname, dev, part, LDFW_FAT_PATH, buf); if (err) { - err = read_fw_from_raw(LDFW_RAW_PART, buf); + err = read_fw_from_raw(ifname, dev, LDFW_RAW_PART, buf); if (err) return err; } diff --git a/board/samsung/e850-96/fw.h b/board/samsung/e850-96/fw.h index 472664e4ed2..73d9615d4a9 100644 --- a/board/samsung/e850-96/fw.h +++ b/board/samsung/e850-96/fw.h @@ -7,6 +7,8 @@ #ifndef __E850_96_FW_H #define __E850_96_FW_H -int load_ldfw(void); +#include <asm/types.h> + +int load_ldfw(const char *ifname, int dev, int part, phys_addr_t addr); #endif /* __E850_96_FW_H */ diff --git a/board/samsung/e850-96/pmic.c b/board/samsung/e850-96/pmic.c new file mode 100644 index 00000000000..037fd4844c5 --- /dev/null +++ b/board/samsung/e850-96/pmic.c @@ -0,0 +1,144 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2025 Linaro Ltd. + * Author: Sam Protsenko <semen.protsenko@linaro.org> + * + * This file contains functions for S2MPU12 PMIC regulators configuration. + * + * Example of voltage calculation for LDO24 and LDO32: + * - V_min = 1800 mV + * - V_step = 25 mV + * - V_wanted = 3300 mV + * - register value: (V_wanted - V_min) / V_step = 60 = 0x3c + * + * NOTE: 0x3c value might mean different voltage for other LDOs. + */ + +#include <linux/errno.h> +#include <linux/kernel.h> +#include "pmic.h" + +/* PMIC definitions */ +#define S2MPU12_CHANNEL 0 /* I3C bus number of PMIC */ +#define S2MPU12_PM_ADDR 0x1 /* I3C slave addr of PM part */ + +/* PMIC I3C registers */ +#define S2MPU12_PM_LDO1_CTRL 0x2b +#define S2MPU12_PM_LDO_CTRL(n) (S2MPU12_PM_LDO1_CTRL + (n) - 1) + +/* LDOx_CTRL values */ +#define S2MPU12_LDO_CTRL_OUT_MASK (0x3 << 6) +#define S2MPU12_LDO_CTRL_OUT_ALWAYS_ON (0x3 << 6) + +struct pmic_ldo { + u8 num; /* LDO number */ + u8 en; /* "enable" bits value in LDOx_CTRL register */ + u8 out; /* "output voltage" bits value in LDOx_CTRL register */ +}; + +/* List of LDOs to enable only */ +static u8 pmic_ldos_en[] = { + 2, /* 1.8V/450mA: multiple lines */ + 11, /* 3.0V/150mA: AVDD33_USB20 */ + 23, /* 2.85V/800mA: VDD_EMMC_2P85 */ + 27, /* 3.0V/150mA: MIPI_SWITCH_3V3 */ + 28, /* 1.8V/150mA: HDMI_CONV_1V8 */ + 30, /* 1.8V/150mA: NPU_VDD18 */ +}; + +/* List of LDOs to enable and set output voltage */ +static struct pmic_ldo pmic_ldos_en_out[] = { + { + .num = 24, /* 3.0V/800mA: VDD_LAN (LAN9514) */ + .en = S2MPU12_LDO_CTRL_OUT_ALWAYS_ON, + .out = 0x3c, /* means 3.3V for LDO24 */ + }, { + .num = 32, /* 3.3V/300mA: CAM_VDD (RPi camera module) */ + .en = S2MPU12_LDO_CTRL_OUT_ALWAYS_ON, + .out = 0x3c, /* means 3.3V for LDO32 */ + }, +}; + +/* Enable specified LDO */ +static int pmic_ldo_set_en(struct acpm *acpm, u8 ldo) +{ + const u8 reg = S2MPU12_PM_LDO_CTRL(ldo); + u8 val; + int err; + + err = acpm_i3c_read(acpm, S2MPU12_CHANNEL, S2MPU12_PM_ADDR, reg, &val); + if (err) + return err; + + val &= ~S2MPU12_LDO_CTRL_OUT_MASK; + val |= S2MPU12_LDO_CTRL_OUT_ALWAYS_ON; + + return acpm_i3c_write(acpm, S2MPU12_CHANNEL, S2MPU12_PM_ADDR, reg, val); +} + +/* Enable specified LDO and set its voltage to 0xc0 value */ +static int pmic_ldo_set_en_out(struct acpm *acpm, struct pmic_ldo *ldo) +{ + const u8 reg = S2MPU12_PM_LDO_CTRL(ldo->num); + const u8 val = ldo->en | ldo->out; + + return acpm_i3c_write(acpm, S2MPU12_CHANNEL, S2MPU12_PM_ADDR, reg, val); +} + +#ifdef DEBUG +static void pmic_trace_ldo(struct acpm *acpm, u8 ldo) +{ + const u8 reg = S2MPU12_PM_LDO_CTRL(ldo); + u8 val; + int err; + + err = acpm_i3c_read(acpm, S2MPU12_CHANNEL, S2MPU12_PM_ADDR, reg, &val); + if (err) + printf(" S2MPU12_PM_LDO%u_CTRL: Read error!\n", ldo); + else + printf(" S2MPU12_PM_LDO%u_CTRL: 0x%x\n", ldo, val); +} + +static void pmic_trace_ldos(struct acpm *acpm) +{ + size_t i; + + printf("Tracing LDOs...\n"); + for (i = 0; i < ARRAY_SIZE(pmic_ldos_en); ++i) + pmic_trace_ldo(acpm, pmic_ldos_en[i]); + for (i = 0; i < ARRAY_SIZE(pmic_ldos_en_out); ++i) + pmic_trace_ldo(acpm, pmic_ldos_en_out[i].num); +} +#endif + +/** + * pmic_init() - Enable power regulators in S2MPU12 PMIC. + * @acpm: Data for I3C communication with PMIC over ACPM protocol + * + * Enable LDOs needed for devices used in the bootloader and kernel. + * + * Return: 0 on success or non-zero code on error. + */ +int pmic_init(struct acpm *acpm) +{ + size_t i; + int err; + + for (i = 0; i < ARRAY_SIZE(pmic_ldos_en); ++i) { + err = pmic_ldo_set_en(acpm, pmic_ldos_en[i]); + if (err) + return -EIO; + } + + for (i = 0; i < ARRAY_SIZE(pmic_ldos_en_out); ++i) { + err = pmic_ldo_set_en_out(acpm, &pmic_ldos_en_out[i]); + if (err) + return -EIO; + } + +#ifdef DEBUG + pmic_trace_ldos(acpm); +#endif + + return 0; +} diff --git a/board/samsung/e850-96/pmic.h b/board/samsung/e850-96/pmic.h new file mode 100644 index 00000000000..46624c2ebd4 --- /dev/null +++ b/board/samsung/e850-96/pmic.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2025 Linaro Ltd. + * Sam Protsenko <semen.protsenko@linaro.org> + */ + +#ifndef __E850_96_PMIC_H +#define __E850_96_PMIC_H + +#include "acpm.h" + +int pmic_init(struct acpm *acpm); + +#endif /* __E850_96_PMIC_H */ diff --git a/board/samsung/n1/Kconfig b/board/samsung/n1/Kconfig new file mode 100644 index 00000000000..a5e5edda9e2 --- /dev/null +++ b/board/samsung/n1/Kconfig @@ -0,0 +1,13 @@ +if TARGET_SAMSUNG_N1 + +config SYS_BOARD + default "n1" + +config SYS_VENDOR + default "samsung" + +config TEGRA_BOARD_STRING + string "Default Tegra board name" + default "Samsung N1" + +endif diff --git a/board/samsung/n1/MAINTAINERS b/board/samsung/n1/MAINTAINERS new file mode 100644 index 00000000000..798cb56cd37 --- /dev/null +++ b/board/samsung/n1/MAINTAINERS @@ -0,0 +1,9 @@ +N1 BOARD +M: Ion Agorria <ion@agorria.com> +M: Svyatoslav Ryhel <clamor95@gmail.com> +S: Maintained +F: arch/arm/dts/tegra20-samsung-bose.dts +F: arch/arm/dts/tegra20-samsung-n1.dts +F: board/samsung/n1/ +F: configs/n1_defconfig +F: doc/board/samsung/n1.rst diff --git a/board/samsung/n1/bose.config b/board/samsung/n1/bose.config new file mode 100644 index 00000000000..6d6d9d3f2ce --- /dev/null +++ b/board/samsung/n1/bose.config @@ -0,0 +1,6 @@ +CONFIG_DEFAULT_DEVICE_TREE="tegra20-samsung-bose" +CONFIG_SYS_PROMPT="Tegra20 (Bose) # " +# CONFIG_VIDEO_BRIDGE_SAMSUNG_CMC623 is not set +# CONFIG_BACKLIGHT_SAMSUNG_CMC623 is not set +# CONFIG_VIDEO_LCD_SONY_L4F00430T01 is not set +CONFIG_VIDEO_LCD_SAMSUNG_S6E63M0=y diff --git a/board/samsung/n1/n1.env b/board/samsung/n1/n1.env new file mode 100644 index 00000000000..e2b883dbc10 --- /dev/null +++ b/board/samsung/n1/n1.env @@ -0,0 +1,16 @@ +#include <env/nvidia/prod_upd.env> + +button_cmd_0_name=Volume Down +button_cmd_0=bootmenu + +boot_block_size_r=0x80000 +boot_block_size=0x400 +boot_dev=1 + +bootmenu_0=mount internal storage=usb start && ums 0 mmc 0; bootmenu +bootmenu_1=mount external storage=usb start && ums 0 mmc 1; bootmenu +bootmenu_2=fastboot=echo Starting Fastboot protocol ...; fastboot usb 0; bootmenu +bootmenu_3=reboot RCM=enterrcm +bootmenu_4=reboot=reset +bootmenu_5=power off=poweroff +bootmenu_delay=-1 diff --git a/board/siemens/capricorn/MAINTAINERS b/board/siemens/capricorn/MAINTAINERS index 9c8c7a6ecdc..6c253983cf0 100644 --- a/board/siemens/capricorn/MAINTAINERS +++ b/board/siemens/capricorn/MAINTAINERS @@ -1,6 +1,6 @@ CAPRICORN BOARD M: Alexander Sverdlin <alexander.sverdlin@siemens.com> -M: Heiko Schocher <hs@denx.de> +M: Heiko Schocher <hs@nabladev.com> M: Walter Schweizer <walter.schweizer@siemens.com> S: Maintained F: arch/arm/dts/imx8-capricorn-cxg3.dts diff --git a/board/siemens/corvus/MAINTAINERS b/board/siemens/corvus/MAINTAINERS index 59176aae575..4471cf3ce3c 100644 --- a/board/siemens/corvus/MAINTAINERS +++ b/board/siemens/corvus/MAINTAINERS @@ -1,5 +1,5 @@ CORVUS BOARD -M: Heiko Schocher <hs@denx.de> +M: Heiko Schocher <hs@nabladev.com> S: Maintained F: board/siemens/corvus/ F: include/configs/corvus.h diff --git a/board/siemens/smartweb/MAINTAINERS b/board/siemens/smartweb/MAINTAINERS index 51298ffb5d6..09d7667241c 100644 --- a/board/siemens/smartweb/MAINTAINERS +++ b/board/siemens/smartweb/MAINTAINERS @@ -1,5 +1,5 @@ SMARTWEB_HW BOARD -M: Heiko Schocher <hs@denx.de> +M: Heiko Schocher <hs@nabladev.com> S: Maintained F: board/siemens/smartweb F: include/configs/smartweb.h diff --git a/board/siemens/taurus/MAINTAINERS b/board/siemens/taurus/MAINTAINERS index 74e3518e0d9..c17bd51a0de 100644 --- a/board/siemens/taurus/MAINTAINERS +++ b/board/siemens/taurus/MAINTAINERS @@ -1,5 +1,5 @@ TAURUS BOARD -M: Heiko Schocher <hs@denx.de> +M: Heiko Schocher <hs@nabladev.com> S: Maintained F: board/siemens/taurus/ F: include/configs/taurus.h diff --git a/board/socrates/MAINTAINERS b/board/socrates/MAINTAINERS index 2b27a73c18c..d5571b0da4f 100644 --- a/board/socrates/MAINTAINERS +++ b/board/socrates/MAINTAINERS @@ -1,5 +1,5 @@ SOCRATES BOARD -M: Heiko Schocher <hs@denx.de> +M: Heiko Schocher <hs@nabladev.com> S: Maintained F: board/socrates/ F: include/configs/socrates.h diff --git a/board/st/common/Kconfig b/board/st/common/Kconfig index 5efac658cf4..94ec806949b 100644 --- a/board/st/common/Kconfig +++ b/board/st/common/Kconfig @@ -1,7 +1,7 @@ config CMD_STBOARD bool "stboard - command for OTP board information" depends on ARCH_STM32MP - default y if TARGET_ST_STM32MP25X || TARGET_ST_STM32MP15X || TARGET_ST_STM32MP13X + default y if TARGET_ST_STM32MP13X || TARGET_ST_STM32MP15X || TARGET_ST_STM32MP23X || TARGET_ST_STM32MP25X help This compile the stboard command to read and write the board in the OTP. diff --git a/board/st/common/stpmic1.c b/board/st/common/stpmic1.c index 45c2bb5bcea..b46f89dacb9 100644 --- a/board/st/common/stpmic1.c +++ b/board/st/common/stpmic1.c @@ -14,8 +14,19 @@ #include <power/pmic.h> #include <power/stpmic1.h> +static bool is_stm32mp13xx(void) +{ + if (!IS_ENABLED(CONFIG_STM32MP13X)) + return false; + + return of_machine_is_compatible("st,stm32mp131") || + of_machine_is_compatible("st,stm32mp133") || + of_machine_is_compatible("st,stm32mp135"); +} + int board_ddr_power_init(enum ddr_type ddr_type) { + bool is_mp13 = is_stm32mp13xx(); struct udevice *dev; bool buck3_at_1800000v = false; int ret; @@ -30,18 +41,21 @@ int board_ddr_power_init(enum ddr_type ddr_type) switch (ddr_type) { case STM32MP_DDR3: /* VTT = Set LDO3 to sync mode */ - ret = pmic_reg_read(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3)); - if (ret < 0) - return ret; - - ret &= ~STPMIC1_LDO3_MODE; - ret &= ~STPMIC1_LDO12356_VOUT_MASK; - ret |= STPMIC1_LDO_VOUT(STPMIC1_LDO3_DDR_SEL); - - ret = pmic_reg_write(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3), - ret); - if (ret < 0) - return ret; + if (!is_mp13) { + /* Enable VTT only on STM32MP15xx */ + ret = pmic_reg_read(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3)); + if (ret < 0) + return ret; + + ret &= ~STPMIC1_LDO3_MODE; + ret &= ~STPMIC1_LDO12356_VOUT_MASK; + ret |= STPMIC1_LDO_VOUT(STPMIC1_LDO3_DDR_SEL); + + ret = pmic_reg_write(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3), + ret); + if (ret < 0) + return ret; + } /* VDD_DDR = Set BUCK2 to 1.35V */ ret = pmic_clrsetbits(dev, @@ -69,11 +83,14 @@ int board_ddr_power_init(enum ddr_type ddr_type) mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS); /* Enable VTT = LDO3 */ - ret = pmic_clrsetbits(dev, - STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3), - STPMIC1_LDO_ENA, STPMIC1_LDO_ENA); - if (ret < 0) - return ret; + if (!is_mp13) { + /* Enable VTT only on STM32MP15xx */ + ret = pmic_clrsetbits(dev, + STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3), + STPMIC1_LDO_ENA, STPMIC1_LDO_ENA); + if (ret < 0) + return ret; + } mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS); diff --git a/board/st/stm32mp1/debug_uart.c b/board/st/stm32mp1/debug_uart.c index 24e3f9f2201..4c2149e0480 100644 --- a/board/st/stm32mp1/debug_uart.c +++ b/board/st/stm32mp1/debug_uart.c @@ -9,17 +9,32 @@ #include <asm/arch/stm32.h> #include <linux/bitops.h> +#if IS_ENABLED(CONFIG_STM32MP13X) +#define RCC_MP_APB1ENSETR (STM32_RCC_BASE + 0x0700) +#define RCC_MP_AHB4ENSETR (STM32_RCC_BASE + 0x0768) +#elif IS_ENABLED(CONFIG_STM32MP15X) #define RCC_MP_APB1ENSETR (STM32_RCC_BASE + 0x0A00) #define RCC_MP_AHB4ENSETR (STM32_RCC_BASE + 0x0A28) +#endif +#define GPIOA_BASE 0x50002000 #define GPIOG_BASE 0x50008000 void board_debug_uart_init(void) { - if (CONFIG_DEBUG_UART_BASE == STM32_UART4_BASE) { - /* UART4 clock enable */ - setbits_le32(RCC_MP_APB1ENSETR, BIT(16)); + if (CONFIG_DEBUG_UART_BASE != STM32_UART4_BASE) + return; + /* UART4 clock enable */ + setbits_le32(RCC_MP_APB1ENSETR, BIT(16)); + + if (IS_ENABLED(CONFIG_STM32MP13X)) { + /* GPIOA clock enable */ + writel(BIT(0), RCC_MP_AHB4ENSETR); + /* GPIO configuration for DH boards: Uart4 TX = A9 */ + writel(0xfffbffff, GPIOA_BASE + 0x00); + writel(0x00000080, GPIOA_BASE + 0x24); + } else if (IS_ENABLED(CONFIG_STM32MP15X)) { /* GPIOG clock enable */ writel(BIT(6), RCC_MP_AHB4ENSETR); /* GPIO configuration for ST boards: Uart4 TX = G11 */ diff --git a/board/st/stm32mp2/Kconfig b/board/st/stm32mp2/Kconfig index f91e25f1f9a..e88c71a278e 100644 --- a/board/st/stm32mp2/Kconfig +++ b/board/st/stm32mp2/Kconfig @@ -1,3 +1,17 @@ +if TARGET_ST_STM32MP23X + +config SYS_BOARD + default "stm32mp2" + +config SYS_VENDOR + default "st" + +config SYS_CONFIG_NAME + default "stm32mp23_st_common" + +source "board/st/common/Kconfig" +endif + if TARGET_ST_STM32MP25X config SYS_BOARD diff --git a/board/starfive/visionfive2/spl.c b/board/starfive/visionfive2/spl.c index 3dfa931b655..9dfe0bea5f1 100644 --- a/board/starfive/visionfive2/spl.c +++ b/board/starfive/visionfive2/spl.c @@ -126,19 +126,11 @@ int board_fit_config_name_match(const char *name) !strncmp(get_product_id_from_eeprom(), "STAR64", 6)) { return 0; } else if (!strcmp(name, "starfive/jh7110-starfive-visionfive-2-v1.2a") && - !strncmp(get_product_id_from_eeprom(), "VF7110", 6)) { - switch (get_pcb_revision_from_eeprom()) { - case 'a': - case 'A': - return 0; - } + !strncmp(get_product_id_from_eeprom(), "VF7110A", 7)) { + return 0; } else if (!strcmp(name, "starfive/jh7110-starfive-visionfive-2-v1.3b") && - !strncmp(get_product_id_from_eeprom(), "VF7110", 6)) { - switch (get_pcb_revision_from_eeprom()) { - case 'b': - case 'B': - return 0; - } + !strncmp(get_product_id_from_eeprom(), "VF7110B", 7)) { + return 0; } return -EINVAL; diff --git a/board/starfive/visionfive2/starfive_visionfive2.c b/board/starfive/visionfive2/starfive_visionfive2.c index bfbb11a2ee7..6271974b9c7 100644 --- a/board/starfive/visionfive2/starfive_visionfive2.c +++ b/board/starfive/visionfive2/starfive_visionfive2.c @@ -59,20 +59,10 @@ static void set_fdtfile(void) fdtfile = "starfive/jh7110-milkv-mars.dtb"; } else if (!strncmp(get_product_id_from_eeprom(), "STAR64", 6)) { fdtfile = "starfive/jh7110-pine64-star64.dtb"; - } else if (!strncmp(get_product_id_from_eeprom(), "VF7110", 6)) { - switch (get_pcb_revision_from_eeprom()) { - case 'a': - case 'A': - fdtfile = "starfive/jh7110-starfive-visionfive-2-v1.2a.dtb"; - break; - case 'b': - case 'B': - fdtfile = "starfive/jh7110-starfive-visionfive-2-v1.3b.dtb"; - break; - default: - log_err("Unknown revision\n"); - return; - } + } else if (!strncmp(get_product_id_from_eeprom(), "VF7110A", 7)) { + fdtfile = "starfive/jh7110-starfive-visionfive-2-v1.2a.dtb"; + } else if (!strncmp(get_product_id_from_eeprom(), "VF7110B", 7)) { + fdtfile = "starfive/jh7110-starfive-visionfive-2-v1.3b.dtb"; } else { log_err("Unknown product\n"); return; diff --git a/board/starfive/visionfive2/visionfive2-i2c-eeprom.c b/board/starfive/visionfive2/visionfive2-i2c-eeprom.c index 010e386e64d..17a44020bcf 100644 --- a/board/starfive/visionfive2/visionfive2-i2c-eeprom.c +++ b/board/starfive/visionfive2/visionfive2-i2c-eeprom.c @@ -275,7 +275,7 @@ static int prog_eeprom(unsigned int size) if (is_match_magic()) { printf("MAGIC ERROR, Please check the data@%p.\n", pbuf.buf); - return -1; + return CMD_RET_FAILURE; } ret = i2c_get_chip_for_busnum(CONFIG_SYS_EEPROM_BUS_NUM, @@ -285,7 +285,7 @@ static int prog_eeprom(unsigned int size) if (ret) { printf("Get i2c bus:%d addr:%d fail.\n", CONFIG_SYS_EEPROM_BUS_NUM, CONFIG_SYS_I2C_EEPROM_ADDR); - return ret; + return CMD_RET_FAILURE; } for (i = 0, p = (u8 *)pbuf.buf; i < size; ) { @@ -314,11 +314,11 @@ static int prog_eeprom(unsigned int size) if (ret) { has_been_read = -1; printf("Programming failed.\n"); - return -1; + return CMD_RET_FAILURE; } printf("Programming passed.\n"); - return 0; + return CMD_RET_SUCCESS; } /** diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS index 1b4b7d87163..e00b54f4535 100644 --- a/board/sunxi/MAINTAINERS +++ b/board/sunxi/MAINTAINERS @@ -137,6 +137,11 @@ M: Chris Morgan <macromorgan@hotmail.com> S: Maintained F: configs/anbernic_rg35xx_h700_defconfig +AVAOTA A1 BOARD +M: Andre Przywara <andre.przywara@arm.com> +S: Maintained +F: configs/avaota-a1_defconfig + BANANAPI M1 PLUS M: Jagan Teki <jagan@amarulasolutions.com> S: Maintained @@ -531,6 +536,11 @@ M: Quentin Schulz <quentin.schulz@free-electrons.com> S: Maintained F: configs/parrot_r16_defconfig +RADXA CUBIE A5E BOARD +M: Andre Przywara <andre.przywara@arm.com> +S: Maintained +F: configs/radxa-cubie-a5e_defconfig + SINLINX SINA31s BOARD M: Chen-Yu Tsai <wens@csie.org> S: Maintained @@ -591,6 +601,11 @@ M: Andre Przywara <andre.przywara@arm.com> S: Maintained F: configs/x96_mate_defconfig +X96Q PRO+ TV BOX +M: Andre Przywara <andre.przywara@arm.com> +S: Maintained +F: configs/x96q_pro_plus_defconfig + YONES TOPTECH BD1078 BOARD M: Paul Kocialkowski <contact@paulk.fr> S: Maintained diff --git a/board/sunxi/board.c b/board/sunxi/board.c index 943b6221b8a..2929bc17f08 100644 --- a/board/sunxi/board.c +++ b/board/sunxi/board.c @@ -118,6 +118,10 @@ void i2c_init_board(void) clock_twi_onoff(5, 1); sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN50I_H616_GPL_R_TWI); sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN50I_H616_GPL_R_TWI); +#elif CONFIG_MACH_SUN55I_A523 + clock_twi_onoff(5, 1); + sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN50I_GPL_R_TWI); + sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN50I_GPL_R_TWI); #else clock_twi_onoff(5, 1); sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_H3_GPL_R_TWI); @@ -435,7 +439,8 @@ static void mmc_pinmux_setup(int sdc) sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); sunxi_gpio_set_drv(pin, 2); } -#elif defined(CONFIG_MACH_SUN50I_H616) || defined(CONFIG_MACH_SUN50I_A133) +#elif defined(CONFIG_MACH_SUN50I_H616) || defined(CONFIG_MACH_SUN50I_A133) || \ + defined(CONFIG_MACH_SUN55I_A523) /* SDC2: PC0-PC1, PC5-PC6, PC8-PC11, PC13-PC16 */ for (pin = SUNXI_GPC(0); pin <= SUNXI_GPC(16); pin++) { if (pin > SUNXI_GPC(1) && pin < SUNXI_GPC(5)) diff --git a/board/theobroma-systems/jaguar_rk3588/jaguar_rk3588.c b/board/theobroma-systems/jaguar_rk3588/jaguar_rk3588.c index a6d44f10db3..3f484646701 100644 --- a/board/theobroma-systems/jaguar_rk3588/jaguar_rk3588.c +++ b/board/theobroma-systems/jaguar_rk3588/jaguar_rk3588.c @@ -51,3 +51,22 @@ int rockchip_early_misc_init_r(void) return 0; } + +#define GPIO0B7_PU_EN BIT(15) + +void spl_board_init(void) +{ + /* + * GPIO0_B7 is routed to CAN TX. This SoC pin has a pull-down per default. + * So on power-up, we block the CAN bus with a dominant zero. We want to keep + * this blocking time to a minimum, so we want to get this pin high in SPL. + * + * The CAN driver in Linux disables the pull-down and sets the pin to + * output high. We don't have a CAN driver in U-Boot and don't need one, + * so we just use the easiest way to get the pin high, which is setting a + * pull-up. + */ + struct rk3588_pmu2_ioc * const ioc = (void *)PMU2_IOC_BASE; + + rk_setreg(&ioc->gpio0b_p, GPIO0B7_PU_EN); +} diff --git a/board/ti/am57xx/Kconfig b/board/ti/am57xx/Kconfig index 0c566820158..b6943938391 100644 --- a/board/ti/am57xx/Kconfig +++ b/board/ti/am57xx/Kconfig @@ -9,6 +9,18 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "am57xx_evm" +config ENV_SOURCE_FILE + default "am57xx" + +source "board/ti/common/Kconfig" + +endif + +if TARGET_DRA7XX_EVM + +config ENV_SOURCE_FILE + default "am57xx" + source "board/ti/common/Kconfig" endif diff --git a/board/ti/am57xx/am57xx.env b/board/ti/am57xx/am57xx.env new file mode 100644 index 00000000000..a7cbbced099 --- /dev/null +++ b/board/ti/am57xx/am57xx.env @@ -0,0 +1,162 @@ +#include <env/ti/ti_common.env> +#include <env/ti/mmc.env> +#include <env/ti/dfu.env> + +bootpart=0:2 +bootdir=/boot +get_name_kern= + if test $boot_fit -eq 1; then + setenv bootfile fitImage; + else + setenv bootfile zImage; + fi +get_fit_config=setexpr name_fit_config gsub "ti/omap/" "" ${fdtfile} +console=ttyS2,115200n8 +fdtfile=undefined +finduuid=part uuid mmc 0:2 uuid +usbtty=cdc_acm +vram=16M + +#if CONFIG_CMD_AVB +avb_verify=avb init 1; avb verify $slot_suffix; +#endif + +partitions=uuid_disk=${uuid_gpt_disk}; + name=bootloader,start=384K,size=1792K,uuid=${uuid_gpt_bootloader}; + name=rootfs,start=2688K,size=-,uuid=${uuid_gpt_rootfs} + partitions_android= + uuid_disk=${uuid_gpt_disk}; + name=xloader,start=128K,size=256K,uuid=${uuid_gpt_xloader}; + name=bootloader,size=2048K,uuid=${uuid_gpt_bootloader}; + name=uboot-env,start=2432K,size=256K,uuid=${uuid_gpt_reserved}; + name=misc,size=128K,uuid=${uuid_gpt_misc}; + name=boot_a,size=20M,uuid=${uuid_gpt_boot_a}; + name=boot_b,size=20M,uuid=${uuid_gpt_boot_b}; + name=dtbo_a,size=8M,uuid=${uuid_gpt_dtbo_a}; + name=dtbo_b,size=8M,uuid=${uuid_gpt_dtbo_b}; + name=vbmeta_a,size=64K,uuid=${uuid_gpt_vbmeta_a}; + name=vbmeta_b,size=64K,uuid=${uuid_gpt_vbmeta_b}; + name=recovery,size=64M,uuid=${uuid_gpt_recovery}; + name=super,size=2560M,uuid=${uuid_gpt_super}; + name=metadata,size=16M,uuid=${uuid_gpt_metadata}; + name=userdata,size=-,uuid=${uuid_gpt_userdata} +optargs= +dofastboot=0 +emmc_android_boot= + setenv mmcdev 1; + mmc dev $mmcdev; + mmc rescan; +#if CONFIG_CMD_BCB +#if CONFIG_ANDROID_AB + if part number mmc 1 misc control_part_number; then + echo "misc partition number:${control_part_number};" + bcb ab_select slot_name mmc ${mmcdev}:${control_part_number}; + else + echo "misc partition not found;" + exit; + fi; + setenv slot_suffix _${slot_name}; +#endif +#endif +if bcb load CONFIG_FASTBOOT_FLASH_MMC_DEV misc; then + setenv ardaddr -; + if bcb test command = bootonce-bootloader; then + echo "Android: Bootloader boot..."; + bcb clear command; bcb store; + fastboot 1; + exit; + elif bcb test command = boot-recovery; then + echo "Android: Recovery boot..."; + setenv ardaddr $loadaddr; + setenv apart recovery; + else + echo "Android: Normal boot..."; + setenv ardaddr $loadaddr; + setenv apart boot${slot_suffix}; + fi; +else + echo "Warning: BCB is corrupted or does not exist"; + echo "Android: Normal boot..."; +fi; +setenv eval_bootargs setenv bootargs $bootargs; +run eval_bootargs; +setenv machid fe6; +#if CONFIG_CMD_AVB +if run avb_verify; then + echo "AVB verification OK."; + set bootargs $bootargs $avb_bootargs; +else + echo "AVB verification failed."; + exit; +fi; +#endif +#if CONFIG_CMD_BCB +#if CONFIG_ANDROID_AB +setenv bootargs_ab androidboot.slot_suffix=${slot_suffix}; +echo "A/B cmdline addition: ${bootargs_ab}"; +setenv bootargs ${bootargs} ${bootargs_ab}; +#endif +#endif +if part start mmc $mmcdev $apart boot_start; then + part size mmc $mmcdev $apart boot_size; + mmc read $loadaddr $boot_start $boot_size; + echo "Preparing FDT..."; + if test $board_name = am57xx_evm_reva3; then + echo " Reading DTBO partition..."; + part start mmc ${mmcdev} dtbo${slot_suffix} p_dtbo_start; + part size mmc ${mmcdev} dtbo${slot_suffix} p_dtbo_size; + mmc read ${dtboaddr} ${p_dtbo_start} ${p_dtbo_size}; + echo " Reading DTB for AM57x EVM RevA3..."; + abootimg get dtb --index=0 dtb_start dtb_size; + cp.b $dtb_start $fdtaddr $dtb_size; + fdt addr $fdtaddr 0x80000; + echo " Applying DTBOs for AM57x EVM RevA3..."; + adtimg addr $dtboaddr; + adtimg get dt --index=0 dtbo0_addr dtbo0_size; + fdt apply $dtbo0_addr; + adtimg get dt --index=1 dtbo1_addr dtbo1_size; + fdt apply $dtbo1_addr; + elif test $board_name = beagle_x15_revc; then + echo " Reading DTB for Beagle X15 RevC..."; + abootimg get dtb --index=0 dtb_start dtb_size; + cp.b $dtb_start $fdtaddr $dtb_size; + fdt addr $fdtaddr 0x80000; + else + echo "Error: Android boot is not supported for $board_name"; + exit; + fi; + bootm $loadaddr $ardaddr $fdtaddr; +else + echo "$apart partition not found"; + exit; +fi; +get_overlay_mmc= + fdt address ${fdtaddr}; + fdt resize 0x100000; + for overlay in $name_overlays; + do; + load mmc ${bootpart} ${dtboaddr} ${bootdir}/dtb/${overlay}; + fdt apply ${dtboaddr}; + done; +#if CONFIG_CMD_NET +static_ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off +nfsopts=nolock +rootpath=/export/rootfs +netloadimage=tftp ${loadaddr} ${bootfile} +netloadfdt=tftp ${fdtaddr} ${fdtfile} +netargs=setenv bootargs console=${console} ${optargs} + root=/dev/nfs + nfsroot=${serverip}:${rootpath},${nfsopts} rw + ip=dhcp +netboot=echo Booting from network ...; + setenv autoload no; + dhcp; + run netloadimage; + run netloadfdt; + run netargs; + bootz ${loadaddr} - ${fdtaddr} +#endif +#if CONFIG_MTD_RAW_NAND +#include <env/ti/nand.env> +#endif +dfu_bufsiz=0x10000 diff --git a/board/ti/am57xx/board.c b/board/ti/am57xx/board.c index fc0d87daae4..4091601d4f2 100644 --- a/board/ti/am57xx/board.c +++ b/board/ti/am57xx/board.c @@ -42,6 +42,7 @@ #include "../common/board_detect.h" #include "../common/cape_detect.h" +#include "../common/fdt_ops.h" #include "mux_data.h" #ifdef CONFIG_SUPPORT_EMMC_BOOT @@ -577,6 +578,18 @@ void do_board_detect(void) "Board: %s REV %s\n", bname, board_ti_get_rev()); } +static struct ti_fdt_map ti_omap_am57_evm_fdt_map[] = { + {"beagle_x15", "ti/omap/am57xx-beagle-x15.dtb"}, + {"beagle_x15_revb1", "ti/omap/am57xx-beagle-x15-revb1.dtb"}, + {"beagle_x15_revc", "ti/omap/am57xx-beagle-x15-revc.dtb"}, + {"am5729_beagleboneai", "ti/omap/am5729-beagleboneai.dtb"}, + {"am572x_idk", "ti/omap/am572x-idk.dtb"}, + {"am574x_idk", "ti/omap/am574x-idk.dtb"}, + {"am57xx_evm", "ti/omap/am57xx-beagle-x15.dtb"}, + {"am57xx_evm_reva3", "ti/omap/am57xx-beagle-x15.dtb"}, + {"am571x_idk", "ti/omap/am571x-idk.dtb"}, +}; + static void setup_board_eeprom_env(void) { char *name = "beagle_x15"; @@ -614,6 +627,7 @@ static void setup_board_eeprom_env(void) invalid_eeprom: set_board_info_env(name); + ti_set_fdt_env(name, ti_omap_am57_evm_fdt_map); } #endif /* CONFIG_XPL_BUILD */ diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c index 98d63e14e29..0966db2bb62 100644 --- a/board/ti/dra7xx/evm.c +++ b/board/ti/dra7xx/evm.c @@ -38,6 +38,7 @@ #include "mux_data.h" #include "../common/board_detect.h" +#include "../common/fdt_ops.h" #define board_is_dra76x_evm() board_ti_is("DRA76/7x") #define board_is_dra74x_evm() board_ti_is("5777xCPU") @@ -665,6 +666,15 @@ static int device_okay(const char *path) } #endif +static struct ti_fdt_map ti_omap_dra7_evm_fdt_map[] = { + {"omap5_uevm", "ti/omap/omap5-uevm.dtb"}, + {"dra7xx", "ti/omap/dra7-evm.dtb"}, + {"dra72x-revc", "ti/omap/dra72-evm-revc.dtb"}, + {"dra72x", "ti/omap/dra72-evm.dtb"}, + {"dra71x", "ti/omap/dra71-evm.dtb"}, + {"dra76x_acd", "ti/omap/dra76-evm.dtb"}, +}; + int board_late_init(void) { #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG @@ -686,6 +696,7 @@ int board_late_init(void) } set_board_info_env(name); + ti_set_fdt_env(name, ti_omap_dra7_evm_fdt_map); /* * Default FIT boot on HS devices. Non FIT images are not allowed diff --git a/board/xilinx/mbv/Kconfig b/board/xilinx/mbv/Kconfig index c52ba1870b0..68acd8955ae 100644 --- a/board/xilinx/mbv/Kconfig +++ b/board/xilinx/mbv/Kconfig @@ -28,7 +28,6 @@ config BOARD_SPECIFIC_OPTIONS imply SPL_RAM_DEVICE imply CMD_SBI imply CMD_PING - imply OF_HAS_PRIOR_STAGE source "board/xilinx/Kconfig" diff --git a/board/xunlong/orangepi-5-ultra-rk3588/Kconfig b/board/xunlong/orangepi-5-ultra-rk3588/Kconfig new file mode 100644 index 00000000000..43fc96b04c0 --- /dev/null +++ b/board/xunlong/orangepi-5-ultra-rk3588/Kconfig @@ -0,0 +1,12 @@ +if TARGET_ORANGEPI_5_ULTRA_RK3588 + +config SYS_BOARD + default "orangepi-5-ultra-rk3588" + +config SYS_VENDOR + default "xunlong" + +config SYS_CONFIG_NAME + default "evb_rk3588" + +endif diff --git a/board/xunlong/orangepi-5-ultra-rk3588/MAINTAINERS b/board/xunlong/orangepi-5-ultra-rk3588/MAINTAINERS new file mode 100644 index 00000000000..be9c93f6b9d --- /dev/null +++ b/board/xunlong/orangepi-5-ultra-rk3588/MAINTAINERS @@ -0,0 +1,6 @@ +ORANGEPI-5-RK3588-ULTRA +M: Niu Zhihong <zhihong@nzhnb.com> +S: Maintained +F: board/xunlong/orangepi-5-rk3588-ultra +F: configs/orangepi-5-ultra-rk3588_defconfig +F: arch/arm/dts/rk3588-orangepi-5-ultra.dts |