diff options
Diffstat (limited to 'board')
169 files changed, 5982 insertions, 947 deletions
diff --git a/board/BuR/brppt2/board.c b/board/BuR/brppt2/board.c index c0a163251b4..de206bdf1bc 100644 --- a/board/BuR/brppt2/board.c +++ b/board/BuR/brppt2/board.c @@ -7,6 +7,7 @@ * */ #include <cpu_func.h> +#include <env.h> #include <hang.h> #include <init.h> #include <spl.h> diff --git a/board/CZ.NIC/turris_omnia/turris_omnia.c b/board/CZ.NIC/turris_omnia/turris_omnia.c index b7588fa4eec..baee5afa46d 100644 --- a/board/CZ.NIC/turris_omnia/turris_omnia.c +++ b/board/CZ.NIC/turris_omnia/turris_omnia.c @@ -29,6 +29,7 @@ #include <linux/bitops.h> #include <linux/bitrev.h> #include <linux/delay.h> +#include <linux/if_ether.h> #include <u-boot/crc.h> #include "../drivers/ddr/marvell/a38x/ddr3_init.h" diff --git a/board/Marvell/mvebu_armada-37xx/board.c b/board/Marvell/mvebu_armada-37xx/board.c index df3fb6d2164..e44b713f96d 100644 --- a/board/Marvell/mvebu_armada-37xx/board.c +++ b/board/Marvell/mvebu_armada-37xx/board.c @@ -20,6 +20,7 @@ #include <asm/arch/cpu.h> #include <asm/arch/soc.h> #include <linux/delay.h> +#include <linux/if_ether.h> DECLARE_GLOBAL_DATA_PTR; diff --git a/board/Synology/common/legacy.h b/board/Synology/common/legacy.h index 0a814324d09..f7ba225bd2b 100644 --- a/board/Synology/common/legacy.h +++ b/board/Synology/common/legacy.h @@ -8,6 +8,8 @@ #ifndef __SYNO_LEGACY_H #define __SYNO_LEGACY_H +#include <linux/if_ether.h> + /* Marvell uboot parameters */ #define ATAG_MV_UBOOT 0x41000403 #define VER_NUM 0x03040400 /* 3.4.4 */ diff --git a/board/Synology/ds414/ds414.c b/board/Synology/ds414/ds414.c index 1a4cea87e1a..02d6a4a1ea8 100644 --- a/board/Synology/ds414/ds414.c +++ b/board/Synology/ds414/ds414.c @@ -4,6 +4,7 @@ * Copyright (C) 2015 Phil Sutter <phil@nwl.cc> */ +#include <env.h> #include <init.h> #include <miiphy.h> #include <asm/global_data.h> diff --git a/board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c b/board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c index b9f47006d61..8c9e9830876 100644 --- a/board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c +++ b/board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c @@ -7,6 +7,7 @@ #include <dwc3-uboot.h> #include <efi.h> #include <efi_loader.h> +#include <env.h> #include <errno.h> #include <miiphy.h> #include <netdev.h> diff --git a/board/advantech/imx8qm_dmsse20_a1/imx8qm_dmsse20-a1.env b/board/advantech/imx8qm_dmsse20_a1/imx8qm_dmsse20-a1.env index 0c9f9c4178a..90861e622ed 100644 --- a/board/advantech/imx8qm_dmsse20_a1/imx8qm_dmsse20-a1.env +++ b/board/advantech/imx8qm_dmsse20_a1/imx8qm_dmsse20-a1.env @@ -6,7 +6,7 @@ earlycon=lpuart32,0x5a060000 fdt_addr=0x83000000 boot_fdt=try fdt_file=imx8qm-dmsse20-a1.dtb -mmcdev= __stringify(CONFIG_SYS_MMC_ENV_DEV) +mmcdev= __stringify(CONFIG_ENV_MMC_DEVICE_INDEX) mmcpart= __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) mmcroot=/dev/mmcblk1p2 rootwait rw mmcautodetect=yes diff --git a/board/advantech/imx8qm_dmsse20_a1/imx8qm_dmsse20_a1.c b/board/advantech/imx8qm_dmsse20_a1/imx8qm_dmsse20_a1.c index 50b35db5f6c..accd300df04 100644 --- a/board/advantech/imx8qm_dmsse20_a1/imx8qm_dmsse20_a1.c +++ b/board/advantech/imx8qm_dmsse20_a1/imx8qm_dmsse20_a1.c @@ -4,6 +4,7 @@ * Copyright 2019-2023 Kococonnector GmbH */ +#include <env.h> #include <errno.h> #include <linux/libfdt.h> #include <asm/io.h> diff --git a/board/amd/versal2/board.c b/board/amd/versal2/board.c index 72967e69a84..7d91d288d2e 100644 --- a/board/amd/versal2/board.c +++ b/board/amd/versal2/board.c @@ -365,9 +365,11 @@ int dram_init(void) return 0; } +#if !CONFIG_IS_ENABLED(SYSRESET) void reset_cpu(void) { } +#endif #if defined(CONFIG_ENV_IS_NOWHERE) enum env_location env_get_location(enum env_operation op, int prio) diff --git a/board/amlogic/jethub-j100/jethub-j100.c b/board/amlogic/jethub-j100/jethub-j100.c index b770a1f8c53..9e87fb9f9d7 100644 --- a/board/amlogic/jethub-j100/jethub-j100.c +++ b/board/amlogic/jethub-j100/jethub-j100.c @@ -5,6 +5,7 @@ */ #include <dm.h> +#include <env.h> #include <init.h> #include <net.h> #include <asm/io.h> diff --git a/board/andestech/ae350/ae350.c b/board/andestech/ae350/ae350.c index 1d9d4a929c2..9bdd2ab1780 100644 --- a/board/andestech/ae350/ae350.c +++ b/board/andestech/ae350/ae350.c @@ -6,6 +6,7 @@ #include <config.h> #include <cpu_func.h> +#include <env.h> #include <flash.h> #include <image.h> #include <init.h> diff --git a/board/astro/mcf5373l/Kconfig b/board/astro/mcf5373l/Kconfig deleted file mode 100644 index a7c04cef83d..00000000000 --- a/board/astro/mcf5373l/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_ASTRO_MCF5373L - -config SYS_CPU - default "mcf532x" - -config SYS_BOARD - default "mcf5373l" - -config SYS_VENDOR - default "astro" - -config SYS_CONFIG_NAME - default "astro_mcf5373l" - -endif diff --git a/board/astro/mcf5373l/MAINTAINERS b/board/astro/mcf5373l/MAINTAINERS deleted file mode 100644 index 6c23da71968..00000000000 --- a/board/astro/mcf5373l/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -MCF5373L BOARD -M: Wolfgang Wegner <w.wegner@astro-kom.de> -S: Maintained -F: board/astro/mcf5373l/ -F: include/configs/astro_mcf5373l.h -F: configs/astro_mcf5373l_defconfig diff --git a/board/astro/mcf5373l/Makefile b/board/astro/mcf5373l/Makefile deleted file mode 100644 index d3ea0d06a8d..00000000000 --- a/board/astro/mcf5373l/Makefile +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. - -obj-y = mcf5373l.o fpga.o diff --git a/board/astro/mcf5373l/astro.h b/board/astro/mcf5373l/astro.h deleted file mode 100644 index b55a6f785ce..00000000000 --- a/board/astro/mcf5373l/astro.h +++ /dev/null @@ -1,44 +0,0 @@ -#ifndef __ASTRO_H__ -#define __ASTRO_H__ - -/* in mcf5373l.c */ -int rs_serial_init(int port, int baud); -void astro_put_char(char ch); -int astro_is_char(void); -int astro_get_char(void); - -/* in fpga.c */ -int astro5373l_altera_load(void); -int astro5373l_xilinx_load(void); - -/* data structures used for communication (update.c) */ -typedef struct card_id { - char card_type; - char hardware_version; - char software_version; - char software_subversion; /* " ","a".."z" */ - char fpga_version_altera; - char fpga_version_xilinx; -} card_id_t; - -typedef struct { - unsigned char mode; - unsigned char deviation; - unsigned short freq; -} __attribute__ ((packed)) output_params_t; - -typedef struct { - unsigned short satfreq; - unsigned char satdatallg; - unsigned short symbolrate; - unsigned char viterbirate; - unsigned char symbolrate_l; - output_params_t output_params; - unsigned char reserve; - unsigned char card_error; - unsigned short dummy_ts_id; - unsigned char dummy_pat_ver; - unsigned char dummy_sdt_ver; -} __attribute__ ((packed)) parameters_t; - -#endif /* __ASTRO_H__ */ diff --git a/board/astro/mcf5373l/fpga.c b/board/astro/mcf5373l/fpga.c deleted file mode 100644 index 6e505c630d1..00000000000 --- a/board/astro/mcf5373l/fpga.c +++ /dev/null @@ -1,407 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2006 - * Wolfgang Wegner, ASTRO Strobel Kommunikationssysteme GmbH, - * w.wegner@astro-kom.de - * - * based on the files by - * Heiko Schocher, DENX Software Engineering, hs@denx.de - * and - * Rich Ireland, Enterasys Networks, rireland@enterasys.com. - * Keith Outwater, keith_outwater@mvis.com. - */ - -/* Altera/Xilinx FPGA configuration support for the ASTRO "URMEL" board */ - -#include <console.h> -#include <watchdog.h> -#include <altera.h> -#include <ACEX1K.h> -#include <spartan3.h> -#include <command.h> -#include <asm/immap_5329.h> -#include <asm/io.h> -#include "fpga.h" - -int altera_pre_fn(int cookie) -{ - gpio_t *gpiop = (gpio_t *)MMAP_GPIO; - unsigned char tmp_char; - unsigned short tmp_short; - - /* first, set the required pins to GPIO function */ - /* PAR_T0IN -> GPIO */ - tmp_char = readb(&gpiop->par_timer); - tmp_char &= 0xfc; - writeb(tmp_char, &gpiop->par_timer); - /* all QSPI pins -> GPIO */ - writew(0x0000, &gpiop->par_qspi); - /* U0RTS, U0CTS -> GPIO */ - tmp_short = __raw_readw(&gpiop->par_uart); - tmp_short &= 0xfff3; - __raw_writew(tmp_short, &gpiop->par_uart); - /* all PWM pins -> GPIO */ - writeb(0x00, &gpiop->par_pwm); - /* next, set data direction registers */ - writeb(0x01, &gpiop->pddr_timer); - writeb(0x25, &gpiop->pddr_qspi); - writeb(0x0c, &gpiop->pddr_uart); - writeb(0x04, &gpiop->pddr_pwm); - - /* ensure other SPI peripherals are deselected */ - writeb(0x08, &gpiop->ppd_uart); - writeb(0x38, &gpiop->ppd_qspi); - - /* CONFIG = 0 STATUS = 0 -> FPGA in reset state */ - writeb(0xFB, &gpiop->pclrr_uart); - /* enable Altera configuration by clearing QSPI_CS2 and DT0IN */ - writeb(0xFE, &gpiop->pclrr_timer); - writeb(0xDF, &gpiop->pclrr_qspi); - return FPGA_SUCCESS; -} - -/* Set the state of CONFIG Pin */ -int altera_config_fn(int assert_config, int flush, int cookie) -{ - gpio_t *gpiop = (gpio_t *)MMAP_GPIO; - - if (assert_config) - writeb(0x04, &gpiop->ppd_uart); - else - writeb(0xFB, &gpiop->pclrr_uart); - return FPGA_SUCCESS; -} - -/* Returns the state of STATUS Pin */ -int altera_status_fn(int cookie) -{ - gpio_t *gpiop = (gpio_t *)MMAP_GPIO; - - if (readb(&gpiop->ppd_pwm) & 0x08) - return FPGA_FAIL; - return FPGA_SUCCESS; -} - -/* Returns the state of CONF_DONE Pin */ -int altera_done_fn(int cookie) -{ - gpio_t *gpiop = (gpio_t *)MMAP_GPIO; - - if (readb(&gpiop->ppd_pwm) & 0x20) - return FPGA_FAIL; - return FPGA_SUCCESS; -} - -/* - * writes the complete buffer to the FPGA - * writing the complete buffer in one function is much faster, - * then calling it for every bit - */ -int altera_write_fn(const void *buf, size_t len, int flush, int cookie) -{ - size_t bytecount = 0; - gpio_t *gpiop = (gpio_t *)MMAP_GPIO; - unsigned char *data = (unsigned char *)buf; - unsigned char val = 0; - int i; - int len_40 = len / 40; - - while (bytecount < len) { - val = data[bytecount++]; - i = 8; - do { - writeb(0xFB, &gpiop->pclrr_qspi); - if (val & 0x01) - writeb(0x01, &gpiop->ppd_qspi); - else - writeb(0xFE, &gpiop->pclrr_qspi); - writeb(0x04, &gpiop->ppd_qspi); - val >>= 1; - i--; - } while (i > 0); - - if (bytecount % len_40 == 0) { -#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG) - schedule(); -#endif -#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK - putc('.'); /* let them know we are alive */ -#endif -#ifdef CONFIG_SYS_FPGA_CHECK_CTRLC - if (ctrlc()) - return FPGA_FAIL; -#endif - } - } - return FPGA_SUCCESS; -} - -/* called, when programming is aborted */ -int altera_abort_fn(int cookie) -{ - gpio_t *gpiop = (gpio_t *)MMAP_GPIO; - - writeb(0x20, &gpiop->ppd_qspi); - writeb(0x08, &gpiop->ppd_uart); - return FPGA_SUCCESS; -} - -/* called, when programming was succesful */ -int altera_post_fn(int cookie) -{ - return altera_abort_fn(cookie); -} - -/* - * Note that these are pointers to code that is in Flash. They will be - * relocated at runtime. - * FIXME: relocation not yet working for coldfire, see below! - */ -Altera_CYC2_Passive_Serial_fns altera_fns = { - altera_pre_fn, - altera_config_fn, - altera_status_fn, - altera_done_fn, - altera_write_fn, - altera_abort_fn, - altera_post_fn -}; - -#define FPGA_COUNT 1 -Altera_desc altera_fpga[FPGA_COUNT] = { - {Altera_CYC2, - passive_serial, - 85903, - (void *)&altera_fns, - NULL, - 0} -}; - -/* Initialize the fpga. Return 1 on success, 0 on failure. */ -int astro5373l_altera_load(void) -{ - int i; - - for (i = 0; i < FPGA_COUNT; i++) { - /* - * I did not yet manage to get relocation work properly, - * so set stuff here instead of static initialisation: - */ - altera_fns.pre = altera_pre_fn; - altera_fns.config = altera_config_fn; - altera_fns.status = altera_status_fn; - altera_fns.done = altera_done_fn; - altera_fns.write = altera_write_fn; - altera_fns.abort = altera_abort_fn; - altera_fns.post = altera_post_fn; - altera_fpga[i].iface_fns = (void *)&altera_fns; - fpga_add(fpga_altera, &altera_fpga[i]); - } - return 1; -} - -/* Set the FPGA's PROG_B line to the specified level */ -int xilinx_pgm_config_fn(int assert, int flush, int cookie) -{ - gpio_t *gpiop = (gpio_t *)MMAP_GPIO; - - if (assert) - writeb(0xFB, &gpiop->pclrr_uart); - else - writeb(0x04, &gpiop->ppd_uart); - return assert; -} - -/* - * Test the state of the active-low FPGA INIT line. Return 1 on INIT - * asserted (low). - */ -int xilinx_init_config_fn(int cookie) -{ - gpio_t *gpiop = (gpio_t *)MMAP_GPIO; - - return (readb(&gpiop->ppd_pwm) & 0x08) == 0; -} - -/* Test the state of the active-high FPGA DONE pin */ -int xilinx_done_config_fn(int cookie) -{ - gpio_t *gpiop = (gpio_t *)MMAP_GPIO; - - return (readb(&gpiop->ppd_pwm) & 0x20) >> 5; -} - -/* Abort an FPGA operation */ -int xilinx_abort_config_fn(int cookie) -{ - gpio_t *gpiop = (gpio_t *)MMAP_GPIO; - /* ensure all SPI peripherals and FPGAs are deselected */ - writeb(0x08, &gpiop->ppd_uart); - writeb(0x01, &gpiop->ppd_timer); - writeb(0x38, &gpiop->ppd_qspi); - return FPGA_FAIL; -} - -/* - * FPGA pre-configuration function. Just make sure that - * FPGA reset is asserted to keep the FPGA from starting up after - * configuration. - */ -int xilinx_pre_config_fn(int cookie) -{ - gpio_t *gpiop = (gpio_t *)MMAP_GPIO; - unsigned char tmp_char; - unsigned short tmp_short; - - /* first, set the required pins to GPIO function */ - /* PAR_T0IN -> GPIO */ - tmp_char = readb(&gpiop->par_timer); - tmp_char &= 0xfc; - writeb(tmp_char, &gpiop->par_timer); - /* all QSPI pins -> GPIO */ - writew(0x0000, &gpiop->par_qspi); - /* U0RTS, U0CTS -> GPIO */ - tmp_short = __raw_readw(&gpiop->par_uart); - tmp_short &= 0xfff3; - __raw_writew(tmp_short, &gpiop->par_uart); - /* all PWM pins -> GPIO */ - writeb(0x00, &gpiop->par_pwm); - /* next, set data direction registers */ - writeb(0x01, &gpiop->pddr_timer); - writeb(0x25, &gpiop->pddr_qspi); - writeb(0x0c, &gpiop->pddr_uart); - writeb(0x04, &gpiop->pddr_pwm); - - /* ensure other SPI peripherals are deselected */ - writeb(0x08, &gpiop->ppd_uart); - writeb(0x38, &gpiop->ppd_qspi); - writeb(0x01, &gpiop->ppd_timer); - - /* CONFIG = 0, STATUS = 0 -> FPGA in reset state */ - writeb(0xFB, &gpiop->pclrr_uart); - /* enable Xilinx configuration by clearing QSPI_CS2 and U0CTS */ - writeb(0xF7, &gpiop->pclrr_uart); - writeb(0xDF, &gpiop->pclrr_qspi); - return 0; -} - -/* - * FPGA post configuration function. Should perform a test if FPGA is running. - */ -int xilinx_post_config_fn(int cookie) -{ - int rc = 0; - - /* - * no test yet - */ - return rc; -} - -int xilinx_clk_config_fn(int assert_clk, int flush, int cookie) -{ - gpio_t *gpiop = (gpio_t *)MMAP_GPIO; - - if (assert_clk) - writeb(0x04, &gpiop->ppd_qspi); - else - writeb(0xFB, &gpiop->pclrr_qspi); - return assert_clk; -} - -int xilinx_wr_config_fn(int assert_write, int flush, int cookie) -{ - gpio_t *gpiop = (gpio_t *)MMAP_GPIO; - - if (assert_write) - writeb(0x01, &gpiop->ppd_qspi); - else - writeb(0xFE, &gpiop->pclrr_qspi); - return assert_write; -} - -int xilinx_fastwr_config_fn(void *buf, size_t len, int flush, int cookie) -{ - size_t bytecount = 0; - gpio_t *gpiop = (gpio_t *)MMAP_GPIO; - unsigned char *data = (unsigned char *)buf; - unsigned char val = 0; - int i; - int len_40 = len / 40; - - for (bytecount = 0; bytecount < len; bytecount++) { - val = *(data++); - for (i = 8; i > 0; i--) { - writeb(0xFB, &gpiop->pclrr_qspi); - if (val & 0x80) - writeb(0x01, &gpiop->ppd_qspi); - else - writeb(0xFE, &gpiop->pclrr_qspi); - writeb(0x04, &gpiop->ppd_qspi); - val <<= 1; - } - if (bytecount % len_40 == 0) { -#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG) - schedule(); -#endif -#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK - putc('.'); /* let them know we are alive */ -#endif -#ifdef CONFIG_SYS_FPGA_CHECK_CTRLC - if (ctrlc()) - return FPGA_FAIL; -#endif - } - } - return FPGA_SUCCESS; -} - -/* - * Note that these are pointers to code that is in Flash. They will be - * relocated at runtime. - * FIXME: relocation not yet working for coldfire, see below! - */ -xilinx_spartan3_slave_serial_fns xilinx_fns = { - xilinx_pre_config_fn, - xilinx_pgm_config_fn, - xilinx_clk_config_fn, - xilinx_init_config_fn, - xilinx_done_config_fn, - xilinx_wr_config_fn, - 0, - xilinx_fastwr_config_fn -}; - -xilinx_desc xilinx_fpga[FPGA_COUNT] = { - {xilinx_spartan3, - slave_serial, - XILINX_XC3S4000_SIZE, - (void *)&xilinx_fns, - 0, - &spartan3_op} -}; - -/* Initialize the fpga. Return 1 on success, 0 on failure. */ -int astro5373l_xilinx_load(void) -{ - int i; - - fpga_init(); - - for (i = 0; i < FPGA_COUNT; i++) { - /* - * I did not yet manage to get relocation work properly, - * so set stuff here instead of static initialisation: - */ - xilinx_fns.pre = xilinx_pre_config_fn; - xilinx_fns.pgm = xilinx_pgm_config_fn; - xilinx_fns.clk = xilinx_clk_config_fn; - xilinx_fns.init = xilinx_init_config_fn; - xilinx_fns.done = xilinx_done_config_fn; - xilinx_fns.wr = xilinx_wr_config_fn; - xilinx_fns.bwr = xilinx_fastwr_config_fn; - xilinx_fpga[i].iface_fns = (void *)&xilinx_fns; - fpga_add(fpga_xilinx, &xilinx_fpga[i]); - } - return 1; -} diff --git a/board/astro/mcf5373l/mcf5373l.c b/board/astro/mcf5373l/mcf5373l.c deleted file mode 100644 index 43fcbc65513..00000000000 --- a/board/astro/mcf5373l/mcf5373l.c +++ /dev/null @@ -1,201 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2000-2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * modified by Wolfgang Wegner <w.wegner@astro-kom.de> for ASTRO 5373l - */ - -#include <config.h> -#include <init.h> -#include <serial.h> -#include <time.h> -#include <watchdog.h> -#include <command.h> -#include <asm/global_data.h> -#include <asm/m5329.h> -#include <asm/immap_5329.h> -#include <asm/io.h> -#include <linux/delay.h> - -/* needed for astro bus: */ -#include <asm/uart.h> -#include "astro.h" - -DECLARE_GLOBAL_DATA_PTR; -extern void uart_port_conf(void); - -int checkboard(void) -{ - puts("Board: "); - puts("ASTRO MCF5373L (Urmel) Board\n"); - return 0; -} - -int dram_init(void) -{ -#if !defined(CONFIG_MONITOR_IS_IN_RAM) - sdram_t *sdp = (sdram_t *)(MMAP_SDRAM); - - /* - * GPIO configuration for bus should be set correctly from reset, - * so we do not care! First, set up address space: at this point, - * we should be running from internal SRAM; - * so use CFG_SYS_SDRAM_BASE as the base address for SDRAM, - * and do not care where it is - */ - __raw_writel((CFG_SYS_SDRAM_BASE & 0xFFF00000) | 0x00000018, - &sdp->cs0); - __raw_writel((CFG_SYS_SDRAM_BASE & 0xFFF00000) | 0x00000000, - &sdp->cs1); - /* - * I am not sure from the data sheet, but it seems burst length - * has to be 8 for the 16 bit data bus we use; - * so these values are for BL = 8 - */ - __raw_writel(0x33211530, &sdp->cfg1); - __raw_writel(0x56570000, &sdp->cfg2); - /* send PrechargeALL, REF and IREF remain cleared! */ - __raw_writel(0xE1462C02, &sdp->ctrl); - udelay(1); - /* refresh SDRAM twice */ - __raw_writel(0xE1462C04, &sdp->ctrl); - udelay(1); - __raw_writel(0xE1462C04, &sdp->ctrl); - /* init MR */ - __raw_writel(0x008D0000, &sdp->mode); - /* initialize EMR */ - __raw_writel(0x80010000, &sdp->mode); - /* wait until DLL is locked */ - udelay(1); - /* - * enable automatic refresh, lock mode register, - * clear iref and ipall - */ - __raw_writel(0x71462C00, &sdp->ctrl); - /* Dummy write to start SDRAM */ - writel(0, CFG_SYS_SDRAM_BASE); -#endif - - /* - * for get_ram_size() to work, both CS areas have to be - * configured, i.e. CS1 has to be explicitely disabled, else - * probing for memory will cause the SDRAM bus to hang! - * (Do not rely on the SDCS register(s) being set to 0x00000000 - * during reset as stated in the data sheet.) - */ - gd->ram_size = get_ram_size((long *)CFG_SYS_SDRAM_BASE, - 0x80000000 - CFG_SYS_SDRAM_BASE); - - return 0; -} - -#define UART_BASE MMAP_UART0 -int rs_serial_init(int port, int baud) -{ - uart_t *uart; - u32 counter; - - switch (port) { - case 0: - uart = (uart_t *)(MMAP_UART0); - break; - case 1: - uart = (uart_t *)(MMAP_UART1); - break; - case 2: - uart = (uart_t *)(MMAP_UART2); - break; - default: - uart = (uart_t *)(MMAP_UART0); - } - - uart_port_conf(); - - /* write to SICR: SIM2 = uart mode,dcd does not affect rx */ - writeb(UART_UCR_RESET_RX, &uart->ucr); - writeb(UART_UCR_RESET_TX, &uart->ucr); - writeb(UART_UCR_RESET_ERROR, &uart->ucr); - writeb(UART_UCR_RESET_MR, &uart->ucr); - __asm__ ("nop"); - - writeb(0, &uart->uimr); - - /* write to CSR: RX/TX baud rate from timers */ - writeb(UART_UCSR_RCS_SYS_CLK | UART_UCSR_TCS_SYS_CLK, &uart->ucsr); - - writeb(UART_UMR_BC_8 | UART_UMR_PM_NONE, &uart->umr); - writeb(UART_UMR_SB_STOP_BITS_1, &uart->umr); - - /* Setting up BaudRate */ - counter = (u32) (gd->bus_clk / (baud)); - counter >>= 5; - - /* write to CTUR: divide counter upper byte */ - writeb((u8) ((counter & 0xff00) >> 8), &uart->ubg1); - /* write to CTLR: divide counter lower byte */ - writeb((u8) (counter & 0x00ff), &uart->ubg2); - - writeb(UART_UCR_RX_ENABLED | UART_UCR_TX_ENABLED, &uart->ucr); - - return 0; -} - -void astro_put_char(char ch) -{ - uart_t *uart; - unsigned long timer; - - uart = (uart_t *)(MMAP_UART0); - /* - * Wait for last character to go. Timeout of 6ms should - * be enough for our lowest baud rate of 2400. - */ - timer = get_timer(0); - while (get_timer(timer) < 6) { - if (readb(&uart->usr) & UART_USR_TXRDY) - break; - } - writeb(ch, &uart->utb); - - return; -} - -int astro_is_char(void) -{ - uart_t *uart; - - uart = (uart_t *)(MMAP_UART0); - return readb(&uart->usr) & UART_USR_RXRDY; -} - -int astro_get_char(void) -{ - uart_t *uart; - - uart = (uart_t *)(MMAP_UART0); - while (!(readb(&uart->usr) & UART_USR_RXRDY)) ; - return readb(&uart->urb); -} - -int misc_init_r(void) -{ - int retval = 0; - - puts("Configure Xilinx FPGA..."); - retval = astro5373l_xilinx_load(); - if (!retval) { - puts("failed!\n"); - return retval; - } - puts("done\n"); - - puts("Configure Altera FPGA..."); - retval = astro5373l_altera_load(); - if (!retval) { - puts("failed!\n"); - return retval; - } - puts("done\n"); - - return retval; -} diff --git a/board/atmel/sam9x75_curiosity/Kconfig b/board/atmel/sam9x75_curiosity/Kconfig new file mode 100644 index 00000000000..8ea93a21aa3 --- /dev/null +++ b/board/atmel/sam9x75_curiosity/Kconfig @@ -0,0 +1,15 @@ +if TARGET_SAM9X75_CURIOSITY + +config SYS_BOARD + default "sam9x75_curiosity" + +config SYS_VENDOR + default "atmel" + +config SYS_SOC + default "at91" + +config SYS_CONFIG_NAME + default "sam9x75_curiosity" + +endif diff --git a/board/atmel/sam9x75_curiosity/MAINTAINERS b/board/atmel/sam9x75_curiosity/MAINTAINERS new file mode 100644 index 00000000000..f0dfdbe8d5c --- /dev/null +++ b/board/atmel/sam9x75_curiosity/MAINTAINERS @@ -0,0 +1,7 @@ +SAM9X75 CURIOSITY BOARD +M: Manikandan Muralidharan <manikandan.m@microchip.com> +S: Maintained +F: board/atmel/sam9x75_curiosity/ +F: include/configs/sam9x75_curiosity.h +F: arch/arm/dts/at91-sam9x75_curiosity-u-boot.dtsi +F: configs/sam9x75_curiosity_mmc_defconfig diff --git a/board/atmel/sam9x75_curiosity/Makefile b/board/atmel/sam9x75_curiosity/Makefile new file mode 100644 index 00000000000..1f36d613229 --- /dev/null +++ b/board/atmel/sam9x75_curiosity/Makefile @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2025 Microchip Technology Inc. and its subsidiaries +# +# Author: Manikandan Muralidharan <manikandan.m@microchip.com> + +obj-y += sam9x75_curiosity.o diff --git a/board/atmel/sam9x75_curiosity/sam9x75_curiosity.c b/board/atmel/sam9x75_curiosity/sam9x75_curiosity.c new file mode 100644 index 00000000000..4e7c5667e21 --- /dev/null +++ b/board/atmel/sam9x75_curiosity/sam9x75_curiosity.c @@ -0,0 +1,66 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2025 Microchip Technology Inc. and its subsidiaries + * + * Author: Manikandan Muralidharan <manikandan.m@microchip.com> + */ + +#include <debug_uart.h> +#include <init.h> +#include <asm/io.h> +#include <asm/arch/at91sam9_smc.h> +#include <asm/arch/at91_common.h> +#include <asm/arch/at91_rstc.h> +#include <asm/arch/at91_sfr.h> +#include <asm/arch/clk.h> +#include <asm/arch/gpio.h> +#include <asm/mach-types.h> + +DECLARE_GLOBAL_DATA_PTR; + +void at91_prepare_cpu_var(void); + +int board_late_init(void) +{ + at91_prepare_cpu_var(); + + return 0; +} + +#if (IS_ENABLED(CONFIG_DEBUG_UART_BOARD_INIT)) +static void board_dbgu0_hw_init(void) +{ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 26, 1); /* DRXD */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 27, 1); /* DTXD */ + + at91_periph_clk_enable(ATMEL_ID_DBGU); +} + +void board_debug_uart_init(void) +{ + board_dbgu0_hw_init(); +} +#endif + +int board_early_init_f(void) +{ + return 0; +} + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100; + + return 0; +} + +int dram_init_banksize(void) +{ + return fdtdec_setup_memory_banksize(); +} + +int dram_init(void) +{ + return fdtdec_setup_mem_size_base(); +} diff --git a/board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c b/board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c index 04de1257eca..897fab58eba 100644 --- a/board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c +++ b/board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c @@ -65,7 +65,7 @@ int board_early_init_f(void) int board_init(void) { /* address of boot parameters */ - gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100; rgb_leds_init(); @@ -82,11 +82,14 @@ int misc_init_r(void) } #endif +int dram_init_banksize(void) +{ + return fdtdec_setup_memory_banksize(); +} + int dram_init(void) { - gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, - CFG_SYS_SDRAM_SIZE); - return 0; + return fdtdec_setup_mem_size_base(); } /* SPL */ diff --git a/board/bosch/guardian/board.c b/board/bosch/guardian/board.c index 33ba7a7751c..ebbae27c0f9 100644 --- a/board/bosch/guardian/board.c +++ b/board/bosch/guardian/board.c @@ -32,7 +32,6 @@ #include <asm/gpio.h> #include <asm/io.h> #include <jffs2/load_kernel.h> -#include <mtd.h> #include <nand.h> #include <video.h> #include <video_console.h> diff --git a/board/bosch/shc/board.h b/board/bosch/shc/board.h index a5e58186c9c..8ff68f5a64b 100644 --- a/board/bosch/shc/board.h +++ b/board/bosch/shc/board.h @@ -14,6 +14,8 @@ #ifndef _BOARD_H_ #define _BOARD_H_ +#include <linux/if_ether.h> + /* Definition to control the GPIOs (for LEDs and Reset) */ #define GPIO_TO_PIN(bank, gpio) (32 * (bank) + (gpio)) @@ -146,7 +148,6 @@ static inline int board_is_series(void) #define RESET_MASK (0x1 << 29) #define HDR_MAGIC 0x43485342 -#define HDR_ETH_ALEN 6 #define HDR_NAME_LEN 8 #define HDR_REV_LEN 8 #define HDR_SER_LEN 16 @@ -176,7 +177,7 @@ struct shc_eeprom { u32 magic; u16 version; u16 lenght; - uint8_t mac_addr[HDR_ETH_ALEN]; + uint8_t mac_addr[ETH_ALEN]; }; void enable_uart0_pin_mux(void); diff --git a/board/bsh/imx6ulz_smm_m2/Kconfig b/board/bsh/imx6ulz_smm_m2/Kconfig index e38df7ce5cb..20971aa4fe1 100644 --- a/board/bsh/imx6ulz_smm_m2/Kconfig +++ b/board/bsh/imx6ulz_smm_m2/Kconfig @@ -9,4 +9,25 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "imx6ulz_smm_m2" +choice + prompt "Memory Type (M2/M2B) board" + default BSH_M2_MEMORY + help + Memory type setup. + Please choose correct memory model here. + +config BSH_M2_MEMORY + bool "Enable for bsh m2 variant" + help + If this option is enabled, U-Boot will be configured to support + imx6ulz bsh m2 revision memories. + +config BSH_M2B_MEMORY + bool "Enable for bsh m2b variant" + help + If this option is enabled, U-Boot will be configured to support + imx6ulz bsh m2b revision memories. + +endchoice + endif diff --git a/board/bsh/imx6ulz_smm_m2/MAINTAINERS b/board/bsh/imx6ulz_smm_m2/MAINTAINERS index 77a033c6cbb..a75cddd72f8 100644 --- a/board/bsh/imx6ulz_smm_m2/MAINTAINERS +++ b/board/bsh/imx6ulz_smm_m2/MAINTAINERS @@ -4,3 +4,4 @@ S: Maintained F: board/bsh/imx6ulz_smm_m2/ F: include/configs/imx6ulz_smm_m2.h F: configs/imx6ulz_smm_m2_defconfig +F: configs/imx6ulz_smm_m2b_defconfig diff --git a/board/bsh/imx6ulz_smm_m2/Makefile b/board/bsh/imx6ulz_smm_m2/Makefile index 4f4d67f659d..233bbff4c16 100644 --- a/board/bsh/imx6ulz_smm_m2/Makefile +++ b/board/bsh/imx6ulz_smm_m2/Makefile @@ -2,4 +2,6 @@ # (C) Copyright 2021 Amarula Solutions B.V. obj-y := imx6ulz_smm_m2.o -obj-$(CONFIG_XPL_BUILD) += spl.o ddr3l_timing_512m.o ddr3l_timing_256m.o ddr3l_timing_128m.o +obj-$(CONFIG_XPL_BUILD) += spl.o +obj-$(CONFIG_BSH_M2_MEMORY) += ddr3l_timing_512m.o ddr3l_timing_256m.o ddr3l_timing_128m.o +obj-$(CONFIG_BSH_M2B_MEMORY) += ddr3l_timing_256m_m2b.o ddr3l_timing_128m_m2b.o diff --git a/board/bsh/imx6ulz_smm_m2/ddr3l_timing_128m.c b/board/bsh/imx6ulz_smm_m2/ddr3l_timing_128m.c index 66c3483adbf..f11654a8ceb 100644 --- a/board/bsh/imx6ulz_smm_m2/ddr3l_timing_128m.c +++ b/board/bsh/imx6ulz_smm_m2/ddr3l_timing_128m.c @@ -166,4 +166,5 @@ static const struct dram_cfg_param ddr_ddrc_cfg_128mb[] = { struct dram_timing_info bsh_dram_timing_128mb = { .ddrc_cfg = ddr_ddrc_cfg_128mb, .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg_128mb), + .dram_size = SZ_128M, }; diff --git a/board/bsh/imx6ulz_smm_m2/ddr3l_timing_128m_m2b.c b/board/bsh/imx6ulz_smm_m2/ddr3l_timing_128m_m2b.c new file mode 100644 index 00000000000..f989e24f567 --- /dev/null +++ b/board/bsh/imx6ulz_smm_m2/ddr3l_timing_128m_m2b.c @@ -0,0 +1,152 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include "spl_mtypes.h" + +static const struct dram_cfg_param ddr_ddrc_cfg_128mb[] = { + /* IOMUX */ + + /* DDR IO Type: */ + {0x020e04b4, 0x000C0000}, /* IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE */ + {0x020e04ac, 0x00000000}, /* IOMUXC_SW_PAD_CTL_GRP_DDRPKE */ + + /* Clock: */ + {0x020e027c, 0x00000028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0 */ + + /* Address: */ + {0x020e0250, 0x00000028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS */ + {0x020e024c, 0x00000028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS */ + {0x020e0490, 0x00000028}, /* IOMUXC_SW_PAD_CTL_GRP_ADDDS */ + + /* Control: */ + {0x020e0288, 0x000C0028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET */ + {0x020e0270, 0x00000000}, /* + * IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2 - DSE can be configured + * using Group Control Register IOMUXC_SW_PAD_CTL_GRP_CTLDS + */ + + {0x020e0260, 0x00000028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT0 */ + {0x020e0264, 0x00000028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT1 */ + {0x020e04a0, 0x00000028}, /* IOMUXC_SW_PAD_CTL_GRP_CTLDS */ + + /* Data Strobes: */ + {0x020e0494, 0x00020000}, /* IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL */ + {0x020e0280, 0x00000028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0 */ + {0x020e0284, 0x00000028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1 */ + + /* Data: */ + {0x020e04b0, 0x00020000}, /* IOMUXC_SW_PAD_CTL_GRP_DDRMODE */ + {0x020e0498, 0x00000028}, /* IOMUXC_SW_PAD_CTL_GRP_B0DS */ + {0x020e04a4, 0x00000028}, /* IOMUXC_SW_PAD_CTL_GRP_B1DS */ + + {0x020e0244, 0x00000028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0 */ + {0x020e0248, 0x00000028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1 */ + + /* + * ============================================================================= + * DDR Controller Registers + * ============================================================================= + * Manufacturer:WINBOND + * Device Part Number:W631GU6RB-11 + * Clock Freq.: 400MHz + * Density per CS in Gb: 1 + * Chip Selects used:1 + * Total DRAM density (Gb)1 + * Number of Banks:8 + * Row address: 13 + * Column address: 10 + * Data bus width16 + * ============================================================================= + */ + {0x021b001c, 0x00008000}, /* + * MMDC0_MDSCR, set the Configuration request bit + * during MMDC set up + */ + + /* + * ============================================================================= + * Calibration setup. + * ============================================================================= + */ + {0x021b0800, 0xA1390003}, /* + * DDR_PHY_P0_MPZQHWCTRL, enable both one-time & periodic + * HW ZQ calibration. + */ + + /* + * For target board, may need to run write leveling calibration to fine tune + * these settings. + */ + {0x021b080c, 0x00060002}, + + /* Read DQS Gating calibration */ + {0x021b083c, 0x414c0150}, /* MPDGCTRL0 PHY0 */ + + /* Read calibration */ + {0x021b0848, 0x4040363e}, /* MPRDDLCTL PHY0 */ + + /* Write calibration */ + {0x021b0850, 0x40402a28}, /* MPWRDLCTL PHY0 */ + + /* + * Read data bit delay: 3 is the recommended default value, although out of reset + * value is 0. + */ + {0x021b081c, 0x33333333}, /* MMDC_MPRDDQBY0DL */ + {0x021b0820, 0x33333333}, /* MMDC_MPRDDQBY1DL */ + + /* Write data bit delay: */ + {0x021b082c, 0xf3333333}, /* MMDC_MPWRDQBY0DL */ + {0x021b0830, 0xf3333333}, /* MMDC_MPWRDQBY1DL */ + + /* DQS&CLK Duty Cycle */ + {0x021b08c0, 0x00944009}, /* [MMDC_MPDCCR] MMDC Duty Cycle Control Register */ + + /* Complete calibration by forced measurement: */ + {0x021b08b8, 0x00000800}, /* DDR_PHY_P0_MPMUR0, frc_msr */ + + /* MMDC init: */ + {0x021b0004, 0x0002002D}, /* MMDC0_MDPDC */ + {0x021b0008, 0x1B333030}, /* MMDC0_MDOTC */ + {0x021b000c, 0x2B2F52F3}, /* MMDC0_MDCFG0 */ + {0x021b0010, 0xB66D0A63}, /* MMDC0_MDCFG1 */ + {0x021b0014, 0x01FF00DB}, /* MMDC0_MDCFG2 */ + {0x021b0018, 0x00201740}, /* MMDC0_MDMISC */ + {0x021b002C, 0x000026D2}, /* MMDC0_MDRWD */ + {0x021b0030, 0x002F1023}, /* MMDC0_MDOR */ + {0x021b0040, 0x00000043}, /* CS0_END */ + {0x021b0000, 0x82180000}, /* MMDC0_MDCTL */ + + /* Mode register writes for CS0 */ + {0x021B001C, 0x02808032}, /* MMDC0_MDSCR, MR2 write, CS0 */ + {0x021B001C, 0x00008033}, /* MMDC0_MDSCR, MR3 write, CS0 */ + {0x021B001C, 0x00048031}, /* MMDC0_MDSCR, MR1 write, CS0 */ + {0x021B001C, 0x15208030}, /* MMDC0_MDSCR, MR0 write, CS0 */ + {0x021B001C, 0x04008040}, /* + * MMDC0_MDSCR, ZQ calibration + * command sent to device on CS0 + */ + + /* final DDR setup, before operation start: */ + {0x021b0020, 0x00000800}, /* MMDC0_MDREF */ + + {0x021b0818, 0x00000227}, /* DDR_PHY_P0_MPODTCTRL */ + + {0x021b0004, 0x0002556D}, /* MMDC0_MDPDC now SDCTL power down enabled */ + + {0x021b0404, 0x00011006}, /* + * MMDC0_MAPSR ADOPT power down enabled, + * MMDC will enter automatically to self-refresh + * while the number of idle cycle reached. + */ + + {0x021b001c, 0x00000000}, /* + * MMDC0_MDSCR, clear this register (especially the + * configuration bit as initialization is complete) + */ +}; + +struct dram_timing_info bsh_dram_timing_128mb = { + .ddrc_cfg = ddr_ddrc_cfg_128mb, + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg_128mb), + .dram_size = SZ_128M, +}; diff --git a/board/bsh/imx6ulz_smm_m2/ddr3l_timing_256m.c b/board/bsh/imx6ulz_smm_m2/ddr3l_timing_256m.c index 0fe5b90a673..5dfc9f5c70d 100644 --- a/board/bsh/imx6ulz_smm_m2/ddr3l_timing_256m.c +++ b/board/bsh/imx6ulz_smm_m2/ddr3l_timing_256m.c @@ -165,4 +165,5 @@ static const struct dram_cfg_param ddr_ddrc_cfg_256mb[] = { struct dram_timing_info bsh_dram_timing_256mb = { .ddrc_cfg = ddr_ddrc_cfg_256mb, .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg_256mb), + .dram_size = SZ_256M, }; diff --git a/board/bsh/imx6ulz_smm_m2/ddr3l_timing_256m_m2b.c b/board/bsh/imx6ulz_smm_m2/ddr3l_timing_256m_m2b.c new file mode 100644 index 00000000000..c44f632b928 --- /dev/null +++ b/board/bsh/imx6ulz_smm_m2/ddr3l_timing_256m_m2b.c @@ -0,0 +1,137 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include "spl_mtypes.h" + +static const struct dram_cfg_param ddr_ddrc_cfg_256mb[] = { + /* IOMUX */ + + /* DDR IO Type: */ + {0x020e04b4, 0x000C0000}, /* IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE */ + {0x020e04ac, 0x00000000}, /* IOMUXC_SW_PAD_CTL_GRP_DDRPKE */ + + /* Clock: */ + {0x020e027c, 0x00000030}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P */ + + /* Address: */ + {0x020e0250, 0x00000030}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS */ + {0x020e024c, 0x00000030}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS */ + {0x020e0490, 0x00000030}, /* IOMUXC_SW_PAD_CTL_GRP_ADDDS */ + + /* Control: */ + {0x020e0288, 0x000C0030}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET */ + {0x020e0270, 0x00000000}, /* + * IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2 - DSE can be + * configured using Group Control Register: + * IOMUXC_SW_PAD_CTL_GRP_CTLDS + */ + + {0x020e0260, 0x00000030}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0 */ + {0x020e0264, 0x00000030}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1 */ + {0x020e04a0, 0x00000028}, /* IOMUXC_SW_PAD_CTL_GRP_CTLDS */ + + /* Data Strobes: */ + {0x020e0494, 0x00020000}, /* IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL */ + {0x020e0280, 0x00000030}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P */ + {0x020e0284, 0x00000030}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P */ + + /* Data: */ + {0x020e04b0, 0x00020000}, /* IOMUXC_SW_PAD_CTL_GRP_DDRMODE */ + {0x020e0498, 0x00000030}, /* IOMUXC_SW_PAD_CTL_GRP_B0DS */ + {0x020e04a4, 0x00000030}, /* IOMUXC_SW_PAD_CTL_GRP_B1DS */ + + {0x020e0244, 0x00000030}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0 */ + {0x020e0248, 0x00000030}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1 */ + + /* + * ============================================================================= + * DDR Controller Registers + * ============================================================================= + * Manufacturer:WINBOND + * Device Part Number:W632GU6RB-11 + * Clock Freq.: 400MHz + * Density per CS in Gb: 2 + * Chip Selects used:1 + * Total DRAM density (Gb)2 + * Number of Banks:8 + * Row address: 14 + * Column address: 10 + * Data bus width16 + * ============================================================================= + */ + {0x021b001c, 0x00008000}, /* + * MMDC0_MDSCR, set the Configuration request bit + * during MMDC set up + */ + + /* + * ============================================================================= + * Calibration setup. + * ============================================================================= + */ + {0x021b0800, 0xA1390003}, /* + * DDR_PHY_P0_MPZQHWCTRL, enable both one-time & periodic + * HW ZQ calibration. + */ + + /* + * For target board, may need to run write leveling calibration to fine tune + * these settings. + */ + {0x021b080c, 0x00070005}, + + /* Read DQS Gating calibration */ + {0x021b083c, 0x414c0150}, /* MPDGCTRL0 PHY0 */ + + /* Read calibration */ + {0x021b0848, 0x4040383e}, /* MMDC_MPRDDLCTL */ + + /* Write calibration */ + {0x021b0850, 0x40402e2a}, /* MMDC_MPWRDLCTL */ + + {0x021B081C, 0x33333333}, /* MMDC_MPRDDQBY0DL */ + {0x021B0820, 0x33333333}, /* MMDC_MPRDDQBY1DL */ + + {0x021B082C, 0xf3333333}, /* MMDC_MPWRDQBY0DL */ + {0x021B0830, 0xf3333333}, /* MMDC_MPWRDQBY1DL */ + + {0x021B08C0, 0x00944009}, /* MMDC_MPDCCR */ + + /* Complete calibration by forced measurement: */ + {0x021B08B8, 0x00000800}, /* DDR_PHY_P0_MPMUR0, frc_msr */ + + /* MMDC init: */ + {0x021b0004, 0x00020024}, /* MMDC0_MDPDC */ + {0x021b0008, 0x1B333030}, /* MMDC0_MDOTC */ + {0x021b000c, 0x3F4352D3}, /* MMDC0_MDCFG0 */ + {0x021b0010, 0xB66D0A63}, /* MMDC0_MDCFG1 */ + {0x021b0014, 0x01FF00DB}, /* MMDC0_MDCFG2 */ + {0x021b0018, 0x00201740}, /* MMDC0_MDMISC */ + {0x021b002C, 0x000026D2}, /* MMDC0_MDRWD */ + {0x021b0030, 0x00431023}, /* MMDC0_MDOR */ + {0x021b0040, 0x00000047}, /* CS0_END */ + {0x021b0000, 0x83180000}, /* MMDC0_MDCTL */ + + /* Mode register writes for CS0 */ + {0x021B001C, 0x02808032}, /* MMDC0_MDSCR, MR2 write, CS0 */ + {0x021B001C, 0x00008033}, /* MMDC0_MDSCR, MR3 write, CS0 */ + {0x021B001C, 0x00048031}, /* MMDC0_MDSCR, MR1 write, CS0 */ + {0x021B001C, 0x15208030}, /* MMDC0_MDSCR, MR0 write, CS0 */ + {0x021B001C, 0x04008040}, /* MMDC0_MDSCR, ZQ calibration */ + + /* final DDR setup, before operation start: */ + {0x021b0020, 0x00000800}, /* MMDC0_MDREF */ + + {0x021b0818, 0x00000227}, /* DDR_PHY_P0_MPODTCTRL */ + {0x021b0004, 0x00025564}, /* MMDC0_MDPDC now SDCTL power down enabled */ + {0x021b0404, 0x00011006}, /* MMDC0_MAPSR ADOPT power down enabled */ + {0x021b001c, 0x00000000}, /* + * MMDC0_MDSCR, clear this register (especially + * the configuration bit as initialization is complete) + */ +}; + +struct dram_timing_info bsh_dram_timing_256mb = { + .ddrc_cfg = ddr_ddrc_cfg_256mb, + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg_256mb), + .dram_size = SZ_256M, +}; diff --git a/board/bsh/imx6ulz_smm_m2/ddr3l_timing_512m.c b/board/bsh/imx6ulz_smm_m2/ddr3l_timing_512m.c index f5989382f5a..4c2ffcd429d 100644 --- a/board/bsh/imx6ulz_smm_m2/ddr3l_timing_512m.c +++ b/board/bsh/imx6ulz_smm_m2/ddr3l_timing_512m.c @@ -165,4 +165,5 @@ static const struct dram_cfg_param ddr_ddrc_cfg_512mb[] = { struct dram_timing_info bsh_dram_timing_512mb = { .ddrc_cfg = ddr_ddrc_cfg_512mb, .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg_512mb), + .dram_size = SZ_512M, }; diff --git a/board/bsh/imx6ulz_smm_m2/spl.c b/board/bsh/imx6ulz_smm_m2/spl.c index c330e4d6d39..7aea73f0f5d 100644 --- a/board/bsh/imx6ulz_smm_m2/spl.c +++ b/board/bsh/imx6ulz_smm_m2/spl.c @@ -52,28 +52,31 @@ static void ddr_cfg_write(const struct dram_timing_info *dram_timing_info) } } +static const struct dram_timing_info *board_dram_timing[] = { +#if defined(CONFIG_M2_MEMORY) + &bsh_dram_timing_512mb, +#endif + &bsh_dram_timing_256mb, + &bsh_dram_timing_128mb, +}; + static void spl_dram_init(void) { /* Configure memory to maximum supported size for detection */ - ddr_cfg_write(&bsh_dram_timing_512mb); + ddr_cfg_write(board_dram_timing[0]); /* Detect memory physically present */ - gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, SZ_512M); - - /* Reconfigure memory for actual detected size */ - switch (gd->ram_size) { - case SZ_512M: - /* Already configured, nothing to do */ - break; - case SZ_256M: - udelay(1); - ddr_cfg_write(&bsh_dram_timing_256mb); - break; - case SZ_128M: - default: - udelay(1); - ddr_cfg_write(&bsh_dram_timing_128mb); - break; + gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, board_dram_timing[0]->dram_size); + + if (board_dram_timing[0]->dram_size == gd->ram_size) + return; + + for (size_t index = 1; index < ARRAY_SIZE(board_dram_timing); index++) { + if (board_dram_timing[index]->dram_size == gd->ram_size) { + udelay(1); + ddr_cfg_write(board_dram_timing[index]); + break; + } } } diff --git a/board/bsh/imx6ulz_smm_m2/spl_mtypes.h b/board/bsh/imx6ulz_smm_m2/spl_mtypes.h index 8da59881c83..06d6f2d76d8 100644 --- a/board/bsh/imx6ulz_smm_m2/spl_mtypes.h +++ b/board/bsh/imx6ulz_smm_m2/spl_mtypes.h @@ -18,6 +18,7 @@ struct dram_cfg_param { struct dram_timing_info { const struct dram_cfg_param *ddrc_cfg; unsigned int ddrc_cfg_num; + size_t dram_size; }; extern struct dram_timing_info bsh_dram_timing_128mb; diff --git a/board/congatec/cgtqmx8/cgtqmx8.c b/board/congatec/cgtqmx8/cgtqmx8.c index 054e4e10867..03be02a2884 100644 --- a/board/congatec/cgtqmx8/cgtqmx8.c +++ b/board/congatec/cgtqmx8/cgtqmx8.c @@ -4,6 +4,7 @@ * Copyright (C) 2019 Oliver Graute <oliver.graute@kococonnector.com> */ #include <config.h> +#include <env.h> #include <errno.h> #include <linux/libfdt.h> #include <fsl_esdhc.h> diff --git a/board/congatec/common/Makefile b/board/congatec/common/Makefile index f8170d9c653..7f1c8994d27 100644 --- a/board/congatec/common/Makefile +++ b/board/congatec/common/Makefile @@ -16,8 +16,8 @@ endif endif ifdef MINIMAL -# necessary to create built-in.o -obj- := __dummy__.o +# necessary to create built-in.a +obj- := __dummy__.a else obj-y += mmc.o diff --git a/board/cssi/cmpc885/u-boot.lds b/board/cssi/cmpc885/u-boot.lds index 53f616fcfe1..167606357e0 100644 --- a/board/cssi/cmpc885/u-boot.lds +++ b/board/cssi/cmpc885/u-boot.lds @@ -18,8 +18,8 @@ SECTIONS { arch/powerpc/cpu/mpc8xx/start.o (.text) arch/powerpc/cpu/mpc8xx/traps.o (.text*) - arch/powerpc/lib/built-in.o (.text*) - drivers/net/built-in.o (.text*) + arch/powerpc/lib/built-in.a (.text*) + drivers/net/built-in.a (.text*) . = DEFINED(env_offset) ? env_offset : .; env/embedded.o (.text.environment) diff --git a/board/cssi/mcr3000/u-boot.lds b/board/cssi/mcr3000/u-boot.lds index 24b535e724a..66afdebc0f7 100644 --- a/board/cssi/mcr3000/u-boot.lds +++ b/board/cssi/mcr3000/u-boot.lds @@ -18,8 +18,8 @@ SECTIONS { arch/powerpc/cpu/mpc8xx/start.o (.text) arch/powerpc/cpu/mpc8xx/traps.o (.text*) - arch/powerpc/lib/built-in.o (.text*) - drivers/net/built-in.o (.text*) + arch/powerpc/lib/built-in.a (.text*) + drivers/net/built-in.a (.text*) . = DEFINED(env_offset) ? env_offset : .; env/embedded.o (.text.environment) diff --git a/board/data_modul/common/common.c b/board/data_modul/common/common.c index 9e35dc5d6cb..7d344792937 100644 --- a/board/data_modul/common/common.c +++ b/board/data_modul/common/common.c @@ -12,6 +12,7 @@ #include <asm/mach-imx/boot_mode.h> #include <asm/mach-imx/iomux-v3.h> #include <dm/uclass.h> +#include <env.h> #include <hang.h> #include <i2c_eeprom.h> #include <image.h> diff --git a/board/dhelectronics/common/dh_common.c b/board/dhelectronics/common/dh_common.c index 71010803f55..8c052c45007 100644 --- a/board/dhelectronics/common/dh_common.c +++ b/board/dhelectronics/common/dh_common.c @@ -5,6 +5,7 @@ */ #include <dm.h> +#include <env.h> #include <i2c_eeprom.h> #include <net.h> #include <u-boot/crc.h> diff --git a/board/dhelectronics/dh_stm32mp1/board.c b/board/dhelectronics/dh_stm32mp1/board.c index d30171f1fbe..f7347bbb826 100644 --- a/board/dhelectronics/dh_stm32mp1/board.c +++ b/board/dhelectronics/dh_stm32mp1/board.c @@ -27,7 +27,6 @@ #include <led.h> #include <memalign.h> #include <misc.h> -#include <mtd.h> #include <mtd_node.h> #include <netdev.h> #include <phy.h> diff --git a/board/emulation/common/qemu_dfu.c b/board/emulation/common/qemu_dfu.c index 393fcaeb742..8a59f5ade13 100644 --- a/board/emulation/common/qemu_dfu.c +++ b/board/emulation/common/qemu_dfu.c @@ -7,6 +7,7 @@ #include <env.h> #include <memalign.h> #include <mtd.h> +#include <linux/sizes.h> #define DFU_ALT_BUF_LEN SZ_1K diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile index b04e19e9428..ed102ae7bf7 100644 --- a/board/freescale/common/Makefile +++ b/board/freescale/common/Makefile @@ -14,8 +14,8 @@ endif endif ifdef MINIMAL -# necessary to create built-in.o -obj- := __dummy__.o +# necessary to create built-in.a +obj- := __dummy__.a else # include i2c_common.o once if either VID or FSL_USE_PCA9547_MUX I2C_COMMON= diff --git a/board/freescale/common/fsl_chain_of_trust.c b/board/freescale/common/fsl_chain_of_trust.c index 194a0907e72..3d44357caf7 100644 --- a/board/freescale/common/fsl_chain_of_trust.c +++ b/board/freescale/common/fsl_chain_of_trust.c @@ -134,7 +134,7 @@ void spl_validate_uboot(uint32_t hdr_addr, uintptr_t img_addr) /* Override weak funtion defined in SPL framework to enable validation * of main u-boot image before jumping to u-boot image. */ -void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image) +void __noreturn jump_to_image(struct spl_image_info *spl_image) { typedef void __noreturn (*image_entry_noargs_t)(void); uint32_t hdr_addr; diff --git a/board/freescale/common/qixis.c b/board/freescale/common/qixis.c index 7815ba2dbce..04cad48f033 100644 --- a/board/freescale/common/qixis.c +++ b/board/freescale/common/qixis.c @@ -12,6 +12,7 @@ #include <asm/io.h> #include <linux/compiler.h> #include <linux/time.h> +#include <linux/string.h> #include <i2c.h> #include "qixis.h" diff --git a/board/freescale/common/qixis.h b/board/freescale/common/qixis.h index 784046ac4e0..0a0df6f34f8 100644 --- a/board/freescale/common/qixis.h +++ b/board/freescale/common/qixis.h @@ -136,8 +136,8 @@ void qixis_write_i2c(unsigned int reg, u8 value); #define QIXIS_SDCLKIN 0x08 #define QIXIS_SDCLKOUT 0x02 -#define QIXIS_DAT5_6_7 0X02 -#define QIXIS_DAT4 0X01 +#define QIXIS_DAT5_6_7 0x02 +#define QIXIS_DAT4 0x01 #define QIXIS_EVDD_BY_SDHC_VS 0x0c diff --git a/board/freescale/imx8mm_evk/imx8mm_evk.c b/board/freescale/imx8mm_evk/imx8mm_evk.c index d41db8d31d8..ecc20768cb5 100644 --- a/board/freescale/imx8mm_evk/imx8mm_evk.c +++ b/board/freescale/imx8mm_evk/imx8mm_evk.c @@ -3,6 +3,8 @@ * Copyright 2018 NXP */ +#include <config.h> +#include <efi_loader.h> #include <env.h> #include <init.h> #include <miiphy.h> @@ -15,6 +17,26 @@ DECLARE_GLOBAL_DATA_PTR; +#if CONFIG_IS_ENABLED(EFI_HAVE_CAPSULE_SUPPORT) +#define IMX_BOOT_IMAGE_GUID \ + EFI_GUID(0xead2005e, 0x7780, 0x400b, 0x93, 0x48, \ + 0xa2, 0x82, 0xeb, 0x85, 0x8b, 0x6b) + +struct efi_fw_image fw_images[] = { + { + .image_type_id = IMX_BOOT_IMAGE_GUID, + .fw_name = u"IMX8MM-EVK-RAW", + .image_index = 1, + }, +}; + +struct efi_capsule_update_info update_info = { + .dfu_string = "mmc 2=flash-bin raw 0x42 0x2000 mmcpart 1", + .num_images = ARRAY_SIZE(fw_images), + .images = fw_images, +}; +#endif /* EFI_HAVE_CAPSULE_SUPPORT */ + #if IS_ENABLED(CONFIG_FEC_MXC) static int setup_fec(void) { diff --git a/board/freescale/imx8mm_evk/imx8mm_evk.env b/board/freescale/imx8mm_evk/imx8mm_evk.env index 29690e75b15..299b8472c74 100644 --- a/board/freescale/imx8mm_evk/imx8mm_evk.env +++ b/board/freescale/imx8mm_evk/imx8mm_evk.env @@ -14,7 +14,7 @@ ip_dyn=yes kernel_addr_r=0x42000000 loadaddr=CONFIG_SYS_LOAD_ADDR mmcautodetect=yes -mmcdev=CONFIG_SYS_MMC_ENV_DEV +mmcdev=CONFIG_ENV_MMC_DEVICE_INDEX mmcpart=1 mmcroot=/dev/mmcblk1p2 rootwait rw prepare_mcore=setenv mcore_clk clk-imx8mm.mcore_booted; diff --git a/board/freescale/imx8mn_evk/imx8mn_evk.c b/board/freescale/imx8mn_evk/imx8mn_evk.c index c62d7a47e21..9d3f29f2253 100644 --- a/board/freescale/imx8mn_evk/imx8mn_evk.c +++ b/board/freescale/imx8mn_evk/imx8mn_evk.c @@ -5,9 +5,31 @@ #include <asm/arch/sys_proto.h> #include <asm/io.h> +#include <config.h> +#include <efi_loader.h> #include <env.h> #include <init.h> +#if CONFIG_IS_ENABLED(EFI_HAVE_CAPSULE_SUPPORT) +#define IMX_BOOT_IMAGE_GUID \ + EFI_GUID(0xcbabf44d, 0x12cc, 0x45dd, 0xb0, 0xc5, \ + 0x29, 0xc5, 0xb7, 0x42, 0x2d, 0x34) + +struct efi_fw_image fw_images[] = { + { + .image_type_id = IMX_BOOT_IMAGE_GUID, + .fw_name = u"IMX8MN-EVK-RAW", + .image_index = 1, + }, +}; + +struct efi_capsule_update_info update_info = { + .dfu_string = "mmc 2=flash-bin raw 0 0x2000 mmcpart 1", + .num_images = ARRAY_SIZE(fw_images), + .images = fw_images, +}; +#endif /* EFI_HAVE_CAPSULE_SUPPORT */ + int board_mmc_get_env_dev(int devno) { return devno; diff --git a/board/freescale/imx8mn_evk/imx8mn_evk.env b/board/freescale/imx8mn_evk/imx8mn_evk.env index 16a6543ffc6..487893f9287 100644 --- a/board/freescale/imx8mn_evk/imx8mn_evk.env +++ b/board/freescale/imx8mn_evk/imx8mn_evk.env @@ -14,7 +14,7 @@ ip_dyn=yes kernel_addr_r=0x42000000 loadaddr=CONFIG_SYS_LOAD_ADDR mmcautodetect=yes -mmcdev=CONFIG_SYS_MMC_ENV_DEV +mmcdev=CONFIG_ENV_MMC_DEVICE_INDEX mmcpart=1 mmcroot=/dev/mmcblk1p2 rootwait rw prepare_mcore=setenv mcore_clk clk-imx8mn.mcore_booted; diff --git a/board/freescale/imx8mp_evk/imx8mp_evk.c b/board/freescale/imx8mp_evk/imx8mp_evk.c index 2ff067bc675..2a9ba7df2bb 100644 --- a/board/freescale/imx8mp_evk/imx8mp_evk.c +++ b/board/freescale/imx8mp_evk/imx8mp_evk.c @@ -4,8 +4,31 @@ */ #include <asm/arch/sys_proto.h> +#include <config.h> +#include <efi_loader.h> #include <env.h> +#if CONFIG_IS_ENABLED(EFI_HAVE_CAPSULE_SUPPORT) +#define IMX_BOOT_IMAGE_GUID \ + EFI_GUID(0x928b33bc, 0xe58b, 0x4247, 0x9f, 0x1d, \ + 0x3b, 0xf1, 0xee, 0x1c, 0xda, 0xff) + +struct efi_fw_image fw_images[] = { + { + .image_type_id = IMX_BOOT_IMAGE_GUID, + .fw_name = u"IMX8MP-EVK-RAW", + .image_index = 1, + }, +}; + +struct efi_capsule_update_info update_info = { + .dfu_string = "mmc 2=flash-bin raw 0 0x2000 mmcpart 1", + .num_images = ARRAY_SIZE(fw_images), + .images = fw_images, +}; +#endif /* EFI_HAVE_CAPSULE_SUPPORT */ + + int board_init(void) { return 0; diff --git a/board/freescale/imx8mp_evk/imx8mp_evk.env b/board/freescale/imx8mp_evk/imx8mp_evk.env index f70e18fa9d9..18cdf3da056 100644 --- a/board/freescale/imx8mp_evk/imx8mp_evk.env +++ b/board/freescale/imx8mp_evk/imx8mp_evk.env @@ -10,7 +10,7 @@ fdt_addr=0x43000000 fdtfile=CONFIG_DEFAULT_FDT_FILE image=Image ip_dyn=yes -mmcdev=CONFIG_SYS_MMC_ENV_DEV +mmcdev=CONFIG_ENV_MMC_DEVICE_INDEX mmcpart=1 mmcroot=/dev/mmcblk1p2 rootwait rw mmcautodetect=yes diff --git a/board/freescale/imx8mq_evk/imx8mq_evk.c b/board/freescale/imx8mq_evk/imx8mq_evk.c index 18e83d90a08..e90c56c33ff 100644 --- a/board/freescale/imx8mq_evk/imx8mq_evk.c +++ b/board/freescale/imx8mq_evk/imx8mq_evk.c @@ -7,6 +7,7 @@ #include <asm/arch/imx8mq_pins.h> #include <asm/arch/sys_proto.h> #include <asm/mach-imx/iomux-v3.h> +#include <efi_loader.h> #include <env.h> #define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1) @@ -22,6 +23,26 @@ static iomux_v3_cfg_t const uart_pads[] = { IMX8MQ_PAD_UART1_TXD__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL), }; +#if CONFIG_IS_ENABLED(EFI_HAVE_CAPSULE_SUPPORT) +#define IMX_BOOT_IMAGE_GUID \ + EFI_GUID(0x296119cf, 0xdd70, 0x43de, 0x8a, 0xc8, \ + 0xa7, 0x05, 0x1f, 0x31, 0x25, 0x77) + +struct efi_fw_image fw_images[] = { + { + .image_type_id = IMX_BOOT_IMAGE_GUID, + .fw_name = u"IMX8MQ-EVK-RAW", + .image_index = 1, + }, +}; + +struct efi_capsule_update_info update_info = { + .dfu_string = "mmc 0=flash-bin raw 0x42 0x2000 mmcpart 1", + .num_images = ARRAY_SIZE(fw_images), + .images = fw_images, +}; +#endif /* EFI_HAVE_CAPSULE_SUPPORT */ + int board_early_init_f(void) { struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR; diff --git a/board/freescale/imx8mq_evk/imx8mq_evk.env b/board/freescale/imx8mq_evk/imx8mq_evk.env index dcfe1c2f2d4..cab8c6b70bf 100644 --- a/board/freescale/imx8mq_evk/imx8mq_evk.env +++ b/board/freescale/imx8mq_evk/imx8mq_evk.env @@ -12,7 +12,7 @@ ip_dyn=yes kernel_addr_r=CONFIG_SYS_LOAD_ADDR loadaddr=CONFIG_SYS_LOAD_ADDR mmcautodetect=yes -mmcdev=CONFIG_SYS_MMC_ENV_DEV +mmcdev=CONFIG_ENV_MMC_DEVICE_INDEX mmcpart=1 mmcroot=/dev/mmcblk1p2 rootwait rw prepare_mcore=setenv mcore_clk clk-imx8mq.mcore_booted; diff --git a/board/freescale/imx8ulp_evk/imx8ulp_evk.c b/board/freescale/imx8ulp_evk/imx8ulp_evk.c index 0af61067263..4bf77a488cc 100644 --- a/board/freescale/imx8ulp_evk/imx8ulp_evk.c +++ b/board/freescale/imx8ulp_evk/imx8ulp_evk.c @@ -3,6 +3,7 @@ * Copyright 2020 NXP */ +#include <env.h> #include <miiphy.h> #include <netdev.h> #include <asm/arch/imx8ulp-pins.h> diff --git a/board/freescale/imx91_evk/imx91_evk.env b/board/freescale/imx91_evk/imx91_evk.env index c972d3eb251..6c10784cf61 100644 --- a/board/freescale/imx91_evk/imx91_evk.env +++ b/board/freescale/imx91_evk/imx91_evk.env @@ -10,7 +10,7 @@ fdt_addr_r=0x83000000 fdt_addr=0x83000000 fdtfile=CONFIG_DEFAULT_FDT_FILE image=Image -mmcdev=CONFIG_SYS_MMC_ENV_DEV +mmcdev=CONFIG_ENV_MMC_DEVICE_INDEX mmcpart=1 mmcroot=/dev/mmcblk1p2 rootwait rw mmcautodetect=yes diff --git a/board/freescale/imx93_evk/imx93_evk.c b/board/freescale/imx93_evk/imx93_evk.c index c9171df330e..d84d56be5e1 100644 --- a/board/freescale/imx93_evk/imx93_evk.c +++ b/board/freescale/imx93_evk/imx93_evk.c @@ -4,6 +4,7 @@ */ #include <env.h> +#include <efi_loader.h> #include <init.h> #include <miiphy.h> #include <netdev.h> @@ -28,6 +29,26 @@ static iomux_v3_cfg_t const uart_pads[] = { MX93_PAD_UART1_TXD__LPUART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL), }; +#if CONFIG_IS_ENABLED(EFI_HAVE_CAPSULE_SUPPORT) +#define IMX_BOOT_IMAGE_GUID \ + EFI_GUID(0xbc550d86, 0xda26, 0x4b70, 0xac, 0x05, \ + 0x2a, 0x44, 0x8e, 0xda, 0x6f, 0x21) + +struct efi_fw_image fw_images[] = { + { + .image_type_id = IMX_BOOT_IMAGE_GUID, + .fw_name = u"IMX93-11X11-EVK-RAW", + .image_index = 1, + }, +}; + +struct efi_capsule_update_info update_info = { + .dfu_string = "mmc 0=flash-bin raw 0 0x2000 mmcpart 1", + .num_images = ARRAY_SIZE(fw_images), + .images = fw_images, +}; +#endif /* EFI_HAVE_CAPSULE_SUPPORT */ + int board_early_init_f(void) { imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads)); diff --git a/board/freescale/imx93_evk/imx93_evk.env b/board/freescale/imx93_evk/imx93_evk.env index 8c3aef6b557..d5ed216f54b 100644 --- a/board/freescale/imx93_evk/imx93_evk.env +++ b/board/freescale/imx93_evk/imx93_evk.env @@ -10,7 +10,7 @@ fdt_addr_r=0x83000000 fdt_addr=0x83000000 fdtfile=CONFIG_DEFAULT_FDT_FILE image=Image -mmcdev=CONFIG_SYS_MMC_ENV_DEV +mmcdev=CONFIG_ENV_MMC_DEVICE_INDEX mmcpart=1 mmcroot=/dev/mmcblk1p2 rootwait rw mmcautodetect=yes diff --git a/board/freescale/imx93_qsb/imx93_qsb.env b/board/freescale/imx93_qsb/imx93_qsb.env index c972d3eb251..6c10784cf61 100644 --- a/board/freescale/imx93_qsb/imx93_qsb.env +++ b/board/freescale/imx93_qsb/imx93_qsb.env @@ -10,7 +10,7 @@ fdt_addr_r=0x83000000 fdt_addr=0x83000000 fdtfile=CONFIG_DEFAULT_FDT_FILE image=Image -mmcdev=CONFIG_SYS_MMC_ENV_DEV +mmcdev=CONFIG_ENV_MMC_DEVICE_INDEX mmcpart=1 mmcroot=/dev/mmcblk1p2 rootwait rw mmcautodetect=yes diff --git a/board/freescale/imx95_evk/imx95_19x19_evk.env b/board/freescale/imx95_evk/imx95_19x19_evk.env index a002767e874..a7309d734b0 100644 --- a/board/freescale/imx95_evk/imx95_19x19_evk.env +++ b/board/freescale/imx95_evk/imx95_19x19_evk.env @@ -14,7 +14,7 @@ cntr_file=os_cntr_signed.bin boot_fit=no fdtfile=CONFIG_DEFAULT_FDT_FILE bootm_size=0x10000000 -mmcdev=CONFIG_SYS_MMC_ENV_DEV +mmcdev=CONFIG_ENV_MMC_DEVICE_INDEX mmcautodetect=yes mmcargs=setenv bootargs console=${console} root=${mmcroot} loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script}; diff --git a/board/freescale/ls1043ardb/cpld.c b/board/freescale/ls1043ardb/cpld.c index bda2f3ac3a6..39b6c6449cf 100644 --- a/board/freescale/ls1043ardb/cpld.c +++ b/board/freescale/ls1043ardb/cpld.c @@ -7,6 +7,7 @@ #include <config.h> #include <command.h> +#include <linux/string.h> #include <asm/io.h> #include "cpld.h" diff --git a/board/freescale/ls1046ardb/cpld.c b/board/freescale/ls1046ardb/cpld.c index 7f8ca2e857f..26a5962bd6e 100644 --- a/board/freescale/ls1046ardb/cpld.c +++ b/board/freescale/ls1046ardb/cpld.c @@ -7,6 +7,7 @@ #include <config.h> #include <command.h> +#include <linux/string.h> #include <asm/io.h> #include "cpld.h" diff --git a/board/freescale/m5253demo/m5253demo.c b/board/freescale/m5253demo/m5253demo.c index 446a79e6723..50c5320b55c 100644 --- a/board/freescale/m5253demo/m5253demo.c +++ b/board/freescale/m5253demo/m5253demo.c @@ -93,6 +93,7 @@ int testdram(void) #ifdef CONFIG_IDE #include <ata.h> +#include <ide.h> void ide_set_reset(int idereset) { atac_t *ata = (atac_t *) CONFIG_SYS_ATA_BASE_ADDR; diff --git a/board/freescale/mx7dsabresd/mx7dsabresd.c b/board/freescale/mx7dsabresd/mx7dsabresd.c index 3db167c0dad..bef4f901ff7 100644 --- a/board/freescale/mx7dsabresd/mx7dsabresd.c +++ b/board/freescale/mx7dsabresd/mx7dsabresd.c @@ -3,6 +3,7 @@ * Copyright (C) 2015 Freescale Semiconductor, Inc. */ +#include <env.h> #include <init.h> #include <net.h> #include <asm/arch/clock.h> diff --git a/board/freescale/p2041rdb/cpld.c b/board/freescale/p2041rdb/cpld.c index 915a8b994d5..2bba377d4d4 100644 --- a/board/freescale/p2041rdb/cpld.c +++ b/board/freescale/p2041rdb/cpld.c @@ -12,6 +12,7 @@ */ #include <command.h> +#include <linux/string.h> #include <asm/io.h> #include "cpld.h" diff --git a/board/freescale/t102xrdb/cpld.c b/board/freescale/t102xrdb/cpld.c index cc933ccd544..00ea9d8f503 100644 --- a/board/freescale/t102xrdb/cpld.c +++ b/board/freescale/t102xrdb/cpld.c @@ -9,6 +9,7 @@ #include <config.h> #include <command.h> +#include <linux/string.h> #include <asm/io.h> #include "cpld.h" diff --git a/board/freescale/t104xrdb/cpld.c b/board/freescale/t104xrdb/cpld.c index c2d526ae15a..038e40e2fae 100644 --- a/board/freescale/t104xrdb/cpld.c +++ b/board/freescale/t104xrdb/cpld.c @@ -12,6 +12,7 @@ #include <config.h> #include <command.h> +#include <linux/string.h> #include <asm/io.h> #include "cpld.h" diff --git a/board/freescale/t208xrdb/cpld.c b/board/freescale/t208xrdb/cpld.c index d2226af6278..838d88d977e 100644 --- a/board/freescale/t208xrdb/cpld.c +++ b/board/freescale/t208xrdb/cpld.c @@ -7,6 +7,7 @@ #include <config.h> #include <command.h> +#include <linux/string.h> #include <asm/io.h> #include "cpld.h" diff --git a/board/freescale/t4rdb/cpld.c b/board/freescale/t4rdb/cpld.c index f076350c1c5..258581eee96 100644 --- a/board/freescale/t4rdb/cpld.c +++ b/board/freescale/t4rdb/cpld.c @@ -16,6 +16,7 @@ #include <config.h> #include <command.h> +#include <linux/string.h> #include <asm/io.h> #include "cpld.h" diff --git a/board/gateworks/fsa.c b/board/gateworks/fsa.c new file mode 100644 index 00000000000..1af8021057c --- /dev/null +++ b/board/gateworks/fsa.c @@ -0,0 +1,736 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2025 Gateworks Corporation + */ + +#include <command.h> +#include <hexdump.h> +#include <i2c.h> +#include <dm.h> +#include <dm/device.h> +#include <dm/device_compat.h> +#include <dm/device-internal.h> // device_remove/device_unbind +#include <asm-generic/gpio.h> +#include <fdt_support.h> +#include <linux/delay.h> + +#include "fsa.h" + +static int fsa; +static struct udevice *fsa_gpiodevs[FSA_MAX] = { NULL }; + +/* find the ofnode of the FSA i2c bus */ +static ofnode fsa_get_ofnode(int fsa) +{ + char str[32]; + + /* by alias */ + snprintf(str, sizeof(str), "fsa%d", fsa); + return ofnode_get_aliases_node(str); +} + +static int fsa_get_dtnode(void *fdt, int fsa) +{ + char str[32]; + + /* by alias */ + snprintf(str, sizeof(str), "fsa%d", fsa); + return fdt_path_offset(fdt, fdt_get_alias(fdt, str)); +} + +static const char * const fsa_gpio_config_names[] = { "NC", "", "input", "output-low", + "output-high" }; + +static const char *fsa_gpio_config_name(struct fsa_gpio_desc *desc) +{ + if (desc->config < ARRAY_SIZE(fsa_gpio_config_names)) + return fsa_gpio_config_names[desc->config]; + return NULL; +}; + +static char *fsa_get_gpio_desc(struct fsa_gpio_desc *desc, char *str, int sz) +{ + str[0] = 0; + if (desc->source == 0xff) { + snprintf(str, sz, "fsa_gpio%d : %s %s", + desc->offset + 1, + desc->name, + fsa_gpio_config_name(desc)); + } else if (desc->config) { + snprintf(str, sz, "gpio@%02x_%02d: %s %s", + desc->source, + desc->offset, + desc->name, + fsa_gpio_config_name(desc)); + } + return str; +} + +static void fsa_show_gpio_descs(const char *prefix, int fsa, struct fsa_board_info *board_info, + struct fsa_user_info *user_info) +{ + char str[128]; + int i; + + /* display slot specific gpios */ + for (i = 0; i < board_info->sockgpios; i++) { + fsa_get_gpio_desc(&user_info->gpios[i], str, sizeof(str)); + printf("%s%-2d: %s\n", prefix, i, str); + } + /* display io-expander specific gpios */ + if (fsa_gpiodevs[fsa]) { + for (i = board_info->sockgpios; + i < (board_info->sockgpios + board_info->ioexpgpios); + i++) { + fsa_get_gpio_desc(&user_info->gpios[i], str, sizeof(str)); + printf("%s%-2d: %s\n", prefix, i, str); + } + } +} + +/* detect gpio expander by address and deal with enabling/disabling/adding gpio expander to dt */ +static int fsa_get_gpiodev(int fsa, int addr, struct udevice **devp) +{ + struct udevice *bus, *dev; + char gpio_name[32]; + int ret; + + ret = device_get_global_by_ofnode(fsa_get_ofnode(fsa), &bus); + if (ret) + return ret; + + sprintf(gpio_name, "gpio@%02x", addr); + + /* probe device on i2c bus */ + ret = dm_i2c_probe(bus, addr, 0, &dev); + switch (ret) { + case -EREMOTEIO: /* chip is not present on i2c bus */ + /* if device is in dt remove/unbind/disable it */ + ret = device_find_child_by_name(bus, gpio_name, &dev); + if (ret) + return ret; + ret = ofnode_set_enabled(dev_ofnode(dev), false); + if (ret) + return ret; + ret = device_unbind(dev); + if (ret) + return ret; + ret = device_remove(dev, DM_REMOVE_NORMAL); + if (ret) + return ret; + return ret; + case -ENOSYS: /* chip found but driver invalid */ + /* if device is in not in dt add/bind it */ + return ret; + case 0: /* chip responded and driver bound */ + break; + } + + if (devp) + *devp = dev; + return 0; +} + +/* add gpio's to gpio device: GPIO device must be probed before you can manipulate it */ +static int fsa_config_gpios(int fsa, struct fsa_user_info *info, int gpios, struct udevice *dev) +{ + struct fsa_gpio_desc *desc; + struct gpio_desc gdesc; + struct udevice *gdev; + int i, ret, flags; + char name[32]; + + /* configure GPIO's */ + for (i = 0; i < gpios; i++) { + desc = &info->gpios[i]; + if (desc->config < FSA_GPIO_INPUT) + continue; + memset(&gdesc, 0, sizeof(gdesc)); + + if (desc->source == 0xff) { + /* Board specific IMX8M GPIO's: find dev of controller by line-name */ + sprintf(name, "fsa%d_gpio%d", fsa, desc->offset + 1); + uclass_foreach_dev_probe(UCLASS_GPIO, gdev) { + ret = dev_read_stringlist_search(gdev, "gpio-line-names", name); + if (ret >= 0) { + gdesc.dev = gdev; + gdesc.offset = ret; + break; + } + } + } else { + /* port expander GPIOs */ + gdesc.dev = dev; + gdesc.offset = desc->offset; + } + + if (!gdesc.dev) + continue; + + sprintf(name, "fsa%d_%s", fsa, desc->name); + switch (desc->config) { + case FSA_GPIO_INPUT: + flags = GPIOD_IS_IN; + break; + case FSA_GPIO_OUTPUT_LOW: + flags = GPIOD_IS_OUT; + break; + case FSA_GPIO_OUTPUT_HIGH: + flags = GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE; + break; + } + if (!dm_gpio_request(&gdesc, name)) + dm_gpio_clrset_flags(&gdesc, GPIOD_MASK_DIR, flags); + } + + return 0; +} + +static int fsa_read_board_config(int fsa, struct fsa_board_info *info) +{ + struct udevice *dev; + int chksum; + int i, ret; + ofnode node; + + /* find eeprom dev */ + node = ofnode_find_subnode(fsa_get_ofnode(fsa), "eeprom@54"); + if (!ofnode_valid(node)) + return -EINVAL; + ret = device_get_global_by_ofnode(node, &dev); + if (ret) + return ret; + + /* read eeprom */ + ret = dm_i2c_read(dev, 0, (uint8_t *)info, sizeof(*info)); + if (ret) { + dev_err(dev, "read failed: %d\n", ret); + return ret; + } + + /* validate checksum */ + for (chksum = 0, i = 0; i < (int)sizeof(*info) - 2; i++) + chksum += ((unsigned char *)info)[i]; + if ((info->chksum[0] != ((chksum >> 8) & 0xff)) || + (info->chksum[1] != (chksum & 0xff))) { + dev_err(dev, "FSA%d EEPROM: Invalid User Config Checksum\n", fsa); + print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, info, sizeof(*info)); + memset(info, 0, sizeof(*info)); + return -EINVAL; + } + + return 0; +} + +static int fsa_read_user_config(int fsa, struct fsa_user_info *info) +{ + struct udevice *dev; + int chksum; + int i, ret; + ofnode node; + + /* find eeprom dev */ + node = ofnode_find_subnode(fsa_get_ofnode(fsa), "eeprom@55"); + if (!ofnode_valid(node)) + return -EINVAL; + ret = device_get_global_by_ofnode(node, &dev); + if (ret) + return ret; + + /* read eeprom */ + ret = dm_i2c_read(dev, 0, (uint8_t *)info, sizeof(*info)); + if (ret) { + dev_err(dev, "read failed: %d\n", ret); + return ret; + } + + /* validate checksum */ + for (chksum = 0, i = 0; i < (int)sizeof(*info) - 2; i++) + chksum += ((unsigned char *)info)[i]; + if ((info->chksum[0] != ((chksum >> 8) & 0xff)) || + (info->chksum[1] != (chksum & 0xff))) { + dev_err(dev, "FSA%d EEPROM: Invalid User Config Checksum\n", fsa); + print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, info, sizeof(*info)); + memset(info, 0, sizeof(*info)); + return -EINVAL; + } + + return 0; +} + +static int fsa_write_user_config(int fsa, struct fsa_user_info *info) +{ + struct udevice *bus, *dev; + int i, n, chunk, slave, base, ret; + ofnode node; + int chksum; + + /* create checksum */ + for (chksum = 0, i = 0; i < (int)sizeof(*info) - 2; i++) + chksum += ((unsigned char *)info)[i]; + info->chksum[0] = chksum >> 8; + info->chksum[1] = chksum & 0xff; + + /* find eeprom dev */ + node = ofnode_find_subnode(fsa_get_ofnode(fsa), "eeprom@55"); + ret = device_get_global_by_ofnode(node, &dev); + if (ret) + return ret; + bus = dev->parent; + base = dev_read_addr(dev); + + /* write in 16byte chunks (multi-byte writes fail larger than that) */ + chunk = 16; + slave = -1; + for (i = 0; i < sizeof(*info); i += chunk) { + /* select device based on offset */ + if ((base + (i / 256)) != slave) { + slave = base + (i / 256); + ret = i2c_get_chip(bus, slave, 1, &dev); + if (ret) { + dev_err(bus, "failed to get eeprom@0x%02x: %d\n", slave, ret); + return ret; + } + } + /* select byte count */ + n = sizeof(*info) - i; + if (n > chunk) + n = chunk; + ret = dm_i2c_write(dev, i % 256, (uint8_t *)info + i, n); + if (ret) { + dev_err(dev, "write failed: %d\n", ret); + return ret; + } + mdelay(11); + } + + return ret; +} + +static int fsa_detect(int fsa, struct fsa_board_info *board_info, struct fsa_user_info *user_info, + bool gpio) +{ + int ret; + + ret = fsa_read_board_config(fsa, board_info); + if (ret) + return ret; + if (user_info) { + ret = fsa_read_user_config(fsa, user_info); + if (ret) + return ret; + /* detect port expander */ + if (gpio && !fsa_get_gpiodev(fsa, 0x20, &fsa_gpiodevs[fsa])) + fsa_config_gpios(fsa, user_info, + board_info->sockgpios + board_info->ioexpgpios, + fsa_gpiodevs[fsa]); + } + + return ret; +} + +static int ft_fixup_stringlist_elem(void *fdt, int offset, const char *prop, int elem, + const char *val) +{ + const char *list, *end; + char *new, *buf; + int length; + int sz = 0; + int i = 0; + int ret; + + if (offset < 0 || elem < 0 || !val) { + printf("%s -EINVAL\n", __func__); + return -EINVAL; + } + + list = fdt_getprop(fdt, offset, prop, &length); + + /* no property or invalid params */ + if (!list || length < 0) { + printf("%s failed - no property\n", __func__); + return -EINVAL; + } + + /* create new buffer with enough space */ + buf = calloc(1, length + strlen(val)); + new = buf; + + /* iterate over current stringlist and build new list into buf */ + end = list + length; + while (list < end) { + length = strnlen(list, end - list) + 1; + sz += length; + /* insert new value into buf */ + if (elem == i) { + strcpy(new, val); + new += strlen(val) + 1; + } else { + strcpy(new, list); + new += length; + } + list += length; + i++; + } + length = new - buf; + ret = fdt_setprop(fdt, offset, prop, buf, length); + free(buf); + if (ret) + printf("%s failed %d\n", __func__, ret); + + return ret; +} + +static int ft_fixup_fsa_gpio_name(void *fdt, int offset, int fsa, int gpio, const char *name) +{ + const char *prop = "gpio-line-names"; + char str[32]; + + sprintf(str, "fsa%d_%s", fsa, name); + + if (!fdt_getprop(fdt, offset, prop, NULL)) { + char buf[16] = { 0 }; + + fdt_setprop(fdt, offset, prop, &buf, sizeof(buf)); + } + + return ft_fixup_stringlist_elem(fdt, offset, prop, gpio, str); +} + +static void fsa_show_details(int fsa, struct fsa_board_info *board, struct fsa_user_info *user) +{ + printf("FSA%d: %s\n", fsa, board->model); + printf("description: %s\n", user->desc); + printf("overlay: %s\n", user->overlay); + fsa_show_gpio_descs("\t", fsa, board, user); +} + +int fsa_init(void) +{ + struct fsa_board_info board_info; + struct fsa_user_info user_info; + int fsa, ret; + + for (fsa = 1; fsa < FSA_MAX; fsa++) { + ret = fsa_detect(fsa, &board_info, &user_info, true); + if (!ret) + printf("FSA%d: %s %s\n", fsa, board_info.model, user_info.desc); + } + + return 0; +} + +int fsa_show(void) +{ + struct fsa_board_info board_info; + int fsa, ret; + + for (fsa = 1; fsa < FSA_MAX; fsa++) { + ret = fsa_detect(fsa, &board_info, NULL, false); + if (!ret) { + printf("FSA%d : %s %d %02x-%02x-%02x%02x\n", fsa, + board_info.model, board_info.serial, + board_info.mfgdate[0], board_info.mfgdate[1], + board_info.mfgdate[2], board_info.mfgdate[3]); + } + } + return 0; +} + +/* fixup gpio line names for fsa gpios */ +int fsa_ft_fixup(void *fdt) +{ + struct fsa_board_info board_info; + struct fsa_user_info user_info; + int fsa, i, ret; + char path[128]; + char str[32]; + ofnode node; + int off; + + /* iterate over FSA's and rename gpio's */ + for (fsa = 1; fsa < FSA_MAX; fsa++) { + /* disable FSA ioexp node if disabled in controlling dt */ + off = fdt_subnode_offset(fdt, fsa_get_dtnode(fdt, fsa), "gpio@20"); + if (off >= 0) { + if (!fdt_get_path(fdt, off, path, sizeof(path))) { + node = ofnode_path(path); + if (ofnode_valid(node) && !ofnode_is_enabled(node)) + fdt_setprop_string(fdt, off, "status", "disabled"); + } + } + + /* detect FSA eeprom */ + if (fsa_detect(fsa, &board_info, &user_info, false)) + continue; + + /* configure GPIO's */ + for (i = 0; i < board_info.sockgpios + board_info.ioexpgpios; i++) { + if (user_info.gpios[i].config < FSA_GPIO_INPUT) + continue; + + if (user_info.gpios[i].source == 0xff) { + /* Board specific IMX8M GPIO's */ + for (off = fdt_node_offset_by_prop_value(fdt, 0, + "gpio-controller", NULL, + 0); + off >= 0; + off = fdt_node_offset_by_prop_value(fdt, off, + "gpio-controller", NULL, + 0) + ) { + sprintf(str, "fsa%d_gpio%d", fsa, + user_info.gpios[i].offset + 1); + ret = fdt_stringlist_search(fdt, off, "gpio-line-names", + str); + if (ret >= 0) { + ft_fixup_fsa_gpio_name(fdt, off, fsa, ret, + user_info.gpios[i].name); + break; + } + } + } else { + /* port expander GPIOs */ + off = fdt_subnode_offset(fdt, fsa_get_dtnode(fdt, fsa), "gpio@20"); + ft_fixup_fsa_gpio_name(fdt, off, fsa, user_info.gpios[i].offset, + user_info.gpios[i].name); + } + } + } + + return 0; +} + +static int do_fsa_dev(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[]) +{ + struct fsa_board_info board_info; + struct fsa_user_info user_info; + int i; + + if (argc < 2) { + /* list FSAs */ + printf("detecting FSA Adapters:\n"); + for (i = 1; i < FSA_MAX; i++) { + if (!fsa_read_board_config(i, &board_info) && + !fsa_read_user_config(i, &user_info)) + printf("FSA%d : %s %s\n", i, board_info.model, user_info.desc); + } + } else { + /* select FSA */ + fsa = simple_strtoul(argv[1], NULL, 10); + } + + if (fsa) { + /* read FSA */ + if (!fsa_read_board_config(fsa, &board_info) && + !fsa_read_user_config(fsa, &user_info)) { + printf("selected:\n"); + fsa_show_details(fsa, &board_info, &user_info); + } else { + printf("FSA%d not detected\n", fsa); + fsa = 0; + } + } else { + printf("no FSA currently selected\n"); + } + + return 0; +} + +static int do_fsa_desc(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[]) +{ + struct fsa_board_info board_info; + struct fsa_user_info user_info; + + /* strip off leading cmd arg */ + argc--; + argv++; + + if (!fsa) { + printf("No FSA selected\n"); + return CMD_RET_USAGE; + } + + if (fsa_read_board_config(fsa, &board_info) || fsa_read_user_config(fsa, &user_info)) { + printf("can't detect FSA%d\n", fsa); + return CMD_RET_USAGE; + } + + /* set */ + if (argc) { + strlcpy(user_info.desc, argv[0], sizeof(user_info.desc)); + if (fsa_write_user_config(fsa, &user_info)) + return CMD_RET_FAILURE; + } + + /* show */ + fsa_show_details(fsa, &board_info, &user_info); + + return CMD_RET_SUCCESS; +} + +static int do_fsa_overlay(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[]) +{ + struct fsa_board_info board_info; + struct fsa_user_info user_info; + + /* strip off leading cmd arg */ + argc--; + argv++; + + if (!fsa) { + printf("No FSA selected\n"); + return CMD_RET_USAGE; + } + + if (fsa_read_board_config(fsa, &board_info) || fsa_read_user_config(fsa, &user_info)) { + printf("can't detect FSA%d\n", fsa); + return CMD_RET_USAGE; + } + + /* set */ + if (argc) { + strlcpy(user_info.overlay, argv[0], sizeof(user_info.overlay)); + if (fsa_write_user_config(fsa, &user_info)) + return CMD_RET_FAILURE; + } + + /* show */ + fsa_show_details(fsa, &board_info, &user_info); + + return CMD_RET_SUCCESS; +} + +static int do_fsa_gpio(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[]) +{ + struct fsa_board_info board_info; + struct fsa_user_info user_info; + struct fsa_gpio_desc desc; + char str[64]; + int i, j; + + /* strip off leading cmd arg */ + argc--; + argv++; + + if (!fsa) { + printf("No FSA selected\n"); + return CMD_RET_USAGE; + } + + if (fsa_read_board_config(fsa, &board_info) || fsa_read_user_config(fsa, &user_info)) { + printf("can't detect FSA%d\n", fsa); + return CMD_RET_USAGE; + } + + if (!argc) { + /* show all gpios */ + fsa_show_gpio_descs("\t", fsa, &board_info, &user_info); + return CMD_RET_SUCCESS; + } + + if (!isdigit(argv[0][0])) { + printf("invalid gpio offset: %s\n", argv[0]); + return CMD_RET_USAGE; + } + + memset(&desc, 0, sizeof(desc)); + i = simple_strtoul(argv[0], NULL, 10); + + if (i >= 0 && i < board_info.sockgpios) { + desc.offset = i; + desc.source = 0xff; + } else if (i >= board_info.sockgpios && + i < (board_info.sockgpios + board_info.ioexpgpios) && + fsa_gpiodevs[fsa]) { + desc.offset = i - board_info.sockgpios; + desc.source = 0x20; + } else { + printf("invalid index %d", i); + return CMD_RET_FAILURE; + } + + if (argc > 1) { + if (user_info.gpios[i].config == FSA_GPIO_NC) { + printf("can not alter NC gpio\n"); + return CMD_RET_FAILURE; + } + strlcpy(desc.name, argv[1], sizeof(desc.name)); + if (!*desc.name) { + printf("FSA%d %s erasing gpio %d\n", fsa, board_info.model, i); + memset(&user_info.gpios[i], 0, sizeof(desc)); + if (fsa_write_user_config(fsa, &user_info)) + return CMD_RET_FAILURE; + return CMD_RET_SUCCESS; + } + } + if (argc > 2) { + if (user_info.gpios[i].config == FSA_GPIO_NC) { + printf("can not alter NC gpio\n"); + return CMD_RET_FAILURE; + } + for (j = 1; j < ARRAY_SIZE(fsa_gpio_config_names); j++) { + if (!strcasecmp(argv[2], fsa_gpio_config_names[j])) { + desc.config = j; + break; + } + }; + if (j >= ARRAY_SIZE(fsa_gpio_config_names)) { + printf("invalid config type '%s\n", argv[2]); + return CMD_RET_FAILURE; + } + } + + /* show a specific gpio */ + if (argc == 1) { + printf("FSA%d %s showing gpio %d\n", fsa, board_info.model, i); + printf("%s\n", fsa_get_gpio_desc(&user_info.gpios[i], str, sizeof(str))); + return CMD_RET_SUCCESS; + } + + /* set a specific gpio */ + else if (argc == 3) { + printf("FSA%d %s updating gpio %d\n", fsa, board_info.model, i); + memcpy(&user_info.gpios[i], &desc, sizeof(desc)); + if (fsa_write_user_config(fsa, &user_info)) + return CMD_RET_FAILURE; + return CMD_RET_SUCCESS; + } + + return CMD_RET_USAGE; +} + +static struct cmd_tbl cmd_fsa_sub[] = { + U_BOOT_CMD_MKENT(dev, 1, 1, do_fsa_dev, "", ""), + U_BOOT_CMD_MKENT(gpio, 4, 1, do_fsa_gpio, "", ""), + U_BOOT_CMD_MKENT(description, 1, 1, do_fsa_desc, "", ""), + U_BOOT_CMD_MKENT(overlay, 1, 1, do_fsa_overlay, "", ""), +}; + +static int do_fsa(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[]) +{ + struct cmd_tbl *c; + + /* strip off leading fsa arg */ + argc--; + argv++; + + c = find_cmd_tbl(argv[0], cmd_fsa_sub, ARRAY_SIZE(cmd_fsa_sub)); + if (c) + return c->cmd(cmdtp, flag, argc, argv); + return CMD_RET_USAGE; +} + +U_BOOT_LONGHELP(fsa, + "dev [dev] - show or set current FSA adapter\n" + "fsa gpio - show current gpio descriptors\n" + "fsa gpio [<offset>]|[<offset> <source>] - show a specific gpio descriptor\n" + "fsa gpio [<offset> <name> <input|output-low|output-high> [source]] - set a gpio descriptor\n" + "fsa description [description] - show or set the FSA user description string\n" + "fsa overlay [overlay] - show or set the FSA overlay string\n" +); + +U_BOOT_CMD(fsa, 6, 1, do_fsa, + "Flexible Socket Adapter", + fsa_help_text +); diff --git a/board/gateworks/fsa.h b/board/gateworks/fsa.h new file mode 100644 index 00000000000..ddb64499d78 --- /dev/null +++ b/board/gateworks/fsa.h @@ -0,0 +1,51 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2025 Gateworks Corporation + */ + +#ifndef _FSA_H_ +#define _FSA_H_ + +#define FSA_MAX 5 + +enum fsa_gpio_cfg { + FSA_GPIO_NC, + FSA_GPIO_UNCONFIGURED, + FSA_GPIO_INPUT, + FSA_GPIO_OUTPUT_LOW, + FSA_GPIO_OUTPUT_HIGH, +}; + +struct fsa_gpio_desc { + u8 offset; + u8 config; + u8 source; + char name[13]; +}; + +struct fsa_board_info { + char model[16]; /* 0x00: model string */ + u8 mac[6]; /* 0x10: MAC base */ + u8 macno; /* 0x16: number of mac addrs */ + u8 resv1; /* 0x17: reserved */ + u32 serial; /* 0x18: Serial Number */ + u8 mfgdate[4]; /* 0x1c: MFG date */ + u8 sockgpios; /* 0x20: number of socket gpio descriptors */ + u8 ioexpgpios; /* 0x21: number of io expander gpio descriptors */ + u8 resv2[220]; /* 0x22: reserved */ + u8 chksum[2]; /* 0xfe: */ +}; + +struct fsa_user_info { + char desc[32]; /* 0x000: user description */ + char overlay[16]; /* 0x020: dt-overlay suffice */ + struct fsa_gpio_desc gpios[20]; /* 0x030: gpio descriptors */ + u8 reserved[398]; /* 0x170: reserved */ + u8 chksum[2]; /* 0x2fe: */ +}; + +int fsa_init(void); +int fsa_show(void); +int fsa_ft_fixup(void *fdt); + +#endif // _FSA_H_ diff --git a/board/gateworks/gw_ventana/gw_ventana.c b/board/gateworks/gw_ventana/gw_ventana.c index 21a908c20dd..457d8281a66 100644 --- a/board/gateworks/gw_ventana/gw_ventana.c +++ b/board/gateworks/gw_ventana/gw_ventana.c @@ -6,6 +6,7 @@ */ #include <command.h> +#include <env.h> #include <fdt_support.h> #include <gsc.h> #include <hwconfig.h> diff --git a/board/gateworks/gw_ventana/gw_ventana_spl.c b/board/gateworks/gw_ventana/gw_ventana_spl.c index 3de4727b2ed..4385732a617 100644 --- a/board/gateworks/gw_ventana/gw_ventana_spl.c +++ b/board/gateworks/gw_ventana/gw_ventana_spl.c @@ -366,34 +366,34 @@ static struct mx6_mmdc_calibration mx6dq_256x32_mmdc_calib = { static struct mx6_mmdc_calibration mx6sdl_256x32_mmdc_calib = { /* write leveling calibration determine */ - .p0_mpwldectrl0 = 0X00480047, - .p0_mpwldectrl1 = 0X003D003F, + .p0_mpwldectrl0 = 0x00480047, + .p0_mpwldectrl1 = 0x003D003F, /* Read DQS Gating calibration */ - .p0_mpdgctrl0 = 0X423E0241, - .p0_mpdgctrl1 = 0X022B022C, + .p0_mpdgctrl0 = 0x423E0241, + .p0_mpdgctrl1 = 0x022B022C, /* Read Calibration: DQS delay relative to DQ read access */ - .p0_mprddlctl = 0X49454A4A, + .p0_mprddlctl = 0x49454A4A, /* Write Calibration: DQ/DM delay relative to DQS write access */ - .p0_mpwrdlctl = 0X2E372C32, + .p0_mpwrdlctl = 0x2E372C32, }; static struct mx6_mmdc_calibration mx6dq_256x64_mmdc_calib = { /* write leveling calibration determine */ - .p0_mpwldectrl0 = 0X00220021, - .p0_mpwldectrl1 = 0X00200030, - .p1_mpwldectrl0 = 0X002D0027, - .p1_mpwldectrl1 = 0X00150026, + .p0_mpwldectrl0 = 0x00220021, + .p0_mpwldectrl1 = 0x00200030, + .p1_mpwldectrl0 = 0x002D0027, + .p1_mpwldectrl1 = 0x00150026, /* Read DQS Gating calibration */ .p0_mpdgctrl0 = 0x43330342, .p0_mpdgctrl1 = 0x0339034A, .p1_mpdgctrl0 = 0x032F0325, .p1_mpdgctrl1 = 0x032F022E, /* Read Calibration: DQS delay relative to DQ read access */ - .p0_mprddlctl = 0X3A2E3437, - .p1_mprddlctl = 0X35312F3F, + .p0_mprddlctl = 0x3A2E3437, + .p1_mprddlctl = 0x35312F3F, /* Write Calibration: DQ/DM delay relative to DQS write access */ - .p0_mpwrdlctl = 0X33363B37, - .p1_mpwrdlctl = 0X40304239, + .p0_mpwrdlctl = 0x33363B37, + .p1_mpwrdlctl = 0x40304239, }; static struct mx6_mmdc_calibration mx6sdl_256x64_mmdc_calib = { diff --git a/board/gateworks/venice/Makefile b/board/gateworks/venice/Makefile index ab69e07ba7b..1aaf0295d5c 100644 --- a/board/gateworks/venice/Makefile +++ b/board/gateworks/venice/Makefile @@ -5,6 +5,7 @@ # obj-y += venice.o eeprom.o +obj-y += ../fsa.o ifdef CONFIG_XPL_BUILD obj-y += spl.o diff --git a/board/gateworks/venice/eeprom.c b/board/gateworks/venice/eeprom.c index afaabf34879..d9a87193434 100644 --- a/board/gateworks/venice/eeprom.c +++ b/board/gateworks/venice/eeprom.c @@ -6,9 +6,11 @@ #include <gsc.h> #include <hexdump.h> #include <i2c.h> +#include <dm/device.h> #include <dm/uclass.h> #include "eeprom.h" +#include "../fsa.h" /* I2C */ #define SOM_EEPROM_BUSNO 0 @@ -18,7 +20,8 @@ struct venice_board_info som_info; struct venice_board_info base_info; -char venice_model[32]; +char venice_model[64]; +char venice_som_model[32]; char venice_baseboard_model[32]; u32 venice_serial; @@ -107,7 +110,7 @@ static int eeprom_read(int busno, int slave, int alen, struct venice_board_info /* validate checksum */ for (chksum = 0, i = 0; i < (int)sizeof(*info) - 2; i++) chksum += buf[i]; - if ((info->chksum[0] != chksum >> 8) || + if ((info->chksum[0] != ((chksum >> 8) & 0xff)) || (info->chksum[1] != (chksum & 0xff))) { printf("EEPROM: I2C%d@0x%02x: Invalid Checksum\n", busno, slave); print_hex_dump_bytes("", DUMP_PREFIX_NONE, buf, sizeof(*info)); @@ -126,6 +129,54 @@ static int eeprom_read(int busno, int slave, int alen, struct venice_board_info return 0; } +static int fsa_eeprom_read(const char *base, int fsa, struct fsa_board_info *info) +{ + int i; + int chksum; + unsigned char *buf = (unsigned char *)info; + struct udevice *dev, *bus; + int ret; + u8 reg; + + /* probe mux */ + ret = uclass_get_device_by_seq(UCLASS_I2C, 2, &bus); + if (!ret) + ret = dm_i2c_probe(bus, 0x70, 0, &dev); + if (ret) + return ret; + /* steer mux */ + if (!strncmp(base, "GW82", 4)) { + if (fsa < 3) + reg = (fsa == 1) ? BIT(1) : BIT(0); + else + return -EINVAL; + } + dm_i2c_write(dev, 0x00, ®, 1); + + /* get eeprom */ + ret = dm_i2c_probe(bus, 0x54, 0, &dev); + if (ret) + return ret; + + /* read eeprom config section */ + ret = dm_i2c_read(dev, 0x00, buf, sizeof(*info)); + if (ret) + return ret; + + /* validate checksum */ + for (chksum = 0, i = 0; i < (int)sizeof(*info) - 2; i++) + chksum += buf[i]; + if ((info->chksum[0] != ((chksum >> 8) & 0xff)) || + (info->chksum[1] != (chksum & 0xff))) { + printf("FSA%d EEPROM (board): %s: Invalid Checksum\n", fsa, dev->name); + print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, buf, sizeof(*info)); + memset(info, 0, sizeof(*info)); + return -EINVAL; + } + + return 0; +} + /* determine BOM revision from model */ int get_bom_rev(const char *str) { @@ -299,6 +350,8 @@ static int eeprom_info(bool verbose) base_info.mfgdate[0], base_info.mfgdate[1], base_info.mfgdate[2], base_info.mfgdate[3]); } + if (verbose) + fsa_show(); return 0; } @@ -315,6 +368,7 @@ int venice_eeprom_init(int quiet) memset(&som_info, 0, sizeof(som_info)); return 0; } + strlcpy(venice_som_model, som_info.model, sizeof(venice_som_model)); /* read optional baseboard EEPROM */ eeprom_read(BASEBOARD_EEPROM_BUSNO, BASEBOARD_EEPROM_ADDR, 2, &base_info); @@ -322,7 +376,7 @@ int venice_eeprom_init(int quiet) /* create model strings */ if (base_info.model[0]) { sprintf(venice_model, "GW%c%c%c%c-%c%c-", - som_info.model[2], /* family */ + base_info.model[2], /* family */ base_info.model[3], /* baseboard */ base_info.model[4], base_info.model[5], /* subload of baseboard */ som_info.model[4], som_info.model[5]); /* last 2digits of SOM */ @@ -347,9 +401,74 @@ int venice_eeprom_init(int quiet) } venice_serial = som_info.serial; + /* GW8xxx product family naming scheme */ + if (venice_model[2] == '8') { + struct fsa_board_info fsa_info; + int i = 0; + int fsa; + + /* baseboard */ + if (base_info.model[0]) { + rev_pcb = get_pcb_rev(base_info.model); + rev_bom = get_bom_rev(base_info.model); + venice_model[i++] = 'G'; + venice_model[i++] = 'W'; + venice_model[i++] = base_info.model[2]; /* baseboard */ + venice_model[i++] = base_info.model[3]; + venice_model[i++] = base_info.model[4]; /* subload */ + venice_model[i++] = base_info.model[5]; + venice_model[i++] = rev_pcb; + if (rev_bom) + venice_model[i++] = rev_bom; + venice_model[i++] = '-'; + venice_model[i++] = 'S'; + } else { + venice_model[i++] = 'G'; + venice_model[i++] = 'W'; + } + + /* som */ + rev_pcb = get_pcb_rev(som_info.model); + rev_bom = get_bom_rev(som_info.model); + venice_model[i++] = som_info.model[4]; + venice_model[i++] = som_info.model[5]; + venice_model[i++] = rev_pcb; + if (rev_bom) + venice_model[i++] = rev_bom; + + /* fsa */ + for (fsa = 1; fsa < FSA_MAX; fsa++) { + if (!fsa_eeprom_read(venice_model, fsa, &fsa_info)) { + venice_model[i++] = '-'; + venice_model[i++] = 'F'; + venice_model[i++] = '0' + fsa; + venice_model[i++] = fsa_info.model[5]; + venice_model[i++] = fsa_info.model[6]; + venice_model[i++] = fsa_info.model[8]; + if (fsa_info.model[9]) + venice_model[i++] = fsa_info.model[9]; + } + } + + /* append extra model info */ + if (som_info.config[0] >= 32 && som_info.config[0] < 0x7f) { + venice_model[i++] = '-'; + strlcpy(venice_model + i, som_info.config, (sizeof(venice_model) - i) - 1); + i += strlen(som_info.config); + if (i >= sizeof(venice_model)) + i = sizeof(venice_model) - 1; + } + venice_model[i++] = 0; + } + if (!quiet) eeprom_info(false); + if (!strncmp(venice_model, "GW7901-SP486", 12) && + strcmp(venice_model, "GW7901-SP486-C")) { + return 2048; + } + return (16 << som_info.sdram_size); } @@ -363,6 +482,11 @@ const char *eeprom_get_model(void) return venice_model; } +const char *eeprom_get_som_model(void) +{ + return venice_som_model; +} + const char *eeprom_get_baseboard_model(void) { return venice_baseboard_model; diff --git a/board/gateworks/venice/eeprom.h b/board/gateworks/venice/eeprom.h index bb7a5fa9ad1..a0f449299aa 100644 --- a/board/gateworks/venice/eeprom.h +++ b/board/gateworks/venice/eeprom.h @@ -20,12 +20,13 @@ struct venice_board_info { u8 sdram_width; /* 0x2D: (8 << n) bit */ u8 res3[2]; /* 0x2E */ char model[16]; /* 0x30: model string */ - u8 res4[14]; /* 0x40 */ + u8 config[14]; /* 0x40: model config */ u8 chksum[2]; /* 0x4E */ }; int venice_eeprom_init(int quiet); const char *eeprom_get_model(void); +const char *eeprom_get_som_model(void); const char *eeprom_get_baseboard_model(void); const char *eeprom_get_dtb_name(int level, char *buf, int len); int eeprom_getmac(int index, uint8_t *enetaddr); diff --git a/board/gateworks/venice/lpddr4_timing.h b/board/gateworks/venice/lpddr4_timing.h index d19902f10ec..21997f6fb2a 100644 --- a/board/gateworks/venice/lpddr4_timing.h +++ b/board/gateworks/venice/lpddr4_timing.h @@ -6,18 +6,6 @@ #ifndef __LPDDR4_TIMING_H__ #define __LPDDR4_TIMING_H__ -#ifdef CONFIG_IMX8MM -extern struct dram_timing_info dram_timing_512mb; -extern struct dram_timing_info dram_timing_1gb; -extern struct dram_timing_info dram_timing_2gb; -extern struct dram_timing_info dram_timing_4gb; -#elif CONFIG_IMX8MN -extern struct dram_timing_info dram_timing_1gb_single_die; -extern struct dram_timing_info dram_timing_2gb_single_die; -extern struct dram_timing_info dram_timing_2gb_dual_die; -#elif CONFIG_IMX8MP -extern struct dram_timing_info dram_timing_1gb_single_die; -extern struct dram_timing_info dram_timing_4gb_dual_die; -#endif +extern struct dram_timing_info *spl_dram_init(const char *model, int sizemb); #endif /* __LPDDR4_TIMING_H__ */ diff --git a/board/gateworks/venice/lpddr4_timing_imx8mm.c b/board/gateworks/venice/lpddr4_timing_imx8mm.c index 3f2c090a94f..956071c5125 100644 --- a/board/gateworks/venice/lpddr4_timing_imx8mm.c +++ b/board/gateworks/venice/lpddr4_timing_imx8mm.c @@ -6,6 +6,7 @@ */ #include <linux/kernel.h> +#include <string.h> #include <asm/arch/ddr.h> #include <asm/arch/lpddr4_define.h> @@ -1333,7 +1334,7 @@ static struct dram_cfg_param ddr_ddrc_cfg_512mb[] = { { 0x3d400304, 0x1 }, { 0x3d400030, 0x1 }, { 0x3d400000, 0xa1080020 }, - { 0x3d400020, 0x203 }, + { 0x3d400020, 0x223 }, { 0x3d400024, 0x3a980 }, { 0x3d400064, 0x5b0062 }, { 0x3d4000d0, 0xc00305ba }, @@ -1385,7 +1386,7 @@ static struct dram_cfg_param ddr_ddrc_cfg_512mb[] = { { 0x3d400498, 0x620096 }, { 0x3d40049c, 0x1100e07 }, { 0x3d4004a0, 0xc8012c }, - { 0x3d402020, 0x1 }, + { 0x3d402020, 0x21 }, { 0x3d402024, 0x7d00 }, { 0x3d402050, 0x20d040 }, { 0x3d402064, 0xc000d }, @@ -1410,7 +1411,7 @@ static struct dram_cfg_param ddr_ddrc_cfg_512mb[] = { { 0x3d402194, 0x80303 }, { 0x3d4021b4, 0x100 }, { 0x3d4020f4, 0xc99 }, - { 0x3d403020, 0x1 }, + { 0x3d403020, 0x21 }, { 0x3d403024, 0x1f40 }, { 0x3d403050, 0x20d040 }, { 0x3d403064, 0x30004 }, @@ -1459,9 +1460,9 @@ static struct dram_cfg_param ddr_ddrphy_cfg_512mb[] = { { 0x120a0, 0x0 }, { 0x120a1, 0x1 }, { 0x120a2, 0x3 }, - { 0x120a3, 0x4 }, + { 0x120a3, 0x2 }, { 0x120a4, 0x5 }, - { 0x120a5, 0x2 }, + { 0x120a5, 0x4 }, { 0x120a6, 0x7 }, { 0x120a7, 0x6 }, { 0x130a0, 0x0 }, @@ -1830,7 +1831,7 @@ static struct dram_fsp_msg ddr_dram_fsp_msg_512mb[] = { }; /* ddr timing config params */ -struct dram_timing_info dram_timing_512mb = { +static struct dram_timing_info dram_timing_512mb = { .ddrc_cfg = ddr_ddrc_cfg_512mb, .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg_512mb), .ddrphy_cfg = ddr_ddrphy_cfg_512mb, @@ -2489,7 +2490,7 @@ static struct dram_fsp_msg lpddr4_dram_fsp_msg_1gb[] = { }; /* lpddr4 timing config params */ -struct dram_timing_info dram_timing_1gb = { +static struct dram_timing_info dram_timing_1gb = { .ddrc_cfg = lpddr4_ddrc_cfg_1gb, .ddrc_cfg_num = ARRAY_SIZE(lpddr4_ddrc_cfg_1gb), .ddrphy_cfg = lpddr4_ddrphy_cfg_1gb, @@ -3005,7 +3006,7 @@ static struct dram_fsp_msg lpddr4_dram_fsp_msg_4gb[] = { }; /* lpddr4 timing config params */ -struct dram_timing_info dram_timing_4gb = { +static struct dram_timing_info dram_timing_4gb = { .ddrc_cfg = lpddr4_ddrc_cfg_4gb, .ddrc_cfg_num = ARRAY_SIZE(lpddr4_ddrc_cfg_4gb), .ddrphy_cfg = lpddr4_ddrphy_cfg_4gb, @@ -3140,12 +3141,12 @@ static struct dram_cfg_param lpddr4_ddrphy_cfg_2gb[] = { { 0x100a7, 0x7 }, { 0x110a0, 0x0 }, { 0x110a1, 0x1 }, - { 0x110a2, 0x2 }, - { 0x110a3, 0x3 }, - { 0x110a4, 0x4 }, - { 0x110a5, 0x5 }, - { 0x110a6, 0x6 }, - { 0x110a7, 0x7 }, + { 0x110a2, 0x3 }, + { 0x110a3, 0x4 }, + { 0x110a4, 0x5 }, + { 0x110a5, 0x2 }, + { 0x110a6, 0x7 }, + { 0x110a7, 0x6 }, { 0x120a0, 0x0 }, { 0x120a1, 0x1 }, { 0x120a2, 0x3 }, @@ -3156,12 +3157,12 @@ static struct dram_cfg_param lpddr4_ddrphy_cfg_2gb[] = { { 0x120a7, 0x6 }, { 0x130a0, 0x0 }, { 0x130a1, 0x1 }, - { 0x130a2, 0x5 }, - { 0x130a3, 0x2 }, - { 0x130a4, 0x3 }, - { 0x130a5, 0x4 }, - { 0x130a6, 0x7 }, - { 0x130a7, 0x6 }, + { 0x130a2, 0x2 }, + { 0x130a3, 0x3 }, + { 0x130a4, 0x4 }, + { 0x130a5, 0x5 }, + { 0x130a6, 0x6 }, + { 0x130a7, 0x7 }, { 0x1005f, 0x1ff }, { 0x1015f, 0x1ff }, { 0x1105f, 0x1ff }, @@ -3521,7 +3522,7 @@ static struct dram_fsp_msg lpddr4_dram_fsp_msg_2gb[] = { }; /* lpddr4 timing config params */ -struct dram_timing_info dram_timing_2gb = { +static struct dram_timing_info dram_timing_2gb = { .ddrc_cfg = lpddr4_ddrc_cfg_2gb, .ddrc_cfg_num = ARRAY_SIZE(lpddr4_ddrc_cfg_2gb), .ddrphy_cfg = lpddr4_ddrphy_cfg_2gb, @@ -3534,3 +3535,63 @@ struct dram_timing_info dram_timing_2gb = { .ddrphy_pie_num = ARRAY_SIZE(lpddr4_phy_pie), .fsp_table = { 3000, 400, 100, }, }; + +static void apply_cfg_patch(struct dram_cfg_param *cfg, int cfg_sz, + struct dram_cfg_param *patch, int patch_sz) +{ + int i, j; + + for (i = 0; i < cfg_sz; i++) + for (j = 0; j < patch_sz; j++) + if (cfg[i].reg == patch[j].reg) + cfg[i].val = patch[j].val; +} + +static struct dram_cfg_param ddr_ddrc_cfg_alt_patch[] = { + { 0x3d400020, 0x203}, + { 0x3d402020, 0x1}, + { 0x3d403020, 0x1} +}; + +static struct dram_cfg_param ddr_ddrphy_cfg_alt_patch[] = { + { 0x120a3, 0x4 }, + { 0x120a5, 0x2 }, +}; + +struct dram_timing_info *spl_dram_init(const char *model, int sizemb) +{ + struct dram_timing_info *dram_timing; + + switch (sizemb) { + case 512: + dram_timing = &dram_timing_512mb; + break; + case 1024: + dram_timing = &dram_timing_1gb; + break; + case 2048: + dram_timing = &dram_timing_2gb; + break; + case 4096: + dram_timing = &dram_timing_4gb; + break; + default: + printf("unsupported"); + dram_timing = &dram_timing_1gb; + } + + /* apply ddrc/phy register changes for alternate dram bus layout */ + if (!strncmp(model, "GW7902", 6) || + !strncmp(model, "GW7903", 6) || + !strncmp(model, "GW7904", 6)) { + apply_cfg_patch(dram_timing->ddrc_cfg, dram_timing->ddrc_cfg_num, + ddr_ddrc_cfg_alt_patch, + ARRAY_SIZE(ddr_ddrc_cfg_alt_patch)); + + apply_cfg_patch(dram_timing->ddrphy_cfg, dram_timing->ddrphy_cfg_num, + ddr_ddrphy_cfg_alt_patch, + ARRAY_SIZE(ddr_ddrphy_cfg_alt_patch)); + } + + return dram_timing; +} diff --git a/board/gateworks/venice/lpddr4_timing_imx8mn.c b/board/gateworks/venice/lpddr4_timing_imx8mn.c index 9ba2d2571ce..e7d04822c9c 100644 --- a/board/gateworks/venice/lpddr4_timing_imx8mn.c +++ b/board/gateworks/venice/lpddr4_timing_imx8mn.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ #include <linux/kernel.h> +#include <string.h> #include <asm/arch/ddr.h> /* @@ -1425,7 +1426,7 @@ static struct dram_fsp_msg ddr_dram_fsp_msg_1gb_single_die[] = { }; /* ddr timing config params */ -struct dram_timing_info dram_timing_1gb_single_die = { +static struct dram_timing_info dram_timing_1gb_single_die = { .ddrc_cfg = ddr_ddrc_cfg_1gb_single_die, .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg_1gb_single_die), .ddrphy_cfg = ddr_ddrphy_cfg_1gb_single_die, @@ -1890,7 +1891,7 @@ static struct dram_fsp_msg ddr_dram_fsp_msg_2gb_single_die[] = { }; /* ddr timing config params */ -struct dram_timing_info dram_timing_2gb_single_die = { +static struct dram_timing_info dram_timing_2gb_single_die = { .ddrc_cfg = ddr_ddrc_cfg_2gb_single_die, .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg_2gb_single_die), .ddrphy_cfg = ddr_ddrphy_cfg_2gb_single_die, @@ -2354,7 +2355,7 @@ static struct dram_fsp_msg ddr_dram_fsp_msg_2gb_dual_die[] = { }; /* ddr timing config params */ -struct dram_timing_info dram_timing_2gb_dual_die = { +static struct dram_timing_info dram_timing_2gb_dual_die = { .ddrc_cfg = ddr_ddrc_cfg_2gb_dual_die, .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg_2gb_dual_die), .ddrphy_cfg = ddr_ddrphy_cfg_2gb_dual_die, @@ -2367,3 +2368,27 @@ struct dram_timing_info dram_timing_2gb_dual_die = { .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), .fsp_table = { 3200, 400, 100, }, }; + +struct dram_timing_info *spl_dram_init(const char *model, int sizemb) +{ + struct dram_timing_info *dram_timing; + + switch (sizemb) { + case 1024: + dram_timing = &dram_timing_1gb_single_die; + break; + case 2048: + if (!strcmp(model, "GW7902-SP466-A") || + !strcmp(model, "GW7902-SP466-B")) { + dram_timing = &dram_timing_2gb_dual_die; + } else { + dram_timing = &dram_timing_2gb_single_die; + } + break; + default: + printf("unsupported"); + dram_timing = &dram_timing_2gb_dual_die; + } + + return dram_timing; +} diff --git a/board/gateworks/venice/lpddr4_timing_imx8mp.c b/board/gateworks/venice/lpddr4_timing_imx8mp.c index 56c6e2b5cff..36c4cb147e8 100644 --- a/board/gateworks/venice/lpddr4_timing_imx8mp.c +++ b/board/gateworks/venice/lpddr4_timing_imx8mp.c @@ -1832,7 +1832,7 @@ struct dram_fsp_msg ddr_dram_fsp_msg_1gb_single_die[] = { }; /* ddr timing config params */ -struct dram_timing_info dram_timing_1gb_single_die = { +static struct dram_timing_info dram_timing_1gb_single_die = { .ddrc_cfg = ddr_ddrc_cfg_1gb_single_die, .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg_1gb_single_die), .ddrphy_cfg = ddr_ddrphy_cfg_1gb_single_die, @@ -2364,7 +2364,7 @@ static struct dram_fsp_msg ddr_dram_fsp_msg_4gb_dual_die[] = { }; /* ddr timing config params */ -struct dram_timing_info dram_timing_4gb_dual_die = { +static struct dram_timing_info dram_timing_4gb_dual_die = { .ddrc_cfg = ddr_ddrc_cfg_4gb_dual_die, .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg_4gb_dual_die), .ddrphy_cfg = ddr_ddrphy_cfg_4gb_dual_die, @@ -2377,3 +2377,22 @@ struct dram_timing_info dram_timing_4gb_dual_die = { .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), .fsp_table = { 4000, 400, 100, }, }; + +struct dram_timing_info *spl_dram_init(const char *model, int sizemb) +{ + struct dram_timing_info *dram_timing; + + switch (sizemb) { + case 1024: + dram_timing = &dram_timing_1gb_single_die; + break; + case 4096: + dram_timing = &dram_timing_4gb_dual_die; + break; + default: + printf("unsupported"); + dram_timing = &dram_timing_4gb_dual_die; + } + + return dram_timing; +} diff --git a/board/gateworks/venice/spl.c b/board/gateworks/venice/spl.c index bcdc1a2a468..e813f3e763e 100644 --- a/board/gateworks/venice/spl.c +++ b/board/gateworks/venice/spl.c @@ -32,69 +32,6 @@ #define PCIE_RSTN IMX_GPIO_NR(4, 6) -static void spl_dram_init(int size) -{ - struct dram_timing_info *dram_timing; - - switch (size) { -#ifdef CONFIG_IMX8MM - case 512: - dram_timing = &dram_timing_512mb; - break; - case 1024: - dram_timing = &dram_timing_1gb; - break; - case 2048: - dram_timing = &dram_timing_2gb; - break; - case 4096: - dram_timing = &dram_timing_4gb; - break; - default: - printf("Unknown DDR configuration: %d MiB\n", size); - dram_timing = &dram_timing_1gb; - size = 1024; -#elif CONFIG_IMX8MN - case 1024: - dram_timing = &dram_timing_1gb_single_die; - break; - case 2048: - if (!strcmp(eeprom_get_model(), "GW7902-SP466-A") || - !strcmp(eeprom_get_model(), "GW7902-SP466-B")) { - dram_timing = &dram_timing_2gb_dual_die; - } else { - dram_timing = &dram_timing_2gb_single_die; - } - break; - default: - printf("Unknown DDR configuration: %d MiB\n", size); - dram_timing = &dram_timing_2gb_dual_die; - size = 2048; -#elif CONFIG_IMX8MP - case 1024: - dram_timing = &dram_timing_1gb_single_die; - break; - case 4096: - dram_timing = &dram_timing_4gb_dual_die; - break; - default: - printf("Unknown DDR configuration: %d GiB\n", size); - dram_timing = &dram_timing_4gb_dual_die; - size = 4096; -#endif - } - - printf("DRAM : LPDDR4 "); - if (size > 512) - printf("%d GiB", size / 1024); - else - printf("%d MiB", size); - printf(" %dMT/s %dMHz\n", - dram_timing->fsp_msg[0].drate, - dram_timing->fsp_msg[0].drate / 2); - ddr_init(dram_timing); -} - /* * Model specific PMIC adjustments necessary prior to DRAM init * @@ -118,21 +55,23 @@ static int dm_i2c_clrsetbits(struct udevice *dev, uint reg, uint clr, uint set) return dm_i2c_write(dev, reg, &val, 1); } -static int power_init_board(struct udevice *gsc) +static int power_init_board(const char *model, struct udevice *gsc) { - const char *model = eeprom_get_model(); + const char *som = eeprom_get_som_model(); struct udevice *bus; struct udevice *dev; int ret; - /* Enable GSC voltage supervisor for new board models */ - if ((!strncmp(model, "GW7100", 6) && model[10] > 'D') || - (!strncmp(model, "GW7101", 6) && model[10] > 'D') || - (!strncmp(model, "GW7200", 6) && model[10] > 'E') || - (!strncmp(model, "GW7201", 6) && model[10] > 'E') || - (!strncmp(model, "GW7300", 6) && model[10] > 'E') || - (!strncmp(model, "GW7301", 6) && model[10] > 'E') || - (!strncmp(model, "GW740", 5) && model[7] > 'B')) { + /* Enable GSC voltage supervisor only for newew board models */ + if ((!strncmp(model, "GW7100", 6) && model[10] < 'E') || + (!strncmp(model, "GW7101", 6) && model[10] < 'E') || + (!strncmp(model, "GW7200", 6) && model[10] < 'F') || + (!strncmp(model, "GW7201", 6) && model[10] < 'F') || + (!strncmp(model, "GW7300", 6) && model[10] < 'F') || + (!strncmp(model, "GW7301", 6) && model[10] < 'F') || + (!strncmp(model, "GW740", 5) && model[7] < 'C')) { + printf("GSC : voltage supervisor disabled\n"); + } else { u8 ver; if (!dm_i2c_read(gsc, 14, &ver, 1) && ver > 62) { @@ -141,10 +80,7 @@ static int power_init_board(struct udevice *gsc) } } - if ((!strncmp(model, "GW71", 4)) || - (!strncmp(model, "GW72", 4)) || - (!strncmp(model, "GW73", 4)) || - (!strncmp(model, "GW75", 4))) { + if (!strncmp(som, "GW70", 4)) { ret = uclass_get_device_by_seq(UCLASS_I2C, 0, &bus); if (ret) { printf("PMIC : failed I2C1 probe: %d\n", ret); @@ -251,9 +187,11 @@ static int power_init_board(struct udevice *gsc) void board_init_f(ulong dummy) { + struct dram_timing_info *dram_timing; struct udevice *bus, *dev; + const char *model; + int dram_szmb; int i, ret; - int dram_sz; arch_cpu_init(); @@ -311,13 +249,23 @@ void board_init_f(ulong dummy) break; mdelay(1); } - dram_sz = venice_eeprom_init(0); + dram_szmb = venice_eeprom_init(0); + model = eeprom_get_model(); /* PMIC */ - power_init_board(dev); + power_init_board(model, dev); /* DDR initialization */ - spl_dram_init(dram_sz); + printf("DRAM : LPDDR4 "); + if (dram_szmb > 512) + printf("%d GiB", dram_szmb / 1024); + else + printf("%d MiB", dram_szmb); + dram_timing = spl_dram_init(model, dram_szmb); + printf(" %dMT/s %dMHz\n", + dram_timing->fsp_msg[0].drate, + dram_timing->fsp_msg[0].drate / 2); + ddr_init(dram_timing); board_init_r(NULL, 0); } diff --git a/board/gateworks/venice/venice.c b/board/gateworks/venice/venice.c index 98b33624f04..6a24f618ae2 100644 --- a/board/gateworks/venice/venice.c +++ b/board/gateworks/venice/venice.c @@ -3,6 +3,7 @@ * Copyright 2021 Gateworks Corporation */ +#include <env.h> #include <fdt_support.h> #include <init.h> #include <led.h> @@ -14,6 +15,7 @@ #include <asm/mach-imx/boot_mode.h> #include "eeprom.h" +#include "../fsa.h" int board_phys_sdram_size(phys_size_t *size) { @@ -75,6 +77,9 @@ int board_init(void) { venice_eeprom_init(1); + /* detect and configure FSA adapters */ + fsa_init(); + return 0; } @@ -221,6 +226,9 @@ int ft_board_setup(void *fdt, struct bd_info *bd) /* set board model dt prop */ fdt_setprop_string(fdt, 0, "board", eeprom_get_model()); + /* fixups for FSA adapters */ + fsa_ft_fixup(fdt); + if (!strncmp(base_model, "GW73", 4)) { pcbrev = get_pcb_rev(base_model); path = fdt_get_alias(fdt, "ethernet1"); diff --git a/board/ge/b1x5v2/b1x5v2.c b/board/ge/b1x5v2/b1x5v2.c index c1aacd1458b..ddb7304d493 100644 --- a/board/ge/b1x5v2/b1x5v2.c +++ b/board/ge/b1x5v2/b1x5v2.c @@ -17,6 +17,7 @@ #include <asm/io.h> #include <asm/mach-imx/video.h> #include <command.h> +#include <env.h> #include <i2c.h> #include <input.h> #include <ipu_pixfmt.h> diff --git a/board/google/chameleonv3/board.c b/board/google/chameleonv3/board.c index 4d3049689d3..d8ffdd25b38 100644 --- a/board/google/chameleonv3/board.c +++ b/board/google/chameleonv3/board.c @@ -2,6 +2,8 @@ /* * Copyright 2022 Google LLC */ + +#include <env.h> #include <net.h> #include <errno.h> #include "mercury_aa1.h" diff --git a/board/google/chromebook_coral/coral.c b/board/google/chromebook_coral/coral.c index db96534857c..b4053fa097d 100644 --- a/board/google/chromebook_coral/coral.c +++ b/board/google/chromebook_coral/coral.c @@ -11,13 +11,13 @@ #include <dm.h> #include <event.h> #include <init.h> +#include <intel_gnvs.h> #include <log.h> #include <sysinfo.h> #include <acpi/acpigen.h> #include <asm-generic/gpio.h> #include <asm/acpi_nhlt.h> #include <asm/cb_sysinfo.h> -#include <asm/intel_gnvs.h> #include <asm/intel_pinctrl.h> #include <dm/acpi.h> #include <linux/delay.h> diff --git a/board/grinn/liteboard/board.c b/board/grinn/liteboard/board.c index c2a44b4aa2d..492d1dc1d8c 100644 --- a/board/grinn/liteboard/board.c +++ b/board/grinn/liteboard/board.c @@ -84,7 +84,7 @@ static int mmc_get_env_devno(void) /* If not boot from sd/mmc, use default value */ if (bootsel != 1) - return CONFIG_SYS_MMC_ENV_DEV; + return CONFIG_ENV_MMC_DEVICE_INDEX; /* BOOT_CFG2[3] and BOOT_CFG2[4] */ dev_no = (soc_sbmr & 0x00001800) >> 11; diff --git a/board/imgtec/malta/malta.c b/board/imgtec/malta/malta.c index 4a72ab5ceca..0ffa964178f 100644 --- a/board/imgtec/malta/malta.c +++ b/board/imgtec/malta/malta.c @@ -6,7 +6,6 @@ #include <config.h> #include <fdt_support.h> -#include <ide.h> #include <init.h> #include <net.h> #include <netdev.h> diff --git a/board/isee/igep00x0/igep00x0.c b/board/isee/igep00x0/igep00x0.c index a35a7cd3b1f..c21b083b62a 100644 --- a/board/isee/igep00x0/igep00x0.c +++ b/board/isee/igep00x0/igep00x0.c @@ -7,6 +7,7 @@ #include <env.h> #include <init.h> #include <malloc.h> +#include <mtd.h> #include <net.h> #include <status_led.h> #include <dm.h> diff --git a/board/keymile/kmcent2/kmcent2.c b/board/keymile/kmcent2/kmcent2.c index 783853d5c6f..0f43ebfec4d 100644 --- a/board/keymile/kmcent2/kmcent2.c +++ b/board/keymile/kmcent2/kmcent2.c @@ -6,6 +6,7 @@ * Copyright 2013 Freescale Semiconductor, Inc. */ +#include <env.h> #include <event.h> #include <asm/cache.h> #include <asm/fsl_fdt.h> diff --git a/board/kontron/sl-mx6ul/spl.c b/board/kontron/sl-mx6ul/spl.c index b1758858705..33e5337bcbc 100644 --- a/board/kontron/sl-mx6ul/spl.c +++ b/board/kontron/sl-mx6ul/spl.c @@ -204,7 +204,7 @@ static struct mx6_ddr3_cfg mem_512M_ddr = { static struct mx6_mmdc_calibration mx6_mmcd_512M_calib = { .p0_mpwldectrl0 = 0x00000000, - .p0_mpdgctrl0 = 0X01440144, + .p0_mpdgctrl0 = 0x01440144, .p0_mprddlctl = 0x40405454, .p0_mpwrdlctl = 0x40404E4C, }; diff --git a/board/lg/star/star.c b/board/lg/star/star.c index dc593754101..0b4a433a5df 100644 --- a/board/lg/star/star.c +++ b/board/lg/star/star.c @@ -9,6 +9,7 @@ #include <fdt_support.h> #include <log.h> #include <spl_gpio.h> +#include <asm/gpio.h> static int star_fix_panel(void *fdt) { diff --git a/board/liebherr/btt/Kconfig b/board/liebherr/btt/Kconfig new file mode 100644 index 00000000000..ff35dd04532 --- /dev/null +++ b/board/liebherr/btt/Kconfig @@ -0,0 +1,24 @@ +if TARGET_BTT + +config SYS_BOARD + default "btt" + +config SYS_VENDOR + default "liebherr" + +config SYS_SOC + default "mxs" + +config SYS_CONFIG_NAME + default "btt" + +config ENV_SIZE + default 0x2000 + +config ENV_SECT_SIZE + default 0x10000 if ENV_IS_IN_SPI_FLASH + +config ENV_OFFSET + default 0x80000 if ENV_IS_IN_SPI_FLASH + +endif diff --git a/board/liebherr/btt/MAINTAINERS b/board/liebherr/btt/MAINTAINERS new file mode 100644 index 00000000000..b4afed5aaeb --- /dev/null +++ b/board/liebherr/btt/MAINTAINERS @@ -0,0 +1,6 @@ +BTT BOARD +M: Lukasz Majewski <lukma@denx.de> +S: Maintained +F: board/liebherr/btt/ +F: include/configs/btt.h +F: configs/imx28_btt3_defconfig diff --git a/board/liebherr/btt/Makefile b/board/liebherr/btt/Makefile new file mode 100644 index 00000000000..a8ab657a9e0 --- /dev/null +++ b/board/liebherr/btt/Makefile @@ -0,0 +1,9 @@ +# +# (C) Copyright 2025 +# Lukasz Majewski, DENX Software Engineering, lukma@denx.de. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := btt.o +obj-$(CONFIG_XPL_BUILD) += spl_btt.o diff --git a/board/liebherr/btt/boot_img_scr.h b/board/liebherr/btt/boot_img_scr.h new file mode 100644 index 00000000000..baa3072b49c --- /dev/null +++ b/board/liebherr/btt/boot_img_scr.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Struct for boot image source description for placing in last + * two SPI NOR flash sectors on legcom. + */ + +struct boot_img_src { + u8 magic; /* Must be 'B' = 0x42 */ + u8 flags; /* flags to specify mmcblk[0|1] boot[0|1] */ + u8 crc8; /* CRC-8 over above two bytes */ +} __packed; + +/* + * Bit definition in boot_img_src.flags: + * Bit 0: mmcblk device 0 or 1 (1 - if this bit set) + * Bit 1: mmcblk boot partition 0 or 1. + * for eMMC: boot0 if this bit is cleared, boot1 - if set + * for SD-card the boot partition value will always be 0 + * (independent of the value of this bit) + * + */ +#define BOOT_SRC_MMC1 BIT(0) +#define BOOT_SRC_PART1 BIT(1) + +/* Offset of the first boot image source descriptor in SPI NOR */ +#define SPI_FLASH_BOOT_SRC_OFFS 0xFE0000 +#define SPI_FLASH_SECTOR_SIZE 0x10000 diff --git a/board/liebherr/btt/btt.c b/board/liebherr/btt/btt.c new file mode 100644 index 00000000000..e05e333ac7e --- /dev/null +++ b/board/liebherr/btt/btt.c @@ -0,0 +1,451 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * BTT[3C] iMX28 board + * + * Copyright (C) 2025 DENX Software Engineering + * Lukasz Majewski, DENX Software Engineering, lukma@denx.de + */ + +#include <fdt_support.h> +#include <init.h> +#include <log.h> +#include <net.h> +#include <env.h> +#include <asm/global_data.h> +#include <asm/gpio.h> +#include <asm/io.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/iomux-mx28.h> +#include <asm/arch/clock.h> +#include <asm/arch/sys_proto.h> +#include <linux/delay.h> +#include <netdev.h> +#include <errno.h> +#include <serial.h> +#include <u-boot/crc.h> +#include "boot_img_scr.h" + +#include <spi.h> +#include <spi_flash.h> + +#ifdef CONFIG_XPL_BUILD +#include <spl.h> +#endif + +DECLARE_GLOBAL_DATA_PTR; + +/* + * Functions + */ + +static void init_clocks(void) +{ + /* IO0 clock at 480MHz */ + mxs_set_ioclk(MXC_IOCLK0, 480000); + /* IO1 clock at 480MHz */ + mxs_set_ioclk(MXC_IOCLK1, 480000); + + /* SSP0 clock at 96MHz */ + mxs_set_sspclk(MXC_SSPCLK0, 96000, 0); + /* SSP2 clock at 160MHz */ + mxs_set_sspclk(MXC_SSPCLK2, 160000, 0); + /* SSP3 clock at 96MHz */ + mxs_set_sspclk(MXC_SSPCLK3, 96000, 0); +} + +#if defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_FRAMEWORK) +void board_init_f(ulong arg) +{ + init_clocks(); + spl_early_init(); + preloader_console_init(); +} + +static struct boot_img_src img_src[2]; +static int spi_load_boot_info(void) +{ + struct spi_flash *flash; + int err; + + flash = spi_flash_probe(CONFIG_SF_DEFAULT_BUS, + CONFIG_SF_DEFAULT_CS, + CONFIG_SF_DEFAULT_SPEED, + CONFIG_SF_DEFAULT_MODE); + if (!flash) { + printf("%s: SPI probe err\n", __func__); + return -ENODEV; + } + + /* + * Load both boot info structs from SPI flash + */ + err = spi_flash_read(flash, SPI_FLASH_BOOT_SRC_OFFS, + sizeof(img_src[0]), + (void *)&img_src[0]); + if (err) { + debug("%s: First boot info NOR sector read error %d\n", + __func__, err); + return err; + } + + err = spi_flash_read(flash, + SPI_FLASH_BOOT_SRC_OFFS + SPI_FLASH_SECTOR_SIZE, + sizeof(img_src[0]), + (void *)&img_src[1]); + if (err) { + debug("%s: First boot info NOR sector read error %d\n", + __func__, err); + return err; + } + + debug("%s: BI0 0x%x 0x%x 0x%x\n", __func__, + img_src[0].magic, img_src[0].flags, img_src[0].crc8); + + debug("%s: BI1 0x%x 0x%x 0x%x\n", __func__, + img_src[1].magic, img_src[1].flags, img_src[1].crc8); + + return 0; +} + +#define BTT_MONITORING_DEVICE_TIMEOUT 100 +static int rescue_val; + +void spl_board_init(void) +{ + struct gpio_desc phy_rst, boot, rescue, wifi_en, bt_en; + int ret, i; + + /* + * On the new HW version of BTTC/3 (with LAN8720ai PHY) the !RST pin + * (15) is pulled LOW by external resistor. As a result it needs to be + * set HIGH as soon as possible to allow correct generation of RESET + * pulse. + * + * In the old BTTC (with TLK105 PHY) the RC circuit was used instead + * to set the RESET pin to HIGH after 100us, so there was no need to + * set it explicitly. + */ + ret = dm_gpio_lookup_name("GPIO4_12", &phy_rst); + if (ret) + printf("Cannot get GPIO4_12\n"); + + ret = dm_gpio_request(&phy_rst, "phy-rst"); + if (ret) + printf("Cannot request GPIO4_12\n"); + + dm_gpio_set_dir_flags(&phy_rst, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); + + /* + * Explicitly set GPIO, which controls WL_EN (wifi) to LOW. On the BTT3 + * it is directly connected to Jody module without any externa pull up + * down register. + */ + ret = dm_gpio_lookup_name("GPIO0_27", &wifi_en); + if (ret) + printf("Cannot get GPIO0_27\n"); + + ret = dm_gpio_request(&wifi_en, "wifi-en"); + if (ret) + printf("Cannot request GPIO0_27\n"); + + dm_gpio_set_dir_flags(&wifi_en, GPIOD_IS_OUT | GPIOD_ACTIVE_LOW | + GPIOD_IS_OUT_ACTIVE); + + /* + * Explicitly set GPIO, which controls BT_EN (Bluetooth) to LOW. On the + * BTT3 it is connected to Jody module via RC circuit (after some R*C + * time this pin is set to HIGH). However, the manual recommends setting + * it high from LOW state. + */ + ret = dm_gpio_lookup_name("GPIO3_27", &bt_en); + if (ret) + printf("Cannot get GPIO3_27\n"); + + ret = dm_gpio_request(&bt_en, "bt-en"); + if (ret) + printf("Cannot request GPIO3_27\n"); + + dm_gpio_set_dir_flags(&bt_en, GPIOD_IS_OUT | GPIOD_ACTIVE_LOW | + GPIOD_IS_OUT_ACTIVE); + + /* 'boot' and 'rescue' pins */ + ret = dm_gpio_lookup_name("GPIO4_9", &boot); + if (ret) + printf("Cannot get GPIO4_9\n"); + + ret = dm_gpio_request(&boot, "boot"); + if (ret) + printf("Cannot request GPIO4_9\n"); + + dm_gpio_set_dir_flags(&boot, GPIOD_IS_IN); + + ret = dm_gpio_lookup_name("GPIO4_11", &rescue); + if (ret) + printf("Cannot get GPIO4_11\n"); + + ret = dm_gpio_request(&rescue, "rescue"); + if (ret) + printf("Cannot request GPIO4_11\n"); + + dm_gpio_set_dir_flags(&rescue, GPIOD_IS_IN); + + /* Wait for ready signal from system "monitoring" device */ + for (i = 0; i < BTT_MONITORING_DEVICE_TIMEOUT; i++) { + if (dm_gpio_get_value(&boot)) + break; + mdelay(10); + } + + rescue_val = dm_gpio_get_value(&rescue); +} + +int spl_mmc_emmc_boot_partition(struct mmc *mmc) +{ + int i, src_idx = -1, ret; + + ret = spi_load_boot_info(); + if (ret) { + printf("%s: Cannot read BTT boot info! [%d]\n", __func__, ret); + /* To avoid bricking board - by default boot from boot0 eMMC */ + return 1; + } + + for (i = 0; i < 2; i++) { + if (img_src[i].magic == 'B' && + img_src[i].crc8 == crc8(0, &img_src[i].magic, 2)) { + src_idx = i; + break; + } + } + + debug("%s: src idx: %d\n", __func__, src_idx); + + if (src_idx < 0) + /* + * Always use eMMC (mmcblkX) boot0 if no + * valid image source description found + */ + return 1; + + if (img_src[src_idx].flags & BOOT_SRC_PART1) + return 2; + + return 1; +} + +void board_boot_order(u32 *spl_boot_list) +{ + spl_boot_list[0] = BOOT_DEVICE_MMC1; + spl_boot_list[1] = BOOT_DEVICE_SPI; + spl_boot_list[2] = BOOT_DEVICE_UART; +} + +int spl_start_uboot(void) +{ + /* break into full u-boot on 'c' */ + if (serial_tstc() && serial_getc() == 'c') + return 1; + + debug("%s: rescue: %d\n", __func__, rescue_val); + return rescue_val; +} +#else + +/* + * Providing proper board name - i.e. 'bttc' vs 'btt3' + * The distinction is made on the size of DRAM memory - i.e. + * bttc has only 128 MiB, whereas btt3 has 256 MiB. + */ +#define STR_BTTC "bttc" +#define STR_BTT3 "btt3" + +static const char *get_board_name(void) +{ + if (gd->bd->bi_dram[0].size == SZ_128M) + return STR_BTTC; + + return STR_BTT3; +} + +/* + * Reading the HW ID number for BTT3 device + * + * GPIOs from Port 4: + * E0: GPIO4_10 + * E1: GPIO4_5 + * E2: GPIO4_14 + * E3: GPIO4_15 + * are used on BTT3 to store HW revision information. + * + * From rev 1+ the REV GPIOs are properly connected on the PCB, so PULL UPs + * shall be disabled (as they are by default on pins' SPL configuration) + *. + * Rev 0: - read all '1' (first production version without HW rev set) + * Rev 1: - read 0x1 (E0 set) + * Rev 2: - read 0x2 (E1 set) + * + */ +#define BTT3_HW_ID_GPIO_PORT (MXS_PINCTRL_BASE + (0x0900 + ((4) * 0x10))) +#define BTT3_HW_ID_E0 BIT(10) +#define BTT3_HW_ID_E1 BIT(5) +#define BTT3_HW_ID_E2 BIT(14) +#define BTT3_HW_ID_E3 BIT(15) + +static u8 get_som_rev(void) +{ + struct mxs_register_32 *reg = + (struct mxs_register_32 *)BTT3_HW_ID_GPIO_PORT; + u32 tmp = ~readl(®->reg); + u8 id = 0; + + if (tmp & BTT3_HW_ID_E0) + id += 1; + + if (tmp & BTT3_HW_ID_E1) + id += 2; + + if (tmp & BTT3_HW_ID_E2) + id += 4; + + if (tmp & BTT3_HW_ID_E3) + id += 8; + + /* + * Special case for first production BTT3 version, without HW + * revision support (so it reads 0x0s as pullups are disabled + * and hence 0xF is set for ID) + */ + if (id == 0xF) + id = 0; + + return id; +} + +int board_early_init_f(void) +{ + init_clocks(); + + return 0; +} + +int board_init(void) +{ + struct gpio_desc phy_rst; + int ret; + + /* Address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; + + cpu_eth_init(NULL); + + /* PHY INT#/PWDN# */ + ret = dm_gpio_lookup_name("GPIO4_13", &phy_rst); + if (ret) { + printf("Cannot get GPIO4_13\n"); + return ret; + } + + ret = dm_gpio_request(&phy_rst, "phy-rst"); + if (ret) { + printf("Cannot request GPIO4_13\n"); + return ret; + } + + dm_gpio_set_dir_flags(&phy_rst, GPIOD_IS_IN); + udelay(1000); + + return 0; +} + +#if defined(CONFIG_BOARD_LATE_INIT) +int board_late_init(void) +{ + int ret = env_set_ulong("board_som_rev", get_som_rev()); + + if (ret) + printf("Cannot set BTT's SoM revision env variable!\n"); + + ret = env_set("arch", get_board_name()); + if (ret) + printf("Cannot set SoM 'arch' env variable!\n"); + + return 0; +} +#endif + +#if defined(CONFIG_DISPLAY_BOARDINFO) +int checkboard(void) +{ + printf("Board: LWE BTT SoM HW rev %d\n", get_som_rev()); + + return 0; +} +#endif + +int dram_init(void) +{ + return mxs_dram_init(); +} + +#if defined(CONFIG_OF_BOARD) +int board_fdt_blob_setup(void **fdtp) +{ + /* + * The only purpose of this function is the specific BTT's DTB + * setup in u-boot proper. To be more specific - the SPL + * cannot support DTB selection due to size constraints + * (SPL < 50 KiB). + * + * Hence, the DTB selection is done in u-boot, which due to + * board's partition sizes (and backward compatibility) has also + * size constrain (~448 KiB). + * + * To support multiple DTBs appended, the compression has been used + * for them. Unfortunately, the initf_malloc() is called + * after the DTB needs to be selected. To fix this problem for this + * particular setup (i.e. BTT board) the initf_malloc() is called here. + */ + initf_malloc(); + + return -EEXIST; +} +#endif + +#if defined(CONFIG_MULTI_DTB_FIT) +int board_fit_config_name_match(const char *name) +{ + u8 rev_id = get_som_rev(); + char board[12]; + + sprintf(board, "imx28-btt3-%d", rev_id); + + if (!strncmp(name, board, sizeof(board))) + return 0; + + return -EINVAL; +} +#endif + +/* + * NOTE: + * + * IMX28 clock "stub" DM driver! + * + * Only used for SPL stage, which is NOT using DM; serial and + * eMMC configuration. + * + * It is required for SPL_OF_PLATDATA proper code generation as, + * this device has hard constrain on the size of the SPL binary + * (u-boot.sb). + */ +static const struct udevice_id imx28_clk_ids[] = { + { .compatible = "fsl,imx28-clkctrl", }, + { } +}; + +U_BOOT_DRIVER(fsl_imx28_clkctrl) = { + .name = "fsl_imx28_clkctrl", + .id = UCLASS_CLK, + .of_match = imx28_clk_ids, +}; +#endif /* CONFIG_XPL_BUILD */ diff --git a/board/liebherr/btt/btt.env b/board/liebherr/btt/btt.env new file mode 100644 index 00000000000..aaf0b8415d1 --- /dev/null +++ b/board/liebherr/btt/btt.env @@ -0,0 +1,139 @@ +bootmode=update +bootpri=mmc_mmc +bootsec=sf_swu +consdev=ttyAMA0 +baudrate=115200 +dtbfile=imx28-btt3-1.dtb +rootdev=/dev/mmcblk0p2 +netdev=eth0 +swufile=swupdate-image-btt3-upd.itb +sf_kernel_offset=0xA0000 +sf_swu_size=0xF40000 +ethact=FEC +arch=btt3 +lwe_env= + if dhcp ${loadaddr} ${hostname}/${lwe_uenv} ; then + source ${loadaddr}; + fi +lwe_uenv=env_uboot_btt3.bin +do_update_mmc= + if mmc rescan ; then + mmc dev 0 ${update_mmc_part} ; + if dhcp ${hostname}/${update_filename} ; then + setexpr fw_sz ${filesize} / 0x200 ; + setexpr fw_sz ${fw_sz} + 1 ; + mmc write ${loadaddr} ${update_offset} ${fw_sz} ; + fi ; + fi +do_update_sf= + if sf probe ; then + if dhcp ${hostname}/${update_filename} ; then + sf erase ${update_offset} +${filesize} ; + sf write ${loadaddr} ${update_offset} ${filesize} ; + fi ; + fi +factory_reset= + if sf probe ; then + run update_swu ; + setenv bootmode update ; + saveenv ; + fi +update_spl_filename=u-boot.sb +update_spl= + setenv update_filename ${update_spl_filename} ; + setenv update_offset 0 ; + run do_update_sf +update_uboot_filename=u-boot.img +update_uboot= + setenv update_filename ${update_uboot_filename} ; + setenv update_offset 0x10000 ; + run do_update_sf ; + setenv update_mmc_part 1 ; + setenv update_offset 0 ; + run do_update_mmc ; + setenv update_mmc_part 2 ; + run do_update_mmc +update_kernel_filename=uImage +update_kernel= + setenv update_mmc_part 1 ; + setenv update_filename ${update_kernel_filename} ; + setenv update_offset 0x800 ; + run do_update_mmc ; + setenv update_filename ${dtbfile} ; + setenv update_offset 0x400 ; + run do_update_mmc +update_swu= + setenv update_filename ${swufile} ; + setenv update_offset ${sf_kernel_offset} ; + run do_update_sf +addcons= + setenv bootargs ${bootargs} + console=${consdev},${baudrate} +addip= + setenv bootargs ${bootargs} + ip=${ipaddr}:${serverip}:${gatewayip}: + ${netmask}:${hostname}:${netdev}:off +addmisc= + setenv bootargs ${bootargs} ${miscargs} +addargs=run addcons addmisc +mmcload= + mmc rescan ; + mmc dev 0 1 ; + mmc read ${loadaddr} 0x800 0x2000 ; + mmc read ${dtbaddr} 0x400 0x80 +netload= + dhcp ${loadaddr} ${hostname}/${bootfile} ; + tftp ${dtbaddr} ${hostname}/${dtbfile} +usbload= + usb start ; + load usb 0:1 ${loadaddr} ${bootfile} +miscargs=panic=1 +mmcargs=setenv bootargs root=${rootdev} rw rootwait +nfsargs= + setenv bootargs root=/dev/nfs rw + nfsroot=${serverip}:${rootpath},v3,tcp +mmc_mmc= + if run mmcload mmcargs addargs ; then + bootm ${loadaddr} - ${dtbaddr} ; + fi +mmc_nfs= + if run mmcload nfsargs addip addargs ; then + bootm ${loadaddr} - ${dtbaddr} ; + fi +sf_mmc= + if run sfload mmcargs addargs ; then + bootm ${loadaddr} - ${dtbaddr} ; + fi +sf_swu= + if sf probe ; then + sf read ${loadaddr} ${sf_kernel_offset} ${sf_swu_size} ; + setenv bootargs root=/dev/ram0 rw ; + run addargs ; + bootm ${loadaddr}#conf-imx28-${arch}-${board_som_rev}.dtb ; + fi +net_mmc= + if run netload mmcargs addargs ; then + bootm ${loadaddr} - ${dtbaddr} ; + fi +net_nfs= + if run netload nfsargs addip addargs ; then + bootm ${loadaddr} - ${dtbaddr} ; + fi +prebootcmd= + if test ${envsaved} != y ; then ; + setenv envsaved y ; + saveenv ; + fi ; + if test ${bootmode} = normal ; then + setenv bootdelay 0 ; + setenv bootpri mmc_mmc ; + elif test ${bootmode} = devel ; then + setenv bootdelay 3 ; + setenv bootpri net_mmc ; + else + if test ${bootmode} != update ; then + echo Warning: unknown bootmode ${bootmode} ; + fi ; + setenv bootdelay 1 ; + setenv bootpri sf_swu ; + fi diff --git a/board/liebherr/btt/spl_btt.c b/board/liebherr/btt/spl_btt.c new file mode 100644 index 00000000000..da17e186b06 --- /dev/null +++ b/board/liebherr/btt/spl_btt.c @@ -0,0 +1,347 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * DENX M28 Boot setup + * + * Copyright (C) 2025 DENX Software Engineering + * Lukasz Majewski, DENX Software Engineering, lukma@denx.de + */ + +#include <config.h> +#include <asm/io.h> +#include <asm/arch/iomux-mx28.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/sys_proto.h> + +#define MUX_CONFIG_LCD (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL) +#define MUX_CONFIG_BOOT (MXS_PAD_3V3) +#define MUX_CONFIG_TSC (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP) +#define MUX_CONFIG_SSP0 (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_PULLUP) +#define MUX_CONFIG_SSP2 (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_PULLUP) +#define MUX_CONFIG_ENET (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_NOPULL) +#define MUX_CONFIG_EMI (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL) + +/* HW_PINCTRL_EMI_DS_CTRL */ +#define EMI_DS_CTRL_CLR 0x3FFF +#define EMI_DS_CTRL_SLICE0_SHIFT 0 +#define EMI_DS_CTRL_SLICE1_SHIFT 2 +#define EMI_DS_CTRL_SLICE2_SHIFT 4 +#define EMI_DS_CTRL_SLICE3_SHIFT 6 +#define EMI_DS_CTRL_DUALPAD_SHIFT 8 +#define EMI_DS_CTRL_CONTROL_SHIFT 10 +#define EMI_DS_CTRL_ADDRESS_SHIFT 12 +#define EMI_DS_CTRL_MA_20 0x10 + +/* + * The BTT devide can be boot in several ways; U-Boot's 'falcon' mode, + * normal boot (through U-Boot proper) and also via recovery system. + * + * To fix some HW issues on the device, as well as providing all the + * above boot method's the same "start" state when kernel starts it + * has been decided to configure PINMUXes for all relevant IP blocks + * (and GPIOs during early SPI state). + * + * It also shall be mentioned, that during early SPL stage, the BTT + * device needs to cooperate with uC based co-processor - this + * requires correct pins configuration. + */ +static const iomux_cfg_t iomux_setup[] = { + /* AUART0 IRDA */ + MX28_PAD_AUART0_RX__AUART0_RX, + MX28_PAD_AUART0_TX__AUART0_TX, + + /* AUART 4 RS422 */ + MX28_PAD_AUART0_CTS__AUART4_RX, + MX28_PAD_AUART0_RTS__AUART4_TX, + + /* USB0 */ + MX28_PAD_AUART1_CTS__USB0_OVERCURRENT, + MX28_PAD_AUART1_RTS__USB0_ID, + MX28_PAD_LCD_VSYNC__GPIO_1_28, /* PRW_On */ + + /* USB1 */ + MX28_PAD_PWM2__USB1_OVERCURRENT, + + /* eMMC */ + MX28_PAD_SSP0_CMD__SSP0_CMD | MUX_CONFIG_SSP0, + MX28_PAD_SSP0_DATA0__SSP0_D0 | MUX_CONFIG_SSP0, + MX28_PAD_SSP0_DATA1__SSP0_D1 | MUX_CONFIG_SSP0, + MX28_PAD_SSP0_DATA2__SSP0_D2 | MUX_CONFIG_SSP0, + MX28_PAD_SSP0_DATA3__SSP0_D3 | MUX_CONFIG_SSP0, + MX28_PAD_SSP0_DATA4__SSP0_D4 | MUX_CONFIG_SSP0, + MX28_PAD_SSP0_DATA5__SSP0_D5 | MUX_CONFIG_SSP0, + MX28_PAD_SSP0_DATA6__SSP0_D6 | MUX_CONFIG_SSP0, + MX28_PAD_SSP0_DATA7__SSP0_D7 | MUX_CONFIG_SSP0, + MX28_PAD_SSP0_DETECT__GPIO_2_9, /* Reset for eMMC */ + MX28_PAD_SSP0_SCK__SSP0_SCK | MUX_CONFIG_SSP0, + + /* DIG Keys */ + MX28_PAD_GPMI_D00__GPIO_0_0, + MX28_PAD_GPMI_D01__GPIO_0_1, + MX28_PAD_GPMI_D02__GPIO_0_2, + MX28_PAD_GPMI_D03__GPIO_0_3, + MX28_PAD_GPMI_D04__GPIO_0_4, + MX28_PAD_GPMI_D05__GPIO_0_5, + MX28_PAD_GPMI_D06__GPIO_0_6, + MX28_PAD_GPMI_D07__GPIO_0_7, + + /* ADR_0-2 */ + MX28_PAD_GPMI_CE1N__GPIO_0_17, + MX28_PAD_GPMI_CE2N__GPIO_0_18, + MX28_PAD_GPMI_CE3N__GPIO_0_19, + + /* Read Keys */ + MX28_PAD_GPMI_RDY0__GPIO_0_20, + + /* LATCH_EN */ + MX28_PAD_GPMI_RDY1__GPIO_0_21, + + /* Power off */ + MX28_PAD_GPMI_RDN__GPIO_0_24, + + /* WIFI EN */ + MX28_PAD_GPMI_CLE__GPIO_0_27, + + /* I2C1 Touch */ + MX28_PAD_AUART2_CTS__GPIO_3_10, + MX28_PAD_AUART2_RTS__GPIO_3_11, + MX28_PAD_GPMI_RDY2__GPIO_0_22, /* Touch Reset */ + MX28_PAD_GPMI_RDY3__GPIO_0_23, /* Touch INT */ + + /* TIVA */ + MX28_PAD_AUART1_RX__SSP2_CARD_DETECT, + MX28_PAD_SSP2_MISO__SSP2_D0, + MX28_PAD_SSP2_MOSI__SSP2_CMD, + MX28_PAD_SSP2_SCK__SSP2_SCK, + MX28_PAD_SSP2_SS0__SSP2_D3, + MX28_PAD_SSP2_SS1__GPIO_2_20, + MX28_PAD_SSP2_SS2__GPIO_2_21, + + /* SPI3 NOR-Flash */ + MX28_PAD_AUART1_TX__SSP3_CARD_DETECT, + MX28_PAD_AUART2_RX__SSP3_D1, + MX28_PAD_AUART2_TX__SSP3_D2, + MX28_PAD_SSP3_MISO__SSP3_D0, + MX28_PAD_SSP3_MOSI__SSP3_CMD, + MX28_PAD_SSP3_SCK__SSP3_SCK, + MX28_PAD_SSP3_SS0__SSP3_D3, + + /* NOR-Flash CMD */ + MX28_PAD_LCD_RS__GPIO_1_26, /* Hold */ + MX28_PAD_LCD_WR_RWN__GPIO_1_25, /* write protect */ + + /* I2C0 Codec */ + MX28_PAD_I2C0_SCL__I2C0_SCL, + MX28_PAD_I2C0_SDA__I2C0_SDA, + + /* I2S Codec */ + MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK, + MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK, + MX28_PAD_SAIF0_MCLK__SAIF0_MCLK, + MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0, + MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0, + + /* BT_EN */ + MX28_PAD_SPDIF__GPIO_3_27, + + /* EMI */ + MX28_PAD_EMI_D00__EMI_DATA0 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D01__EMI_DATA1 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D02__EMI_DATA2 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D03__EMI_DATA3 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D04__EMI_DATA4 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D05__EMI_DATA5 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D06__EMI_DATA6 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D07__EMI_DATA7 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D08__EMI_DATA8 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D09__EMI_DATA9 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D10__EMI_DATA10 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D11__EMI_DATA11 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D12__EMI_DATA12 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D13__EMI_DATA13 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D14__EMI_DATA14 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D15__EMI_DATA15 | MUX_CONFIG_EMI, + MX28_PAD_EMI_ODT0__EMI_ODT0 | MUX_CONFIG_EMI, + MX28_PAD_EMI_DQM0__EMI_DQM0 | MUX_CONFIG_EMI, + MX28_PAD_EMI_ODT1__EMI_ODT1 | MUX_CONFIG_EMI, + MX28_PAD_EMI_DQM1__EMI_DQM1 | MUX_CONFIG_EMI, + MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK | MUX_CONFIG_EMI, + MX28_PAD_EMI_CLK__EMI_CLK | MUX_CONFIG_EMI, + MX28_PAD_EMI_DQS0__EMI_DQS0 | MUX_CONFIG_EMI, + MX28_PAD_EMI_DQS1__EMI_DQS1 | MUX_CONFIG_EMI, + MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN | MUX_CONFIG_EMI, + + MX28_PAD_EMI_A00__EMI_ADDR0 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A01__EMI_ADDR1 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A02__EMI_ADDR2 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A03__EMI_ADDR3 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A04__EMI_ADDR4 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A05__EMI_ADDR5 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A06__EMI_ADDR6 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A07__EMI_ADDR7 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A08__EMI_ADDR8 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A09__EMI_ADDR9 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A10__EMI_ADDR10 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A11__EMI_ADDR11 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A12__EMI_ADDR12 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A13__EMI_ADDR13 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A14__EMI_ADDR14 | MUX_CONFIG_EMI, + MX28_PAD_EMI_BA0__EMI_BA0 | MUX_CONFIG_EMI, + MX28_PAD_EMI_BA1__EMI_BA1 | MUX_CONFIG_EMI, + MX28_PAD_EMI_BA2__EMI_BA2 | MUX_CONFIG_EMI, + MX28_PAD_EMI_CASN__EMI_CASN | MUX_CONFIG_EMI, + MX28_PAD_EMI_RASN__EMI_RASN | MUX_CONFIG_EMI, + MX28_PAD_EMI_WEN__EMI_WEN | MUX_CONFIG_EMI, + MX28_PAD_EMI_CE0N__EMI_CE0N | MUX_CONFIG_EMI, + MX28_PAD_EMI_CE1N__EMI_CE1N | MUX_CONFIG_EMI, + MX28_PAD_EMI_CKE__EMI_CKE | MUX_CONFIG_EMI, + + /* Uart3 Bluetooth-Interface */ + MX28_PAD_AUART3_CTS__AUART3_CTS, + MX28_PAD_AUART3_RTS__AUART3_RTS, + MX28_PAD_AUART3_RX__AUART3_RX, + MX28_PAD_AUART3_TX__AUART3_TX, + + /* framebuffer */ + MX28_PAD_LCD_CS__LCD_CS | MUX_CONFIG_LCD, + MX28_PAD_LCD_D00__LCD_D0 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D01__LCD_D1 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D02__LCD_D2 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D03__LCD_D3 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D04__LCD_D4 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D05__LCD_D5 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D06__LCD_D6 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D07__LCD_D7 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D08__LCD_D8 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D09__LCD_D9 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D10__LCD_D10 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D11__LCD_D11 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D12__LCD_D12 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D13__LCD_D13 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D14__LCD_D14 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D15__LCD_D15 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D16__LCD_D16 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D17__LCD_D17 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D18__LCD_D18 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D19__LCD_D19 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D20__LCD_D20 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D21__LCD_D21 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D22__LCD_D22 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D23__LCD_D23 | MUX_CONFIG_LCD, + MX28_PAD_LCD_DOTCLK__LCD_DOTCLK | MUX_CONFIG_LCD, + MX28_PAD_LCD_ENABLE__LCD_ENABLE | MUX_CONFIG_LCD, + MX28_PAD_LCD_HSYNC__LCD_HSYNC | MUX_CONFIG_LCD, + MX28_PAD_LCD_RD_E__LCD_VSYNC | MUX_CONFIG_LCD, + MX28_PAD_LCD_RESET__LCD_RESET | MUX_CONFIG_LCD, + + /* DUART RS232 */ + MX28_PAD_PWM0__DUART_RX, + MX28_PAD_PWM1__DUART_TX, + + /* Backlight */ + MX28_PAD_PWM3__PWM_3, + + /* FEC Ethernet */ + MX28_PAD_ENET_CLK__CLKCTRL_ENET | MUX_CONFIG_ENET, + MX28_PAD_ENET0_COL__ENET1_TX_EN | MUX_CONFIG_ENET, + MX28_PAD_ENET0_CRS__ENET1_RX_EN | MUX_CONFIG_ENET, + MX28_PAD_ENET0_MDC__ENET0_MDC | MUX_CONFIG_ENET, + MX28_PAD_ENET0_MDIO__ENET0_MDIO | MUX_CONFIG_ENET, + MX28_PAD_ENET0_RX_CLK__GPIO_4_13, /* Phy Interrupt */ + MX28_PAD_ENET0_RX_EN__ENET0_RX_EN | MUX_CONFIG_ENET, + MX28_PAD_ENET0_RXD0__ENET0_RXD0 | MUX_CONFIG_ENET, + MX28_PAD_ENET0_RXD1__ENET0_RXD1 | MUX_CONFIG_ENET, + MX28_PAD_ENET0_RXD3__ENET1_RXD1 | MUX_CONFIG_ENET, + MX28_PAD_ENET0_TX_CLK__GPIO_4_5, /* n.c. */ + MX28_PAD_ENET0_TX_EN__ENET0_TX_EN | MUX_CONFIG_ENET, + MX28_PAD_ENET0_TXD0__ENET0_TXD0 | MUX_CONFIG_ENET, + MX28_PAD_ENET0_TXD1__ENET0_TXD1 | MUX_CONFIG_ENET, + MX28_PAD_ENET0_TXD3__ENET1_TXD1 | MUX_CONFIG_ENET, + MX28_PAD_ENET0_TXD3__GPIO_4_12, /* PHY reset */ + + /* boot/rescue pins */ + MX28_PAD_ENET0_RXD2__GPIO_4_9, + MX28_PAD_ENET0_TXD2__GPIO_4_11, + + /* HW revision setup pins - by default pullup DISABLED */ + MX28_PAD_ENET0_RXD3__GPIO_4_10, + MX28_PAD_ENET0_TX_CLK__GPIO_4_5, + MX28_PAD_ENET0_COL__GPIO_4_14, + MX28_PAD_ENET0_CRS__GPIO_4_15, +}; + +u32 mxs_dram_vals[] = { + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000100, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00010101, 0x01010101, + 0x000f0f01, 0x0f02010a, 0x00000000, 0x00010101, + 0x00000100, 0x00000100, 0x00000000, 0x00000002, + 0x01010000, 0x07080403, 0x07005303, 0x0b0000c8, + 0x0200a0c1, 0x0002040c, 0x0038430a, 0x04290322, + 0x02040203, 0x00c8002b, 0x00000000, 0x00000000, + 0x00012100, 0xffff0303, 0x00012100, 0xffff0303, + 0x00012100, 0xffff0303, 0x00012100, 0xffff0303, + 0x00000003, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000612, 0x01000102, + 0x06120612, 0x00000200, 0x00020007, 0xf4004a27, + 0xf4004a27, 0xf4004a27, 0xf4004a27, 0x07400300, + 0x07400300, 0x07400300, 0x07400300, 0x00000005, + 0x00000000, 0x00000000, 0x01000000, 0x00000000, + 0x00000001, 0x000f1133, 0x00000000, 0x00001f04, + 0x00001f04, 0x00001f04, 0x00001f04, 0x00001f04, + 0x00001f04, 0x00001f04, 0x00001f04, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00010000, 0x00030404, + 0x00000002, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x01010000, + 0x01000000, 0x03030000, 0x00010303, 0x01020202, + 0x00000000, 0x02040101, 0x21002103, 0x00061200, + 0x06120612, 0x00000642, 0x00000000, 0x00000004, + 0x00000000, 0x00000080, 0x00000000, 0x00000000, + 0x00000000, 0xffffffff +}; + +#ifndef CONFIG_SPL_FRAMEWORK +void board_init_ll(const u32 arg, const uint32_t *resptr) +{ + mxs_common_spl_init(arg, resptr, iomux_setup, ARRAY_SIZE(iomux_setup)); +} +#else +void lowlevel_init(void) +{ + struct mxs_pinctrl_regs *pinctrl_regs = + (struct mxs_pinctrl_regs *)MXS_PINCTRL_BASE; + + /* Set EMI drive strength - the HW_PINCTRL_EMI_DS_CTRL */ + writel(EMI_DS_CTRL_CLR, &pinctrl_regs->hw_pinctrl_emi_ds_ctrl_clr); + writel(EMI_DS_CTRL_MA_20 << EMI_DS_CTRL_SLICE0_SHIFT | + EMI_DS_CTRL_MA_20 << EMI_DS_CTRL_SLICE1_SHIFT | + EMI_DS_CTRL_MA_20 << EMI_DS_CTRL_SLICE2_SHIFT | + EMI_DS_CTRL_MA_20 << EMI_DS_CTRL_SLICE3_SHIFT | + EMI_DS_CTRL_MA_20 << EMI_DS_CTRL_DUALPAD_SHIFT | + EMI_DS_CTRL_MA_20 << EMI_DS_CTRL_CONTROL_SHIFT | + EMI_DS_CTRL_MA_20 << EMI_DS_CTRL_ADDRESS_SHIFT, + &pinctrl_regs->hw_pinctrl_emi_ds_ctrl_set); + + mxs_common_spl_init(0, NULL, iomux_setup, ARRAY_SIZE(iomux_setup)); +} +#endif diff --git a/board/liebherr/mccmon6/spl.c b/board/liebherr/mccmon6/spl.c index b1f6881275d..e612d9e9ce0 100644 --- a/board/liebherr/mccmon6/spl.c +++ b/board/liebherr/mccmon6/spl.c @@ -5,6 +5,7 @@ * Richard Hu <hakahu@gmail.com> */ +#include <env.h> #include <image.h> #include <init.h> #include <asm/arch/clock.h> diff --git a/board/liebherr/xea/xea.c b/board/liebherr/xea/xea.c index 1d4f165fd13..9630e7f576b 100644 --- a/board/liebherr/xea/xea.c +++ b/board/liebherr/xea/xea.c @@ -13,6 +13,7 @@ * */ +#include <env.h> #include <fdt_support.h> #include <init.h> #include <log.h> diff --git a/board/menlo/mx8menlo/Makefile b/board/menlo/mx8menlo/Makefile index 62939395ba1..c71fa9edfd9 100644 --- a/board/menlo/mx8menlo/Makefile +++ b/board/menlo/mx8menlo/Makefile @@ -16,8 +16,8 @@ endif # Common for all Toradex modules ifeq ($(CONFIG_XPL_BUILD),y) -# Necessary to create built-in.o -obj- := __dummy__.o +# Necessary to create built-in.a +obj- := __dummy__.a else obj-$(CONFIG_TDX_CFG_BLOCK) += ../../toradex/common/tdx-cfg-block.o obj-y += ../../toradex/common/tdx-common.o diff --git a/board/microchip/mpfs_icicle/mpfs_icicle.c b/board/microchip/mpfs_icicle/mpfs_icicle.c index 4d7d843dfa3..6b6984eae3f 100644 --- a/board/microchip/mpfs_icicle/mpfs_icicle.c +++ b/board/microchip/mpfs_icicle/mpfs_icicle.c @@ -9,6 +9,7 @@ #include <init.h> #include <asm/global_data.h> #include <asm/io.h> +#include <asm/sections.h> DECLARE_GLOBAL_DATA_PTR; @@ -50,6 +51,68 @@ static void read_device_serial_number(u8 *response, u8 response_size) response_buf[idx] = readb(MPFS_SYS_SERVICE_MAILBOX + idx); } +#if defined(CONFIG_MULTI_DTB_FIT) +int board_fit_config_name_match(const char *name) +{ + const void *fdt; + int list_len; + + /* + * If there's not a HSS provided dtb, there's no point re-selecting + * since we'd just end up re-selecting the same dtb again. + */ + if (!gd->arch.firmware_fdt_addr) + return -EINVAL; + + fdt = (void *)gd->arch.firmware_fdt_addr; + + list_len = fdt_stringlist_count(fdt, 0, "compatible"); + if (list_len < 1) + return -EINVAL; + + for (int i = 0; i < list_len; i++) { + int len, match; + const char *compat; + char *devendored; + + compat = fdt_stringlist_get(fdt, 0, "compatible", i, &len); + if (!compat) + return -EINVAL; + + strtok((char *)compat, ","); + + devendored = strtok(NULL, ","); + if (!devendored) + return -EINVAL; + + match = strcmp(devendored, name); + if (!match) + return 0; + } + + return -EINVAL; +} +#endif + +int board_fdt_blob_setup(void **fdtp) +{ + fdtp = (void *)_end; + + /* + * The devicetree provided by the previous stage is very minimal due to + * severe space constraints. The firmware performs no fixups etc. + * U-Boot, if providing a devicetree, almost certainly has a better + * more complete one than the firmware so that provided by the firmware + * is ignored for OF_SEPARATE. + */ + if (IS_ENABLED(CONFIG_OF_BOARD) && !IS_ENABLED(CONFIG_MULTI_DTB_FIT)) { + if (gd->arch.firmware_fdt_addr) + fdtp = (void *)(uintptr_t)gd->arch.firmware_fdt_addr; + } + + return 0; +} + int board_init(void) { /* For now nothing to do here. */ diff --git a/board/phytec/common/Makefile b/board/phytec/common/Makefile index 8126f7356e1..948f9dab626 100644 --- a/board/phytec/common/Makefile +++ b/board/phytec/common/Makefile @@ -3,8 +3,8 @@ # Author: Teresa Remmet <t.remmet@phytec.de> ifdef CONFIG_XPL_BUILD -# necessary to create built-in.o -obj- := __dummy__.o +# necessary to create built-in.a +obj- := __dummy__.a endif obj-y += phytec_som_detection.o phytec_som_detection_blocks.o diff --git a/board/phytec/common/k3/board.c b/board/phytec/common/k3/board.c index 828973a8e28..7f34d71d530 100644 --- a/board/phytec/common/k3/board.c +++ b/board/phytec/common/k3/board.c @@ -94,7 +94,7 @@ int mmc_get_env_dev(void) return 1; }; - return CONFIG_SYS_MMC_ENV_DEV; + return CONFIG_ENV_MMC_DEVICE_INDEX; } #endif @@ -121,24 +121,37 @@ enum env_location env_get_location(enum env_operation op, int prio) } #if IS_ENABLED(CONFIG_BOARD_LATE_INIT) -int board_late_init(void) +/** + * Ensure the boot order favors the device we just booted from. + * If boot_targets is still at its default value, move the current + * boot device to the front of the list. Otherwise, leave any customized + * order untouched. + */ +static void boot_targets_setup(void) { u32 boot_device = get_boot_device(); + const char *boot_targets = NULL; + char boot_targets_default[100]; + int ret; switch (boot_device) { case BOOT_DEVICE_MMC1: env_set_ulong("mmcdev", 0); env_set("boot", "mmc"); + boot_targets = "mmc0 mmc1 spi_flash dhcp"; break; case BOOT_DEVICE_MMC2: env_set_ulong("mmcdev", 1); env_set("boot", "mmc"); + boot_targets = "mmc1 mmc0 spi_flash dhcp"; break; case BOOT_DEVICE_SPI: env_set("boot", "spi"); + boot_targets = "spi_flash mmc0 mmc1 dhcp"; break; case BOOT_DEVICE_ETHERNET: env_set("boot", "net"); + boot_targets = "dhcp mmc0 mmc1 spi_flash"; break; case BOOT_DEVICE_UART: env_set("boot", "uart"); @@ -148,26 +161,49 @@ int board_late_init(void) break; }; - if (IS_ENABLED(CONFIG_PHYTEC_SOM_DETECTION_BLOCKS)) { - struct phytec_api3_element *block_element; - struct phytec_eeprom_data data; - int ret; - - ret = phytec_eeprom_data_setup(&data, 0, EEPROM_ADDR); - if (ret || !data.valid) - return 0; - - PHYTEC_API3_FOREACH_BLOCK(block_element, &data) { - switch (block_element->block_type) { - case PHYTEC_API3_BLOCK_MAC: - phytec_blocks_add_mac_to_env(block_element); - break; - default: - debug("%s: Unknown block type %i\n", __func__, - block_element->block_type); - } + if (!boot_targets) + return; + + ret = env_get_default_into("boot_targets", boot_targets_default, sizeof(boot_targets_default)); + if (ret < 0) + boot_targets_default[0] = '\0'; + + if (strcmp(boot_targets_default, env_get("boot_targets"))) { + debug("boot_targets not default, don't change it\n"); + return; + } + + env_set("boot_targets", boot_targets); +} + +static void setup_mac_from_eeprom(void) +{ + struct phytec_api3_element *block_element; + struct phytec_eeprom_data data; + int ret; + + ret = phytec_eeprom_data_setup(&data, 0, EEPROM_ADDR); + if (ret || !data.valid) + return; + + PHYTEC_API3_FOREACH_BLOCK(block_element, &data) { + switch (block_element->block_type) { + case PHYTEC_API3_BLOCK_MAC: + phytec_blocks_add_mac_to_env(block_element); + break; + default: + debug("%s: Unknown block type %i\n", __func__, + block_element->block_type); } } +} + +int board_late_init(void) +{ + boot_targets_setup(); + + if (IS_ENABLED(CONFIG_PHYTEC_SOM_DETECTION_BLOCKS)) + setup_mac_from_eeprom(); #if IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT) configure_capsule_updates(); diff --git a/board/phytec/common/phytec_som_detection_blocks.c b/board/phytec/common/phytec_som_detection_blocks.c index 5f3c27ef0c2..b44ff85972f 100644 --- a/board/phytec/common/phytec_som_detection_blocks.c +++ b/board/phytec/common/phytec_som_detection_blocks.c @@ -4,6 +4,7 @@ * Author: Daniel Schultz <d.schultz@phytec.de> */ +#include <env.h> #include <malloc.h> #include <u-boot/crc.h> #include <net.h> diff --git a/board/phytec/phycore_am62ax/phycore_am62ax.env b/board/phytec/phycore_am62ax/phycore_am62ax.env index 40787b0cbcb..797904013dc 100644 --- a/board/phytec/phycore_am62ax/phycore_am62ax.env +++ b/board/phytec/phycore_am62ax/phycore_am62ax.env @@ -24,3 +24,6 @@ get_cmd=tftp spi_fdt_addr=0x700000 spi_image_addr=0x800000 spi_ramdisk_addr=0x2200000 + +bootmeths=script efi extlinux pxe +boot_targets=mmc1 mmc0 spi_flash dhcp diff --git a/board/phytec/phycore_am62x/phycore_am62x.env b/board/phytec/phycore_am62x/phycore_am62x.env index 5c48e856685..797904013dc 100644 --- a/board/phytec/phycore_am62x/phycore_am62x.env +++ b/board/phytec/phycore_am62x/phycore_am62x.env @@ -10,6 +10,7 @@ fdt_addr_r=0x88000000 kernel_addr_r=0x82000000 ramdisk_addr_r=0x88080000 fdtoverlay_addr_r=0x89000000 +fit_addr_r=0x90000000 fdtfile=CONFIG_DEFAULT_FDT_FILE mmcdev=1 @@ -23,3 +24,6 @@ get_cmd=tftp spi_fdt_addr=0x700000 spi_image_addr=0x800000 spi_ramdisk_addr=0x2200000 + +bootmeths=script efi extlinux pxe +boot_targets=mmc1 mmc0 spi_flash dhcp diff --git a/board/phytec/phycore_am62x/rm-cfg.yaml b/board/phytec/phycore_am62x/rm-cfg.yaml index e4221f82f92..26d99b03b80 100644 --- a/board/phytec/phycore_am62x/rm-cfg.yaml +++ b/board/phytec/phycore_am62x/rm-cfg.yaml @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0+ -# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/ +# Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/ # -# Resource management configuration for AM62 +# Resource management configuration for AM62X # --- @@ -244,7 +244,7 @@ rm-cfg: subhdr: magic: 0x7B25 size: 8 - resasg_entries_size: 960 + resasg_entries_size: 976 reserved: 0 resasg_entries: - @@ -285,11 +285,23 @@ rm-cfg: reserved: 0 - start_resource: 0 - num_resource: 4 + num_resource: 2 type: 320 host_id: 12 reserved: 0 - + start_resource: 2 + num_resource: 2 + type: 320 + host_id: 35 + reserved: 0 + - + start_resource: 2 + num_resource: 2 + type: 320 + host_id: 36 + reserved: 0 + - start_resource: 4 num_resource: 4 type: 320 @@ -501,13 +513,13 @@ rm-cfg: reserved: 0 - start_resource: 44 - num_resource: 36 + num_resource: 35 type: 1802 host_id: 35 reserved: 0 - start_resource: 44 - num_resource: 36 + num_resource: 35 type: 1802 host_id: 36 reserved: 0 @@ -543,7 +555,7 @@ rm-cfg: reserved: 0 - start_resource: 909 - num_resource: 627 + num_resource: 626 type: 1805 host_id: 128 reserved: 0 diff --git a/board/phytec/phycore_am64x/phycore_am64x.env b/board/phytec/phycore_am64x/phycore_am64x.env index d69dfe75674..36ab16e2f7a 100644 --- a/board/phytec/phycore_am64x/phycore_am64x.env +++ b/board/phytec/phycore_am64x/phycore_am64x.env @@ -9,6 +9,7 @@ fdt_addr_r=0x88000000 kernel_addr_r=0x82000000 ramdisk_addr_r=0x88080000 fdtoverlay_addr_r=0x89000000 +fit_addr_r=0x90000000 fdtfile=CONFIG_DEFAULT_FDT_FILE mmcdev=1 @@ -22,3 +23,6 @@ get_cmd=tftp spi_fdt_addr=0x700000 spi_image_addr=0x800000 spi_ramdisk_addr=0x2200000 + +bootmeths=script efi extlinux pxe +boot_targets=mmc1 mmc0 spi_flash dhcp diff --git a/board/phytec/phycore_imx8mm/phycore_imx8mm.env b/board/phytec/phycore_imx8mm/phycore_imx8mm.env index a7d14e774a0..402d967ab7d 100644 --- a/board/phytec/phycore_imx8mm/phycore_imx8mm.env +++ b/board/phytec/phycore_imx8mm/phycore_imx8mm.env @@ -34,7 +34,7 @@ mmcboot= echo WARN: Cannot load the DT; fi; fi; -mmcdev=CONFIG_SYS_MMC_ENV_DEV +mmcdev=CONFIG_ENV_MMC_DEVICE_INDEX mmcpart=1 mmcroot=2 netargs= diff --git a/board/phytec/phycore_imx8mp/phycore_imx8mp.env b/board/phytec/phycore_imx8mp/phycore_imx8mp.env index 2c12fc65432..69690aa92e4 100644 --- a/board/phytec/phycore_imx8mp/phycore_imx8mp.env +++ b/board/phytec/phycore_imx8mp/phycore_imx8mp.env @@ -51,7 +51,7 @@ mmcboot= else echo WARN: Cannot load the DT; fi; -mmcdev=CONFIG_SYS_MMC_ENV_DEV +mmcdev=CONFIG_ENV_MMC_DEVICE_INDEX mmcpart=1 mmcroot=2 netargs= diff --git a/board/phytec/phycore_imx93/phycore_imx93.env b/board/phytec/phycore_imx93/phycore_imx93.env index 3b2f30118e7..7b0a90e6447 100644 --- a/board/phytec/phycore_imx93/phycore_imx93.env +++ b/board/phytec/phycore_imx93/phycore_imx93.env @@ -23,7 +23,7 @@ bootenv_addr_r=0x90500000 fdtfile=CONFIG_DEFAULT_FDT_FILE ip_dyn=yes prepare_mcore=setenv optargs "${optargs} clk-imx93.mcore_booted" -mmcdev=CONFIG_SYS_MMC_ENV_DEV +mmcdev=CONFIG_ENV_MMC_DEVICE_INDEX mmcpart=1 mmcroot=2 mmcautodetect=yes diff --git a/board/purism/librem5/librem5.c b/board/purism/librem5/librem5.c index 8ca8792fa42..5178ee6929d 100644 --- a/board/purism/librem5/librem5.c +++ b/board/purism/librem5/librem5.c @@ -6,6 +6,7 @@ #include <malloc.h> #include <errno.h> +#include <env.h> #include <asm/io.h> #include <miiphy.h> #include <asm/mach-imx/iomux-v3.h> diff --git a/board/qualcomm/MAINTAINERS b/board/qualcomm/MAINTAINERS new file mode 100644 index 00000000000..3767a2a7949 --- /dev/null +++ b/board/qualcomm/MAINTAINERS @@ -0,0 +1,24 @@ +# This MAINTAINERS file is for folks with an interest in a particular platform +# or board under ARM SNAPDRAGON + +QUALCOMM DRAGONWING QCS615 +M: Aswin Murugan <aswin.murugan@oss.qualcomm.com> +S: Maintained +N: qcs615 + +# RB3 Gen 2 and similar boards +QUALCOMM DRAGONWING QCS6490 +M: Casey Connolly <casey.connolly@linaro.org> +S: Maintained +N: qcs6490 +N: sc7280 + +QUALCOMM DRAGONWING QCS8300 +M: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com> +S: Maintained +N: qcs8300 + +QUALCOMM DRAGONWING QCS9100 +M: Varadarajan Narayanan <quic_varada@quicinc.com> +S: Maintained +N: qcs9100 diff --git a/board/qualcomm/qcom-phone.config b/board/qualcomm/qcom-phone.config index 913c91757c1..d24094eefdd 100644 --- a/board/qualcomm/qcom-phone.config +++ b/board/qualcomm/qcom-phone.config @@ -1,5 +1,5 @@ # Settings for phones -CONFIG_DEFAULT_ENV_FILE="board/qualcomm/qcom-phone.env" +CONFIG_ENV_DEFAULT_ENV_TEXT_FILE="board/qualcomm/qcom-phone.env" # Hang on panic so the error message can be read CONFIG_PANIC_HANG=y # We use pause in various places to allow text to be read diff --git a/board/renesas/common/Makefile b/board/renesas/common/Makefile index 5e51b691178..1849c995aee 100644 --- a/board/renesas/common/Makefile +++ b/board/renesas/common/Makefile @@ -5,6 +5,7 @@ # # R-Car SoCs +ifndef CONFIG_RZA1 ifndef CONFIG_RZG2L # 32 bit SoCs @@ -45,3 +46,10 @@ endif endif endif +endif + +# RZ/A1 SoCs +ifdef CONFIG_RZA1 +obj-y += rza1-common.o +obj-y += rza1-lowlevel_init.o +endif diff --git a/board/renesas/common/rcar64-spl.c b/board/renesas/common/rcar64-spl.c index 76f2bde924e..d8f05d2ffbe 100644 --- a/board/renesas/common/rcar64-spl.c +++ b/board/renesas/common/rcar64-spl.c @@ -6,7 +6,7 @@ #include <image.h> #include <spl.h> -void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image) +void __noreturn jump_to_image(struct spl_image_info *spl_image) { debug("image entry point: 0x%lx\n", spl_image->entry_point); if (spl_image->os == IH_OS_ARM_TRUSTED_FIRMWARE) { diff --git a/board/renesas/common/rza1-common.c b/board/renesas/common/rza1-common.c new file mode 100644 index 00000000000..5027319a58a --- /dev/null +++ b/board/renesas/common/rza1-common.c @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2017 Renesas Electronics + * Copyright (C) Chris Brandt + */ + +#include <init.h> +#include <asm/io.h> + +#define RZA1_WDT_BASE 0xfcfe0000 +#define WTCSR 0x00 +#define WTCNT 0x02 +#define WRCSR 0x04 + +void __weak reset_cpu(void) +{ + /* Dummy read (must read WRCSR:WOVF at least once before clearing) */ + readb(RZA1_WDT_BASE + WRCSR); + + writew(0xa500, RZA1_WDT_BASE + WRCSR); + writew(0x5a5f, RZA1_WDT_BASE + WRCSR); + writew(0x5a00, RZA1_WDT_BASE + WTCNT); + writew(0xa578, RZA1_WDT_BASE + WTCSR); + + for (;;) + asm volatile("wfi"); +} diff --git a/board/renesas/grpeach/lowlevel_init.S b/board/renesas/common/rza1-lowlevel_init.S index b83c4e86867..b83c4e86867 100644 --- a/board/renesas/grpeach/lowlevel_init.S +++ b/board/renesas/common/rza1-lowlevel_init.S diff --git a/board/renesas/genmai/Kconfig b/board/renesas/genmai/Kconfig new file mode 100644 index 00000000000..4e67a9b325a --- /dev/null +++ b/board/renesas/genmai/Kconfig @@ -0,0 +1,12 @@ +if TARGET_GENMAI + +config SYS_BOARD + default "genmai" + +config SYS_VENDOR + default "renesas" + +config SYS_CONFIG_NAME + default "genmai" + +endif diff --git a/board/renesas/genmai/MAINTAINERS b/board/renesas/genmai/MAINTAINERS new file mode 100644 index 00000000000..1f1c2944632 --- /dev/null +++ b/board/renesas/genmai/MAINTAINERS @@ -0,0 +1,5 @@ +GENMAI BOARD +M: Magnus Damm <damm@opensource.se> +S: Maintained +F: arch/arm/dts/r7s72100* +N: genmai diff --git a/board/renesas/genmai/Makefile b/board/renesas/genmai/Makefile new file mode 100644 index 00000000000..73f5e45affd --- /dev/null +++ b/board/renesas/genmai/Makefile @@ -0,0 +1,7 @@ +# +# Copyright (C) 2025 Magnus Damm <damm@opensource.se> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := genmai.o diff --git a/board/renesas/genmai/genmai.c b/board/renesas/genmai/genmai.c new file mode 100644 index 00000000000..8153aed15e3 --- /dev/null +++ b/board/renesas/genmai/genmai.c @@ -0,0 +1,49 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2025 Magnus Damm <damm@opensource.se> + */ + +#include <init.h> +#include <asm/global_data.h> +#include <asm/io.h> + +#define RZA1_BCR_BASE 0x3FFFC000 +#define CS0BCR (RZA1_BCR_BASE + 0x04) +#define CS0WCR (RZA1_BCR_BASE + 0x28) +#define CS1BCR (RZA1_BCR_BASE + 0x08) +#define CS1WCR (RZA1_BCR_BASE + 0x2c) + +DECLARE_GLOBAL_DATA_PTR; + +int board_init(void) +{ + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; + + /* setup NOR Flash on CS0 and CS1 */ + writel(0x00000b40, CS0WCR); + writel(0x10000c00, CS0BCR); + writel(0x00000b40, CS1WCR); + writel(0x10000c00, CS1BCR); + return 0; +} + +/* + * The Genmai DT will most likely contain memory nodes describing the external + * SDRAM memory connected to CS2 and CS3, however we do not yet have any code + * in U-Boot to setup the memory controller. For now ignore DT and make use of + * the RZ/A1H on-chip memory which is 10 MiB at CFG_SYS_SDRAM_BASE. + */ + +int dram_init(void) +{ + gd->ram_base = CFG_SYS_SDRAM_BASE; + gd->ram_size = 10 << 20; + return 0; +} + +int dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = gd->ram_base; + gd->bd->bi_dram[0].size = gd->ram_size; + return 0; +} diff --git a/board/renesas/grpeach/Makefile b/board/renesas/grpeach/Makefile index 48e185ce3e8..89f8e0e8544 100644 --- a/board/renesas/grpeach/Makefile +++ b/board/renesas/grpeach/Makefile @@ -5,4 +5,3 @@ # SPDX-License-Identifier: GPL-2.0+ obj-y := grpeach.o -obj-y += lowlevel_init.o diff --git a/board/renesas/grpeach/grpeach.c b/board/renesas/grpeach/grpeach.c index 88f65c3b6a0..3a6393fdce1 100644 --- a/board/renesas/grpeach/grpeach.c +++ b/board/renesas/grpeach/grpeach.c @@ -4,17 +4,9 @@ * Copyright (C) Chris Brandt */ -#include <cpu_func.h> #include <errno.h> #include <init.h> #include <asm/global_data.h> -#include <asm/io.h> -#include <asm/arch/sys_proto.h> - -#define RZA1_WDT_BASE 0xfcfe0000 -#define WTCSR 0x00 -#define WTCNT 0x02 -#define WRCSR 0x04 DECLARE_GLOBAL_DATA_PTR; @@ -39,17 +31,3 @@ int dram_init_banksize(void) return 0; } - -void reset_cpu(void) -{ - /* Dummy read (must read WRCSR:WOVF at least once before clearing) */ - readb(RZA1_WDT_BASE + WRCSR); - - writew(0xa500, RZA1_WDT_BASE + WRCSR); - writew(0x5a5f, RZA1_WDT_BASE + WRCSR); - writew(0x5a00, RZA1_WDT_BASE + WTCNT); - writew(0xa578, RZA1_WDT_BASE + WTCSR); - - for (;;) - asm volatile("wfi"); -} diff --git a/board/ronetix/imx8mq-cm/imx8mq_cm.c b/board/ronetix/imx8mq-cm/imx8mq_cm.c index fbee2c39771..602216854ba 100644 --- a/board/ronetix/imx8mq-cm/imx8mq_cm.c +++ b/board/ronetix/imx8mq-cm/imx8mq_cm.c @@ -3,6 +3,7 @@ * Copyright 2018 NXP */ +#include <env.h> #include <miiphy.h> #include <asm-generic/gpio.h> #include <asm/arch/imx8mq_pins.h> diff --git a/board/samsung/origen/Makefile b/board/samsung/origen/Makefile index 940f689a601..30c637e322a 100644 --- a/board/samsung/origen/Makefile +++ b/board/samsung/origen/Makefile @@ -3,8 +3,8 @@ # Copyright (C) 2011 Samsung Electronics ifdef CONFIG_XPL_BUILD -# necessary to create built-in.o -obj- := __dummy__.o +# necessary to create built-in.a +obj- := __dummy__.a hostprogs-y := tools/mkorigenspl always := $(hostprogs-y) diff --git a/board/samsung/smdkv310/Makefile b/board/samsung/smdkv310/Makefile index b7f9d5a254c..360300a7851 100644 --- a/board/samsung/smdkv310/Makefile +++ b/board/samsung/smdkv310/Makefile @@ -3,8 +3,8 @@ # Copyright (C) 2011 Samsung Electronics ifdef CONFIG_XPL_BUILD -# necessary to create built-in.o -obj- := __dummy__.o +# necessary to create built-in.a +obj- := __dummy__.a hostprogs-y := tools/mksmdkv310spl always := $(hostprogs-y) diff --git a/board/sandbox/sandbox.c b/board/sandbox/sandbox.c index d97945e58fc..43f4edc39e9 100644 --- a/board/sandbox/sandbox.c +++ b/board/sandbox/sandbox.c @@ -101,7 +101,6 @@ enum env_location env_get_location(enum env_operation op, int prio) int dram_init(void) { - gd->ram_size = CFG_SYS_SDRAM_SIZE; return 0; } diff --git a/board/siemens/common/board_am335x.c b/board/siemens/common/board_am335x.c index daf0bb930ec..939ff81797d 100644 --- a/board/siemens/common/board_am335x.c +++ b/board/siemens/common/board_am335x.c @@ -10,6 +10,7 @@ */ #include <command.h> +#include <env.h> #include <serial.h> #include <watchdog.h> #include <asm/arch/clock.h> diff --git a/board/siemens/iot2050/board.c b/board/siemens/iot2050/board.c index d827f728a08..161210c60a9 100644 --- a/board/siemens/iot2050/board.c +++ b/board/siemens/iot2050/board.c @@ -11,6 +11,7 @@ #include <config.h> #include <bootstage.h> #include <dm.h> +#include <env.h> #include <fdt_support.h> #include <i2c.h> #include <led.h> diff --git a/board/socionext/developerbox/fwu_plat.c b/board/socionext/developerbox/fwu_plat.c index a8b111477ef..5d2f40f241c 100644 --- a/board/socionext/developerbox/fwu_plat.c +++ b/board/socionext/developerbox/fwu_plat.c @@ -4,6 +4,7 @@ */ #include <efi_loader.h> +#include <env.h> #include <fwu.h> #include <fwu_mdata.h> #include <memalign.h> diff --git a/board/st/stm32h747-disco/Kconfig b/board/st/stm32h747-disco/Kconfig new file mode 100644 index 00000000000..a7b2c09a327 --- /dev/null +++ b/board/st/stm32h747-disco/Kconfig @@ -0,0 +1,15 @@ +if TARGET_STM32H747_DISCO + +config SYS_BOARD + default "stm32h747-disco" + +config SYS_VENDOR + default "st" + +config SYS_SOC + default "stm32h7" + +config SYS_CONFIG_NAME + default "stm32h747-disco" + +endif diff --git a/board/st/stm32h747-disco/MAINTAINERS b/board/st/stm32h747-disco/MAINTAINERS new file mode 100644 index 00000000000..d48649f773f --- /dev/null +++ b/board/st/stm32h747-disco/MAINTAINERS @@ -0,0 +1,7 @@ +STM32H747 DISCOVERY BOARD +M: Dario Binacchi <dario.binacchi@amarulasolutions.com> +S: Maintained +F: board/st/stm32h747-disco +F: include/configs/stm32h747-disco.h +F: configs/stm32h747-disco_defconfig +F: arch/arm/dts/stm32h747* diff --git a/board/st/stm32h747-disco/Makefile b/board/st/stm32h747-disco/Makefile new file mode 100644 index 00000000000..e11f052cc88 --- /dev/null +++ b/board/st/stm32h747-disco/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (c) 2025 Dario Binacchi <dario.binacchi@amarulasolutions.com> +# + +obj-y := stm32h747-disco.o diff --git a/board/st/stm32h747-disco/stm32h747-disco.c b/board/st/stm32h747-disco/stm32h747-disco.c new file mode 100644 index 00000000000..be0884bdeb4 --- /dev/null +++ b/board/st/stm32h747-disco/stm32h747-disco.c @@ -0,0 +1,42 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * stm32h747i-disco support + * + * Copyright (C) 2025 Dario Binacchi <dario.binacchi@amarulasolutions.com> + */ + +#include <dm.h> +#include <init.h> +#include <log.h> +#include <asm/global_data.h> + +DECLARE_GLOBAL_DATA_PTR; + +int dram_init(void) +{ + struct udevice *dev; + int ret; + + ret = uclass_get_device(UCLASS_RAM, 0, &dev); + if (ret) { + debug("DRAM init failed: %d\n", ret); + return ret; + } + + if (fdtdec_setup_mem_size_base() != 0) + ret = -EINVAL; + + return ret; +} + +int dram_init_banksize(void) +{ + fdtdec_setup_memory_banksize(); + + return 0; +} + +int board_init(void) +{ + return 0; +} diff --git a/board/st/stm32mp1/stm32mp1.c b/board/st/stm32mp1/stm32mp1.c index 15fb9e4b062..ab7af69d472 100644 --- a/board/st/stm32mp1/stm32mp1.c +++ b/board/st/stm32mp1/stm32mp1.c @@ -828,7 +828,7 @@ const char *env_ext4_get_dev_part(void) int mmc_get_env_dev(void) { - const int mmc_env_dev = CONFIG_IS_ENABLED(ENV_IS_IN_MMC, (CONFIG_SYS_MMC_ENV_DEV), (-1)); + const int mmc_env_dev = CONFIG_IS_ENABLED(ENV_IS_IN_MMC, (CONFIG_ENV_MMC_DEVICE_INDEX), (-1)); if (mmc_env_dev >= 0) return mmc_env_dev; diff --git a/board/st/stm32mp2/stm32mp2.c b/board/st/stm32mp2/stm32mp2.c index 2547f2e4bb7..a72056e12d6 100644 --- a/board/st/stm32mp2/stm32mp2.c +++ b/board/st/stm32mp2/stm32mp2.c @@ -183,7 +183,7 @@ int mmc_get_boot(void) int mmc_get_env_dev(void) { - const int mmc_env_dev = CONFIG_IS_ENABLED(ENV_IS_IN_MMC, (CONFIG_SYS_MMC_ENV_DEV), (-1)); + const int mmc_env_dev = CONFIG_IS_ENABLED(ENV_IS_IN_MMC, (CONFIG_ENV_MMC_DEVICE_INDEX), (-1)); if (mmc_env_dev >= 0) return mmc_env_dev; diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS index 84799879e85..1b4b7d87163 100644 --- a/board/sunxi/MAINTAINERS +++ b/board/sunxi/MAINTAINERS @@ -296,6 +296,11 @@ M: Adam Sampson <ats@offog.org> S: Maintained F: configs/Linksprite_pcDuino3_Nano_defconfig +LIONTRON H-A133L BOARD +M: Andre Przywara <andre.przywara@arm.com> +S: Maintained +F: configs/liontron-h-a133l_defconfig + MARSBOARD-A10 BOARD M: Aleksei Mamlin <mamlinav@gmail.com> S: Maintained @@ -596,6 +601,11 @@ M: Peter Korsgaard <peter@korsgaard.com> S: Maintained F: configs/Yones_Toptech_BS1078_V2_defconfig +YUZUKIHD CHAMELEON BOARD +M: Andre Przywara <andre.przywara@arm.com> +S: Maintained +F: configs/yuzukihd-chameleon_defconfig + ZEROPI BOARD M: Yu-Tung Chang <mtwget@gmail.com> S: Maintained diff --git a/board/sunxi/board.c b/board/sunxi/board.c index ac9cefc6eac..943b6221b8a 100644 --- a/board/sunxi/board.c +++ b/board/sunxi/board.c @@ -114,7 +114,7 @@ void i2c_init_board(void) clock_twi_onoff(5, 1); sunxi_gpio_set_cfgpin(SUNXI_GPL(8), SUN50I_GPL_R_TWI); sunxi_gpio_set_cfgpin(SUNXI_GPL(9), SUN50I_GPL_R_TWI); -#elif CONFIG_MACH_SUN50I_H616 +#elif defined(CONFIG_MACH_SUN50I_H616) clock_twi_onoff(5, 1); sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN50I_H616_GPL_R_TWI); sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN50I_H616_GPL_R_TWI); @@ -435,7 +435,7 @@ static void mmc_pinmux_setup(int sdc) sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); sunxi_gpio_set_drv(pin, 2); } -#elif defined(CONFIG_MACH_SUN50I_H616) +#elif defined(CONFIG_MACH_SUN50I_H616) || defined(CONFIG_MACH_SUN50I_A133) /* SDC2: PC0-PC1, PC5-PC6, PC8-PC11, PC13-PC16 */ for (pin = SUNXI_GPC(0); pin <= SUNXI_GPC(16); pin++) { if (pin > SUNXI_GPC(1) && pin < SUNXI_GPC(5)) @@ -516,7 +516,7 @@ int board_mmc_init(struct bd_info *bis) return 0; } -#ifdef CONFIG_SYS_MMC_ENV_DEV +#ifdef CONFIG_ENV_MMC_DEVICE_INDEX int mmc_get_env_dev(void) { switch (sunxi_get_boot_device()) { @@ -525,7 +525,7 @@ int mmc_get_env_dev(void) case BOOT_DEVICE_MMC2: return 1; default: - return CONFIG_SYS_MMC_ENV_DEV; + return CONFIG_ENV_MMC_DEVICE_INDEX; } } #endif diff --git a/board/technexion/pico-imx7d/pico-imx7d.c b/board/technexion/pico-imx7d/pico-imx7d.c index d0f739c624a..cf6b7fcbd95 100644 --- a/board/technexion/pico-imx7d/pico-imx7d.c +++ b/board/technexion/pico-imx7d/pico-imx7d.c @@ -3,6 +3,7 @@ * Copyright (C) 2017 NXP Semiconductors */ +#include <env.h> #include <init.h> #include <net.h> #include <asm/arch/clock.h> diff --git a/board/thead/th1520_lpi4a/spl.c b/board/thead/th1520_lpi4a/spl.c index 25dfa387c36..d75fa6f3eff 100644 --- a/board/thead/th1520_lpi4a/spl.c +++ b/board/thead/th1520_lpi4a/spl.c @@ -39,6 +39,9 @@ void board_init_f(ulong dummy) if (ret) panic("failed to bind CPU: %d\n", ret); + riscv_cpu_setup(); + th1520_kick_secondary_cores(); + spl_dram_init(); icache_enable(); diff --git a/board/ti/am335x/mux.c b/board/ti/am335x/mux.c index 960de15398f..d2d87c304f6 100644 --- a/board/ti/am335x/mux.c +++ b/board/ti/am335x/mux.c @@ -274,6 +274,47 @@ static struct module_pin_mux uart3_icev2_pin_mux[] = { {-1}, }; +#if (IS_ENABLED(CONFIG_AM335X_LCD)) +static struct module_pin_mux lcd_pin_mux[] = { + {OFFSET(lcd_data0), (MODE(0))}, /* LCD-Data(0) */ + {OFFSET(lcd_data1), (MODE(0))}, /* LCD-Data(1) */ + {OFFSET(lcd_data2), (MODE(0))}, /* LCD-Data(2) */ + {OFFSET(lcd_data3), (MODE(0))}, /* LCD-Data(3) */ + {OFFSET(lcd_data4), (MODE(0))}, /* LCD-Data(4) */ + {OFFSET(lcd_data5), (MODE(0))}, /* LCD-Data(5) */ + {OFFSET(lcd_data6), (MODE(0))}, /* LCD-Data(6) */ + {OFFSET(lcd_data7), (MODE(0))}, /* LCD-Data(7) */ + {OFFSET(lcd_data8), (MODE(0))}, /* LCD-Data(8) */ + {OFFSET(lcd_data9), (MODE(0))}, /* LCD-Data(9) */ + {OFFSET(lcd_data10), (MODE(0))}, /* LCD-Data(10) */ + {OFFSET(lcd_data11), (MODE(0))}, /* LCD-Data(11) */ + {OFFSET(lcd_data12), (MODE(0))}, /* LCD-Data(12) */ + {OFFSET(lcd_data13), (MODE(0))}, /* LCD-Data(13) */ + {OFFSET(lcd_data14), (MODE(0))}, /* LCD-Data(14) */ + {OFFSET(lcd_data15), (MODE(0))}, /* LCD-Data(15) */ + {OFFSET(gpmc_ad15), (MODE(1))}, /* LCD-Data(16) */ + {OFFSET(gpmc_ad14), (MODE(1))}, /* LCD-Data(17) */ + {OFFSET(gpmc_ad13), (MODE(1))}, /* LCD-Data(18) */ + {OFFSET(gpmc_ad12), (MODE(1))}, /* LCD-Data(19) */ + {OFFSET(gpmc_ad11), (MODE(1))}, /* LCD-Data(20) */ + {OFFSET(gpmc_ad10), (MODE(1))}, /* LCD-Data(21) */ + {OFFSET(gpmc_ad9), (MODE(1))}, /* LCD-Data(22) */ + {OFFSET(gpmc_ad8), (MODE(1))}, /* LCD-Data(23) */ + {OFFSET(lcd_vsync), (MODE(0))}, /* LCD-VSync */ + {OFFSET(lcd_hsync), (MODE(0))}, /* LCD-HSync */ + {OFFSET(lcd_ac_bias_en), (MODE(0))}, /* LCD-DE */ + {OFFSET(lcd_pclk), (MODE(0))}, /* LCD-CLK */ + {-1}, +}; +#endif + +#if (IS_ENABLED(CONFIG_PWM_TI_ECAP)) +static struct module_pin_mux ecap_pin_mux[] = { + {OFFSET(ecap0_in_pwm0_out), (MODE(0))}, /* ecap0_in_pwm0_out */ + {-1}, +}; +#endif + #if defined(CONFIG_NOR_BOOT) void enable_norboot_pin_mux(void) { @@ -389,6 +430,13 @@ void enable_board_pin_mux(void) configure_module_pin_mux(mmc1_pin_mux); configure_module_pin_mux(spi0_pin_mux); } + #if IS_ENABLED(CONFIG_AM335X_LCD) + configure_module_pin_mux(lcd_pin_mux); + #endif + + #if IS_ENABLED(CONFIG_PWM_TI_ECAP) + configure_module_pin_mux(ecap_pin_mux); + #endif } else if (board_is_idk()) { /* Industrial Motor Control (IDK) */ configure_module_pin_mux(mii1_pin_mux); @@ -408,6 +456,9 @@ void enable_board_pin_mux(void) if (subtype_id == 'L') configure_module_pin_mux(spi0_pin_mux); + } else if (board_is_bbge()) { + /* Beaglebone Green Eco pinmux */ + configure_module_pin_mux(rgmii1_pin_mux); } else { /* Beaglebone LT pinmux */ configure_module_pin_mux(mii1_pin_mux); diff --git a/board/ti/common/board_detect.h b/board/ti/common/board_detect.h index ca1aa80f2f0..b057f3b2269 100644 --- a/board/ti/common/board_detect.h +++ b/board/ti/common/board_detect.h @@ -10,6 +10,8 @@ /* TI EEPROM MAGIC Header identifier */ #include <linux/bitops.h> +#include <linux/if_ether.h> + #define TI_EEPROM_HEADER_MAGIC 0xEE3355AA #define TI_DEAD_EEPROM_MAGIC 0xADEAD12C @@ -18,7 +20,7 @@ #define TI_EEPROM_HDR_SERIAL_LEN 12 #define TI_EEPROM_HDR_CONFIG_LEN 32 #define TI_EEPROM_HDR_NO_OF_MAC_ADDR 3 -#define TI_EEPROM_HDR_ETH_ALEN 6 +#define TI_EEPROM_HDR_ETH_ALEN ETH_ALEN /** * struct ti_am_eeprom - This structure holds data read in from the diff --git a/board/ti/j7200/j7200.env b/board/ti/j7200/j7200.env index 6cc92bf0d8d..292fc72fd58 100644 --- a/board/ti/j7200/j7200.env +++ b/board/ti/j7200/j7200.env @@ -36,5 +36,5 @@ main_cpsw0_qsgmii_phyinit= #endif #if CONFIG_TARGET_J7200_A72_EVM -rproc_fw_binaries=2 /lib/firmware/j7200-main-r5f0_0-fw 3 /lib/firmware/j7200-main-r5f0_1-fw +rproc_fw_binaries= 1 /lib/firmware/j7200-mcu-r5f0_1-fw 2 /lib/firmware/j7200-main-r5f0_0-fw 3 /lib/firmware/j7200-main-r5f0_1-fw #endif diff --git a/board/ti/j721e/evm.c b/board/ti/j721e/evm.c index 0525f6e6f97..b1ed29af001 100644 --- a/board/ti/j721e/evm.c +++ b/board/ti/j721e/evm.c @@ -8,6 +8,7 @@ */ #include <efi_loader.h> +#include <env.h> #include <generic-phy.h> #include <image.h> #include <net.h> diff --git a/board/ti/j721e/j721e.env b/board/ti/j721e/j721e.env index e5b4225b3ce..ead7fbdb212 100644 --- a/board/ti/j721e/j721e.env +++ b/board/ti/j721e/j721e.env @@ -38,5 +38,5 @@ main_cpsw0_qsgmii_phyinit= #endif #if CONFIG_TARGET_J721E_A72_EVM -rproc_fw_binaries=2 /lib/firmware/j7-main-r5f0_0-fw 3 /lib/firmware/j7-main-r5f0_1-fw 4 /lib/firmware/j7-main-r5f1_0-fw 5 /lib/firmware/j7-main-r5f1_1-fw 6 /lib/firmware/j7-c66_0-fw 7 /lib/firmware/j7-c66_1-fw 8 /lib/firmware/j7-c71_0-fw +rproc_fw_binaries= 1 /lib/firmware/j7-mcu-r5f0_1-fw 2 /lib/firmware/j7-main-r5f0_0-fw 3 /lib/firmware/j7-main-r5f0_1-fw 4 /lib/firmware/j7-main-r5f1_0-fw 5 /lib/firmware/j7-main-r5f1_1-fw 6 /lib/firmware/j7-c66_0-fw 7 /lib/firmware/j7-c66_1-fw 8 /lib/firmware/j7-c71_0-fw #endif diff --git a/board/ti/j721s2/j721s2.env b/board/ti/j721s2/j721s2.env index a6b22550809..abd4faea6ee 100644 --- a/board/ti/j721s2/j721s2.env +++ b/board/ti/j721s2/j721s2.env @@ -24,6 +24,6 @@ name_mcur5f0_0fw=/lib/firmware/j7-mcu-r5f0_0-fw #endif rd_spec=- -rproc_fw_binaries= 2 /lib/firmware/j721s2-main-r5f0_0-fw 3 /lib/firmware/j721s2-main-r5f0_1-fw 4 /lib/firmware/j721s2-main-r5f1_0-fw 5 /lib/firmware/j721s2-main-r5f1_1-fw 6 /lib/firmware/j721s2-c71_0-fw 7 /lib/firmware/j721s2-c71_1-fw +rproc_fw_binaries= 1 /lib/firmware/j721s2-mcu-r5f0_1-fw 2 /lib/firmware/j721s2-main-r5f0_0-fw 3 /lib/firmware/j721s2-main-r5f0_1-fw 4 /lib/firmware/j721s2-main-r5f1_0-fw 5 /lib/firmware/j721s2-main-r5f1_1-fw 6 /lib/firmware/j721s2-c71_0-fw 7 /lib/firmware/j721s2-c71_1-fw diff --git a/board/ti/j784s4/j784s4.env b/board/ti/j784s4/j784s4.env index 9e1741be424..2f1a5f549d1 100644 --- a/board/ti/j784s4/j784s4.env +++ b/board/ti/j784s4/j784s4.env @@ -21,7 +21,7 @@ bootdir=/boot rd_spec=- #if CONFIG_TARGET_J784S4_A72_EVM -rproc_fw_binaries= 2 /lib/firmware/j784s4-main-r5f0_0-fw 3 /lib/firmware/j784s4-main-r5f0_1-fw 4 /lib/firmware/j784s4-main-r5f1_0-fw 5 /lib/firmware/j784s4-main-r5f1_1-fw 6 /lib/firmware/j784s4-main-r5f2_0-fw 7 /lib/firmware/j784s4-main-r5f2_1-fw 8 /lib/firmware/j784s4-c71_0-fw 9 /lib/firmware/j784s4-c71_1-fw 10 /lib/firmware/j784s4-c71_2-fw 11 /lib/firmware/j784s4-c71_3-fw +rproc_fw_binaries= 1 /lib/firmware/j784s4-mcu-r5f0_1-fw 2 /lib/firmware/j784s4-main-r5f0_0-fw 3 /lib/firmware/j784s4-main-r5f0_1-fw 4 /lib/firmware/j784s4-main-r5f1_0-fw 5 /lib/firmware/j784s4-main-r5f1_1-fw 6 /lib/firmware/j784s4-main-r5f2_0-fw 7 /lib/firmware/j784s4-main-r5f2_1-fw 8 /lib/firmware/j784s4-c71_0-fw 9 /lib/firmware/j784s4-c71_1-fw 10 /lib/firmware/j784s4-c71_2-fw 11 /lib/firmware/j784s4-c71_3-fw #elif CONFIG_TARGET_J742S2_A72_EVM -rproc_fw_binaries= 2 /lib/firmware/j742s2-main-r5f0_0-fw 3 /lib/firmware/j742s2-main-r5f0_1-fw 4 /lib/firmware/j742s2-main-r5f1_0-fw 5 /lib/firmware/j742s2-main-r5f1_1-fw 6 /lib/firmware/j742s2-main-r5f2_0-fw 7 /lib/firmware/j742s2-main-r5f2_1-fw 8 /lib/firmware/j742s2-c71_0-fw 9 /lib/firmware/j742s2-c71_1-fw 10 /lib/firmware/j742s2-c71_2-fw +rproc_fw_binaries= 1 /lib/firmware/j742s2-mcu-r5f0_1-fw 2 /lib/firmware/j742s2-main-r5f0_0-fw 3 /lib/firmware/j742s2-main-r5f0_1-fw 4 /lib/firmware/j742s2-main-r5f1_0-fw 5 /lib/firmware/j742s2-main-r5f1_1-fw 6 /lib/firmware/j742s2-main-r5f2_0-fw 7 /lib/firmware/j742s2-main-r5f2_1-fw 8 /lib/firmware/j742s2-c71_0-fw 9 /lib/firmware/j742s2-c71_1-fw 10 /lib/firmware/j742s2-c71_2-fw #endif diff --git a/board/toradex/apalis_imx6/do_fuse.c b/board/toradex/apalis_imx6/do_fuse.c index 698b05bc5ad..8721276bed8 100644 --- a/board/toradex/apalis_imx6/do_fuse.c +++ b/board/toradex/apalis_imx6/do_fuse.c @@ -11,6 +11,7 @@ #include <command.h> #include <console.h> #include <fuse.h> +#include <linux/string.h> static int mfgr_fuse(void) { diff --git a/board/toradex/colibri_imx6/do_fuse.c b/board/toradex/colibri_imx6/do_fuse.c index 698b05bc5ad..8721276bed8 100644 --- a/board/toradex/colibri_imx6/do_fuse.c +++ b/board/toradex/colibri_imx6/do_fuse.c @@ -11,6 +11,7 @@ #include <command.h> #include <console.h> #include <fuse.h> +#include <linux/string.h> static int mfgr_fuse(void) { diff --git a/board/toradex/colibri_imx7/colibri_imx7.c b/board/toradex/colibri_imx7/colibri_imx7.c index 7de29e3abfb..69a8a18d3a7 100644 --- a/board/toradex/colibri_imx7/colibri_imx7.c +++ b/board/toradex/colibri_imx7/colibri_imx7.c @@ -4,6 +4,7 @@ */ #include <cpu_func.h> +#include <env.h> #include <init.h> #include <net.h> #include <asm/arch/clock.h> diff --git a/board/toradex/common/Makefile b/board/toradex/common/Makefile index 7e3905445a5..24496a7c997 100644 --- a/board/toradex/common/Makefile +++ b/board/toradex/common/Makefile @@ -3,8 +3,8 @@ # Common for all Toradex modules ifeq ($(CONFIG_XPL_BUILD),y) -# Necessary to create built-in.o -obj- := __dummy__.o +# Necessary to create built-in.a +obj- := __dummy__.a else obj-$(CONFIG_TDX_CFG_BLOCK) += tdx-cfg-block.o obj-y += tdx-common.o diff --git a/board/toradex/common/tdx-cfg-block.c b/board/toradex/common/tdx-cfg-block.c index 6c1cea77c8c..a89c5bf2c19 100644 --- a/board/toradex/common/tdx-cfg-block.c +++ b/board/toradex/common/tdx-cfg-block.c @@ -166,6 +166,23 @@ const struct toradex_som toradex_modules[] = { { APALIS_IMX8QM_8GB_WIFI_BT_IT_1300MHZ, "Apalis iMX8QM 8GB WB IT", TARGET_IS_ENABLED(APALIS_IMX8) }, { SMARC_IMX95_HEXA_8GB_WB_IT, "SMARC iMX95 Hexa 8GB WB IT", TARGET_IS_ENABLED(TORADEX_SMARC_IMX95) }, { SMARC_IMX8MPQ_4GB_WB_IT, "SMARC iMX8M Plus Quad 4GB WB IT", TARGET_IS_ENABLED(TORADEX_SMARC_IMX8MP) }, + { AQUILA_IMX95_HEXA_16GB_WB_IT, "Aquila iMX95 Hexa 16GB WB IT", TARGET_IS_ENABLED(AQUILA_IMX95) }, + { VERDIN_AM62PQ_2G_WIFI_BT_IT, "Verdin AM62P Quad 2GB WB IT", TARGET_IS_ENABLED(VERDIN_AM62P_A53) }, + { SMARC_IMX95_HEXA_8GB_IT, "SMARC iMX95 Hexa 8GB IT", TARGET_IS_ENABLED(TORADEX_SMARC_IMX95) }, + { SMARC_IMX95_HEXA_4GB_WB_IT, "SMARC iMX95 Hexa 4GB WB IT", TARGET_IS_ENABLED(TORADEX_SMARC_IMX95) }, + { SMARC_IMX95_HEXA_4GB_ET, "SMARC iMX95 Hexa 4GB ET", TARGET_IS_ENABLED(TORADEX_SMARC_IMX95) }, + { SMARC_IMX95_HEXA_2GB_WB_IT, "SMARC iMX95 Hexa 2GB WB IT", TARGET_IS_ENABLED(TORADEX_SMARC_IMX95) }, + { SMARC_IMX95_HEXA_2GB_ET, "SMARC iMX95 Hexa 2GB ET", TARGET_IS_ENABLED(TORADEX_SMARC_IMX95) }, + { SMARC_IMX8MPQ_4GB_IT, "SMARC iMX8M Plus Quad 4GB IT", TARGET_IS_ENABLED(TORADEX_SMARC_IMX8MP) }, + { SMARC_IMX8MPQ_2GB_WB_IT, "SMARC iMX8M Plus Quad 2GB WB IT", TARGET_IS_ENABLED(TORADEX_SMARC_IMX8MP) }, + { SMARC_IMX8MPQ_2GB_IT, "SMARC iMX8M Plus Quad 2GB IT", TARGET_IS_ENABLED(TORADEX_SMARC_IMX8MP) }, + { SMARC_IMX8MPQL_1GB_WB_ET, "SMARC iMX8M Plus Quadlite 1GB WB ET", TARGET_IS_ENABLED(TORADEX_SMARC_IMX8MP) }, + { SMARC_IMX8MPQL_1GB_ET, "SMARC iMX8M Plus Quadlite 1GB ET", TARGET_IS_ENABLED(TORADEX_SMARC_IMX8MP) }, + { AQUILA_AM69O_32GB_IT, "Aquila AM69 Octa 32GB IT", TARGET_IS_ENABLED(AQUILA_AM69_A72) }, + { AQUILA_AM69O_16GB_WB_IT, "Aquila AM69 Octa 16GB WB IT", TARGET_IS_ENABLED(AQUILA_AM69_A72) }, + { AQUILA_AM69O_16GB_IT, "Aquila AM69 Octa 16GB IT", TARGET_IS_ENABLED(AQUILA_AM69_A72) }, + { AQUILA_AM69O_8GB_WB_IT, "Aquila AM69 Octa 8GB WB IT", TARGET_IS_ENABLED(AQUILA_AM69_A72) }, + { AQUILA_AM69O_8GB_IT, "Aquila AM69 Octa 8GB IT", TARGET_IS_ENABLED(AQUILA_AM69_A72) }, }; struct pid4list { diff --git a/board/toradex/common/tdx-cfg-block.h b/board/toradex/common/tdx-cfg-block.h index f4dd853306b..db612811c5c 100644 --- a/board/toradex/common/tdx-cfg-block.h +++ b/board/toradex/common/tdx-cfg-block.h @@ -124,6 +124,23 @@ enum { APALIS_IMX8QM_8GB_WIFI_BT_IT_1300MHZ, /* 95 */ SMARC_IMX95_HEXA_8GB_WB_IT, SMARC_IMX8MPQ_4GB_WB_IT, + AQUILA_IMX95_HEXA_16GB_WB_IT, + VERDIN_AM62PQ_2G_WIFI_BT_IT, /* 99 */ + SMARC_IMX95_HEXA_8GB_IT = 201, + SMARC_IMX95_HEXA_4GB_WB_IT, + SMARC_IMX95_HEXA_4GB_ET, + SMARC_IMX95_HEXA_2GB_WB_IT, + SMARC_IMX95_HEXA_2GB_ET, /* 205 */ + SMARC_IMX8MPQ_4GB_IT, + SMARC_IMX8MPQ_2GB_WB_IT, + SMARC_IMX8MPQ_2GB_IT, + SMARC_IMX8MPQL_1GB_WB_ET, + SMARC_IMX8MPQL_1GB_ET, /* 210 */ + AQUILA_AM69O_32GB_IT, + AQUILA_AM69O_16GB_WB_IT, + AQUILA_AM69O_16GB_IT, + AQUILA_AM69O_8GB_WB_IT, + AQUILA_AM69O_8GB_IT, /* 215 */ }; enum { diff --git a/board/toradex/verdin-am62/verdin-am62.c b/board/toradex/verdin-am62/verdin-am62.c index 7b2eecbf659..eca2cc8bc7f 100644 --- a/board/toradex/verdin-am62/verdin-am62.c +++ b/board/toradex/verdin-am62/verdin-am62.c @@ -15,6 +15,7 @@ #include <init.h> #include <k3-ddrss.h> #include <spl.h> +#include <linux/sizes.h> #include <asm/arch/k3-ddr.h> #include "../common/tdx-cfg-block.h" diff --git a/board/toradex/verdin-am62p/Kconfig b/board/toradex/verdin-am62p/Kconfig new file mode 100644 index 00000000000..7bf0133b669 --- /dev/null +++ b/board/toradex/verdin-am62p/Kconfig @@ -0,0 +1,83 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# +# Copyright 2025 Toradex +# + +choice + prompt "Toradex Verdin AM62P based boards" + optional + +config TARGET_VERDIN_AM62P_A53 + bool "Toradex Verdin AM62P running on A53" + select ARM64 + select BINMAN + select OF_SYSTEM_SETUP + +config TARGET_VERDIN_AM62P_R5 + bool "Toradex Verdin AM62P running on R5" + select CPU_V7R + select SYS_THUMB_BUILD + select K3_LOAD_SYSFW + select RAM + select SPL_RAM + select K3_DDRSS + select BINMAN + imply SYS_K3_SPL_ATF + +endchoice + +if TARGET_VERDIN_AM62P_A53 + +config SYS_BOARD + default "verdin-am62p" + +config SYS_CONFIG_NAME + default "verdin-am62p" + +config SYS_VENDOR + default "toradex" + +config TDX_CFG_BLOCK + default y + +config TDX_CFG_BLOCK_2ND_ETHADDR + default y + +config TDX_CFG_BLOCK_DEV + default "0" + +config TDX_CFG_BLOCK_EXTRA + default y + +# Toradex config block in eMMC, at the end of 1st "boot sector" +config TDX_CFG_BLOCK_OFFSET + default "-512" + +config TDX_CFG_BLOCK_PART + default "1" + +config TDX_HAVE_EEPROM_EXTRA + default y + +config TDX_HAVE_MMC + default y + +source "board/toradex/common/Kconfig" + +endif + +if TARGET_VERDIN_AM62P_R5 + +config SPL_LDSCRIPT + default "arch/arm/mach-omap2/u-boot-spl.lds" + +config SYS_BOARD + default "verdin-am62p" + +config SYS_CONFIG_NAME + default "verdin-am62p" + +config SYS_VENDOR + default "toradex" + +endif diff --git a/board/toradex/verdin-am62p/MAINTAINERS b/board/toradex/verdin-am62p/MAINTAINERS new file mode 100644 index 00000000000..97094e0e756 --- /dev/null +++ b/board/toradex/verdin-am62p/MAINTAINERS @@ -0,0 +1,17 @@ +Verdin AM62P +M: Francesco Dolcini <francesco.dolcini@toradex.com> +W: https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62p +S: Maintained +F: arch/arm/dts/k3-am62p-verdin-dev.dtsi +F: arch/arm/dts/k3-am62p-verdin-wifi.dtsi +F: arch/arm/dts/k3-am62p-verdin.dtsi +F: arch/arm/dts/k3-am62p5-verdin-lpddr4-1600.dtsi +F: arch/arm/dts/k3-am62p5-verdin-r5.dts +F: arch/arm/dts/k3-am62p5-verdin-wifi-dev-binman.dtsi +F: arch/arm/dts/k3-am62p5-verdin-wifi-dev-u-boot.dtsi +F: arch/arm/dts/k3-am62p5-verdin-wifi-dev.dts +F: board/toradex/verdin-am62p/ +F: configs/verdin-am62p_a53_defconfig +F: configs/verdin-am62p_r5_defconfig +F: doc/board/toradex/verdin-am62p.rst +F: include/configs/verdin-am62p.h diff --git a/board/toradex/verdin-am62p/Makefile b/board/toradex/verdin-am62p/Makefile new file mode 100644 index 00000000000..2eef6f4f592 --- /dev/null +++ b/board/toradex/verdin-am62p/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# +# Copyright 2025 Toradex +# + +obj-y += verdin-am62p.o diff --git a/board/toradex/verdin-am62p/board-cfg.yaml b/board/toradex/verdin-am62p/board-cfg.yaml new file mode 100644 index 00000000000..d539011aff9 --- /dev/null +++ b/board/toradex/verdin-am62p/board-cfg.yaml @@ -0,0 +1,37 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ +# +# Board configuration for AM62Px SoCs +# + +--- + +board-cfg: + rev: + boardcfg_abi_maj: 0x0 + boardcfg_abi_min: 0x1 + control: + subhdr: + magic: 0xC1D3 + size: 7 + main_isolation_enable: 0x5A + main_isolation_hostid: 0x2 + secproxy: + subhdr: + magic: 0x1207 + size: 7 + scaling_factor: 0x1 + scaling_profile: 0x1 + disable_main_nav_secure_proxy: 0 + msmc: + subhdr: + magic: 0xA5C3 + size: 5 + msmc_cache_size: 0x10 + debug_cfg: + subhdr: + magic: 0x020C + size: 8 + trace_dst_enables: 0x00 + trace_src_enables: 0x00 diff --git a/board/toradex/verdin-am62p/pm-cfg.yaml b/board/toradex/verdin-am62p/pm-cfg.yaml new file mode 100644 index 00000000000..3ff27ce702c --- /dev/null +++ b/board/toradex/verdin-am62p/pm-cfg.yaml @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ +# +# Power management configuration for AM62Px +# +# +--- +pm-cfg: + rev: + boardcfg_abi_maj: 0x0 + boardcfg_abi_min: 0x1 diff --git a/board/toradex/verdin-am62p/rm-cfg.yaml b/board/toradex/verdin-am62p/rm-cfg.yaml new file mode 100644 index 00000000000..73da85eeade --- /dev/null +++ b/board/toradex/verdin-am62p/rm-cfg.yaml @@ -0,0 +1,1083 @@ +# SPDX-License-Identifier: GPL-2.0+ +# Copyright (C) 2022-2025 Texas Instruments Incorporated - https://www.ti.com/ +# +# Resource management configuration for AM62P +# + +--- + +rm-cfg: + rm_boardcfg: + rev: + boardcfg_abi_maj: 0x0 + boardcfg_abi_min: 0x1 + host_cfg: + subhdr: + magic: 0x4C41 + size: 356 + host_cfg_entries: + - # 1 + host_id: 12 + allowed_atype: 0x2A + allowed_qos: 0xAAAA + allowed_orderid: 0xAAAAAAAA + allowed_priority: 0xAAAA + allowed_sched_priority: 0xAA + - # 2 + host_id: 30 + allowed_atype: 0x2A + allowed_qos: 0xAAAA + allowed_orderid: 0xAAAAAAAA + allowed_priority: 0xAAAA + allowed_sched_priority: 0xAA + - # 3 + host_id: 36 + allowed_atype: 0x2A + allowed_qos: 0xAAAA + allowed_orderid: 0xAAAAAAAA + allowed_priority: 0xAAAA + allowed_sched_priority: 0xAA + - # 4 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 5 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 6 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 7 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 8 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 9 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 10 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 11 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 12 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 13 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 14 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 15 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 16 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 17 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 18 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 19 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + 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host_id: 128 + reserved: 0 + - + start_resource: 0 + num_resource: 6 + type: 12750 + host_id: 12 + reserved: 0 + - + start_resource: 0 + num_resource: 6 + type: 12769 + host_id: 12 + reserved: 0 + - + start_resource: 0 + num_resource: 8 + type: 12810 + host_id: 12 + reserved: 0 + - + start_resource: 12288 + num_resource: 128 + type: 12813 + host_id: 12 + reserved: 0 + - + start_resource: 3072 + num_resource: 6 + type: 12826 + host_id: 128 + reserved: 0 + - + start_resource: 3584 + num_resource: 6 + type: 12827 + host_id: 128 + reserved: 0 + - + start_resource: 4096 + num_resource: 6 + type: 12828 + host_id: 128 + reserved: 0 diff --git a/board/toradex/verdin-am62p/sec-cfg.yaml b/board/toradex/verdin-am62p/sec-cfg.yaml new file mode 100644 index 00000000000..bfd6a4e5dbd --- /dev/null +++ b/board/toradex/verdin-am62p/sec-cfg.yaml @@ -0,0 +1,378 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ +# +# Security configuration for AM62Px +# +--- +sec-cfg: + rev: + boardcfg_abi_maj: 0x0 + boardcfg_abi_min: 0x1 + processor_acl_list: + subhdr: + magic: 0xF1EA + size: 164 + proc_acl_entries: + - # 1 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 2 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 3 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 4 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 5 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 6 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 7 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 8 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 9 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 10 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 11 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 12 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 13 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 14 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 15 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 16 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 17 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 18 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 19 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 20 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 21 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 22 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 23 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 24 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 25 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 26 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 27 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 28 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 29 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 30 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 31 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 32 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + host_hierarchy: + subhdr: + magic: 0x8D27 + size: 68 + host_hierarchy_entries: + - # 1 + host_id: 0 + supervisor_host_id: 0 + - # 2 + host_id: 0 + supervisor_host_id: 0 + - # 3 + host_id: 0 + supervisor_host_id: 0 + - # 4 + host_id: 0 + supervisor_host_id: 0 + - # 5 + host_id: 0 + supervisor_host_id: 0 + - # 6 + host_id: 0 + supervisor_host_id: 0 + - # 7 + host_id: 0 + supervisor_host_id: 0 + - # 8 + host_id: 0 + supervisor_host_id: 0 + - # 9 + host_id: 0 + supervisor_host_id: 0 + - # 10 + host_id: 0 + supervisor_host_id: 0 + - # 11 + host_id: 0 + supervisor_host_id: 0 + - # 12 + host_id: 0 + supervisor_host_id: 0 + - # 13 + host_id: 0 + supervisor_host_id: 0 + - # 14 + host_id: 0 + supervisor_host_id: 0 + - # 15 + host_id: 0 + supervisor_host_id: 0 + - # 16 + host_id: 0 + supervisor_host_id: 0 + - # 17 + host_id: 0 + supervisor_host_id: 0 + - # 18 + host_id: 0 + supervisor_host_id: 0 + - # 19 + host_id: 0 + supervisor_host_id: 0 + - # 20 + host_id: 0 + supervisor_host_id: 0 + - # 21 + host_id: 0 + supervisor_host_id: 0 + - # 22 + host_id: 0 + supervisor_host_id: 0 + - # 23 + host_id: 0 + supervisor_host_id: 0 + - # 24 + host_id: 0 + supervisor_host_id: 0 + - # 25 + host_id: 0 + supervisor_host_id: 0 + - # 26 + host_id: 0 + supervisor_host_id: 0 + - # 27 + host_id: 0 + supervisor_host_id: 0 + - # 28 + host_id: 0 + supervisor_host_id: 0 + - # 29 + host_id: 0 + supervisor_host_id: 0 + - # 30 + host_id: 0 + supervisor_host_id: 0 + - # 31 + host_id: 0 + supervisor_host_id: 0 + - # 32 + host_id: 0 + supervisor_host_id: 0 + otp_config: + subhdr: + magic: 0x4081 + size: 69 + otp_entry: + - # 1 + host_id: 0 + host_perms: 0 + - # 2 + host_id: 0 + host_perms: 0 + - # 3 + host_id: 0 + host_perms: 0 + - # 4 + host_id: 0 + host_perms: 0 + - # 5 + host_id: 0 + host_perms: 0 + - # 6 + host_id: 0 + host_perms: 0 + - # 7 + host_id: 0 + host_perms: 0 + - # 8 + host_id: 0 + host_perms: 0 + - # 9 + host_id: 0 + host_perms: 0 + - # 10 + host_id: 0 + host_perms: 0 + - # 11 + host_id: 0 + host_perms: 0 + - # 12 + host_id: 0 + host_perms: 0 + - # 13 + host_id: 0 + host_perms: 0 + - # 14 + host_id: 0 + host_perms: 0 + - # 15 + host_id: 0 + host_perms: 0 + - # 16 + host_id: 0 + host_perms: 0 + - # 17 + host_id: 0 + host_perms: 0 + - # 18 + host_id: 0 + host_perms: 0 + - # 19 + host_id: 0 + host_perms: 0 + - # 20 + host_id: 0 + host_perms: 0 + - # 21 + host_id: 0 + host_perms: 0 + - # 22 + host_id: 0 + host_perms: 0 + - # 23 + host_id: 0 + host_perms: 0 + - # 24 + host_id: 0 + host_perms: 0 + - # 25 + host_id: 0 + host_perms: 0 + - # 26 + host_id: 0 + host_perms: 0 + - # 27 + host_id: 0 + host_perms: 0 + - # 28 + host_id: 0 + host_perms: 0 + - # 29 + host_id: 0 + host_perms: 0 + - # 30 + host_id: 0 + host_perms: 0 + - # 31 + host_id: 0 + host_perms: 0 + - # 32 + host_id: 0 + host_perms: 0 + write_host_id: 0 + dkek_config: + subhdr: + magic: 0x5170 + size: 12 + allowed_hosts: [128, 0, 0, 0] + allow_dkek_export_tisci: 0x5A + rsvd: [0, 0, 0] + sa2ul_cfg: + subhdr: + magic: 0x23BE + size: 0 + auth_resource_owner: 0 + enable_saul_psil_global_config_writes: 0x5A + rsvd: [0, 0] + sec_dbg_config: + subhdr: + magic: 0x42AF + size: 16 + allow_jtag_unlock: 0x5A + allow_wildcard_unlock: 0x5A + allowed_debug_level_rsvd: 0 + rsvd: 0 + min_cert_rev: 0x0 + jtag_unlock_hosts: [0, 0, 0, 0] + sec_handover_cfg: + subhdr: + magic: 0x608F + size: 10 + handover_msg_sender: 0 + handover_to_host_id: 0 + rsvd: [0, 0, 0, 0] diff --git a/board/toradex/verdin-am62p/tifs-rm-cfg.yaml b/board/toradex/verdin-am62p/tifs-rm-cfg.yaml new file mode 100644 index 00000000000..80269748057 --- /dev/null +++ b/board/toradex/verdin-am62p/tifs-rm-cfg.yaml @@ -0,0 +1,927 @@ +# SPDX-License-Identifier: GPL-2.0+ +# Copyright (C) 2022-2025 Texas Instruments Incorporated - https://www.ti.com/ +# +# Resource management configuration for AM62P +# + +--- + +tifs-rm-cfg: + rm_boardcfg: + rev: + boardcfg_abi_maj : 0x0 + boardcfg_abi_min : 0x1 + host_cfg: + subhdr: + magic: 0x4C41 + size : 356 + host_cfg_entries: + - #1 + host_id: 12 + allowed_atype: 0x2A + allowed_qos: 0xAAAA + allowed_orderid: 0xAAAAAAAA + allowed_priority: 0xAAAA + allowed_sched_priority: 0xAA + - #2 + host_id: 30 + allowed_atype: 0x2A + allowed_qos: 0xAAAA + allowed_orderid: 0xAAAAAAAA + allowed_priority: 0xAAAA + allowed_sched_priority: 0xAA + - #3 + host_id: 36 + allowed_atype: 0x2A + allowed_qos: 0xAAAA + allowed_orderid: 0xAAAAAAAA + allowed_priority: 0xAAAA + allowed_sched_priority: 0xAA + - #4 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #5 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #6 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #7 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #8 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #9 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #10 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #11 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #12 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #13 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #14 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #15 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #16 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #17 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #18 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #19 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #20 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #21 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #22 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #23 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #24 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #25 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #26 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #27 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #28 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #29 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #30 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #31 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #32 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + resasg: + subhdr: + magic: 0x7B25 + size: 8 + resasg_entries_size: 904 + reserved: 0 + resasg_entries: + - + start_resource: 0 + num_resource: 18 + type: 1677 + host_id: 12 + reserved: 0 + - + start_resource: 18 + num_resource: 6 + type: 1677 + host_id: 35 + reserved: 0 + - + start_resource: 18 + num_resource: 6 + type: 1677 + host_id: 36 + reserved: 0 + - + start_resource: 24 + num_resource: 2 + type: 1677 + host_id: 30 + reserved: 0 + - + start_resource: 26 + num_resource: 6 + type: 1677 + host_id: 128 + reserved: 0 + - + start_resource: 57 + num_resource: 18 + type: 1678 + host_id: 12 + reserved: 0 + - + start_resource: 75 + num_resource: 5 + type: 1678 + host_id: 35 + reserved: 0 + - + start_resource: 75 + num_resource: 5 + type: 1678 + host_id: 36 + reserved: 0 + - + start_resource: 80 + num_resource: 2 + type: 1678 + host_id: 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host_id: 12 + reserved: 0 + - + start_resource: 23 + num_resource: 1 + type: 1971 + host_id: 12 + reserved: 0 + - + start_resource: 43 + num_resource: 8 + type: 1972 + host_id: 12 + reserved: 0 + - + start_resource: 0 + num_resource: 1 + type: 2112 + host_id: 128 + reserved: 0 + - + start_resource: 2 + num_resource: 2 + type: 2122 + host_id: 12 + reserved: 0 + - + start_resource: 0 + num_resource: 6 + type: 12750 + host_id: 12 + reserved: 0 + - + start_resource: 0 + num_resource: 6 + type: 12769 + host_id: 12 + reserved: 0 + - + start_resource: 0 + num_resource: 8 + type: 12810 + host_id: 12 + reserved: 0 + - + start_resource: 3072 + num_resource: 6 + type: 12826 + host_id: 128 + reserved: 0 + - + start_resource: 3584 + num_resource: 6 + type: 12827 + host_id: 128 + reserved: 0 + - + start_resource: 4096 + num_resource: 6 + type: 12828 + host_id: 128 + reserved: 0 diff --git a/board/toradex/verdin-am62p/verdin-am62p.c b/board/toradex/verdin-am62p/verdin-am62p.c new file mode 100644 index 00000000000..43d1c9312fe --- /dev/null +++ b/board/toradex/verdin-am62p/verdin-am62p.c @@ -0,0 +1,160 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Board specific initialization for Verdin AM62P SoM + * + * Copyright 2025 Toradex - https://www.toradex.com/ + * + */ + +#include <config.h> +#include <asm/arch/hardware.h> +#include <asm/arch/k3-common-fdt.h> +#include <asm/gpio.h> +#include <asm/io.h> +#include <dm/uclass.h> +#include <env.h> +#include <fdt_support.h> +#include <init.h> +#include <k3-ddrss.h> +#include <spl.h> +#include <linux/sizes.h> + +#include "../common/tdx-cfg-block.h" + +DECLARE_GLOBAL_DATA_PTR; +static u8 hw_cfg; + +static void read_hw_cfg(void) +{ + struct gpio_desc gpio_hw_cfg; + static const int gpios[] = { 58, 61, 62 }; /* HW_CFG0, HW_CFG1, HW_CFG2 */ + char gpio_name[20]; + int i; + + printf("HW CFG: "); + + for (i = 0; i < ARRAY_SIZE(gpios); i++) { + snprintf(gpio_name, sizeof(gpio_name), "gpio@600000_%d", gpios[i]); + + if (dm_gpio_lookup_name(gpio_name, &gpio_hw_cfg) < 0) { + printf("Lookup error: GPIO %d\n", gpios[i]); + continue; + } + + if (dm_gpio_request(&gpio_hw_cfg, "hw_cfg")) { + printf("GPIO request error: %d\n", gpios[i]); + continue; + } + + if (dm_gpio_get_value(&gpio_hw_cfg) == 1) + hw_cfg |= BIT(i); + + dm_gpio_free(NULL, &gpio_hw_cfg); + } + + printf("0x%02x\n", hw_cfg); +} + +int board_init(void) +{ + return 0; +} + +int dram_init(void) +{ + gd->ram_size = get_ram_size((long *)CFG_SYS_SDRAM_BASE, CFG_SYS_SDRAM_SIZE); + + if (gd->ram_size < SZ_1G) + puts("## WARNING: Less than 1GB RAM detected\n"); + + return 0; +} + +int dram_init_banksize(void) +{ + s32 ret; + + ret = fdtdec_setup_memory_banksize(); + if (ret) + printf("Error setting up memory banksize. %d\n", ret); + + /* Use the detected RAM size, we only support 1 bank right now. */ + gd->bd->bi_dram[0].size = gd->ram_size; + + return ret; +} + +#if IS_ENABLED(CONFIG_SPL_LOAD_FIT) +int board_fit_config_name_match(const char *name) +{ + return 0; +} +#endif + +#if IS_ENABLED(CONFIG_OF_LIBFDT) && IS_ENABLED(CONFIG_OF_BOARD_SETUP) +int ft_board_setup(void *blob, struct bd_info *bd) +{ + return ft_common_board_setup(blob, bd); +} +#endif + +#if IS_ENABLED(CONFIG_OF_BOARD_SETUP_EXTENDED) +void ft_board_setup_ex(void *blob, struct bd_info *bd) +{ + fdt_fixup_thermal_critical_trips_k3(blob, 105); +} +#endif + +static void select_dt_from_module_version(void) +{ + char variant[32]; + char *env_variant = env_get("variant"); + int is_wifi = 0; + + if (IS_ENABLED(CONFIG_TDX_CFG_BLOCK)) { + /* + * If we have a valid config block and it says we are a module with + * Wi-Fi/Bluetooth make sure we use the -wifi device tree. + */ + is_wifi = (tdx_hw_tag.prodid == VERDIN_AM62PQ_2G_WIFI_BT_IT); + } + + if (is_wifi) + strlcpy(&variant[0], "wifi", sizeof(variant)); + else + strlcpy(&variant[0], "nonwifi", sizeof(variant)); + + if (strcmp(variant, env_variant)) { + printf("Setting variant to %s\n", variant); + env_set("variant", variant); + } +} + +int board_late_init(void) +{ + select_dt_from_module_version(); + + return 0; +} + +#define MCU_CTRL_LFXOSC_32K_BYPASS_VAL BIT(4) + +void spl_board_init(void) +{ + u32 val; + + /* + * We use the 32k FOUT from the Epson RX8130CE RTC chip, + * configure LFXOSC accordingly, see AM62P datasheet, + * Table 6-23, LFXOSC Modes of Operation. + */ + val = readl(MCU_CTRL_LFXOSC_CTRL); + val &= ~MCU_CTRL_LFXOSC_32K_DISABLE_VAL; + val |= MCU_CTRL_LFXOSC_32K_BYPASS_VAL; + writel(val, MCU_CTRL_LFXOSC_CTRL); + /* Make sure to mux up to take the SoC 32k from the LFOSC input */ + writel(MCU_CTRL_DEVICE_CLKOUT_LFOSC_SELECT_VAL, + MCU_CTRL_DEVICE_CLKOUT_32K_CTRL); + + read_hw_cfg(); +} diff --git a/board/toradex/verdin-am62p/verdin-am62p.env b/board/toradex/verdin-am62p/verdin-am62p.env new file mode 100644 index 00000000000..f8b7363dcf5 --- /dev/null +++ b/board/toradex/verdin-am62p/verdin-am62p.env @@ -0,0 +1,41 @@ +#define CFG_RAMDISK_ADDR_R 0x90300000 +#define CFG_SCRIPTADDR 0x90280000 + +boot_script_dhcp=boot.scr +boot_targets=mmc1 mmc0 dhcp +console=ttyS2 +fdt_addr_r=0x90200000 +fdt_board=dev +kernel_addr_r=CONFIG_SYS_LOAD_ADDR +kernel_comp_addr_r=0x80200000 +kernel_comp_size=0x08000000 +ramdisk_addr_r=CFG_RAMDISK_ADDR_R +scriptaddr=CFG_SCRIPTADDR + +dfu_alt_info_ram= + tispl.bin ram 0x80080000 0x200000; + u-boot.img ram 0x81000000 0x400000; + loadaddr ram CONFIG_SYS_LOAD_ADDR 0x80000; + scriptaddr ram CFG_SCRIPTADDR 0x80000; + ramdisk_addr_r ram CFG_RAMDISK_ADDR_R 0x8000000 + +update_tiboot3= + askenv confirm Did you load tiboot3.bin (y/N)?; + if test $confirm = y; then + setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt ${blkcnt} / 0x200; + mmc dev 0 1; mmc write ${loadaddr} 0x0 ${blkcnt}; + fi + +update_tispl= + askenv confirm Did you load tispl.bin (y/N)?; + if test $confirm = y; then + setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt ${blkcnt} / 0x200; + mmc dev 0 1; mmc write ${loadaddr} 0x400 ${blkcnt}; + fi + +update_uboot= + askenv confirm Did you load u-boot.img (y/N)?; + if test $confirm = y; then + setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt ${blkcnt} / 0x200; + mmc dev 0 1; mmc write ${loadaddr} 0x1400 ${blkcnt}; + fi diff --git a/board/toradex/verdin-imx8mm/verdin-imx8mm.c b/board/toradex/verdin-imx8mm/verdin-imx8mm.c index 9359e0ac6bf..066e8db678f 100644 --- a/board/toradex/verdin-imx8mm/verdin-imx8mm.c +++ b/board/toradex/verdin-imx8mm/verdin-imx8mm.c @@ -3,7 +3,7 @@ * Copyright 2020-2021 Toradex */ -#include <config.h> +#include <env.h> #include <init.h> #include <asm/arch/clock.h> #include <asm/arch/sys_proto.h> diff --git a/board/xilinx/common/board.c b/board/xilinx/common/board.c index 8ffe7429901..ceb58da6d3c 100644 --- a/board/xilinx/common/board.c +++ b/board/xilinx/common/board.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * (C) Copyright 2014 - 2022, Xilinx, Inc. - * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. + * (C) Copyright 2022 - 2025, Advanced Micro Devices, Inc. * * Michal Simek <michal.simek@amd.com> */ @@ -712,3 +712,34 @@ phys_addr_t board_get_usable_ram_top(phys_size_t total_size) } #endif + +#if IS_ENABLED(CONFIG_BOARD_RNG_SEED) +/* Use hardware rng to seed Linux random. */ +__weak int board_rng_seed(struct abuf *buf) +{ + struct udevice *dev; + ulong len = 64; + u64 *data; + + if (uclass_get_device(UCLASS_RNG, 0, &dev) || !dev) { + printf("No RNG device\n"); + return -ENODEV; + } + + data = malloc(len); + if (!data) { + printf("Out of memory\n"); + return -ENOMEM; + } + + if (dm_rng_read(dev, data, len)) { + printf("Reading RNG failed\n"); + free(data); + return -EIO; + } + + abuf_init_set(buf, data, len); + + return 0; +} +#endif diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c index 735ef3cd1be..789b945d462 100644 --- a/board/xilinx/zynqmp/zynqmp.c +++ b/board/xilinx/zynqmp/zynqmp.c @@ -14,6 +14,7 @@ #include <efi_loader.h> #include <init.h> #include <log.h> +#include <mtd.h> #include <net.h> #include <sata.h> #include <ahci.h> |