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Diffstat (limited to 'doc/board/openpiton/riscv64.rst')
| -rw-r--r-- | doc/board/openpiton/riscv64.rst | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/doc/board/openpiton/riscv64.rst b/doc/board/openpiton/riscv64.rst index 3a97793f070..c379fbf9ffe 100644 --- a/doc/board/openpiton/riscv64.rst +++ b/doc/board/openpiton/riscv64.rst @@ -11,14 +11,14 @@ OpenPiton has been verified in both ASIC and multiple Xilinx FPGA prototypes running full-stack Debian linux. RISC-V Standard Bootflow -------------------------- +------------------------ Currently, OpenPiton implements RISC-V standard bootflow in the following steps mover.S -> u-boot-spl -> opensbi -> u-boot -> Linux This board supports S-mode u-boot as well as M-mode SPL Building OpenPition ---------------------- +------------------- If you'd like to build OpenPiton, please go to OpenPiton github repo (at https://github.com/PrincetonUniversity/openpiton) to build from the latest |