diff options
Diffstat (limited to 'drivers/clk/altera/clk-agilex.c')
| -rw-r--r-- | drivers/clk/altera/clk-agilex.c | 37 |
1 files changed, 33 insertions, 4 deletions
diff --git a/drivers/clk/altera/clk-agilex.c b/drivers/clk/altera/clk-agilex.c index e1ddd02f356..242740a4b00 100644 --- a/drivers/clk/altera/clk-agilex.c +++ b/drivers/clk/altera/clk-agilex.c @@ -1,11 +1,14 @@ // SPDX-License-Identifier: GPL-2.0 /* * Copyright (C) 2019 Intel Corporation <www.intel.com> + * Copyright (C) 2025 Altera Corporation <www.altera.com> */ #include <log.h> +#include <wait_bit.h> #include <asm/global_data.h> #include <asm/io.h> +#include <asm/system.h> #include <clk-uclass.h> #include <dm.h> #include <dm/lists.h> @@ -27,21 +30,33 @@ struct socfpga_clk_plat { */ static void clk_write_bypass_mainpll(struct socfpga_clk_plat *plat, u32 val) { + void __iomem *base = plat->regs; + CM_REG_WRITEL(plat, val, CLKMGR_MAINPLL_BYPASS); - cm_wait_for_fsm(); + + wait_for_bit_le32(base + CLKMGR_STAT, + CLKMGR_STAT_BUSY, false, 20000, false); } static void clk_write_bypass_perpll(struct socfpga_clk_plat *plat, u32 val) { + void __iomem *base = plat->regs; + CM_REG_WRITEL(plat, val, CLKMGR_PERPLL_BYPASS); - cm_wait_for_fsm(); + + wait_for_bit_le32(base + CLKMGR_STAT, + CLKMGR_STAT_BUSY, false, 20000, false); } /* function to write the ctrl register which requires a poll of the busy bit */ static void clk_write_ctrl(struct socfpga_clk_plat *plat, u32 val) { + void __iomem *base = plat->regs; + CM_REG_WRITEL(plat, val, CLKMGR_CTRL); - cm_wait_for_fsm(); + + wait_for_bit_le32(base + CLKMGR_STAT, + CLKMGR_STAT_BUSY, false, 20000, false); } #define MEMBUS_MAINPLL 0 @@ -238,6 +253,7 @@ static void clk_basic_init(struct udevice *dev, { struct socfpga_clk_plat *plat = dev_get_plat(dev); u32 vcocalib; + uintptr_t base_addr = (uintptr_t)plat->regs; if (!cfg) return; @@ -302,7 +318,8 @@ static void clk_basic_init(struct udevice *dev, /* Membus programming for peripll */ membus_pll_configs(plat, MEMBUS_PERPLL); - cm_wait_for_lock(CLKMGR_STAT_ALLPLL_LOCKED_MASK); + wait_for_bit_le32((const void *)(base_addr + CLKMGR_STAT), + CLKMGR_STAT_ALLPLL_LOCKED_MASK, true, 20000, false); /* Configure ping pong counters in altera group */ CM_REG_WRITEL(plat, cfg->alt_emacactr, CLKMGR_ALTR_EMACACTR); @@ -337,6 +354,18 @@ static void clk_basic_init(struct udevice *dev, CM_REG_CLRBITS(plat, CLKMGR_ALTR_EXTCNTRST, CLKMGR_ALT_EXTCNTRST_ALLCNTRST); +#ifdef COUNTER_FREQUENCY_REAL + u32 cntfrq = COUNTER_FREQUENCY_REAL; + u32 counter_freq = 0; + + /* Update with accurate clock frequency */ + if (current_el() == 3) { + asm volatile("msr cntfrq_el0, %0" : : "r" (cntfrq) : "memory"); + asm volatile("mrs %0, cntfrq_el0" : "=r" (counter_freq)); + debug("Counter freq = 0x%x\n", counter_freq); + } +#endif + /* Out of boot mode */ clk_write_ctrl(plat, CM_REG_READL(plat, CLKMGR_CTRL) & ~CLKMGR_CTRL_BOOTMODE); |