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-rw-r--r--drivers/clk/at91/Makefile1
-rw-r--r--drivers/clk/at91/clk-main.c2
-rw-r--r--drivers/clk/at91/clk-sam9x60-pll.c55
-rw-r--r--drivers/clk/at91/pmc.h2
-rw-r--r--drivers/clk/at91/sam9x60.c7
-rw-r--r--drivers/clk/at91/sam9x7.c1085
-rw-r--r--drivers/clk/at91/sama7g5.c6
7 files changed, 1147 insertions, 11 deletions
diff --git a/drivers/clk/at91/Makefile b/drivers/clk/at91/Makefile
index e53dcb4ca7a..6cca861f81c 100644
--- a/drivers/clk/at91/Makefile
+++ b/drivers/clk/at91/Makefile
@@ -12,6 +12,7 @@ obj-$(CONFIG_AT91_SAM9X60_PLL) += clk-sam9x60-pll.o
obj-$(CONFIG_AT91_SAM9X60_USB) += clk-sam9x60-usb.o
obj-$(CONFIG_SAMA7G5) += sama7g5.o
obj-$(CONFIG_SAM9X60) += sam9x60.o
+obj-$(CONFIG_SAM9X7) += sam9x7.o
else
obj-y += compat.o
endif
diff --git a/drivers/clk/at91/clk-main.c b/drivers/clk/at91/clk-main.c
index 09daae97676..a5186f885f0 100644
--- a/drivers/clk/at91/clk-main.c
+++ b/drivers/clk/at91/clk-main.c
@@ -110,7 +110,7 @@ struct clk *at91_clk_main_rc(void __iomem *reg, const char *name,
struct clk *clk;
int ret;
- if (!reg || !name || !parent_name)
+ if (!reg || !name)
return ERR_PTR(-EINVAL);
main_rc = kzalloc(sizeof(*main_rc), GFP_KERNEL);
diff --git a/drivers/clk/at91/clk-sam9x60-pll.c b/drivers/clk/at91/clk-sam9x60-pll.c
index a30035eb8ce..df8172bccac 100644
--- a/drivers/clk/at91/clk-sam9x60-pll.c
+++ b/drivers/clk/at91/clk-sam9x60-pll.c
@@ -22,6 +22,7 @@
#define UBOOT_DM_CLK_AT91_SAM9X60_DIV_PLL "at91-sam9x60-div-pll-clk"
#define UBOOT_DM_CLK_AT91_SAM9X60_FRAC_PLL "at91-sam9x60-frac-pll-clk"
+#define UBOOT_DM_CLK_AT91_SAM9X60_FIXED_DIV_PLL "at91-sam9x60-fixed-div-pll-clk"
#define PMC_PLL_CTRL0_DIV_MSK GENMASK(7, 0)
#define PMC_PLL_CTRL1_MUL_MSK GENMASK(31, 24)
@@ -31,9 +32,6 @@
#define UPLL_DIV 2
#define PLL_MUL_MAX (FIELD_GET(PMC_PLL_CTRL1_MUL_MSK, UINT_MAX) + 1)
-#define FCORE_MIN (600000000)
-#define FCORE_MAX (1200000000)
-
#define PLL_MAX_ID 7
struct sam9x60_pll {
@@ -55,14 +53,15 @@ static inline bool sam9x60_pll_ready(void __iomem *base, int id)
return !!(status & BIT(id));
}
-static long sam9x60_frac_pll_compute_mul_frac(u32 *mul, u32 *frac, ulong rate,
+static long sam9x60_frac_pll_compute_mul_frac(const struct clk_range *core_clk,
+ u32 *mul, u32 *frac, ulong rate,
ulong parent_rate)
{
unsigned long tmprate, remainder;
unsigned long nmul = 0;
unsigned long nfrac = 0;
- if (rate < FCORE_MIN || rate > FCORE_MAX)
+ if (rate < core_clk->min || rate > core_clk->max)
return -ERANGE;
/*
@@ -82,7 +81,7 @@ static long sam9x60_frac_pll_compute_mul_frac(u32 *mul, u32 *frac, ulong rate,
}
/* Check if resulted rate is valid. */
- if (tmprate < FCORE_MIN || tmprate > FCORE_MAX)
+ if (tmprate < core_clk[0].min || tmprate > core_clk[0].max)
return -ERANGE;
*mul = nmul - 1;
@@ -103,8 +102,8 @@ static ulong sam9x60_frac_pll_set_rate(struct clk *clk, ulong rate)
if (!parent_rate)
return 0;
- ret = sam9x60_frac_pll_compute_mul_frac(&nmul, &nfrac, rate,
- parent_rate);
+ ret = sam9x60_frac_pll_compute_mul_frac(pll->characteristics->core_output,
+ &nmul, &nfrac, rate, parent_rate);
if (ret < 0)
return 0;
@@ -142,6 +141,7 @@ static ulong sam9x60_frac_pll_get_rate(struct clk *clk)
void __iomem *base = pll->base;
ulong parent_rate = clk_get_parent_rate(clk);
u32 mul, frac, val;
+ ulong pll_rate;
if (!parent_rate)
return 0;
@@ -151,8 +151,12 @@ static ulong sam9x60_frac_pll_get_rate(struct clk *clk)
pmc_read(base, AT91_PMC_PLL_CTRL1, &val);
mul = (val & pll->layout->mul_mask) >> pll->layout->mul_shift;
frac = (val & pll->layout->frac_mask) >> pll->layout->frac_shift;
+ pll_rate = (parent_rate * (mul + 1) + ((u64)parent_rate * frac >> 22));
+
+ if (pll->layout->div2)
+ pll_rate >>= 1;
- return (parent_rate * (mul + 1) + ((u64)parent_rate * frac >> 22));
+ return pll_rate;
}
static int sam9x60_frac_pll_enable(struct clk *clk)
@@ -163,7 +167,8 @@ static int sam9x60_frac_pll_enable(struct clk *clk)
ulong crate;
crate = sam9x60_frac_pll_get_rate(clk);
- if (crate < FCORE_MIN || crate > FCORE_MAX)
+ if (crate < pll->characteristics->core_output[0].min ||
+ crate > pll->characteristics->core_output[0].max)
return -ERANGE;
pmc_update_bits(base, AT91_PMC_PLL_UPDT, AT91_PMC_PLL_UPDT_ID_MSK,
@@ -360,6 +365,16 @@ static ulong sam9x60_div_pll_get_rate(struct clk *clk)
return parent_rate / (div + 1);
}
+static ulong sam9x60_fixed_div_pll_get_rate(struct clk *clk)
+{
+ ulong parent_rate = clk_get_parent_rate(clk);
+
+ if (!parent_rate)
+ return 0;
+
+ return parent_rate >> 1;
+}
+
static const struct clk_ops sam9x60_div_pll_ops = {
.enable = sam9x60_div_pll_enable,
.disable = sam9x60_div_pll_disable,
@@ -367,6 +382,12 @@ static const struct clk_ops sam9x60_div_pll_ops = {
.get_rate = sam9x60_div_pll_get_rate,
};
+static const struct clk_ops sam9x60_fixed_div_pll_ops = {
+ .enable = sam9x60_div_pll_enable,
+ .disable = sam9x60_div_pll_disable,
+ .get_rate = sam9x60_fixed_div_pll_get_rate,
+};
+
static struct clk *
sam9x60_clk_register_pll(void __iomem *base, const char *type,
const char *name, const char *parent_name, u8 id,
@@ -407,6 +428,13 @@ sam9x60_clk_register_div_pll(void __iomem *base, const char *name,
const struct clk_pll_characteristics *characteristics,
const struct clk_pll_layout *layout, bool critical)
{
+ if (layout->div2) {
+ return sam9x60_clk_register_pll(base,
+ UBOOT_DM_CLK_AT91_SAM9X60_FIXED_DIV_PLL, name, parent_name,
+ id, characteristics, layout,
+ CLK_GET_RATE_NOCACHE | (critical ? CLK_IS_CRITICAL : 0));
+ }
+
return sam9x60_clk_register_pll(base,
UBOOT_DM_CLK_AT91_SAM9X60_DIV_PLL, name, parent_name, id,
characteristics, layout,
@@ -432,6 +460,13 @@ U_BOOT_DRIVER(at91_sam9x60_div_pll_clk) = {
.flags = DM_FLAG_PRE_RELOC,
};
+U_BOOT_DRIVER(at91_sam9x60_fixed_div_pll_clk) = {
+ .name = UBOOT_DM_CLK_AT91_SAM9X60_FIXED_DIV_PLL,
+ .id = UCLASS_CLK,
+ .ops = &sam9x60_fixed_div_pll_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
+
U_BOOT_DRIVER(at91_sam9x60_frac_pll_clk) = {
.name = UBOOT_DM_CLK_AT91_SAM9X60_FRAC_PLL,
.id = UCLASS_CLK,
diff --git a/drivers/clk/at91/pmc.h b/drivers/clk/at91/pmc.h
index ff464522aa0..580c9964ff4 100644
--- a/drivers/clk/at91/pmc.h
+++ b/drivers/clk/at91/pmc.h
@@ -38,6 +38,7 @@ struct clk_pll_characteristics {
struct clk_range input;
int num_output;
const struct clk_range *output;
+ const struct clk_range *core_output;
u16 *icpll;
u8 *out;
u8 upll : 1;
@@ -53,6 +54,7 @@ struct clk_pll_layout {
u8 frac_shift;
u8 div_shift;
u8 endiv_shift;
+ u8 div2;
};
struct clk_programmable_layout {
diff --git a/drivers/clk/at91/sam9x60.c b/drivers/clk/at91/sam9x60.c
index b7d64bdbb3d..e04266a2be2 100644
--- a/drivers/clk/at91/sam9x60.c
+++ b/drivers/clk/at91/sam9x60.c
@@ -112,17 +112,24 @@ static const struct clk_range upll_outputs[] = {
{ .min = 300000000, .max = 500000000 },
};
+/* Fractional PLL core output range. */
+static const struct clk_range core_outputs[] = {
+ { .min = 600000000, .max = 1200000000 },
+};
+
/* PLL characteristics. */
static const struct clk_pll_characteristics apll_characteristics = {
.input = { .min = 12000000, .max = 48000000 },
.num_output = ARRAY_SIZE(plla_outputs),
.output = plla_outputs,
+ .core_output = core_outputs,
};
static const struct clk_pll_characteristics upll_characteristics = {
.input = { .min = 12000000, .max = 48000000 },
.num_output = ARRAY_SIZE(upll_outputs),
.output = upll_outputs,
+ .core_output = core_outputs,
.upll = true,
};
diff --git a/drivers/clk/at91/sam9x7.c b/drivers/clk/at91/sam9x7.c
new file mode 100644
index 00000000000..ad9865feff0
--- /dev/null
+++ b/drivers/clk/at91/sam9x7.c
@@ -0,0 +1,1085 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2025 Microchip Technology Inc. and its subsidiaries
+ *
+ * Author: Varshini Rajendran <varshini.rajendran@microchip.com>
+ *
+ */
+
+#include <clk-uclass.h>
+#include <dm.h>
+#include <dt-bindings/clock/at91.h>
+#include <linux/clk-provider.h>
+
+#include "pmc.h"
+
+/**
+ * Clock identifiers to be used in conjunction with macros like
+ * AT91_TO_CLK_ID()
+ *
+ * @ID_MD_SLCK: TD slow clock identifier
+ * @ID_TD_SLCK: MD slow clock identifier
+ * @ID_MAIN_XTAL: Main Xtal clock identifier
+ * @ID_MAIN_RC: Main RC clock identifier
+ * @ID_MAIN_RC_OSC: Main RC Oscillator clock identifier
+ * @ID_MAIN_OSC: Main Oscillator clock identifier
+ * @ID_MAINCK: MAINCK clock identifier
+ * @ID_PLL_U_FRAC: UPLL fractional clock identifier
+ * @ID_PLL_U_DIV: UPLL divider clock identifier
+ * @ID_PLL_A_FRAC: APLL fractional clock identifier
+ * @ID_PLL_A_DIV: APLL divider clock identifier
+ * @ID_PLL_A_2_DIV: PLLA DIV2 divider clock identifier
+ * @ID_PLL_AUDIO_FRAC: Audio PLL fractional clock identifier
+ * @ID_PLL_AUDIO_DIVPMC: Audio PLL divider clock identifier
+ * @ID_PLL_AUDIO_DIVIO: Audio PLL IO divider clock identifier
+ * @ID_PLL_LVDS_FRAC: LVDS PLL fractional clock identifier
+ * @ID_PLL_LVDS_DIV: LVDS PLL divider clock identifier
+
+ * @ID_MCK_DIV: MCK DIV clock identifier
+
+ * @ID_UTMI: UTMI clock identifier
+
+ * @ID_PROG0: Programmable 0 clock identifier
+ * @ID_PROG1: Programmable 1 clock identifier
+
+ * @ID_PCK0: PCK0 system clock identifier
+ * @ID_PCK1: PCK1 system clock identifier
+ * @ID_DDR: DDR system clock identifier
+ * @ID_QSPI: QSPI system clock identifier
+ *
+ * @ID_MCK_PRES: MCK PRES clock identifier
+ *
+ * Note: if changing the values of this enums please sync them with
+ * device tree
+ */
+enum pmc_clk_ids {
+ ID_MD_SLCK = 0,
+ ID_TD_SLCK = 1,
+ ID_MAIN_XTAL = 2,
+ ID_MAIN_RC = 3,
+ ID_MAIN_RC_OSC = 4,
+ ID_MAIN_OSC = 5,
+ ID_MAINCK = 6,
+
+ ID_PLL_U_FRAC = 7,
+ ID_PLL_U_DIV = 8,
+ ID_PLL_A_FRAC = 9,
+ ID_PLL_A_DIV = 10,
+ ID_PLL_A_2_DIV = 11,
+ ID_PLL_AUDIO_FRAC = 12,
+ ID_PLL_AUDIO_DIVPMC = 13,
+ ID_PLL_AUDIO_DIVIO = 14,
+ ID_PLL_LVDS_FRAC = 15,
+ ID_PLL_LVDS_DIV = 16,
+
+ ID_MCK_DIV = 17,
+
+ ID_UTMI = 18,
+
+ ID_PROG0 = 19,
+ ID_PROG1 = 20,
+
+ ID_PCK0 = 21,
+ ID_PCK1 = 22,
+
+ ID_DDR = 23,
+ ID_QSPI = 24,
+
+ ID_MCK_PRES = 25,
+
+ ID_MAX,
+};
+
+/**
+ * PLL type identifiers
+ * @PLL_TYPE_FRAC: fractional PLL identifier
+ * @PLL_TYPE_DIV: divider PLL identifier
+ */
+enum pll_type {
+ PLL_TYPE_FRAC,
+ PLL_TYPE_DIV,
+};
+
+/* Clock names used as parents for multiple clocks. */
+static const char *clk_names[] = {
+ [ID_MAIN_RC] = "main_rc",
+ [ID_MAIN_RC_OSC] = "main_rc_osc",
+ [ID_MAIN_OSC] = "main_osc",
+ [ID_MAINCK] = "mainck",
+ [ID_PLL_U_DIV] = "upll_divpmcck",
+ [ID_PLL_A_DIV] = "plla_divpmcck",
+ [ID_PLL_A_2_DIV] = "plla_div2pmcck",
+ [ID_PLL_AUDIO_DIVPMC] = "pll_audio_divpmcck",
+ [ID_PLL_AUDIO_DIVIO] = "pll_audio_diviock",
+ [ID_PLL_LVDS_DIV] = "pll_lvds_divpmcck",
+ [ID_MCK_PRES] = "mck_pres",
+ [ID_MCK_DIV] = "mck_div",
+};
+
+/* Fractional PLL core output range. */
+static const struct clk_range plla_core_outputs[] = {
+ { .min = 800000000, .max = 1600000000 },
+};
+
+static const struct clk_range upll_core_outputs[] = {
+ { .min = 600000000, .max = 960000000 },
+};
+
+static const struct clk_range lvdspll_core_outputs[] = {
+ { .min = 600000000, .max = 1200000000 },
+};
+
+static const struct clk_range audiopll_core_outputs[] = {
+ { .min = 600000000, .max = 1200000000 },
+};
+
+static const struct clk_range plladiv2_core_outputs[] = {
+ { .min = 800000000, .max = 1600000000 },
+};
+
+/* Fractional PLL output range. */
+static const struct clk_range plla_outputs[] = {
+ { .min = 400000000, .max = 800000000 },
+};
+
+static const struct clk_range upll_outputs[] = {
+ { .min = 300000000, .max = 480000000 },
+};
+
+static const struct clk_range lvdspll_outputs[] = {
+ { .min = 175000000, .max = 550000000 },
+};
+
+static const struct clk_range audiopll_outputs[] = {
+ { .min = 0, .max = 300000000 },
+};
+
+static const struct clk_range plladiv2_outputs[] = {
+ { .min = 200000000, .max = 400000000 },
+};
+
+/* PLL characteristics. */
+static const struct clk_pll_characteristics plla_characteristics = {
+ .input = { .min = 20000000, .max = 50000000 },
+ .num_output = ARRAY_SIZE(plla_outputs),
+ .output = plla_outputs,
+ .core_output = plla_core_outputs,
+};
+
+static const struct clk_pll_characteristics upll_characteristics = {
+ .input = { .min = 20000000, .max = 50000000 },
+ .num_output = ARRAY_SIZE(upll_outputs),
+ .output = upll_outputs,
+ .core_output = upll_core_outputs,
+ .upll = true,
+};
+
+static const struct clk_pll_characteristics lvdspll_characteristics = {
+ .input = { .min = 20000000, .max = 50000000 },
+ .num_output = ARRAY_SIZE(lvdspll_outputs),
+ .output = lvdspll_outputs,
+ .core_output = lvdspll_core_outputs,
+};
+
+static const struct clk_pll_characteristics audiopll_characteristics = {
+ .input = { .min = 20000000, .max = 50000000 },
+ .num_output = ARRAY_SIZE(audiopll_outputs),
+ .output = audiopll_outputs,
+ .core_output = audiopll_core_outputs,
+};
+
+static const struct clk_pll_characteristics plladiv2_characteristics = {
+ .input = { .min = 20000000, .max = 50000000 },
+ .num_output = ARRAY_SIZE(plladiv2_outputs),
+ .output = plladiv2_outputs,
+ .core_output = plladiv2_core_outputs,
+};
+
+/* Layout for fractional PLLs. */
+static const struct clk_pll_layout pll_layout_frac = {
+ .mul_mask = GENMASK(31, 24),
+ .frac_mask = GENMASK(21, 0),
+ .mul_shift = 24,
+ .frac_shift = 0,
+};
+
+/* Layout for fractional PLL ID PLLA. */
+static const struct clk_pll_layout plla_layout_frac = {
+ .mul_mask = GENMASK(31, 24),
+ .frac_mask = GENMASK(21, 0),
+ .mul_shift = 24,
+ .frac_shift = 0,
+ .div2 = 1,
+};
+
+/* Layout for DIV PLLs. */
+static const struct clk_pll_layout pll_layout_divpmc = {
+ .div_mask = GENMASK(7, 0),
+ .endiv_mask = BIT(29),
+ .div_shift = 0,
+ .endiv_shift = 29,
+};
+
+/* Layout for DIV PLLs. */
+static const struct clk_pll_layout plladiv2_layout_divpmc = {
+ .div_mask = GENMASK(7, 0),
+ .endiv_mask = BIT(29),
+ .div_shift = 0,
+ .endiv_shift = 29,
+ .div2 = 1,
+};
+
+/* Layout for DIVIO dividers. */
+static const struct clk_pll_layout pll_layout_divio = {
+ .div_mask = GENMASK(19, 12),
+ .endiv_mask = BIT(30),
+ .div_shift = 12,
+ .endiv_shift = 30,
+};
+
+/* MCK characteristics. */
+static const struct clk_master_characteristics mck_characteristics = {
+ .output = { .min = 32000000, .max = 266666666 },
+ .divisors = { 1, 2, 4, 3, 5},
+ .have_div3_pres = 1,
+};
+
+/* MCK layout. */
+static const struct clk_master_layout mck_layout = {
+ .mask = 0x373,
+ .pres_shift = 4,
+ .offset = 0x28,
+};
+
+/* Programmable clock layout. */
+static const struct clk_programmable_layout programmable_layout = {
+ .pres_mask = 0xff,
+ .pres_shift = 8,
+ .css_mask = 0x1f,
+ .have_slck_mck = 0,
+ .is_pres_direct = 1,
+};
+
+/* Peripheral clock layout. */
+static const struct clk_pcr_layout sam9x7_pcr_layout = {
+ .offset = 0x88,
+ .cmd = BIT(31),
+ .gckcss_mask = GENMASK(12, 8),
+ .pid_mask = GENMASK(6, 0),
+};
+
+/**
+ * PLL clocks description
+ * @n: clock name
+ * @p: clock parent
+ * @l: clock layout
+ * @t: clock type
+ * @c: pll characteristics
+ * @f: true if clock is fixed and not changeable by driver
+ * @id: clock id corresponding to PLL driver
+ * @cid: clock id corresponding to clock subsystem
+ */
+static const struct {
+ const char *n;
+ const char *p;
+ const struct clk_pll_layout *l;
+ const struct clk_pll_characteristics *c;
+ u8 t;
+ u8 f;
+ u8 id;
+ u8 cid;
+} sam9x7_plls[] = {
+ {
+ .n = "plla_fracck",
+ .p = "mainck",
+ .l = &plla_layout_frac,
+ .c = &plla_characteristics,
+ .t = PLL_TYPE_FRAC,
+ .f = 1,
+ .id = 0,
+ .cid = ID_PLL_A_FRAC,
+ },
+
+ {
+ .n = "plla_divpmcck",
+ .p = "plla_fracck",
+ .l = &pll_layout_divpmc,
+ .c = &plla_characteristics,
+ .t = PLL_TYPE_DIV,
+ .f = 1,
+ .id = 0,
+ .cid = ID_PLL_A_DIV,
+ },
+
+ {
+ .n = "upll_fracck",
+ .p = "main_osc",
+ .l = &pll_layout_frac,
+ .c = &upll_characteristics,
+ .t = PLL_TYPE_FRAC,
+ .f = 1,
+ .id = 1,
+ .cid = ID_PLL_U_FRAC,
+ },
+
+ {
+ .n = "upll_divpmcck",
+ .p = "upll_fracck",
+ .l = &pll_layout_divpmc,
+ .c = &upll_characteristics,
+ .t = PLL_TYPE_DIV,
+ .f = 1,
+ .id = 1,
+ .cid = ID_PLL_U_DIV,
+ },
+
+ {
+ .n = "audiopll_fracck",
+ .p = "main_osc",
+ .l = &pll_layout_frac,
+ .c = &audiopll_characteristics,
+ .t = PLL_TYPE_FRAC,
+ .f = 1,
+ .id = 2,
+ .cid = ID_PLL_AUDIO_FRAC,
+ },
+
+ {
+ .n = "audiopll_divpmcck",
+ .p = "audiopll_fracck",
+ .l = &pll_layout_divpmc,
+ .c = &audiopll_characteristics,
+ .t = PLL_TYPE_DIV,
+ .f = 1,
+ .id = 2,
+ .cid = ID_PLL_AUDIO_DIVPMC,
+ },
+
+ {
+ .n = "audiopll_diviock",
+ .p = "audiopll_fracck",
+ .l = &pll_layout_divio,
+ .c = &audiopll_characteristics,
+ .t = PLL_TYPE_DIV,
+ .f = 1,
+ .id = 2,
+ .cid = ID_PLL_AUDIO_DIVIO,
+ },
+
+ {
+ .n = "lvdspll_fracck",
+ .p = "main_osc",
+ .l = &pll_layout_frac,
+ .c = &lvdspll_characteristics,
+ .t = PLL_TYPE_FRAC,
+ .f = 1,
+ .id = 3,
+ .cid = ID_PLL_LVDS_FRAC,
+ },
+
+ {
+ .n = "lvdspll_divpmcck",
+ .p = "lvdspll_fracck",
+ .l = &pll_layout_divpmc,
+ .c = &lvdspll_characteristics,
+ .t = PLL_TYPE_DIV,
+ .f = 1,
+ .id = 3,
+ .cid = ID_PLL_LVDS_DIV,
+ },
+
+ {
+ .n = "plla_div2pmcck",
+ .p = "plla_fracck",
+ .l = &plladiv2_layout_divpmc,
+ .c = &plladiv2_characteristics,
+ .t = PLL_TYPE_DIV,
+ .f = 1,
+ .id = 4,
+ .cid = ID_PLL_A_2_DIV,
+ },
+
+};
+
+/**
+ * Programmable clock description
+ * @n: clock name
+ * @cid: clock id corresponding to clock subsystem
+ */
+static const struct {
+ const char *n;
+ u8 cid;
+} sam9x7_prog[] = {
+ { .n = "prog0", .cid = ID_PROG0, },
+ { .n = "prog1", .cid = ID_PROG1, },
+};
+
+/* Mux table for programmable clocks. */
+static u32 sam9x7_prog_mux_table[] = { 0, 1, 2, 3, 4, 5, 6, };
+
+/**
+ * System clock description
+ * @n: clock name
+ * @p: parent clock name
+ * @id: clock id corresponding to system clock driver
+ * @cid: clock id corresponding to clock subsystem
+ */
+static const struct {
+ const char *n;
+ const char *p;
+ u8 id;
+ u8 cid;
+} sam9x7_systemck[] = {
+ { .n = "ddrck", .p = "mck_pres", .id = 2, .cid = ID_DDR, },
+ { .n = "pck0", .p = "prog0", .id = 8, .cid = ID_PCK0, },
+ { .n = "pck1", .p = "prog1", .id = 9, .cid = ID_PCK1, },
+};
+
+/**
+ * Peripheral clock description
+ * @n: clock name
+ * @id: clock id
+ */
+static const struct {
+ const char *n;
+ u8 id;
+} sam9x7_periphck[] = {
+ { .n = "pioA_clk", .id = 2, },
+ { .n = "pioB_clk", .id = 3, },
+ { .n = "pioC_clk", .id = 4, },
+ { .n = "flex0_clk", .id = 5, },
+ { .n = "flex1_clk", .id = 6, },
+ { .n = "flex2_clk", .id = 7, },
+ { .n = "flex3_clk", .id = 8, },
+ { .n = "flex6_clk", .id = 9, },
+ { .n = "flex7_clk", .id = 10, },
+ { .n = "flex8_clk", .id = 11, },
+ { .n = "sdmmc0_clk", .id = 12, },
+ { .n = "flex4_clk", .id = 13, },
+ { .n = "flex5_clk", .id = 14, },
+ { .n = "flex9_clk", .id = 15, },
+ { .n = "flex10_clk", .id = 16, },
+ { .n = "tcb0_clk", .id = 17, },
+ { .n = "pwm_clk", .id = 18, },
+ { .n = "adc_clk", .id = 19, },
+ { .n = "dma0_clk", .id = 20, },
+ { .n = "uhphs_clk", .id = 22, },
+ { .n = "udphs_clk", .id = 23, },
+ { .n = "gmac_clk", .id = 24, },
+ { .n = "lcd_clk", .id = 25, },
+ { .n = "sdmmc1_clk", .id = 26, },
+ { .n = "ssc_clk", .id = 28, },
+ { .n = "mcan0_clk", .id = 29, },
+ { .n = "mcan1_clk", .id = 30, },
+ { .n = "flex11_clk", .id = 32, },
+ { .n = "flex12_clk", .id = 33, },
+ { .n = "i2s_clk", .id = 34, },
+ { .n = "qspi_clk", .id = 35, },
+ { .n = "gfx2d_clk", .id = 36, },
+ { .n = "pit64b0_clk", .id = 37, },
+ { .n = "trng_clk", .id = 38, },
+ { .n = "aes_clk", .id = 39, },
+ { .n = "tdes_clk", .id = 40, },
+ { .n = "sha_clk", .id = 41, },
+ { .n = "classd_clk", .id = 42, },
+ { .n = "isi_clk", .id = 43, },
+ { .n = "pioD_clk", .id = 44, },
+ { .n = "tcb1_clk", .id = 45, },
+ { .n = "dbgu_clk", .id = 47, },
+ { .n = "pmecc_clk", .id = 48, },
+ { .n = "mpddr_clk", .id = 49, },
+ { .n = "csi2dc_clk", .id = 52, },
+ { .n = "csi4l_clk", .id = 53, },
+ { .n = "dsi4l_clk", .id = 54, },
+ { .n = "lvdsc_clk", .id = 56, },
+ { .n = "pit64b1_clk", .id = 58, },
+ { .n = "puf_clk", .id = 59, },
+ { .n = "gmactsu_clk", .id = 67, },
+};
+
+/**
+ * Generic clock description
+ * @n: clock name
+ * @ep: extra parents names
+ * @ep_mux_table: extra parents mux table
+ * @ep_clk_mux_table: extra parents clock mux table (for CCF)
+ * @r: clock output range
+ * @ep_count: extra parents count
+ * @id: clock id
+ */
+static const struct {
+ const char *n;
+ const char *ep[8];
+ const char ep_mux_table[8];
+ const char ep_clk_mux_table[8];
+ struct clk_range r;
+ u8 ep_count;
+ u8 id;
+} sam9x7_gck[] = {
+ {
+ .n = "flex0_gclk",
+ .id = 5,
+ .ep = { "plla_div2pmcck", },
+ .ep_mux_table = { 8, },
+ .ep_clk_mux_table = { ID_PLL_A_2_DIV, },
+ .ep_count = 1,
+ },
+
+ {
+ .n = "flex1_gclk",
+ .id = 6,
+ .ep = { "plla_div2pmcck", },
+ .ep_mux_table = { 8, },
+ .ep_clk_mux_table = { ID_PLL_A_2_DIV, },
+ .ep_count = 1,
+ },
+
+ {
+ .n = "flex2_gclk",
+ .id = 7,
+ .ep = { "plla_div2pmcck", },
+ .ep_mux_table = { 8, },
+ .ep_clk_mux_table = { ID_PLL_A_2_DIV, },
+ .ep_count = 1,
+ },
+
+ {
+ .n = "flex3_gclk",
+ .id = 8,
+ .ep = { "plla_div2pmcck", },
+ .ep_mux_table = { 8, },
+ .ep_clk_mux_table = { ID_PLL_A_2_DIV, },
+ .ep_count = 1,
+ },
+
+ {
+ .n = "flex6_gclk",
+ .id = 9,
+ .ep = { "plla_div2pmcck", },
+ .ep_mux_table = { 8, },
+ .ep_clk_mux_table = { ID_PLL_A_2_DIV, },
+ .ep_count = 1,
+ },
+
+ {
+ .n = "flex7_gclk",
+ .id = 10,
+ .ep = { "plla_div2pmcck", },
+ .ep_mux_table = { 8, },
+ .ep_clk_mux_table = { ID_PLL_A_2_DIV, },
+ .ep_count = 1,
+ },
+
+ {
+ .n = "flex8_gclk",
+ .id = 11,
+ .ep = { "plla_div2pmcck", },
+ .ep_mux_table = { 8, },
+ .ep_clk_mux_table = { ID_PLL_A_2_DIV, },
+ .ep_count = 1,
+ },
+
+ {
+ .n = "sdmmc0_gclk",
+ .id = 12,
+ .r = { .max = 105000000 },
+ .ep = { "audiopll_divpmcck", "plla_div2pmcck", },
+ .ep_mux_table = { 6, 8, },
+ .ep_clk_mux_table = { ID_PLL_AUDIO_DIVPMC, ID_PLL_A_2_DIV, },
+ .ep_count = 2,
+ },
+
+ {
+ .n = "flex4_gclk",
+ .id = 13,
+ .ep = { "plla_div2pmcck", },
+ .ep_mux_table = { 8, },
+ .ep_clk_mux_table = { ID_PLL_A_2_DIV, },
+ .ep_count = 1,
+ },
+
+ {
+ .n = "flex5_gclk",
+ .id = 14,
+ .ep = { "plla_div2pmcck", },
+ .ep_mux_table = { 8, },
+ .ep_clk_mux_table = { ID_PLL_A_2_DIV, },
+ .ep_count = 1,
+ },
+
+ {
+ .n = "flex9_gclk",
+ .id = 15,
+ .ep = { "plla_div2pmcck", },
+ .ep_mux_table = { 8, },
+ .ep_clk_mux_table = { ID_PLL_A_2_DIV, },
+ .ep_count = 1,
+ },
+
+ {
+ .n = "flex10_gclk",
+ .id = 16,
+ .ep = { "plla_div2pmcck", },
+ .ep_mux_table = { 8, },
+ .ep_clk_mux_table = { ID_PLL_A_2_DIV, },
+ .ep_count = 1,
+ },
+
+ {
+ .n = "tcb0_gclk",
+ .id = 17,
+ .ep = { "audiopll_divpmcck", "plla_div2pmcck", },
+ .ep_mux_table = { 6, 8, },
+ .ep_clk_mux_table = { ID_PLL_AUDIO_DIVPMC, ID_PLL_A_2_DIV, },
+ .ep_count = 2,
+ },
+
+ {
+ .n = "adc_gclk",
+ .id = 19,
+ .ep = { "upll_divpmcck", "plla_div2pmcck", },
+ .ep_mux_table = { 5, 8, },
+ .ep_clk_mux_table = { ID_PLL_U_DIV, ID_PLL_A_2_DIV, },
+ .ep_count = 2,
+ },
+
+ {
+ .n = "gmac_gclk",
+ .id = 24,
+ .ep = { "audiopll_divpmcck", "plla_div2pmcck", },
+ .ep_mux_table = { 6, 8, },
+ .ep_clk_mux_table = { ID_PLL_AUDIO_DIVPMC, ID_PLL_A_2_DIV, },
+ .ep_count = 2,
+ },
+
+ {
+ .n = "lcd_gclk",
+ .id = 25,
+ .r = { .max = 75000000 },
+ .ep = { "audiopll_divpmcck", "plla_div2pmcck", },
+ .ep_mux_table = { 6, 8, },
+ .ep_clk_mux_table = { ID_PLL_AUDIO_DIVPMC, ID_PLL_A_2_DIV, },
+ .ep_count = 2,
+ },
+
+ {
+ .n = "sdmmc1_gclk",
+ .id = 26,
+ .r = { .max = 105000000 },
+ .ep = { "audiopll_divpmcck", "plla_div2pmcck", },
+ .ep_mux_table = { 6, 8, },
+ .ep_clk_mux_table = { ID_PLL_AUDIO_DIVPMC, ID_PLL_A_2_DIV, },
+ .ep_count = 2,
+ },
+
+ {
+ .n = "mcan0_gclk",
+ .id = 29,
+ .r = { .max = 80000000 },
+ .ep = { "upll_divpmcck", "plla_div2pmcck", },
+ .ep_mux_table = { 5, 8, },
+ .ep_clk_mux_table = { ID_PLL_U_DIV, ID_PLL_A_2_DIV, },
+ .ep_count = 2,
+ },
+
+ {
+ .n = "mcan1_gclk",
+ .id = 30,
+ .r = { .max = 80000000 },
+ .ep = { "upll_divpmcck", "plla_div2pmcck", },
+ .ep_mux_table = { 5, 8, },
+ .ep_clk_mux_table = { ID_PLL_U_DIV, ID_PLL_A_2_DIV, },
+ .ep_count = 2,
+ },
+
+ {
+ .n = "flex11_gclk",
+ .id = 32,
+ .ep = { "plla_div2pmcck", },
+ .ep_mux_table = { 8, },
+ .ep_clk_mux_table = { ID_PLL_A_2_DIV, },
+ .ep_count = 1,
+ },
+
+ {
+ .n = "flex12_gclk",
+ .id = 33,
+ .ep = { "plla_div2pmcck", },
+ .ep_mux_table = { 8, },
+ .ep_clk_mux_table = { ID_PLL_A_2_DIV, },
+ .ep_count = 1,
+ },
+
+ {
+ .n = "i2s_gclk",
+ .id = 34,
+ .r = { .max = 100000000 },
+ .ep = { "audiopll_divpmcck", "plla_div2pmcck", },
+ .ep_mux_table = { 6, 8, },
+ .ep_clk_mux_table = { ID_PLL_AUDIO_DIVPMC, ID_PLL_A_2_DIV, },
+ .ep_count = 2,
+ },
+
+ {
+ .n = "qspi_gclk",
+ .id = 35,
+ .r = { .max = 200000000 },
+ .ep = { "audiopll_divpmcck", "plla_div2pmcck", },
+ .ep_mux_table = { 6, 8, },
+ .ep_clk_mux_table = { ID_PLL_AUDIO_DIVPMC, ID_PLL_A_2_DIV, },
+ .ep_count = 2,
+ },
+
+ {
+ .n = "pit64b0_gclk",
+ .id = 37,
+ .ep = { "plla_div2pmcck", },
+ .ep_mux_table = { 8, },
+ .ep_clk_mux_table = { ID_PLL_A_2_DIV, },
+ .ep_count = 1,
+ },
+
+ {
+ .n = "classd_gclk",
+ .id = 42,
+ .r = { .max = 100000000 },
+ .ep = { "audiopll_divpmcck", "plla_div2pmcck", },
+ .ep_mux_table = { 6, 8, },
+ .ep_clk_mux_table = { ID_PLL_AUDIO_DIVPMC, ID_PLL_A_2_DIV, },
+ .ep_count = 2,
+ },
+
+ {
+ .n = "tcb1_gclk",
+ .id = 45,
+ .ep = { "audiopll_divpmcck", "plla_div2pmcck", },
+ .ep_mux_table = { 6, 8, },
+ .ep_clk_mux_table = { ID_PLL_AUDIO_DIVPMC, ID_PLL_A_2_DIV, },
+ .ep_count = 2,
+ },
+
+ {
+ .n = "dbgu_gclk",
+ .id = 47,
+ .ep = { "plla_div2pmcck", },
+ .ep_mux_table = { 8, },
+ .ep_clk_mux_table = { ID_PLL_A_2_DIV, },
+ .ep_count = 1,
+ },
+
+ {
+ .n = "mipiphy_gclk",
+ .id = 55,
+ .r = { .max = 27000000 },
+ .ep = { "plla_div2pmcck", },
+ .ep_mux_table = { 8, },
+ .ep_clk_mux_table = { ID_PLL_A_2_DIV, },
+ .ep_count = 1,
+ },
+
+ {
+ .n = "pit64b1_gclk",
+ .id = 58,
+ .ep = { "plla_div2pmcck", },
+ .ep_mux_table = { 8, },
+ .ep_clk_mux_table = { ID_PLL_A_2_DIV, },
+ .ep_count = 1,
+ },
+
+ {
+ .n = "gmac_tsu_gclk",
+ .id = 67,
+ .ep = { "audiopll_divpmcck", "plla_div2pmcck", },
+ .ep_mux_table = { 6, 8, },
+ .ep_clk_mux_table = { ID_PLL_AUDIO_DIVPMC, ID_PLL_A_2_DIV, },
+ .ep_count = 2,
+ },
+
+};
+
+#define prepare_mux_table(_allocs, _index, _dst, _src, _num, _label) \
+ do { \
+ int _i; \
+ (_dst) = kzalloc(sizeof(*(_dst)) * (_num), GFP_KERNEL); \
+ if (!(_dst)) { \
+ ret = -ENOMEM; \
+ goto _label; \
+ } \
+ (_allocs)[(_index)++] = (_dst); \
+ for (_i = 0; _i < (_num); _i++) \
+ (_dst)[_i] = (_src)[_i]; \
+ } while (0)
+
+static int sam9x7_clk_probe(struct udevice *dev)
+{
+ void __iomem *base = (void *)devfdt_get_addr_ptr(dev);
+ unsigned int *clkmuxallocs[64], *muxallocs[64];
+ const char *p[10];
+ unsigned int cm[10], m[10], *tmpclkmux, *tmpmux;
+ struct clk clk, *c;
+ int ret, muxallocindex = 0, clkmuxallocindex = 0, i, j;
+ static const struct clk_range r = { 0, 0 };
+
+ if (!base)
+ return -EINVAL;
+
+ memset(muxallocs, 0, ARRAY_SIZE(muxallocs));
+ memset(clkmuxallocs, 0, ARRAY_SIZE(clkmuxallocs));
+
+ ret = clk_get_by_index(dev, 0, &clk);
+ if (ret)
+ return ret;
+
+ ret = clk_get_by_id(clk.id, &c);
+ if (ret)
+ return ret;
+
+ clk_names[ID_TD_SLCK] = kmemdup(clk_hw_get_name(c),
+ strlen(clk_hw_get_name(c)) + 1,
+ GFP_KERNEL);
+ if (!clk_names[ID_TD_SLCK])
+ return -ENOMEM;
+
+ ret = clk_get_by_index(dev, 1, &clk);
+ if (ret)
+ return ret;
+
+ ret = clk_get_by_id(clk.id, &c);
+ if (ret)
+ return ret;
+
+ clk_names[ID_MD_SLCK] = kmemdup(clk_hw_get_name(c),
+ strlen(clk_hw_get_name(c)) + 1,
+ GFP_KERNEL);
+ if (!clk_names[ID_MD_SLCK])
+ return -ENOMEM;
+
+ ret = clk_get_by_index(dev, 2, &clk);
+ if (ret)
+ return ret;
+
+ clk_names[ID_MAIN_XTAL] = kmemdup(clk_hw_get_name(&clk),
+ strlen(clk_hw_get_name(&clk)) + 1,
+ GFP_KERNEL);
+ if (!clk_names[ID_MAIN_XTAL])
+ return -ENOMEM;
+
+ /* Register main rc oscillator. */
+ c = at91_clk_main_rc(base, clk_names[ID_MAIN_RC_OSC],
+ NULL);
+ if (IS_ERR(c)) {
+ ret = PTR_ERR(c);
+ goto fail;
+ }
+ clk_dm(AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MAIN_RC_OSC), c);
+
+ /* Register main oscillator. */
+ c = at91_clk_main_osc(base, clk_names[ID_MAIN_OSC],
+ clk_names[ID_MAIN_XTAL], false);
+ if (IS_ERR(c)) {
+ ret = PTR_ERR(c);
+ goto fail;
+ }
+ clk_dm(AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MAIN_OSC), c);
+
+ /* Register mainck. */
+ p[0] = clk_names[ID_MAIN_RC_OSC];
+ p[1] = clk_names[ID_MAIN_OSC];
+ cm[0] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MAIN_RC_OSC);
+ cm[1] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MAIN_OSC);
+ prepare_mux_table(clkmuxallocs, clkmuxallocindex, tmpclkmux, cm, 2,
+ fail);
+ c = at91_clk_sam9x5_main(base, clk_names[ID_MAINCK], p,
+ 2, tmpclkmux, PMC_TYPE_CORE);
+ if (IS_ERR(c)) {
+ ret = PTR_ERR(c);
+ goto fail;
+ }
+ clk_dm(AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MAINCK), c);
+
+ /* Register PLL fracs clocks. */
+ for (i = 0; i < ARRAY_SIZE(sam9x7_plls); i++) {
+ if (sam9x7_plls[i].t != PLL_TYPE_FRAC)
+ continue;
+
+ c = sam9x60_clk_register_frac_pll(base, sam9x7_plls[i].n,
+ sam9x7_plls[i].p,
+ sam9x7_plls[i].id,
+ sam9x7_plls[i].c,
+ sam9x7_plls[i].l,
+ sam9x7_plls[i].f);
+ if (IS_ERR(c)) {
+ ret = PTR_ERR(c);
+ goto fail;
+ }
+ clk_dm(AT91_TO_CLK_ID(PMC_TYPE_CORE, sam9x7_plls[i].cid), c);
+ }
+
+ /* Register PLL div clocks. */
+ for (i = 0; i < ARRAY_SIZE(sam9x7_plls); i++) {
+ if (sam9x7_plls[i].t != PLL_TYPE_DIV)
+ continue;
+
+ c = sam9x60_clk_register_div_pll(base, sam9x7_plls[i].n,
+ sam9x7_plls[i].p,
+ sam9x7_plls[i].id,
+ sam9x7_plls[i].c,
+ sam9x7_plls[i].l,
+ sam9x7_plls[i].f);
+ if (IS_ERR(c)) {
+ ret = PTR_ERR(c);
+ goto fail;
+ }
+ clk_dm(AT91_TO_CLK_ID(PMC_TYPE_CORE, sam9x7_plls[i].cid), c);
+ }
+
+ /* Register MCK pres clock. */
+ p[0] = clk_names[ID_MD_SLCK];
+ p[1] = clk_names[ID_MAINCK];
+ p[2] = clk_names[ID_PLL_A_DIV];
+ p[3] = clk_names[ID_PLL_U_DIV];
+ cm[0] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MD_SLCK);
+ cm[1] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MAINCK);
+ cm[2] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_PLL_A_DIV);
+ cm[3] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_PLL_U_DIV);
+ prepare_mux_table(clkmuxallocs, clkmuxallocindex, tmpclkmux, cm, 4,
+ fail);
+ c = at91_clk_register_master_pres(base, clk_names[ID_MCK_PRES], p, 4,
+ &mck_layout, &mck_characteristics,
+ tmpclkmux);
+ if (IS_ERR(c)) {
+ ret = PTR_ERR(c);
+ goto fail;
+ }
+ clk_dm(AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MCK_PRES), c);
+
+ /* Register MCK div clock. */
+ c = at91_clk_register_master_div(base, clk_names[ID_MCK_DIV],
+ clk_names[ID_MCK_PRES],
+ &mck_layout, &mck_characteristics);
+ if (IS_ERR(c)) {
+ ret = PTR_ERR(c);
+ goto fail;
+ }
+ clk_dm(AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MCK_DIV), c);
+
+ /* Register programmable clocks. */
+ p[0] = clk_names[ID_MD_SLCK];
+ p[1] = clk_names[ID_TD_SLCK];
+ p[2] = clk_names[ID_MAINCK];
+ p[3] = clk_names[ID_MCK_DIV];
+ p[4] = clk_names[ID_PLL_A_DIV];
+ p[5] = clk_names[ID_PLL_U_DIV];
+ p[6] = clk_names[ID_PLL_AUDIO_DIVPMC];
+ cm[0] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MD_SLCK);
+ cm[1] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_TD_SLCK);
+ cm[2] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MAINCK);
+ cm[3] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MCK_DIV);
+ cm[4] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_PLL_A_DIV);
+ cm[5] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_PLL_U_DIV);
+ cm[6] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_PLL_AUDIO_DIVPMC);
+ for (i = 0; i < ARRAY_SIZE(sam9x7_prog); i++) {
+ prepare_mux_table(clkmuxallocs, clkmuxallocindex, tmpclkmux, cm,
+ 7, fail);
+
+ c = at91_clk_register_programmable(base, sam9x7_prog[i].n, p,
+ 7, i, &programmable_layout,
+ tmpclkmux,
+ sam9x7_prog_mux_table);
+ if (IS_ERR(c)) {
+ ret = PTR_ERR(c);
+ goto fail;
+ }
+ clk_dm(AT91_TO_CLK_ID(PMC_TYPE_CORE, sam9x7_prog[i].cid), c);
+ }
+
+ /* System clocks. */
+ for (i = 0; i < ARRAY_SIZE(sam9x7_systemck); i++) {
+ c = at91_clk_register_system(base, sam9x7_systemck[i].n,
+ sam9x7_systemck[i].p,
+ sam9x7_systemck[i].id);
+ if (IS_ERR(c)) {
+ ret = PTR_ERR(c);
+ goto fail;
+ }
+ clk_dm(AT91_TO_CLK_ID(PMC_TYPE_SYSTEM, sam9x7_systemck[i].cid),
+ c);
+ }
+
+ /* Peripheral clocks. */
+ for (i = 0; i < ARRAY_SIZE(sam9x7_periphck); i++) {
+ c = at91_clk_register_sam9x5_peripheral(base, &sam9x7_pcr_layout,
+ sam9x7_periphck[i].n,
+ clk_names[ID_MCK_DIV],
+ sam9x7_periphck[i].id,
+ &r);
+ if (IS_ERR(c)) {
+ ret = PTR_ERR(c);
+ goto fail;
+ }
+ clk_dm(AT91_TO_CLK_ID(PMC_TYPE_PERIPHERAL,
+ sam9x7_periphck[i].id), c);
+ }
+
+ /* Generic clocks. */
+ p[0] = clk_names[ID_MD_SLCK];
+ p[1] = clk_names[ID_TD_SLCK];
+ p[2] = clk_names[ID_MAINCK];
+ p[3] = clk_names[ID_MCK_DIV];
+ m[0] = 0;
+ m[1] = 1;
+ m[2] = 2;
+ m[3] = 3;
+ cm[0] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MD_SLCK);
+ cm[1] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_TD_SLCK);
+ cm[2] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MAINCK);
+ cm[3] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MCK_DIV);
+ for (i = 0; i < ARRAY_SIZE(sam9x7_gck); i++) {
+ for (j = 0; j < sam9x7_gck[i].ep_count; j++) {
+ p[4 + j] = sam9x7_gck[i].ep[j];
+ m[4 + j] = sam9x7_gck[i].ep_mux_table[j];
+ cm[4 + j] = AT91_TO_CLK_ID(PMC_TYPE_CORE,
+ sam9x7_gck[i].ep_clk_mux_table[j]);
+ }
+ prepare_mux_table(clkmuxallocs, clkmuxallocindex, tmpclkmux, cm,
+ 4 + sam9x7_gck[i].ep_count, fail);
+ prepare_mux_table(muxallocs, muxallocindex, tmpmux, m,
+ 4 + sam9x7_gck[i].ep_count, fail);
+
+ c = at91_clk_register_generic(base, &sam9x7_pcr_layout,
+ sam9x7_gck[i].n, p, tmpclkmux,
+ tmpmux, 4 + sam9x7_gck[i].ep_count,
+ sam9x7_gck[i].id,
+ &sam9x7_gck[i].r);
+ if (IS_ERR(c)) {
+ ret = PTR_ERR(c);
+ goto fail;
+ }
+ clk_dm(AT91_TO_CLK_ID(PMC_TYPE_GCK, sam9x7_gck[i].id), c);
+ }
+
+ return 0;
+
+fail:
+ for (i = 0; i < ARRAY_SIZE(muxallocs); i++)
+ kfree(muxallocs[i]);
+
+ for (i = 0; i < ARRAY_SIZE(clkmuxallocs); i++)
+ kfree(clkmuxallocs[i]);
+
+ return ret;
+}
+
+static const struct udevice_id sam9x7_clk_ids[] = {
+ { .compatible = "microchip,sam9x7-pmc" },
+ { /* Sentinel. */ },
+};
+
+U_BOOT_DRIVER(at91_sam9x7_pmc) = {
+ .name = "at91-sam9x7-pmc",
+ .id = UCLASS_CLK,
+ .of_match = sam9x7_clk_ids,
+ .ops = &at91_clk_ops,
+ .probe = sam9x7_clk_probe,
+ .flags = DM_FLAG_PRE_RELOC,
+};
diff --git a/drivers/clk/at91/sama7g5.c b/drivers/clk/at91/sama7g5.c
index 63b2c647467..c0e27828b1a 100644
--- a/drivers/clk/at91/sama7g5.c
+++ b/drivers/clk/at91/sama7g5.c
@@ -158,11 +158,17 @@ static const struct clk_range pll_outputs[] = {
{ .min = 2343750, .max = 1200000000 },
};
+/* Fractional PLL core output range. */
+static const struct clk_range core_outputs[] = {
+ { .min = 600000000, .max = 1200000000 },
+};
+
/* PLL characteristics. */
static const struct clk_pll_characteristics pll_characteristics = {
.input = { .min = 12000000, .max = 50000000 },
.num_output = ARRAY_SIZE(pll_outputs),
.output = pll_outputs,
+ .core_output = core_outputs,
};
/* Layout for fractional PLLs. */
generated by cgit v1.2.3 (git 2.0.4) at 2025-07-16 15:44:40 +0000