diff options
Diffstat (limited to 'drivers/clk/clk_versal.c')
| -rw-r--r-- | drivers/clk/clk_versal.c | 55 |
1 files changed, 30 insertions, 25 deletions
diff --git a/drivers/clk/clk_versal.c b/drivers/clk/clk_versal.c index cb98f34b5ec..c62a747036d 100644 --- a/drivers/clk/clk_versal.c +++ b/drivers/clk/clk_versal.c @@ -121,25 +121,19 @@ static unsigned int clock_max_idx __section(".data"); #define PM_QUERY_DATA 35 -static int versal_pm_query(struct versal_pm_query_data qdata, u32 *ret_payload) -{ - struct pt_regs regs; - - regs.regs[0] = PM_SIP_SVC | PM_QUERY_DATA; - regs.regs[1] = ((u64)qdata.arg1 << 32) | qdata.qid; - regs.regs[2] = ((u64)qdata.arg3 << 32) | qdata.arg2; +typedef int (*versal_pm_query_t)(struct versal_pm_query_data qdata, + u32 *ret_payload); +static versal_pm_query_t __data versal_pm_query; - smc_call(®s); +static int versal_pm_query_legacy(struct versal_pm_query_data qdata, + u32 *ret_payload) +{ + int ret; - if (ret_payload) { - ret_payload[0] = (u32)regs.regs[0]; - ret_payload[1] = upper_32_bits(regs.regs[0]); - ret_payload[2] = (u32)regs.regs[1]; - ret_payload[3] = upper_32_bits(regs.regs[1]); - ret_payload[4] = (u32)regs.regs[2]; - } + ret = smc_call_handler(PM_QUERY_DATA, qdata.qid, qdata.arg1, qdata.arg2, + qdata.arg3, 0, 0, ret_payload); - return qdata.qid == PM_QID_CLOCK_GET_NAME ? 0 : regs.regs[0]; + return qdata.qid == PM_QID_CLOCK_GET_NAME ? 0 : ret; } static inline int versal_is_valid_clock(u32 clk_id) @@ -356,7 +350,8 @@ static u32 versal_clock_get_div(u32 clk_id) u32 ret_payload[PAYLOAD_ARG_CNT]; u32 div; - xilinx_pm_request(PM_CLOCK_GETDIVIDER, clk_id, 0, 0, 0, ret_payload); + xilinx_pm_request(PM_CLOCK_GETDIVIDER, clk_id, 0, 0, 0, 0, 0, + ret_payload); div = ret_payload[1]; return div; @@ -366,7 +361,8 @@ static u32 versal_clock_set_div(u32 clk_id, u32 div) { u32 ret_payload[PAYLOAD_ARG_CNT]; - xilinx_pm_request(PM_CLOCK_SETDIVIDER, clk_id, div, 0, 0, ret_payload); + xilinx_pm_request(PM_CLOCK_SETDIVIDER, clk_id, div, 0, 0, 0, 0, + ret_payload); return div; } @@ -424,7 +420,7 @@ static u32 versal_clock_get_parentid(u32 clk_id) if (versal_clock_mux(clk_id)) { xilinx_pm_request(PM_CLOCK_GETPARENT, clk_id, 0, 0, 0, - ret_payload); + 0, 0, ret_payload); parent_id = ret_payload[1]; } @@ -442,7 +438,8 @@ static u64 versal_clock_get_pll_rate(u32 clk_id) u32 parent_rate, parent_id, parent_ref_clk_id; u32 id = clk_id & 0xFFF; - xilinx_pm_request(PM_CLOCK_GETSTATE, clk_id, 0, 0, 0, ret_payload); + xilinx_pm_request(PM_CLOCK_GETSTATE, clk_id, 0, 0, 0, 0, 0, + ret_payload); res = ret_payload[1]; if (!res) { printf("0%x PLL not enabled\n", clk_id); @@ -453,9 +450,11 @@ static u64 versal_clock_get_pll_rate(u32 clk_id) parent_ref_clk_id = versal_clock_get_parentid(parent_id); parent_rate = versal_clock_get_ref_rate(parent_ref_clk_id); - xilinx_pm_request(PM_CLOCK_GETDIVIDER, clk_id, 0, 0, 0, ret_payload); + xilinx_pm_request(PM_CLOCK_GETDIVIDER, clk_id, 0, 0, 0, 0, 0, + ret_payload); fbdiv = ret_payload[1]; - xilinx_pm_request(PM_CLOCK_PLL_GETPARAM, clk_id, 2, 0, 0, ret_payload); + xilinx_pm_request(PM_CLOCK_PLL_GETPARAM, clk_id, 2, 0, 0, 0, 0, + ret_payload); frac = ret_payload[1]; freq = (fbdiv * parent_rate) >> (1 << frac); @@ -679,6 +678,10 @@ static int versal_clk_probe(struct udevice *dev) debug("%s\n", __func__); + versal_pm_query = (versal_pm_query_t)dev_get_driver_data(dev); + if (!versal_pm_query) + return -EINVAL; + ret = versal_clock_get_freq_by_name("pl_alt_ref", dev, &pl_alt_ref_clk); if (ret == -ENODATA) { @@ -767,8 +770,10 @@ static int versal_clk_enable(struct clk *clk) clk_id = priv->clk[clk->id].clk_id; - if (versal_clock_gate(clk_id)) - return xilinx_pm_request(PM_CLOCK_ENABLE, clk_id, 0, 0, 0, NULL); + if (versal_clock_gate(clk_id)) { + return xilinx_pm_request(PM_CLOCK_ENABLE, clk_id, 0, 0, 0, + 0, 0, NULL); + } return 0; } @@ -783,7 +788,7 @@ static struct clk_ops versal_clk_ops = { }; static const struct udevice_id versal_clk_ids[] = { - { .compatible = "xlnx,versal-clk" }, + { .compatible = "xlnx,versal-clk", .data = (ulong)versal_pm_query_legacy }, { } }; |