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path: root/drivers/clk/stm32/clk-stm32h7.c
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Diffstat (limited to 'drivers/clk/stm32/clk-stm32h7.c')
-rw-r--r--drivers/clk/stm32/clk-stm32h7.c5
1 files changed, 5 insertions, 0 deletions
diff --git a/drivers/clk/stm32/clk-stm32h7.c b/drivers/clk/stm32/clk-stm32h7.c
index 6acf2ff0a8f..aa3be414a29 100644
--- a/drivers/clk/stm32/clk-stm32h7.c
+++ b/drivers/clk/stm32/clk-stm32h7.c
@@ -114,6 +114,7 @@
#define QSPISRC_PER_CK 3
#define PWR_CR3 0x0c
+#define PWR_CR3_LDOEN BIT(1)
#define PWR_CR3_SCUEN BIT(2)
#define PWR_D3CR 0x18
#define PWR_D3CR_VOS_MASK GENMASK(15, 14)
@@ -375,7 +376,11 @@ int configure_clocks(struct udevice *dev)
clrsetbits_le32(pwr_base + PWR_D3CR, PWR_D3CR_VOS_MASK,
VOS_SCALE_1 << PWR_D3CR_VOS_SHIFT);
/* Lock supply configuration update */
+#if IS_ENABLED(CONFIG_TARGET_STM32H747_DISCO)
+ clrbits_le32(pwr_base + PWR_CR3, PWR_CR3_LDOEN);
+#else
clrbits_le32(pwr_base + PWR_CR3, PWR_CR3_SCUEN);
+#endif
while (!(readl(pwr_base + PWR_D3CR) & PWR_D3CR_VOSREADY))
;