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-rw-r--r--drivers/clk/altera/clk-agilex.c130
-rw-r--r--drivers/clk/altera/clk-agilex.h20
-rw-r--r--drivers/clk/clk-cdce9xx.c3
-rw-r--r--drivers/clk/clk-uclass.c2
-rw-r--r--drivers/clk/clk_scmi.c22
-rw-r--r--drivers/clk/clk_zynqmp.c2
-rw-r--r--drivers/clk/imx/Kconfig9
-rw-r--r--drivers/clk/imx/Makefile1
-rw-r--r--drivers/clk/imx/clk-imx6q.c6
-rw-r--r--drivers/clk/imx/clk-imx95-blkctrl.c183
-rw-r--r--drivers/clk/meson/g12a.c2
-rw-r--r--drivers/clk/stm32/clk-stm32mp25.c2
-rw-r--r--drivers/clk/thead/clk-th1520-ap.c3
13 files changed, 364 insertions, 21 deletions
diff --git a/drivers/clk/altera/clk-agilex.c b/drivers/clk/altera/clk-agilex.c
index 242740a4b00..fdbf834bb2f 100644
--- a/drivers/clk/altera/clk-agilex.c
+++ b/drivers/clk/altera/clk-agilex.c
@@ -14,6 +14,7 @@
#include <dm/lists.h>
#include <dm/util.h>
#include <dt-bindings/clock/agilex-clock.h>
+#include <linux/bitfield.h>
#include <linux/bitops.h>
#include <asm/arch/clock_manager.h>
@@ -22,6 +23,8 @@ DECLARE_GLOBAL_DATA_PTR;
struct socfpga_clk_plat {
void __iomem *regs;
+ int pllgrp;
+ int bitmask;
};
/*
@@ -544,14 +547,11 @@ static u32 clk_get_emac_clk_hz(struct socfpga_clk_plat *plat, u32 emac_id)
/* Get EMAC clock source */
ctl = CM_REG_READL(plat, CLKMGR_PERPLL_EMACCTL);
if (emac_id == AGILEX_EMAC0_CLK)
- ctl = (ctl >> CLKMGR_PERPLLGRP_EMACCTL_EMAC0SELB_OFFSET) &
- CLKMGR_PERPLLGRP_EMACCTL_EMAC0SELB_MASK;
+ ctl = FIELD_GET(CLKMGR_PERPLLGRP_EMACCTL_EMAC0SELB_MASK, ctl);
else if (emac_id == AGILEX_EMAC1_CLK)
- ctl = (ctl >> CLKMGR_PERPLLGRP_EMACCTL_EMAC1SELB_OFFSET) &
- CLKMGR_PERPLLGRP_EMACCTL_EMAC1SELB_MASK;
+ ctl = FIELD_GET(CLKMGR_PERPLLGRP_EMACCTL_EMAC1SELB_MASK, ctl);
else if (emac_id == AGILEX_EMAC2_CLK)
- ctl = (ctl >> CLKMGR_PERPLLGRP_EMACCTL_EMAC2SELB_OFFSET) &
- CLKMGR_PERPLLGRP_EMACCTL_EMAC2SELB_MASK;
+ ctl = FIELD_GET(CLKMGR_PERPLLGRP_EMACCTL_EMAC2SELB_MASK, ctl);
else
return 0;
@@ -643,8 +643,125 @@ static ulong socfpga_clk_get_rate(struct clk *clk)
}
}
+static int bitmask_from_clk_id(struct clk *clk)
+{
+ struct socfpga_clk_plat *plat = dev_get_plat(clk->dev);
+
+ switch (clk->id) {
+ case AGILEX_MPU_CLK:
+ plat->pllgrp = CLKMGR_MAINPLL_EN;
+ plat->bitmask = CLKMGR_MAINPLLGRP_EN_MPUCLK_MASK;
+ break;
+ case AGILEX_L4_MAIN_CLK:
+ plat->pllgrp = CLKMGR_MAINPLL_EN;
+ plat->bitmask = CLKMGR_MAINPLLGRP_EN_L4MAINCLK_MASK;
+ break;
+ case AGILEX_L4_MP_CLK:
+ plat->pllgrp = CLKMGR_MAINPLL_EN;
+ plat->bitmask = CLKMGR_MAINPLLGRP_EN_L4MPCLK_MASK;
+ break;
+ case AGILEX_L4_SP_CLK:
+ plat->pllgrp = CLKMGR_MAINPLL_EN;
+ plat->bitmask = CLKMGR_MAINPLLGRP_EN_L4SPCLK_MASK;
+ break;
+ case AGILEX_CS_AT_CLK:
+ plat->pllgrp = CLKMGR_MAINPLL_EN;
+ plat->bitmask = CLKMGR_MAINPLLGRP_EN_CSCLK_MASK;
+ break;
+ case AGILEX_CS_TRACE_CLK:
+ plat->pllgrp = CLKMGR_MAINPLL_EN;
+ plat->bitmask = CLKMGR_MAINPLLGRP_EN_CSCLK_MASK;
+ break;
+ case AGILEX_CS_PDBG_CLK:
+ plat->pllgrp = CLKMGR_MAINPLL_EN;
+ plat->bitmask = CLKMGR_MAINPLLGRP_EN_CSCLK_MASK;
+ break;
+ case AGILEX_CS_TIMER_CLK:
+ plat->pllgrp = CLKMGR_MAINPLL_EN;
+ plat->bitmask = CLKMGR_MAINPLLGRP_EN_CSTIMERCLK_MASK;
+ break;
+ case AGILEX_S2F_USER0_CLK:
+ plat->pllgrp = CLKMGR_MAINPLL_EN;
+ plat->bitmask = CLKMGR_MAINPLLGRP_EN_S2FUSER0CLK_MASK;
+ break;
+ case AGILEX_EMAC0_CLK:
+ plat->pllgrp = CLKMGR_PERPLL_EN;
+ plat->bitmask = CLKMGR_PERPLLGRP_EN_EMAC0CLK_MASK;
+ break;
+ case AGILEX_EMAC1_CLK:
+ plat->pllgrp = CLKMGR_PERPLL_EN;
+ plat->bitmask = CLKMGR_PERPLLGRP_EN_EMAC1CLK_MASK;
+ break;
+ case AGILEX_EMAC2_CLK:
+ plat->pllgrp = CLKMGR_PERPLL_EN;
+ plat->bitmask = CLKMGR_PERPLLGRP_EN_EMAC2CLK_MASK;
+ break;
+ case AGILEX_EMAC_PTP_CLK:
+ plat->pllgrp = CLKMGR_PERPLL_EN;
+ plat->bitmask = CLKMGR_PERPLLGRP_EN_EMACPTPCLK_MASK;
+ break;
+ case AGILEX_GPIO_DB_CLK:
+ plat->pllgrp = CLKMGR_PERPLL_EN;
+ plat->bitmask = CLKMGR_PERPLLGRP_EN_GPIODBCLK_MASK;
+ break;
+ case AGILEX_SDMMC_CLK:
+ plat->pllgrp = CLKMGR_PERPLL_EN;
+ plat->bitmask = CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK;
+ break;
+ case AGILEX_S2F_USER1_CLK:
+ plat->pllgrp = CLKMGR_PERPLL_EN;
+ plat->bitmask = CLKMGR_PERPLLGRP_EN_S2FUSER1CLK_MASK;
+ break;
+ case AGILEX_PSI_REF_CLK:
+ plat->pllgrp = CLKMGR_PERPLL_EN;
+ plat->bitmask = CLKMGR_PERPLLGRP_EN_PSIREFCLK_MASK;
+ break;
+ case AGILEX_USB_CLK:
+ plat->pllgrp = CLKMGR_PERPLL_EN;
+ plat->bitmask = CLKMGR_PERPLLGRP_EN_USBCLK_MASK;
+ break;
+ case AGILEX_SPI_M_CLK:
+ plat->pllgrp = CLKMGR_PERPLL_EN;
+ plat->bitmask = CLKMGR_PERPLLGRP_EN_SPIMCLK_MASK;
+ break;
+ case AGILEX_NAND_CLK:
+ plat->pllgrp = CLKMGR_PERPLL_EN;
+ plat->bitmask = CLKMGR_PERPLLGRP_EN_NANDCLK_MASK;
+ break;
+ default:
+ return -ENXIO;
+ }
+
+ return 0;
+}
+
static int socfpga_clk_enable(struct clk *clk)
{
+ struct socfpga_clk_plat *plat = dev_get_plat(clk->dev);
+ uintptr_t base_addr = (uintptr_t)plat->regs;
+ int ret;
+
+ ret = bitmask_from_clk_id(clk);
+ if (ret)
+ return ret;
+
+ setbits_le32(base_addr + plat->pllgrp, plat->bitmask);
+
+ return 0;
+}
+
+static int socfpga_clk_disable(struct clk *clk)
+{
+ struct socfpga_clk_plat *plat = dev_get_plat(clk->dev);
+ uintptr_t base_addr = (uintptr_t)plat->regs;
+ int ret;
+
+ ret = bitmask_from_clk_id(clk);
+ if (ret)
+ return ret;
+
+ clrbits_le32(base_addr + plat->pllgrp, plat->bitmask);
+
return 0;
}
@@ -672,6 +789,7 @@ static int socfpga_clk_of_to_plat(struct udevice *dev)
static struct clk_ops socfpga_clk_ops = {
.enable = socfpga_clk_enable,
+ .disable = socfpga_clk_disable,
.get_rate = socfpga_clk_get_rate,
};
diff --git a/drivers/clk/altera/clk-agilex.h b/drivers/clk/altera/clk-agilex.h
index b3e8841a512..be639957940 100644
--- a/drivers/clk/altera/clk-agilex.h
+++ b/drivers/clk/altera/clk-agilex.h
@@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2019 Intel Corporation <www.intel.com>
+ * Copyright (C) 2025 Altera Corporation <www.altera.com>
*/
#ifndef _CLK_AGILEX_
@@ -210,7 +211,26 @@ struct cm_config {
#define CLKMGR_LOSTLOCK_SET_MASK BIT(0)
+#define CLKMGR_MAINPLLGRP_EN_MPUCLK_MASK BIT(0)
+#define CLKMGR_MAINPLLGRP_EN_L4MAINCLK_MASK BIT(1)
+#define CLKMGR_MAINPLLGRP_EN_L4MPCLK_MASK BIT(2)
+#define CLKMGR_MAINPLLGRP_EN_L4SPCLK_MASK BIT(3)
+#define CLKMGR_MAINPLLGRP_EN_CSCLK_MASK BIT(4)
+#define CLKMGR_MAINPLLGRP_EN_CSTIMERCLK_MASK BIT(5)
+#define CLKMGR_MAINPLLGRP_EN_S2FUSER0CLK_MASK BIT(6)
+
+#define CLKMGR_PERPLLGRP_EN_EMAC0CLK_MASK BIT(0)
+#define CLKMGR_PERPLLGRP_EN_EMAC1CLK_MASK BIT(1)
+#define CLKMGR_PERPLLGRP_EN_EMAC2CLK_MASK BIT(2)
+#define CLKMGR_PERPLLGRP_EN_EMACPTPCLK_MASK BIT(3)
+#define CLKMGR_PERPLLGRP_EN_GPIODBCLK_MASK BIT(4)
#define CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK BIT(5)
+#define CLKMGR_PERPLLGRP_EN_S2FUSER1CLK_MASK BIT(6)
+#define CLKMGR_PERPLLGRP_EN_PSIREFCLK_MASK BIT(7)
+#define CLKMGR_PERPLLGRP_EN_USBCLK_MASK BIT(8)
+#define CLKMGR_PERPLLGRP_EN_SPIMCLK_MASK BIT(9)
+#define CLKMGR_PERPLLGRP_EN_NANDCLK_MASK BIT(10)
+
#define CLKMGR_PERPLLGRP_EMACCTL_EMAC0SELB_OFFSET 26
#define CLKMGR_PERPLLGRP_EMACCTL_EMAC0SELB_MASK BIT(26)
#define CLKMGR_PERPLLGRP_EMACCTL_EMAC1SELB_OFFSET 27
diff --git a/drivers/clk/clk-cdce9xx.c b/drivers/clk/clk-cdce9xx.c
index e5f74e714d5..996cc30683e 100644
--- a/drivers/clk/clk-cdce9xx.c
+++ b/drivers/clk/clk-cdce9xx.c
@@ -116,8 +116,7 @@ static int cdce9xx_clk_probe(struct udevice *dev)
ret = clk_get_by_index(dev, 0, &clk);
data->xtal_rate = clk_get_rate(&clk);
- val = dev_read_u32_default(dev, "xtal-load-pf", -1);
- if (val >= 0)
+ if (!dev_read_u32(dev, "xtal-load-pf", &val))
cdce9xx_reg_write(dev, CDCE9XX_REG_XCSEL, val << 3);
return 0;
diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c
index 7262e89b512..3dbe1ce9441 100644
--- a/drivers/clk/clk-uclass.c
+++ b/drivers/clk/clk-uclass.c
@@ -358,7 +358,7 @@ static int clk_set_default_rates(struct udevice *dev,
ret = clk_set_rate(c, rates[index]);
- if (ret < 0) {
+ if (IS_ERR_VALUE(ret)) {
dev_warn(dev,
"failed to set rate on clock index %d (%ld) (error = %d)\n",
index, clk.id, ret);
diff --git a/drivers/clk/clk_scmi.c b/drivers/clk/clk_scmi.c
index 0c9a81cabcc..a7d89f32cd7 100644
--- a/drivers/clk/clk_scmi.c
+++ b/drivers/clk/clk_scmi.c
@@ -7,6 +7,7 @@
#include <clk-uclass.h>
#include <dm.h>
+#include <dm/device_compat.h>
#include <scmi_agent.h>
#include <scmi_agent-uclass.h>
#include <scmi_protocols.h>
@@ -41,19 +42,21 @@ static int scmi_clk_get_permissions(struct udevice *dev, int clkid, u32 *perm)
};
if (priv->version < CLOCK_PROTOCOL_VERSION_3_0) {
- log_debug("%s: SCMI clock management protocol version is less than 3.0.\n", __func__);
+ dev_dbg(dev,
+ "%s: SCMI clock management protocol version is less than 3.0.\n", __func__);
return -EINVAL;
}
ret = devm_scmi_process_msg(dev, &msg);
if (ret) {
- log_debug("%s: get SCMI clock management protocol permissions failed\n", __func__);
+ dev_dbg(dev,
+ "%s: get SCMI clock management protocol permissions failed\n", __func__);
return ret;
}
ret = scmi_to_linux_errno(out.status);
if (ret < 0) {
- log_debug("%s: the status code of getting permissions: %d\n", __func__, ret);
+ dev_dbg(dev, "%s: the status code of getting permissions: %d\n", __func__, ret);
return ret;
}
@@ -167,7 +170,7 @@ static int scmi_clk_enable(struct clk *clk)
return scmi_clk_gate(clk, 1);
/* Following Linux drivers/clk/clk-scmi.c, directly return 0 if agent has no permission. */
- log_debug("%s: SCMI CLOCK: the clock cannot be enabled by the agent.\n", __func__);
+ dev_dbg(clk->dev, "%s: SCMI CLOCK: the clock cannot be enabled by the agent.\n", __func__);
return 0;
}
@@ -190,7 +193,8 @@ static int scmi_clk_disable(struct clk *clk)
return scmi_clk_gate(clk, 0);
/* Following Linux drivers/clk/clk-scmi.c, directly return 0 if agent has no permission. */
- log_debug("%s: SCMI CLOCK: the clock cannot be disabled by the agent.\n", __func__);
+ dev_dbg(clk->dev,
+ "%s: SCMI CLOCK: the clock cannot be disabled by the agent.\n", __func__);
return 0;
}
@@ -260,7 +264,8 @@ static ulong scmi_clk_set_rate(struct clk *clk, ulong rate)
return __scmi_clk_set_rate(clk, rate);
/* Following Linux drivers/clk/clk-scmi.c, directly return 0 if agent has no permission. */
- log_debug("%s: SCMI CLOCK: the clock rate cannot be changed by the agent.\n", __func__);
+ dev_dbg(clk->dev,
+ "%s: SCMI CLOCK: the clock rate cannot be changed by the agent.\n", __func__);
return 0;
}
@@ -291,7 +296,7 @@ static int scmi_clk_probe(struct udevice *dev)
ret = scmi_generic_protocol_version(dev, SCMI_PROTOCOL_ID_CLOCK, &priv->version);
if (ret) {
- log_debug("%s: get SCMI clock management protocol version failed\n", __func__);
+ dev_dbg(dev, "%s: get SCMI clock management protocol version failed\n", __func__);
return ret;
}
@@ -371,7 +376,8 @@ static int scmi_clk_set_parent(struct clk *clk, struct clk *parent)
return __scmi_clk_set_parent(clk, parent);
/* Following Linux drivers/clk/clk-scmi.c, directly return 0 if agent has no permission. */
- log_debug("%s: SCMI CLOCK: the clock's parent cannot be changed by the agent.\n", __func__);
+ dev_dbg(clk->dev,
+ "%s: SCMI CLOCK: the clock's parent cannot be changed by the agent.\n", __func__);
return 0;
}
diff --git a/drivers/clk/clk_zynqmp.c b/drivers/clk/clk_zynqmp.c
index 4f67c958d0f..7a433a667a4 100644
--- a/drivers/clk/clk_zynqmp.c
+++ b/drivers/clk/clk_zynqmp.c
@@ -882,7 +882,7 @@ static int zynqmp_clk_enable(struct clk *clk)
return ret;
}
-static struct clk_ops zynqmp_clk_ops = {
+static const struct clk_ops zynqmp_clk_ops = {
.set_rate = zynqmp_clk_set_rate,
.get_rate = zynqmp_clk_get_rate,
.enable = zynqmp_clk_enable,
diff --git a/drivers/clk/imx/Kconfig b/drivers/clk/imx/Kconfig
index 74d5fe73f94..644ab162af4 100644
--- a/drivers/clk/imx/Kconfig
+++ b/drivers/clk/imx/Kconfig
@@ -167,3 +167,12 @@ config CLK_IMXRT1170
select CLK_CCF
help
This enables support clock driver for i.MXRT1170 platforms.
+
+config CLK_IMX95_BLKCTRL
+ bool "Enable i.MX95 blkctrl clock driver"
+ depends on IMX95 || IMX94
+ select CLK
+ select CLK_CCF
+ select CLK_AUTO_ID
+ help
+ Enable support for clocks in i.MX95 MIX blkctrl like HSIO and LVDS.
diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile
index b10221a195c..f2fd6ff8ca0 100644
--- a/drivers/clk/imx/Makefile
+++ b/drivers/clk/imx/Makefile
@@ -25,3 +25,4 @@ obj-$(CONFIG_$(PHASE_)CLK_IMX93) += clk-imx93.o clk-fracn-gppll.o \
obj-$(CONFIG_$(PHASE_)CLK_IMXRT1020) += clk-imxrt1020.o
obj-$(CONFIG_$(PHASE_)CLK_IMXRT1050) += clk-imxrt1050.o
obj-$(CONFIG_$(PHASE_)CLK_IMXRT1170) += clk-imxrt1170.o
+obj-$(CONFIG_CLK_IMX95_BLKCTRL) += clk-imx95-blkctrl.o
diff --git a/drivers/clk/imx/clk-imx6q.c b/drivers/clk/imx/clk-imx6q.c
index 13239f2f64d..b69355cefc7 100644
--- a/drivers/clk/imx/clk-imx6q.c
+++ b/drivers/clk/imx/clk-imx6q.c
@@ -156,6 +156,12 @@ static int imx6q_clk_probe(struct udevice *dev)
imx_clk_gate2(dev, "i2c3", "ipg_per", base + 0x70, 10));
clk_dm(IMX6QDL_CLK_PWM1,
imx_clk_gate2(dev, "pwm1", "ipg_per", base + 0x78, 16));
+ clk_dm(IMX6QDL_CLK_PWM2,
+ imx_clk_gate2(dev, "pwm2", "ipg_per", base + 0x78, 18));
+ clk_dm(IMX6QDL_CLK_PWM3,
+ imx_clk_gate2(dev, "pwm3", "ipg_per", base + 0x78, 20));
+ clk_dm(IMX6QDL_CLK_PWM4,
+ imx_clk_gate2(dev, "pwm4", "ipg_per", base + 0x78, 22));
clk_dm(IMX6QDL_CLK_ENET, imx_clk_gate2(dev, "enet", "ipg", base + 0x6c, 10));
clk_dm(IMX6QDL_CLK_ENET_REF,
diff --git a/drivers/clk/imx/clk-imx95-blkctrl.c b/drivers/clk/imx/clk-imx95-blkctrl.c
new file mode 100644
index 00000000000..3e6f53b4a16
--- /dev/null
+++ b/drivers/clk/imx/clk-imx95-blkctrl.c
@@ -0,0 +1,183 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2023-2025 NXP
+ *
+ */
+
+#include <asm/io.h>
+#include <clk-uclass.h>
+#include <dm.h>
+#include <dm/device_compat.h>
+#include <dt-bindings/clock/nxp,imx95-clock.h>
+#include <linux/clk-provider.h>
+
+#include "clk.h"
+
+enum {
+ CLK_GATE,
+ CLK_DIVIDER,
+ CLK_MUX,
+};
+
+struct imx95_blk_ctl_clk_dev_data {
+ const char *name;
+ const char * const *parent_names;
+ u32 num_parents;
+ u32 reg;
+ u32 bit_idx;
+ u32 clk_type;
+ u32 flags;
+ u32 flags2;
+ u32 type;
+};
+
+struct imx95_blk_ctl_dev_data {
+ const struct imx95_blk_ctl_clk_dev_data *clk_dev_data;
+ u32 num_clks;
+ u32 clk_reg_offset;
+};
+
+static const struct imx95_blk_ctl_clk_dev_data hsio_blk_ctl_clk_dev_data[] = {
+ [0] = {
+ .name = "hsio_blk_ctl_clk",
+ .parent_names = (const char *[]){ "hsiopll", },
+ .num_parents = 1,
+ .reg = 0,
+ .bit_idx = 6,
+ .type = CLK_GATE,
+ .flags = CLK_SET_RATE_PARENT,
+ }
+};
+
+static const struct imx95_blk_ctl_dev_data hsio_blk_ctl_dev_data = {
+ .num_clks = 1,
+ .clk_dev_data = hsio_blk_ctl_clk_dev_data,
+ .clk_reg_offset = 0,
+};
+
+static const struct imx95_blk_ctl_clk_dev_data imx95_lvds_clk_dev_data[] = {
+ [IMX95_CLK_DISPMIX_LVDS_PHY_DIV] = {
+ .name = "ldb_phy_div",
+ .parent_names = (const char *[]){ "ldbpll", },
+ .num_parents = 1,
+ .reg = 0,
+ .bit_idx = 0,
+ .type = CLK_DIVIDER,
+ .flags2 = CLK_DIVIDER_POWER_OF_TWO,
+ },
+
+ [IMX95_CLK_DISPMIX_LVDS_CH0_GATE] = {
+ .name = "lvds_ch0_gate",
+ .parent_names = (const char *[]){ "ldb_phy_div", },
+ .num_parents = 1,
+ .reg = 0,
+ .bit_idx = 1,
+ .type = CLK_GATE,
+ .flags = CLK_SET_RATE_PARENT,
+ .flags2 = CLK_GATE_SET_TO_DISABLE,
+ },
+ [IMX95_CLK_DISPMIX_LVDS_CH1_GATE] = {
+ .name = "lvds_ch1_gate",
+ .parent_names = (const char *[]){ "ldb_phy_div", },
+ .num_parents = 1,
+ .reg = 0,
+ .bit_idx = 2,
+ .type = CLK_GATE,
+ .flags = CLK_SET_RATE_PARENT,
+ .flags2 = CLK_GATE_SET_TO_DISABLE,
+ },
+ [IMX95_CLK_DISPMIX_PIX_DI0_GATE] = {
+ .name = "lvds_di0_gate",
+ .parent_names = (const char *[]){ "ldb_pll_div7", },
+ .num_parents = 1,
+ .reg = 0,
+ .bit_idx = 3,
+ .type = CLK_GATE,
+ .flags = CLK_SET_RATE_PARENT,
+ .flags2 = CLK_GATE_SET_TO_DISABLE,
+ },
+ [IMX95_CLK_DISPMIX_PIX_DI1_GATE] = {
+ .name = "lvds_di1_gate",
+ .parent_names = (const char *[]){ "ldb_pll_div7", },
+ .num_parents = 1,
+ .reg = 0,
+ .bit_idx = 4,
+ .type = CLK_GATE,
+ .flags = CLK_SET_RATE_PARENT,
+ .flags2 = CLK_GATE_SET_TO_DISABLE,
+ },
+};
+
+static const struct imx95_blk_ctl_dev_data imx95_lvds_csr_dev_data = {
+ .num_clks = ARRAY_SIZE(imx95_lvds_clk_dev_data),
+ .clk_dev_data = imx95_lvds_clk_dev_data,
+ .clk_reg_offset = 0,
+};
+
+static int imx95_blkctrl_clk_probe(struct udevice *dev)
+{
+ int i;
+ void __iomem *addr;
+ struct imx95_blk_ctl_dev_data *dev_data = (void *)dev_get_driver_data(dev);
+ const struct imx95_blk_ctl_clk_dev_data *clk_dev_data;
+
+ addr = dev_read_addr_ptr(dev);
+ if (addr == (void *)FDT_ADDR_T_NONE) {
+ dev_err(dev, "No blkctrl register base address\n");
+ return -EINVAL;
+ }
+
+ if (!dev_data) {
+ dev_err(dev, "driver data is NULL\n");
+ return -EINVAL;
+ }
+
+ clk_dev_data = dev_data->clk_dev_data;
+ for (i = 0; i < dev_data->num_clks; i++) {
+ if (clk_dev_data[i].clk_type == CLK_GATE) {
+ dev_clk_dm(dev, i,
+ clk_register_gate(dev,
+ clk_dev_data[i].name,
+ clk_dev_data[i].parent_names[0],
+ clk_dev_data[i].flags, addr +
+ dev_data->clk_reg_offset,
+ clk_dev_data[i].bit_idx,
+ clk_dev_data[i].flags2, NULL));
+ } else if (clk_dev_data[i].clk_type == CLK_DIVIDER) {
+ dev_clk_dm(dev, i,
+ clk_register_divider(dev, clk_dev_data[i].name,
+ clk_dev_data[i].parent_names[0],
+ clk_dev_data[i].flags, addr +
+ dev_data->clk_reg_offset,
+ clk_dev_data[i].bit_idx, 1,
+ clk_dev_data[i].flags2));
+ } else if (clk_dev_data[i].clk_type == CLK_MUX) {
+ dev_clk_dm(dev, i,
+ clk_register_mux(dev,
+ clk_dev_data[i].name,
+ clk_dev_data[i].parent_names,
+ clk_dev_data[i].num_parents,
+ clk_dev_data[i].flags, addr +
+ dev_data->clk_reg_offset,
+ clk_dev_data[i].bit_idx, 1,
+ clk_dev_data[i].flags2));
+ }
+ }
+
+ return 0;
+}
+
+static const struct udevice_id imx95_blkctrl_clk_ids[] = {
+ { .compatible = "nxp,imx95-lvds-csr", .data = (ulong)&imx95_lvds_csr_dev_data, },
+ { .compatible = "nxp,imx95-hsio-blk-ctl", .data = (ulong)&hsio_blk_ctl_dev_data, },
+ { },
+};
+
+U_BOOT_DRIVER(imx95_blkctrl_clk) = {
+ .name = "imx95_blkctrl_clk",
+ .id = UCLASS_CLK,
+ .of_match = imx95_blkctrl_clk_ids,
+ .ops = &ccf_clk_ops,
+ .probe = imx95_blkctrl_clk_probe,
+ .flags = DM_FLAG_PRE_RELOC,
+};
diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c
index 5d7faaa3eab..a7a42b2edb6 100644
--- a/drivers/clk/meson/g12a.c
+++ b/drivers/clk/meson/g12a.c
@@ -916,8 +916,6 @@ static ulong meson_clk_set_rate_by_id(struct clk *clk, unsigned long id,
return -EINVAL;
case CLKID_PCIE_PLL:
return meson_pcie_pll_set_rate(clk, rate);
-
- return 0;
case CLKID_VPU:
return meson_clk_set_rate_by_id(clk,
meson_mux_get_parent(clk, CLKID_VPU), rate,
diff --git a/drivers/clk/stm32/clk-stm32mp25.c b/drivers/clk/stm32/clk-stm32mp25.c
index 18c0b1cb867..b487f33b6c7 100644
--- a/drivers/clk/stm32/clk-stm32mp25.c
+++ b/drivers/clk/stm32/clk-stm32mp25.c
@@ -430,7 +430,7 @@ static int stm32mp25_check_security(struct udevice *dev, void __iomem *base,
u32 index = (u32)cfg->sec_id;
if (index & SEC_RIFSC_FLAG)
- ret = stm32_rifsc_check_access_by_id(dev_ofnode(dev),
+ ret = stm32_rifsc_grant_access_by_id(dev_ofnode(dev),
index & ~SEC_RIFSC_FLAG);
else
ret = stm32_rcc_get_access(dev, index);
diff --git a/drivers/clk/thead/clk-th1520-ap.c b/drivers/clk/thead/clk-th1520-ap.c
index 822cf0809d5..6899e1b595a 100644
--- a/drivers/clk/thead/clk-th1520-ap.c
+++ b/drivers/clk/thead/clk-th1520-ap.c
@@ -235,6 +235,7 @@ U_BOOT_DRIVER(th1520_clk_div) = {
.name = "th1520_clk_div",
.id = UCLASS_CLK,
.ops = &ccu_div_ops,
+ .flags = DM_FLAG_PRE_RELOC,
};
static unsigned long th1520_pll_vco_recalc_rate(struct clk *clk,
@@ -302,6 +303,7 @@ U_BOOT_DRIVER(th1520_clk_pll) = {
.name = "th1520_clk_pll",
.id = UCLASS_CLK,
.ops = &clk_pll_ops,
+ .flags = DM_FLAG_PRE_RELOC,
};
static struct ccu_pll cpu_pll0_clk = {
@@ -1030,4 +1032,5 @@ U_BOOT_DRIVER(th1520_clk) = {
.of_match = th1520_clk_match,
.probe = th1520_clk_probe,
.ops = &th1520_clk_ops,
+ .flags = DM_FLAG_PRE_RELOC,
};
generated by cgit v1.2.3 (git 2.0.4) at 2025-10-11 15:49:02 +0000