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path: root/drivers/ddr/marvell/a38x/ddr3_training_ip_flow.h
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Diffstat (limited to 'drivers/ddr/marvell/a38x/ddr3_training_ip_flow.h')
-rw-r--r--drivers/ddr/marvell/a38x/ddr3_training_ip_flow.h10
1 files changed, 7 insertions, 3 deletions
diff --git a/drivers/ddr/marvell/a38x/ddr3_training_ip_flow.h b/drivers/ddr/marvell/a38x/ddr3_training_ip_flow.h
index ab152cb455e..55832a55405 100644
--- a/drivers/ddr/marvell/a38x/ddr3_training_ip_flow.h
+++ b/drivers/ddr/marvell/a38x/ddr3_training_ip_flow.h
@@ -8,6 +8,7 @@
#include "ddr3_training_ip.h"
#include "ddr3_training_ip_db.h"
+#include "mv_ddr_plat.h"
#define KILLER_PATTERN_LENGTH 32
#define EXT_ACCESS_BURST_LENGTH 8
@@ -112,9 +113,12 @@ int ddr3_tip_configure_odpg(u32 dev_num, enum hws_access_type access_type,
int ddr3_tip_write_mrs_cmd(u32 dev_num, u32 *cs_mask_arr, enum mr_number mr_num, u32 data, u32 mask);
int ddr3_tip_write_cs_result(u32 dev_num, u32 offset);
int ddr3_tip_reset_fifo_ptr(u32 dev_num);
-int ddr3_tip_read_pup_value(u32 dev_num, u32 pup_values[], int reg_addr, u32 mask);
-int ddr3_tip_read_adll_value(u32 dev_num, u32 pup_values[], u32 reg_addr, u32 mask);
-int ddr3_tip_write_adll_value(u32 dev_num, u32 pup_values[], u32 reg_addr);
+int ddr3_tip_read_adll_value(u32 dev_num,
+ u32 pup_values[MAX_INTERFACE_NUM * MAX_BUS_NUM],
+ u32 reg_addr, u32 mask);
+int ddr3_tip_write_adll_value(u32 dev_num,
+ u32 pup_values[MAX_INTERFACE_NUM * MAX_BUS_NUM],
+ u32 reg_addr);
int ddr3_tip_tune_training_params(u32 dev_num, struct tune_train_params *params);
#endif /* _DDR3_TRAINING_IP_FLOW_H_ */