diff options
Diffstat (limited to 'drivers/mtd/nand/raw/atmel_nand.c')
| -rw-r--r-- | drivers/mtd/nand/raw/atmel_nand.c | 40 |
1 files changed, 20 insertions, 20 deletions
diff --git a/drivers/mtd/nand/raw/atmel_nand.c b/drivers/mtd/nand/raw/atmel_nand.c index a541af6db4a..9fbb0b57cf1 100644 --- a/drivers/mtd/nand/raw/atmel_nand.c +++ b/drivers/mtd/nand/raw/atmel_nand.c @@ -1227,16 +1227,16 @@ static void at91_nand_hwcontrol(struct mtd_info *mtd, if (ctrl & NAND_CTRL_CHANGE) { ulong IO_ADDR_W = (ulong) this->IO_ADDR_W; - IO_ADDR_W &= ~(CONFIG_SYS_NAND_MASK_ALE - | CONFIG_SYS_NAND_MASK_CLE); + IO_ADDR_W &= ~(CFG_SYS_NAND_MASK_ALE + | CFG_SYS_NAND_MASK_CLE); if (ctrl & NAND_CLE) - IO_ADDR_W |= CONFIG_SYS_NAND_MASK_CLE; + IO_ADDR_W |= CFG_SYS_NAND_MASK_CLE; if (ctrl & NAND_ALE) - IO_ADDR_W |= CONFIG_SYS_NAND_MASK_ALE; + IO_ADDR_W |= CFG_SYS_NAND_MASK_ALE; -#ifdef CONFIG_SYS_NAND_ENABLE_PIN - at91_set_gpio_value(CONFIG_SYS_NAND_ENABLE_PIN, +#ifdef CFG_SYS_NAND_ENABLE_PIN + at91_set_gpio_value(CFG_SYS_NAND_ENABLE_PIN, !(ctrl & NAND_NCE)); #endif this->IO_ADDR_W = (void *) IO_ADDR_W; @@ -1246,10 +1246,10 @@ static void at91_nand_hwcontrol(struct mtd_info *mtd, writeb(cmd, this->IO_ADDR_W); } -#ifdef CONFIG_SYS_NAND_READY_PIN +#ifdef CFG_SYS_NAND_READY_PIN static int at91_nand_ready(struct mtd_info *mtd) { - return at91_get_gpio_value(CONFIG_SYS_NAND_READY_PIN); + return at91_get_gpio_value(CFG_SYS_NAND_READY_PIN); } #endif @@ -1314,10 +1314,10 @@ static int nand_is_bad_block(int block) } #ifdef CONFIG_SPL_NAND_ECC -static int nand_ecc_pos[] = CONFIG_SYS_NAND_ECCPOS; +static int nand_ecc_pos[] = CFG_SYS_NAND_ECCPOS; #define ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / \ - CONFIG_SYS_NAND_ECCSIZE) -#define ECCTOTAL (ECCSTEPS * CONFIG_SYS_NAND_ECCBYTES) + CFG_SYS_NAND_ECCSIZE) +#define ECCTOTAL (ECCSTEPS * CFG_SYS_NAND_ECCBYTES) static int nand_read_page(int block, int page, void *dst) { @@ -1325,8 +1325,8 @@ static int nand_read_page(int block, int page, void *dst) u_char ecc_calc[ECCTOTAL]; u_char ecc_code[ECCTOTAL]; u_char oob_data[CONFIG_SYS_NAND_OOBSIZE]; - int eccsize = CONFIG_SYS_NAND_ECCSIZE; - int eccbytes = CONFIG_SYS_NAND_ECCBYTES; + int eccsize = CFG_SYS_NAND_ECCSIZE; + int eccbytes = CFG_SYS_NAND_ECCBYTES; int eccsteps = ECCSTEPS; int i; uint8_t *p = dst; @@ -1415,7 +1415,7 @@ int board_nand_init(struct nand_chip *nand) nand->read_buf = nand_read_buf; #endif nand->cmd_ctrl = at91_nand_hwcontrol; -#ifdef CONFIG_SYS_NAND_READY_PIN +#ifdef CFG_SYS_NAND_READY_PIN nand->dev_ready = at91_nand_ready; #else nand->dev_ready = at91_nand_wait_ready; @@ -1439,8 +1439,8 @@ void nand_init(void) mtd = nand_to_mtd(&nand_chip); mtd->writesize = CONFIG_SYS_NAND_PAGE_SIZE; mtd->oobsize = CONFIG_SYS_NAND_OOBSIZE; - nand_chip.IO_ADDR_R = (void __iomem *)CONFIG_SYS_NAND_BASE; - nand_chip.IO_ADDR_W = (void __iomem *)CONFIG_SYS_NAND_BASE; + nand_chip.IO_ADDR_R = (void __iomem *)CFG_SYS_NAND_BASE; + nand_chip.IO_ADDR_W = (void __iomem *)CFG_SYS_NAND_BASE; board_nand_init(&nand_chip); #ifdef CONFIG_SPL_NAND_ECC @@ -1464,11 +1464,11 @@ void nand_deselect(void) #else -#ifndef CONFIG_SYS_NAND_BASE_LIST -#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } +#ifndef CFG_SYS_NAND_BASE_LIST +#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE } #endif static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE]; -static ulong base_addr[CONFIG_SYS_MAX_NAND_DEVICE] = CONFIG_SYS_NAND_BASE_LIST; +static ulong base_addr[CONFIG_SYS_MAX_NAND_DEVICE] = CFG_SYS_NAND_BASE_LIST; int atmel_nand_chip_init(int devnum, ulong base_addr) { @@ -1487,7 +1487,7 @@ int atmel_nand_chip_init(int devnum, ulong base_addr) nand->options = NAND_BUSWIDTH_16; #endif nand->cmd_ctrl = at91_nand_hwcontrol; -#ifdef CONFIG_SYS_NAND_READY_PIN +#ifdef CFG_SYS_NAND_READY_PIN nand->dev_ready = at91_nand_ready; #endif nand->chip_delay = 75; |