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-rw-r--r--drivers/pinctrl/Kconfig7
-rw-r--r--drivers/pinctrl/meson/pinctrl-meson.c20
-rw-r--r--drivers/pinctrl/nexell/pinctrl-s5pxx18.c3
-rw-r--r--drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c2
-rw-r--r--drivers/pinctrl/nxp/pinctrl-imx-scmi.c5
-rw-r--r--drivers/pinctrl/pinctrl-single.c2
-rw-r--r--drivers/pinctrl/pinctrl-stmfx.c2
-rw-r--r--drivers/pinctrl/pinctrl-sx150x.c30
-rw-r--r--drivers/pinctrl/pinctrl-th1520.c1
-rw-r--r--drivers/pinctrl/tegra/Kconfig4
10 files changed, 53 insertions, 23 deletions
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 5e2808abc8a..48119694031 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -197,7 +197,7 @@ config PINCTRL_AR933X
config PINCTRL_AT91
bool "AT91 pinctrl driver"
- depends on DM
+ depends on DM && ARCH_AT91
help
This option is to enable the AT91 pinctrl driver for AT91 PIO
controller.
@@ -213,13 +213,14 @@ config PINCTRL_AT91
config PINCTRL_AT91PIO4
bool "AT91 PIO4 pinctrl driver"
- depends on DM
+ depends on DM && ARCH_AT91
help
This option is to enable the AT91 pinctrl driver for AT91 PIO4
controller which is available on SAMA5D2 SoC.
config PINCTRL_INTEL
bool "Standard Intel pin-control and pin-mux driver"
+ depends on X86
help
Recent Intel chips such as Apollo Lake (APL) use a common pin control
and GPIO scheme. The settings for this come from an SoC-specific
@@ -248,7 +249,7 @@ config PINCTRL_QCA953X
config PINCTRL_QE
bool "QE based pinctrl driver, like on mpc83xx"
- depends on DM
+ depends on DM && MPC83xx
help
This option is to enable the QE pinctrl driver for QE based io
controller.
diff --git a/drivers/pinctrl/meson/pinctrl-meson.c b/drivers/pinctrl/meson/pinctrl-meson.c
index babf1bccc96..7dbaf966f93 100644
--- a/drivers/pinctrl/meson/pinctrl-meson.c
+++ b/drivers/pinctrl/meson/pinctrl-meson.c
@@ -117,8 +117,26 @@ int meson_gpio_get(struct udevice *dev, unsigned int offset)
struct meson_pinctrl *priv = dev_get_priv(dev->parent);
unsigned int reg, bit;
int ret;
+ enum gpio_func_t direction;
+ enum meson_reg_type reg_type;
- ret = meson_gpio_calc_reg_and_bit(dev->parent, offset, REG_IN, &reg,
+ direction = meson_gpio_get_direction(dev, offset);
+
+ switch (direction) {
+ case GPIOF_INPUT:
+ reg_type = REG_IN;
+ break;
+
+ case GPIOF_OUTPUT:
+ reg_type = REG_OUT;
+ break;
+
+ default:
+ dev_warn(dev, "Failed to get current direction of Pin %u\n", offset);
+ return -EINVAL;
+ }
+
+ ret = meson_gpio_calc_reg_and_bit(dev->parent, offset, reg_type, &reg,
&bit);
if (ret)
return ret;
diff --git a/drivers/pinctrl/nexell/pinctrl-s5pxx18.c b/drivers/pinctrl/nexell/pinctrl-s5pxx18.c
index e7d0994f29e..a6ae5764fbc 100644
--- a/drivers/pinctrl/nexell/pinctrl-s5pxx18.c
+++ b/drivers/pinctrl/nexell/pinctrl-s5pxx18.c
@@ -130,7 +130,8 @@ static int is_pin_alive(const char *name)
static int s5pxx18_pinctrl_set_state(struct udevice *dev,
struct udevice *config)
{
- unsigned int count, idx, pin;
+ u32 pin;
+ int count, idx;
unsigned int pinfunc, pinpud, pindrv;
unsigned long reg;
const char *name;
diff --git a/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c b/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c
index 67e564f85c3..c960ca3393d 100644
--- a/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c
+++ b/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c
@@ -23,6 +23,7 @@
#define TIPRSTC 0x50
#define CORSTC 0x5c
#define FLOCKR1 0x74
+#define INTCR 0x3c
#define INTCR4 0xc0
#define I2CSEGSEL 0xe0
#define MFSEL1 0x260
@@ -280,6 +281,7 @@ struct npcm8xx_pinctrl_priv {
FUNC(lkgpo2, FLOCKR1, 8, 9) \
FUNC(nprd_smi, FLOCKR1, 20, 190) \
FUNC(mmcwp, FLOCKR1, 24, 153) \
+ FUNC(vcdhs, INTCR, 27) \
FUNC(rg2refck, INTCR4, 6) \
FUNC(r1en, INTCR4, 12) \
FUNC(r2en, INTCR4, 13) \
diff --git a/drivers/pinctrl/nxp/pinctrl-imx-scmi.c b/drivers/pinctrl/nxp/pinctrl-imx-scmi.c
index aed47be337d..781835c6852 100644
--- a/drivers/pinctrl/nxp/pinctrl-imx-scmi.c
+++ b/drivers/pinctrl/nxp/pinctrl-imx-scmi.c
@@ -16,6 +16,7 @@
#include "pinctrl-imx.h"
#define DAISY_OFFSET_IMX95 0x408
+#define DAISY_OFFSET_IMX94 0x608
/* SCMI pin control types */
#define PINCTRL_TYPE_MUX 192
@@ -133,6 +134,8 @@ static int imx_scmi_pinctrl_probe(struct udevice *dev)
if (IS_ENABLED(CONFIG_IMX95))
priv->daisy_offset = DAISY_OFFSET_IMX95;
+ else if (IS_ENABLED(CONFIG_IMX94))
+ priv->daisy_offset = DAISY_OFFSET_IMX94;
else
return -EINVAL;
@@ -141,7 +144,7 @@ static int imx_scmi_pinctrl_probe(struct udevice *dev)
static int imx_scmi_pinctrl_bind(struct udevice *dev)
{
- if (IS_ENABLED(CONFIG_IMX95))
+ if (IS_ENABLED(CONFIG_IMX95) || IS_ENABLED(CONFIG_IMX94))
return 0;
return -ENODEV;
diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c
index a3802d22d4f..c96b293aadf 100644
--- a/drivers/pinctrl/pinctrl-single.c
+++ b/drivers/pinctrl/pinctrl-single.c
@@ -109,8 +109,6 @@ static unsigned int single_read(struct udevice *dev, void *reg)
default: /* 32 bits */
return readl(reg);
}
-
- return readb(reg);
}
static void single_write(struct udevice *dev, unsigned int val, void *reg)
diff --git a/drivers/pinctrl/pinctrl-stmfx.c b/drivers/pinctrl/pinctrl-stmfx.c
index 61f335c4eb1..0d5778faef9 100644
--- a/drivers/pinctrl/pinctrl-stmfx.c
+++ b/drivers/pinctrl/pinctrl-stmfx.c
@@ -87,7 +87,7 @@ static int stmfx_read_reg(struct udevice *dev, u8 reg_base, uint offset)
if (ret < 0)
return ret;
- return ret < 0 ? ret : !!(ret & mask);
+ return !!(ret & mask);
}
static int stmfx_write_reg(struct udevice *dev, u8 reg_base, uint offset,
diff --git a/drivers/pinctrl/pinctrl-sx150x.c b/drivers/pinctrl/pinctrl-sx150x.c
index 324d7af8fcd..0d64f4d5ad6 100644
--- a/drivers/pinctrl/pinctrl-sx150x.c
+++ b/drivers/pinctrl/pinctrl-sx150x.c
@@ -3,11 +3,14 @@
* Copyright (C) 2024, Exfo Inc - All Rights Reserved
*
* Author: Anis CHALI <anis.chali@exfo.com>
- * inspired and adapted from linux driver of sx150x written by Gregory Bean
- * <gbean@codeaurora.org>
+ *
+ * Inspired and adapted from the Linux pinctrl-sx150x driver:
+ * Copyright (c) 2016, BayLibre, SAS. All rights reserved.
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ * Copyright (c) 2010, Code Aurora Forum. All rights reserved.
+ * Author: Gregory Bean <gbean@codeaurora.org>
*/
-#include <asm/gpio.h>
#include <dm.h>
#include <dm/device-internal.h>
#include <dm/device.h>
@@ -22,6 +25,8 @@
#include <log.h>
#include <power/regulator.h>
#include <regmap.h>
+#include <linux/bug.h>
+#include <asm/gpio.h>
#define err(format, arg...) printf("ERR:" format "\n", ##arg)
#define dbg(format, arg...) printf("DBG:" format "\n", ##arg)
@@ -413,7 +418,7 @@ static int sx150x_reg_read(struct sx150x_pinctrl_priv *pctl, unsigned int reg,
{
int ret, n;
const int width = sx150x_reg_width(pctl, reg);
- unsigned int idx, val;
+ unsigned int val, idx;
/*
* There are four potential cases covered by this function:
@@ -444,8 +449,9 @@ static int sx150x_reg_read(struct sx150x_pinctrl_priv *pctl, unsigned int reg,
* reg 3 [ 3 3 2 2 1 1 0 0 ]
*/
- for (n = width, val = 0, idx = reg; n > 0; n -= 8, idx) {
+ for (n = width, val = 0; n > 0; n -= 8) {
val <<= 8;
+ idx = reg;
ret = dm_i2c_reg_read(pctl->i2c, idx);
if (ret < 0)
@@ -475,7 +481,6 @@ static int sx150x_reg_write(struct sx150x_pinctrl_priv *pctl, unsigned int reg,
if (ret < 0)
return ret;
- reg;
n -= 8;
} while (n >= 0);
@@ -724,7 +729,7 @@ static const struct udevice_id sx150x_pinctrl_of_match[] = {
{},
};
-static const struct pinconf_param sx150x_conf_params[] = {
+static const struct pinconf_param __maybe_unused sx150x_conf_params[] = {
{ "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 },
{ "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 1 },
{ "bias-pull-down", PIN_CONFIG_BIAS_PULL_DOWN, 1 },
@@ -750,7 +755,7 @@ static const char *sx150x_pinctrl_get_pin_name(struct udevice *dev,
return pin_name;
}
-static int sx150x_pinctrl_conf_set(struct udevice *dev, unsigned int pin,
+static int __maybe_unused sx150x_pinctrl_conf_set(struct udevice *dev, unsigned int pin,
unsigned int param, unsigned int arg)
{
int ret;
@@ -834,13 +839,11 @@ static int sx150x_pinctrl_conf_set(struct udevice *dev, unsigned int pin,
static int sx150x_pinctrl_bind(struct udevice *dev)
{
struct sx150x_pinctrl_priv *pctl = dev_get_plat(dev);
- int ret, reg;
+ int ret;
if (!dev_read_bool(dev, "gpio-controller"))
return 0;
- reg = (int)dev_read_addr_ptr(dev);
-
ret = device_bind(dev, &sx150x_gpio_driver, dev_read_name(dev), NULL,
dev_ofnode(dev), &pctl->gpio);
if (ret)
@@ -861,7 +864,10 @@ static int sx150x_pinctrl_probe(struct udevice *dev)
pctl->data = drv_data;
- reg = (int)dev_read_addr_ptr(dev);
+ reg = dev_read_u32_default(dev, "reg", -ENODEV);
+ if (reg < 0)
+ return -ENODEV;
+
ret = dm_i2c_probe(dev->parent, reg, 0, &pctl->i2c);
if (ret) {
err("Cannot find I2C chip %02x (%d)", reg, ret);
diff --git a/drivers/pinctrl/pinctrl-th1520.c b/drivers/pinctrl/pinctrl-th1520.c
index be7e508f8a4..4eead0875d8 100644
--- a/drivers/pinctrl/pinctrl-th1520.c
+++ b/drivers/pinctrl/pinctrl-th1520.c
@@ -697,4 +697,5 @@ U_BOOT_DRIVER(th1520_pinctrl) = {
.probe = th1520_pinctrl_probe,
.priv_auto = sizeof(struct th1520_pinctrl),
.ops = &th1520_pinctrl_ops,
+ .flags = DM_FLAG_PRE_RELOC,
};
diff --git a/drivers/pinctrl/tegra/Kconfig b/drivers/pinctrl/tegra/Kconfig
index 669d8e258e4..d2630289d75 100644
--- a/drivers/pinctrl/tegra/Kconfig
+++ b/drivers/pinctrl/tegra/Kconfig
@@ -2,7 +2,7 @@
config PINCTRL_TEGRA
bool "Nvidia Tegra pinctrl driver"
- depends on DM
+ depends on DM && ARCH_TEGRA
help
Support pin multiplexing control on Nvidia Tegra SoCs.
The driver is an overlay to existing driver and allows
@@ -11,7 +11,7 @@ config PINCTRL_TEGRA
config SPL_PINCTRL_TEGRA
bool "Nvidia Tegra SPL pinctrl driver"
- depends on SPL_PINCTRL
+ depends on SPL_PINCTRL && ARCH_TEGRA
help
Enables support of pre-DM version of pin multiplexing
control driver used on SPL stage for board setup and
generated by cgit v1.2.3 (git 2.0.4) at 2025-10-11 08:28:16 +0000