diff options
Diffstat (limited to 'drivers/reset/reset-imx7.c')
| -rw-r--r-- | drivers/reset/reset-imx7.c | 143 |
1 files changed, 122 insertions, 21 deletions
diff --git a/drivers/reset/reset-imx7.c b/drivers/reset/reset-imx7.c index eaef2cc2cdf..a3b3132f2fa 100644 --- a/drivers/reset/reset-imx7.c +++ b/drivers/reset/reset-imx7.c @@ -9,12 +9,13 @@ #include <common.h> #include <dm.h> #include <dt-bindings/reset/imx7-reset.h> +#include <dt-bindings/reset/imx8mp-reset.h> #include <dt-bindings/reset/imx8mq-reset.h> #include <reset-uclass.h> #include <linux/bitops.h> #include <linux/delay.h> -struct imx7_reset_priv { +struct imx_reset_priv { void __iomem *base; struct reset_ops ops; }; @@ -64,9 +65,9 @@ static const struct imx7_src_signal imx7_src_signals[IMX7_RESET_NUM] = { [IMX7_RESET_DDRC_CORE_RST] = { SRC_DDRC_RCR, BIT(1) }, }; -static int imx7_reset_deassert_imx7(struct reset_ctl *rst) +static int imx7_reset_deassert(struct reset_ctl *rst) { - struct imx7_reset_priv *priv = dev_get_priv(rst->dev); + struct imx_reset_priv *priv = dev_get_priv(rst->dev); const struct imx7_src_signal *sig = imx7_src_signals; u32 val; @@ -95,9 +96,9 @@ static int imx7_reset_deassert_imx7(struct reset_ctl *rst) return 0; } -static int imx7_reset_assert_imx7(struct reset_ctl *rst) +static int imx7_reset_assert(struct reset_ctl *rst) { - struct imx7_reset_priv *priv = dev_get_priv(rst->dev); + struct imx_reset_priv *priv = dev_get_priv(rst->dev); const struct imx7_src_signal *sig = imx7_src_signals; u32 val; @@ -185,9 +186,9 @@ static const struct imx7_src_signal imx8mq_src_signals[IMX8MQ_RESET_NUM] = { [IMX8MQ_RESET_DDRC2_PRST] = { SRC_DDRC2_RCR, BIT(2) }, }; -static int imx7_reset_deassert_imx8mq(struct reset_ctl *rst) +static int imx8mq_reset_deassert(struct reset_ctl *rst) { - struct imx7_reset_priv *priv = dev_get_priv(rst->dev); + struct imx_reset_priv *priv = dev_get_priv(rst->dev); const struct imx7_src_signal *sig = imx8mq_src_signals; u32 val; @@ -223,9 +224,9 @@ static int imx7_reset_deassert_imx8mq(struct reset_ctl *rst) return 0; } -static int imx7_reset_assert_imx8mq(struct reset_ctl *rst) +static int imx8mq_reset_assert(struct reset_ctl *rst) { - struct imx7_reset_priv *priv = dev_get_priv(rst->dev); + struct imx_reset_priv *priv = dev_get_priv(rst->dev); const struct imx7_src_signal *sig = imx8mq_src_signals; u32 val; @@ -252,43 +253,143 @@ static int imx7_reset_assert_imx8mq(struct reset_ctl *rst) return 0; } -static int imx7_reset_assert(struct reset_ctl *rst) +enum imx8mp_src_registers { + SRC_SUPERMIX_RCR = 0x0018, + SRC_AUDIOMIX_RCR = 0x001c, + SRC_MLMIX_RCR = 0x0028, + SRC_GPU2D_RCR = 0x0038, + SRC_GPU3D_RCR = 0x003c, + SRC_VPU_G1_RCR = 0x0048, + SRC_VPU_G2_RCR = 0x004c, + SRC_VPUVC8KE_RCR = 0x0050, + SRC_NOC_RCR = 0x0054, +}; + +static const struct imx7_src_signal imx8mp_src_signals[IMX8MP_RESET_NUM] = { + [IMX8MP_RESET_A53_CORE_POR_RESET0] = { SRC_A53RCR0, BIT(0) }, + [IMX8MP_RESET_A53_CORE_POR_RESET1] = { SRC_A53RCR0, BIT(1) }, + [IMX8MP_RESET_A53_CORE_POR_RESET2] = { SRC_A53RCR0, BIT(2) }, + [IMX8MP_RESET_A53_CORE_POR_RESET3] = { SRC_A53RCR0, BIT(3) }, + [IMX8MP_RESET_A53_CORE_RESET0] = { SRC_A53RCR0, BIT(4) }, + [IMX8MP_RESET_A53_CORE_RESET1] = { SRC_A53RCR0, BIT(5) }, + [IMX8MP_RESET_A53_CORE_RESET2] = { SRC_A53RCR0, BIT(6) }, + [IMX8MP_RESET_A53_CORE_RESET3] = { SRC_A53RCR0, BIT(7) }, + [IMX8MP_RESET_A53_DBG_RESET0] = { SRC_A53RCR0, BIT(8) }, + [IMX8MP_RESET_A53_DBG_RESET1] = { SRC_A53RCR0, BIT(9) }, + [IMX8MP_RESET_A53_DBG_RESET2] = { SRC_A53RCR0, BIT(10) }, + [IMX8MP_RESET_A53_DBG_RESET3] = { SRC_A53RCR0, BIT(11) }, + [IMX8MP_RESET_A53_ETM_RESET0] = { SRC_A53RCR0, BIT(12) }, + [IMX8MP_RESET_A53_ETM_RESET1] = { SRC_A53RCR0, BIT(13) }, + [IMX8MP_RESET_A53_ETM_RESET2] = { SRC_A53RCR0, BIT(14) }, + [IMX8MP_RESET_A53_ETM_RESET3] = { SRC_A53RCR0, BIT(15) }, + [IMX8MP_RESET_A53_SOC_DBG_RESET] = { SRC_A53RCR0, BIT(20) }, + [IMX8MP_RESET_A53_L2RESET] = { SRC_A53RCR0, BIT(21) }, + [IMX8MP_RESET_SW_NON_SCLR_M7C_RST] = { SRC_M4RCR, BIT(0) }, + [IMX8MP_RESET_OTG1_PHY_RESET] = { SRC_USBOPHY1_RCR, BIT(0) }, + [IMX8MP_RESET_OTG2_PHY_RESET] = { SRC_USBOPHY2_RCR, BIT(0) }, + [IMX8MP_RESET_SUPERMIX_RESET] = { SRC_SUPERMIX_RCR, BIT(0) }, + [IMX8MP_RESET_AUDIOMIX_RESET] = { SRC_AUDIOMIX_RCR, BIT(0) }, + [IMX8MP_RESET_MLMIX_RESET] = { SRC_MLMIX_RCR, BIT(0) }, + [IMX8MP_RESET_PCIEPHY] = { SRC_PCIEPHY_RCR, BIT(2) }, + [IMX8MP_RESET_PCIEPHY_PERST] = { SRC_PCIEPHY_RCR, BIT(3) }, + [IMX8MP_RESET_PCIE_CTRL_APPS_EN] = { SRC_PCIEPHY_RCR, BIT(6) }, + [IMX8MP_RESET_PCIE_CTRL_APPS_TURNOFF] = { SRC_PCIEPHY_RCR, BIT(11) }, + [IMX8MP_RESET_HDMI_PHY_APB_RESET] = { SRC_HDMI_RCR, BIT(0) }, + [IMX8MP_RESET_MEDIA_RESET] = { SRC_DISP_RCR, BIT(0) }, + [IMX8MP_RESET_GPU2D_RESET] = { SRC_GPU2D_RCR, BIT(0) }, + [IMX8MP_RESET_GPU3D_RESET] = { SRC_GPU3D_RCR, BIT(0) }, + [IMX8MP_RESET_GPU_RESET] = { SRC_GPU_RCR, BIT(0) }, + [IMX8MP_RESET_VPU_RESET] = { SRC_VPU_RCR, BIT(0) }, + [IMX8MP_RESET_VPU_G1_RESET] = { SRC_VPU_G1_RCR, BIT(0) }, + [IMX8MP_RESET_VPU_G2_RESET] = { SRC_VPU_G2_RCR, BIT(0) }, + [IMX8MP_RESET_VPUVC8KE_RESET] = { SRC_VPUVC8KE_RCR, BIT(0) }, + [IMX8MP_RESET_NOC_RESET] = { SRC_NOC_RCR, BIT(0) }, +}; + +static int imx8mp_reset_set(struct reset_ctl *rst, bool assert) { - struct imx7_reset_priv *priv = dev_get_priv(rst->dev); + struct imx_reset_priv *priv = dev_get_priv(rst->dev); + unsigned int bit, value; + + if (rst->id >= IMX8MP_RESET_NUM) + return -EINVAL; + + bit = imx8mp_src_signals[rst->id].bit; + value = assert ? bit : 0; + + switch (rst->id) { + case IMX8MP_RESET_PCIEPHY: + /* + * wait for more than 10us to release phy g_rst and + * btnrst + */ + if (!assert) + udelay(10); + break; + + case IMX8MP_RESET_PCIE_CTRL_APPS_EN: + case IMX8MP_RESET_PCIEPHY_PERST: + value = assert ? 0 : bit; + break; + } + + clrsetbits_le32(priv->base + imx8mp_src_signals[rst->id].offset, bit, + value); + + return 0; +} + +static int imx8mp_reset_assert(struct reset_ctl *rst) +{ + return imx8mp_reset_set(rst, true); +} + +static int imx8mp_reset_deassert(struct reset_ctl *rst) +{ + return imx8mp_reset_set(rst, false); +} + +static int imx_reset_assert(struct reset_ctl *rst) +{ + struct imx_reset_priv *priv = dev_get_priv(rst->dev); return priv->ops.rst_assert(rst); } -static int imx7_reset_deassert(struct reset_ctl *rst) +static int imx_reset_deassert(struct reset_ctl *rst) { - struct imx7_reset_priv *priv = dev_get_priv(rst->dev); + struct imx_reset_priv *priv = dev_get_priv(rst->dev); return priv->ops.rst_deassert(rst); } static const struct reset_ops imx7_reset_reset_ops = { - .rst_assert = imx7_reset_assert, - .rst_deassert = imx7_reset_deassert, + .rst_assert = imx_reset_assert, + .rst_deassert = imx_reset_deassert, }; static const struct udevice_id imx7_reset_ids[] = { { .compatible = "fsl,imx7d-src" }, { .compatible = "fsl,imx8mq-src" }, + { .compatible = "fsl,imx8mp-src" }, { } }; static int imx7_reset_probe(struct udevice *dev) { - struct imx7_reset_priv *priv = dev_get_priv(dev); + struct imx_reset_priv *priv = dev_get_priv(dev); priv->base = dev_remap_addr(dev); if (!priv->base) return -ENOMEM; if (device_is_compatible(dev, "fsl,imx8mq-src")) { - priv->ops.rst_assert = imx7_reset_assert_imx8mq; - priv->ops.rst_deassert = imx7_reset_deassert_imx8mq; + priv->ops.rst_assert = imx8mq_reset_assert; + priv->ops.rst_deassert = imx8mq_reset_deassert; } else if (device_is_compatible(dev, "fsl,imx7d-src")) { - priv->ops.rst_assert = imx7_reset_assert_imx7; - priv->ops.rst_deassert = imx7_reset_deassert_imx7; + priv->ops.rst_assert = imx7_reset_assert; + priv->ops.rst_deassert = imx7_reset_deassert; + } else if (device_is_compatible(dev, "fsl,imx8mp-src")) { + priv->ops.rst_assert = imx8mp_reset_assert; + priv->ops.rst_deassert = imx8mp_reset_deassert; } return 0; @@ -300,5 +401,5 @@ U_BOOT_DRIVER(imx7_reset) = { .of_match = imx7_reset_ids, .ops = &imx7_reset_reset_ops, .probe = imx7_reset_probe, - .priv_auto = sizeof(struct imx7_reset_priv), + .priv_auto = sizeof(struct imx_reset_priv), }; |