diff options
Diffstat (limited to 'drivers/reset')
| -rw-r--r-- | drivers/reset/Kconfig | 30 | ||||
| -rw-r--r-- | drivers/reset/Makefile | 4 | ||||
| -rw-r--r-- | drivers/reset/reset-brcmstb-rescal.c | 103 | ||||
| -rw-r--r-- | drivers/reset/reset-brcmstb.c | 97 | ||||
| -rw-r--r-- | drivers/reset/reset-socfpga.c | 2 | ||||
| -rw-r--r-- | drivers/reset/rst-rk3506.c | 222 | ||||
| -rw-r--r-- | drivers/reset/stm32/stm32-reset-mp1.c | 2 | ||||
| -rw-r--r-- | drivers/reset/stm32/stm32-reset-mp21.c | 2 |
8 files changed, 455 insertions, 7 deletions
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index 2fd91d6299c..e7c0870c918 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -64,6 +64,22 @@ config RESET_BCM6345 help Support reset controller on BCM6345. +config RESET_BRCMSTB + depends on ARCH_BCM283X + bool "Generic Reset controller driver for Broadcom" + help + This enables reset controller for Broadcom devices. + If you wish to use reset resources managed by the Broadcom + Reset Controller, say Y here. Otherwise, say N. + +config RESET_BRCMSTB_RESCAL + depends on ARCH_BCM283X + bool "Generic Rescal Reset controller driver for Broadcom" + help + Support rescal reset controller on Broadcom. + If you wish to use reset resources managed by the Broadcom + Reset Controller, say Y here. Otherwise, say N. + config RESET_UNIPHIER bool "Reset controller driver for UniPhier SoCs" depends on ARCH_UNIPHIER @@ -100,6 +116,15 @@ config RESET_ROCKCHIP though is that some reset signals, like I2C or MISC reset multiple devices. +config SPL_RESET_ROCKCHIP + bool "SPL reset controller driver for Rockchip SoCs" + depends on SPL_DM_RESET && ARCH_ROCKCHIP && SPL_CLK + default y + help + Support for the reset controller on Rockchip SoCs in SPL. Select this + if you observe any reset-related warnings or errors when booting SPL, + such as when using UFS storage + config RESET_HSDK bool "Synopsys HSDK Reset Driver" depends on DM_RESET && TARGET_HSDK @@ -208,7 +233,7 @@ config RESET_RASPBERRYPI config RESET_SCMI bool "Enable SCMI reset domain driver" - select SCMI_FIRMWARE + depends on SCMI_FIRMWARE help Enable this option if you want to support reset controller devices exposed by a SCMI agent based on SCMI reset domain @@ -239,8 +264,7 @@ config RESET_AT91 config RESET_RZG2L_USBPHY_CTRL bool "Enable support for Renesas RZ/G2L USB 2.0 PHY control" - depends on DM_RESET - select REGULATOR_RZG2L_USBPHY + depends on DM_RESET && REGULATOR_RZG2L_USBPHY help Enable support for controlling USB 2.0 PHY resets on the Renesas RZ/G2L SoC. This is required for USB 2.0 functionality to work on this diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile index ee5b009d134..2c83f858895 100644 --- a/drivers/reset/Makefile +++ b/drivers/reset/Makefile @@ -13,10 +13,12 @@ obj-$(CONFIG_RESET_AIROHA) += reset-airoha.o obj-$(CONFIG_RESET_TI_SCI) += reset-ti-sci.o obj-$(CONFIG_RESET_HSDK) += reset-hsdk.o obj-$(CONFIG_RESET_BCM6345) += reset-bcm6345.o +obj-$(CONFIG_RESET_BRCMSTB) += reset-brcmstb.o +obj-$(CONFIG_RESET_BRCMSTB_RESCAL) += reset-brcmstb-rescal.o obj-$(CONFIG_RESET_UNIPHIER) += reset-uniphier.o obj-$(CONFIG_RESET_AST2500) += reset-ast2500.o obj-$(CONFIG_RESET_AST2600) += reset-ast2600.o -obj-$(CONFIG_RESET_ROCKCHIP) += reset-rockchip.o rst-rk3528.o rst-rk3576.o rst-rk3588.o +obj-$(CONFIG_$(PHASE_)RESET_ROCKCHIP) += reset-rockchip.o rst-rk3506.o rst-rk3528.o rst-rk3576.o rst-rk3588.o obj-$(CONFIG_RESET_MESON) += reset-meson.o obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o obj-$(CONFIG_RESET_MEDIATEK) += reset-mediatek.o diff --git a/drivers/reset/reset-brcmstb-rescal.c b/drivers/reset/reset-brcmstb-rescal.c new file mode 100644 index 00000000000..fc8fcfa8b3f --- /dev/null +++ b/drivers/reset/reset-brcmstb-rescal.c @@ -0,0 +1,103 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Broadcom STB generic reset controller + * + * Copyright (C) 2024 EPAM Systems + * Moved from linux kernel: + * Copyright (C) 2018-2020 Broadcom + */ + +#include <asm/io.h> +#include <dm.h> +#include <dm/device_compat.h> +#include <errno.h> +#include <linux/bitops.h> +#include <linux/delay.h> +#include <linux/iopoll.h> +#include <log.h> +#include <malloc.h> +#include <reset-uclass.h> + +#define BRCM_RESCAL_START 0x0 +#define BRCM_RESCAL_START_BIT BIT(0) +#define BRCM_RESCAL_CTRL 0x4 +#define BRCM_RESCAL_STATUS 0x8 +#define BRCM_RESCAL_STATUS_BIT BIT(0) + +struct brcm_rescal_reset { + void __iomem *base; +}; + +/* Also doubles a deassert */ +static int brcm_rescal_reset_set(struct reset_ctl *rst) +{ + struct brcm_rescal_reset *data = dev_get_priv(rst->dev); + void __iomem *base = data->base; + u32 reg; + int ret; + + reg = readl(base + BRCM_RESCAL_START); + writel(reg | BRCM_RESCAL_START_BIT, base + BRCM_RESCAL_START); + reg = readl(base + BRCM_RESCAL_START); + if (!(reg & BRCM_RESCAL_START_BIT)) { + dev_err(rst->dev, "failed to start SATA/PCIe rescal\n"); + return -EIO; + } + + ret = readl_poll_timeout(base + BRCM_RESCAL_STATUS, reg, + (reg & BRCM_RESCAL_STATUS_BIT), 100); + if (ret) { + dev_err(rst->dev, "time out on SATA/PCIe rescal\n"); + return ret; + } + + reg = readl(base + BRCM_RESCAL_START); + writel(reg & ~BRCM_RESCAL_START_BIT, base + BRCM_RESCAL_START); + + dev_dbg(rst->dev, "SATA/PCIe rescal success\n"); + return 0; +} + +/* A dummy function - deassert/reset does all the work */ +static int brcm_rescal_reset_assert(struct reset_ctl *rst) +{ + return 0; +} + +static int brcm_rescal_reset_xlate(struct reset_ctl *reset_ctl, + struct ofnode_phandle_args *args) +{ + /* This is needed if #reset-cells == 0. */ + return 0; +} + +static const struct reset_ops brcm_rescal_reset_ops = { + .rst_deassert = brcm_rescal_reset_set, + .rst_assert = brcm_rescal_reset_assert, + .of_xlate = brcm_rescal_reset_xlate, +}; + +static int brcm_rescal_reset_probe(struct udevice *dev) +{ + struct brcm_rescal_reset *data = dev_get_priv(dev); + + data->base = dev_remap_addr(dev); + if (!data->base) + return -EINVAL; + + return 0; +} + +static const struct udevice_id brcm_rescal_reset_of_match[] = { + {.compatible = "brcm,bcm7216-pcie-sata-rescal"}, + {}, +}; + +U_BOOT_DRIVER(brcmstb_reset_rescal) = { + .name = "brcmstb-reset-rescal", + .id = UCLASS_RESET, + .of_match = brcm_rescal_reset_of_match, + .ops = &brcm_rescal_reset_ops, + .probe = brcm_rescal_reset_probe, + .priv_auto = sizeof(struct brcm_rescal_reset), +}; diff --git a/drivers/reset/reset-brcmstb.c b/drivers/reset/reset-brcmstb.c new file mode 100644 index 00000000000..7861f7c9baf --- /dev/null +++ b/drivers/reset/reset-brcmstb.c @@ -0,0 +1,97 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Broadcom STB generic reset controller + * + * Copyright (C) 2024 EPAM Systems + * + * Moved from linux kernel: + * Author: Florian Fainelli <f.fainelli@gmail.com> + * Copyright (C) 2018 Broadcom + */ + +#include <asm/io.h> +#include <dm.h> +#include <errno.h> +#include <linux/bitops.h> +#include <linux/delay.h> +#include <log.h> +#include <malloc.h> +#include <reset-uclass.h> + +struct brcmstb_reset { + void __iomem *base; +}; + +#define SW_INIT_SET 0x00 +#define SW_INIT_CLEAR 0x04 +#define SW_INIT_STATUS 0x08 + +#define SW_INIT_BIT(id) BIT((id) & 0x1f) +#define SW_INIT_BANK(id) ((id) >> 5) + +#define usleep_range(a, b) udelay((b)) + +/* A full bank contains extra registers that we are not utilizing but still + * qualify as a single bank. + */ +#define SW_INIT_BANK_SIZE 0x18 + +static int brcmstb_reset_assert(struct reset_ctl *rst) +{ + unsigned int off = SW_INIT_BANK(rst->id) * SW_INIT_BANK_SIZE; + struct brcmstb_reset *priv = dev_get_priv(rst->dev); + + writel_relaxed(SW_INIT_BIT(rst->id), priv->base + off + SW_INIT_SET); + return 0; +} + +static int brcmstb_reset_deassert(struct reset_ctl *rst) +{ + unsigned int off = SW_INIT_BANK(rst->id) * SW_INIT_BANK_SIZE; + struct brcmstb_reset *priv = dev_get_priv(rst->dev); + + writel_relaxed(SW_INIT_BIT(rst->id), priv->base + off + SW_INIT_CLEAR); + /* Maximum reset delay after de-asserting a line and seeing block + * operation is typically 14us for the worst case, build some slack + * here. + */ + usleep_range(100, 200); + return 0; +} + +static int brcmstb_reset_status(struct reset_ctl *rst) +{ + unsigned int off = SW_INIT_BANK(rst->id) * SW_INIT_BANK_SIZE; + struct brcmstb_reset *priv = dev_get_priv(rst->dev); + + return readl_relaxed(priv->base + off + SW_INIT_STATUS) & + SW_INIT_BIT(rst->id); +} + +struct reset_ops brcmstb_reset_reset_ops = { + .rst_assert = brcmstb_reset_assert, + .rst_deassert = brcmstb_reset_deassert, + .rst_status = brcmstb_reset_status}; + +static int brcmstb_reset_probe(struct udevice *dev) +{ + struct brcmstb_reset *priv = dev_get_priv(dev); + + priv->base = dev_remap_addr(dev); + if (!priv->base) + return -EINVAL; + + return 0; +} + +static const struct udevice_id brcmstb_reset_ids[] = { + {.compatible = "brcm,brcmstb-reset"}, {/* sentinel */}}; + +U_BOOT_DRIVER(brcmstb_reset) = { + .name = "brcmstb-reset", + .id = UCLASS_RESET, + .of_match = brcmstb_reset_ids, + .ops = &brcmstb_reset_reset_ops, + .probe = brcmstb_reset_probe, + .priv_auto = sizeof(struct brcmstb_reset), +}; diff --git a/drivers/reset/reset-socfpga.c b/drivers/reset/reset-socfpga.c index e57729f0ef9..36a205f9fca 100644 --- a/drivers/reset/reset-socfpga.c +++ b/drivers/reset/reset-socfpga.c @@ -115,7 +115,7 @@ static int socfpga_reset_remove(struct udevice *dev) if (socfpga_reset_keep_enabled()) { puts("Deasserting all peripheral resets\n"); writel(0, data->modrst_base + 4); - if (IS_ENABLED(CONFIG_TARGET_SOCFPGA_ARRIA10)) + if (IS_ENABLED(CONFIG_ARCH_SOCFPGA_ARRIA10)) writel(0, data->modrst_base + 8); } diff --git a/drivers/reset/rst-rk3506.c b/drivers/reset/rst-rk3506.c new file mode 100644 index 00000000000..9c384db0589 --- /dev/null +++ b/drivers/reset/rst-rk3506.c @@ -0,0 +1,222 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2025 Rockchip Electronics Co., Ltd. + * Author: Finley Xiao <finley.xiao@rock-chips.com> + */ + +#include <dm.h> +#include <asm/arch-rockchip/clock.h> +#include <dt-bindings/reset/rockchip,rk3506-cru.h> + +/* 0xFF9A0000 + 0x0A00 */ +#define RK3506_CRU_RESET_OFFSET(id, reg, bit) [id] = (0 + reg * 16 + bit) + +/* mapping table for reset ID to register offset */ +static const int rk3506_register_offset[] = { + /* CRU-->SOFTRST_CON00 */ + RK3506_CRU_RESET_OFFSET(SRST_NCOREPORESET0_AC, 0, 0), + RK3506_CRU_RESET_OFFSET(SRST_NCOREPORESET1_AC, 0, 1), + RK3506_CRU_RESET_OFFSET(SRST_NCOREPORESET2_AC, 0, 2), + RK3506_CRU_RESET_OFFSET(SRST_NCORESET0_AC, 0, 4), + RK3506_CRU_RESET_OFFSET(SRST_NCORESET1_AC, 0, 5), + RK3506_CRU_RESET_OFFSET(SRST_NCORESET2_AC, 0, 6), + RK3506_CRU_RESET_OFFSET(SRST_NL2RESET_AC, 0, 8), + RK3506_CRU_RESET_OFFSET(SRST_A_CORE_BIU_AC, 0, 9), + RK3506_CRU_RESET_OFFSET(SRST_H_M0_AC, 0, 10), + + /* CRU-->SOFTRST_CON02 */ + RK3506_CRU_RESET_OFFSET(SRST_NDBGRESET, 2, 10), + RK3506_CRU_RESET_OFFSET(SRST_P_CORE_BIU, 2, 14), + RK3506_CRU_RESET_OFFSET(SRST_PMU, 2, 15), + + /* CRU-->SOFTRST_CON03 */ + RK3506_CRU_RESET_OFFSET(SRST_P_DBG, 3, 1), + RK3506_CRU_RESET_OFFSET(SRST_POT_DBG, 3, 2), + RK3506_CRU_RESET_OFFSET(SRST_P_CORE_GRF, 3, 4), + RK3506_CRU_RESET_OFFSET(SRST_CORE_EMA_DETECT, 3, 6), + RK3506_CRU_RESET_OFFSET(SRST_REF_PVTPLL_CORE, 3, 7), + RK3506_CRU_RESET_OFFSET(SRST_P_GPIO1, 3, 8), + RK3506_CRU_RESET_OFFSET(SRST_DB_GPIO1, 3, 9), + + /* CRU-->SOFTRST_CON04 */ + RK3506_CRU_RESET_OFFSET(SRST_A_CORE_PERI_BIU, 4, 3), + RK3506_CRU_RESET_OFFSET(SRST_A_DSMC, 4, 5), + RK3506_CRU_RESET_OFFSET(SRST_P_DSMC, 4, 6), + RK3506_CRU_RESET_OFFSET(SRST_FLEXBUS, 4, 7), + RK3506_CRU_RESET_OFFSET(SRST_A_FLEXBUS, 4, 9), + RK3506_CRU_RESET_OFFSET(SRST_H_FLEXBUS, 4, 10), + RK3506_CRU_RESET_OFFSET(SRST_A_DSMC_SLV, 4, 11), + RK3506_CRU_RESET_OFFSET(SRST_H_DSMC_SLV, 4, 12), + RK3506_CRU_RESET_OFFSET(SRST_DSMC_SLV, 4, 13), + + /* CRU-->SOFTRST_CON05 */ + RK3506_CRU_RESET_OFFSET(SRST_A_BUS_BIU, 5, 3), + RK3506_CRU_RESET_OFFSET(SRST_H_BUS_BIU, 5, 4), + RK3506_CRU_RESET_OFFSET(SRST_P_BUS_BIU, 5, 5), + RK3506_CRU_RESET_OFFSET(SRST_A_SYSRAM, 5, 6), + RK3506_CRU_RESET_OFFSET(SRST_H_SYSRAM, 5, 7), + RK3506_CRU_RESET_OFFSET(SRST_A_DMAC0, 5, 8), + RK3506_CRU_RESET_OFFSET(SRST_A_DMAC1, 5, 9), + RK3506_CRU_RESET_OFFSET(SRST_H_M0, 5, 10), + RK3506_CRU_RESET_OFFSET(SRST_M0_JTAG, 5, 11), + RK3506_CRU_RESET_OFFSET(SRST_H_CRYPTO, 5, 15), + + /* CRU-->SOFTRST_CON06 */ + RK3506_CRU_RESET_OFFSET(SRST_H_RNG, 6, 0), + RK3506_CRU_RESET_OFFSET(SRST_P_BUS_GRF, 6, 1), + RK3506_CRU_RESET_OFFSET(SRST_P_TIMER0, 6, 2), + RK3506_CRU_RESET_OFFSET(SRST_TIMER0_CH0, 6, 3), + RK3506_CRU_RESET_OFFSET(SRST_TIMER0_CH1, 6, 4), + RK3506_CRU_RESET_OFFSET(SRST_TIMER0_CH2, 6, 5), + RK3506_CRU_RESET_OFFSET(SRST_TIMER0_CH3, 6, 6), + RK3506_CRU_RESET_OFFSET(SRST_TIMER0_CH4, 6, 7), + RK3506_CRU_RESET_OFFSET(SRST_TIMER0_CH5, 6, 8), + RK3506_CRU_RESET_OFFSET(SRST_P_WDT0, 6, 9), + RK3506_CRU_RESET_OFFSET(SRST_T_WDT0, 6, 10), + RK3506_CRU_RESET_OFFSET(SRST_P_WDT1, 6, 11), + RK3506_CRU_RESET_OFFSET(SRST_T_WDT1, 6, 12), + RK3506_CRU_RESET_OFFSET(SRST_P_MAILBOX, 6, 13), + RK3506_CRU_RESET_OFFSET(SRST_P_INTMUX, 6, 14), + RK3506_CRU_RESET_OFFSET(SRST_P_SPINLOCK, 6, 15), + + /* CRU-->SOFTRST_CON07 */ + RK3506_CRU_RESET_OFFSET(SRST_P_DDRC, 7, 0), + RK3506_CRU_RESET_OFFSET(SRST_H_DDRPHY, 7, 1), + RK3506_CRU_RESET_OFFSET(SRST_P_DDRMON, 7, 2), + RK3506_CRU_RESET_OFFSET(SRST_DDRMON_OSC, 7, 3), + RK3506_CRU_RESET_OFFSET(SRST_P_DDR_LPC, 7, 4), + RK3506_CRU_RESET_OFFSET(SRST_H_USBOTG0, 7, 5), + RK3506_CRU_RESET_OFFSET(SRST_USBOTG0_ADP, 7, 7), + RK3506_CRU_RESET_OFFSET(SRST_H_USBOTG1, 7, 8), + RK3506_CRU_RESET_OFFSET(SRST_USBOTG1_ADP, 7, 10), + RK3506_CRU_RESET_OFFSET(SRST_P_USBPHY, 7, 11), + RK3506_CRU_RESET_OFFSET(SRST_USBPHY_POR, 7, 12), + RK3506_CRU_RESET_OFFSET(SRST_USBPHY_OTG0, 7, 13), + RK3506_CRU_RESET_OFFSET(SRST_USBPHY_OTG1, 7, 14), + + /* CRU-->SOFTRST_CON08 */ + RK3506_CRU_RESET_OFFSET(SRST_A_DMA2DDR, 8, 0), + RK3506_CRU_RESET_OFFSET(SRST_P_DMA2DDR, 8, 1), + + /* CRU-->SOFTRST_CON09 */ + RK3506_CRU_RESET_OFFSET(SRST_USBOTG0_UTMI, 9, 0), + RK3506_CRU_RESET_OFFSET(SRST_USBOTG1_UTMI, 9, 1), + + /* CRU-->SOFTRST_CON10 */ + RK3506_CRU_RESET_OFFSET(SRST_A_DDRC_0, 10, 0), + RK3506_CRU_RESET_OFFSET(SRST_A_DDRC_1, 10, 1), + RK3506_CRU_RESET_OFFSET(SRST_A_DDR_BIU, 10, 2), + RK3506_CRU_RESET_OFFSET(SRST_DDRC, 10, 3), + RK3506_CRU_RESET_OFFSET(SRST_DDRMON, 10, 4), + + /* CRU-->SOFTRST_CON11 */ + RK3506_CRU_RESET_OFFSET(SRST_H_LSPERI_BIU, 11, 2), + RK3506_CRU_RESET_OFFSET(SRST_P_UART0, 11, 4), + RK3506_CRU_RESET_OFFSET(SRST_P_UART1, 11, 5), + RK3506_CRU_RESET_OFFSET(SRST_P_UART2, 11, 6), + RK3506_CRU_RESET_OFFSET(SRST_P_UART3, 11, 7), + RK3506_CRU_RESET_OFFSET(SRST_P_UART4, 11, 8), + RK3506_CRU_RESET_OFFSET(SRST_UART0, 11, 9), + RK3506_CRU_RESET_OFFSET(SRST_UART1, 11, 10), + RK3506_CRU_RESET_OFFSET(SRST_UART2, 11, 11), + RK3506_CRU_RESET_OFFSET(SRST_UART3, 11, 12), + RK3506_CRU_RESET_OFFSET(SRST_UART4, 11, 13), + RK3506_CRU_RESET_OFFSET(SRST_P_I2C0, 11, 14), + RK3506_CRU_RESET_OFFSET(SRST_I2C0, 11, 15), + + /* CRU-->SOFTRST_CON12 */ + RK3506_CRU_RESET_OFFSET(SRST_P_I2C1, 12, 0), + RK3506_CRU_RESET_OFFSET(SRST_I2C1, 12, 1), + RK3506_CRU_RESET_OFFSET(SRST_P_I2C2, 12, 2), + RK3506_CRU_RESET_OFFSET(SRST_I2C2, 12, 3), + RK3506_CRU_RESET_OFFSET(SRST_P_PWM1, 12, 4), + RK3506_CRU_RESET_OFFSET(SRST_PWM1, 12, 5), + RK3506_CRU_RESET_OFFSET(SRST_P_SPI0, 12, 10), + RK3506_CRU_RESET_OFFSET(SRST_SPI0, 12, 11), + RK3506_CRU_RESET_OFFSET(SRST_P_SPI1, 12, 12), + RK3506_CRU_RESET_OFFSET(SRST_SPI1, 12, 13), + RK3506_CRU_RESET_OFFSET(SRST_P_GPIO2, 12, 14), + RK3506_CRU_RESET_OFFSET(SRST_DB_GPIO2, 12, 15), + + /* CRU-->SOFTRST_CON13 */ + RK3506_CRU_RESET_OFFSET(SRST_P_GPIO3, 13, 0), + RK3506_CRU_RESET_OFFSET(SRST_DB_GPIO3, 13, 1), + RK3506_CRU_RESET_OFFSET(SRST_P_GPIO4, 13, 2), + RK3506_CRU_RESET_OFFSET(SRST_DB_GPIO4, 13, 3), + RK3506_CRU_RESET_OFFSET(SRST_H_CAN0, 13, 4), + RK3506_CRU_RESET_OFFSET(SRST_CAN0, 13, 5), + RK3506_CRU_RESET_OFFSET(SRST_H_CAN1, 13, 6), + RK3506_CRU_RESET_OFFSET(SRST_CAN1, 13, 7), + RK3506_CRU_RESET_OFFSET(SRST_H_PDM, 13, 8), + RK3506_CRU_RESET_OFFSET(SRST_M_PDM, 13, 9), + RK3506_CRU_RESET_OFFSET(SRST_PDM, 13, 10), + RK3506_CRU_RESET_OFFSET(SRST_SPDIFTX, 13, 11), + RK3506_CRU_RESET_OFFSET(SRST_H_SPDIFTX, 13, 12), + RK3506_CRU_RESET_OFFSET(SRST_H_SPDIFRX, 13, 13), + RK3506_CRU_RESET_OFFSET(SRST_SPDIFRX, 13, 14), + RK3506_CRU_RESET_OFFSET(SRST_M_SAI0, 13, 15), + + /* CRU-->SOFTRST_CON14 */ + RK3506_CRU_RESET_OFFSET(SRST_H_SAI0, 14, 0), + RK3506_CRU_RESET_OFFSET(SRST_M_SAI1, 14, 2), + RK3506_CRU_RESET_OFFSET(SRST_H_SAI1, 14, 3), + RK3506_CRU_RESET_OFFSET(SRST_H_ASRC0, 14, 5), + RK3506_CRU_RESET_OFFSET(SRST_ASRC0, 14, 6), + RK3506_CRU_RESET_OFFSET(SRST_H_ASRC1, 14, 7), + RK3506_CRU_RESET_OFFSET(SRST_ASRC1, 14, 8), + + /* CRU-->SOFTRST_CON17 */ + RK3506_CRU_RESET_OFFSET(SRST_H_HSPERI_BIU, 17, 4), + RK3506_CRU_RESET_OFFSET(SRST_H_SDMMC, 17, 7), + RK3506_CRU_RESET_OFFSET(SRST_H_FSPI, 17, 8), + RK3506_CRU_RESET_OFFSET(SRST_S_FSPI, 17, 9), + RK3506_CRU_RESET_OFFSET(SRST_P_SPI2, 17, 10), + RK3506_CRU_RESET_OFFSET(SRST_A_MAC0, 17, 11), + RK3506_CRU_RESET_OFFSET(SRST_A_MAC1, 17, 12), + + /* CRU-->SOFTRST_CON18 */ + RK3506_CRU_RESET_OFFSET(SRST_M_SAI2, 18, 2), + RK3506_CRU_RESET_OFFSET(SRST_H_SAI2, 18, 3), + RK3506_CRU_RESET_OFFSET(SRST_H_SAI3, 18, 6), + RK3506_CRU_RESET_OFFSET(SRST_M_SAI3, 18, 7), + RK3506_CRU_RESET_OFFSET(SRST_H_SAI4, 18, 10), + RK3506_CRU_RESET_OFFSET(SRST_M_SAI4, 18, 11), + RK3506_CRU_RESET_OFFSET(SRST_H_DSM, 18, 12), + RK3506_CRU_RESET_OFFSET(SRST_M_DSM, 18, 13), + RK3506_CRU_RESET_OFFSET(SRST_P_AUDIO_ADC, 18, 14), + RK3506_CRU_RESET_OFFSET(SRST_M_AUDIO_ADC, 18, 15), + + /* CRU-->SOFTRST_CON19 */ + RK3506_CRU_RESET_OFFSET(SRST_P_SARADC, 19, 0), + RK3506_CRU_RESET_OFFSET(SRST_SARADC, 19, 1), + RK3506_CRU_RESET_OFFSET(SRST_SARADC_PHY, 19, 2), + RK3506_CRU_RESET_OFFSET(SRST_P_OTPC_NS, 19, 3), + RK3506_CRU_RESET_OFFSET(SRST_SBPI_OTPC_NS, 19, 4), + RK3506_CRU_RESET_OFFSET(SRST_USER_OTPC_NS, 19, 5), + RK3506_CRU_RESET_OFFSET(SRST_P_UART5, 19, 6), + RK3506_CRU_RESET_OFFSET(SRST_UART5, 19, 7), + RK3506_CRU_RESET_OFFSET(SRST_P_GPIO234_IOC, 19, 8), + + /* CRU-->SOFTRST_CON21 */ + RK3506_CRU_RESET_OFFSET(SRST_A_VIO_BIU, 21, 3), + RK3506_CRU_RESET_OFFSET(SRST_H_VIO_BIU, 21, 4), + RK3506_CRU_RESET_OFFSET(SRST_H_RGA, 21, 6), + RK3506_CRU_RESET_OFFSET(SRST_A_RGA, 21, 7), + RK3506_CRU_RESET_OFFSET(SRST_CORE_RGA, 21, 8), + RK3506_CRU_RESET_OFFSET(SRST_A_VOP, 21, 9), + RK3506_CRU_RESET_OFFSET(SRST_H_VOP, 21, 10), + RK3506_CRU_RESET_OFFSET(SRST_VOP, 21, 11), + RK3506_CRU_RESET_OFFSET(SRST_P_DPHY, 21, 12), + RK3506_CRU_RESET_OFFSET(SRST_P_DSI_HOST, 21, 13), + RK3506_CRU_RESET_OFFSET(SRST_P_TSADC, 21, 14), + RK3506_CRU_RESET_OFFSET(SRST_TSADC, 21, 15), + + /* CRU-->SOFTRST_CON22 */ + RK3506_CRU_RESET_OFFSET(SRST_P_GPIO1_IOC, 22, 1), +}; + +int rk3506_reset_bind_lut(struct udevice *pdev, u32 reg_offset, u32 reg_number) +{ + return rockchip_reset_bind_lut(pdev, rk3506_register_offset, + reg_offset, reg_number); +} diff --git a/drivers/reset/stm32/stm32-reset-mp1.c b/drivers/reset/stm32/stm32-reset-mp1.c index ce4532561e5..e7ac2c6f066 100644 --- a/drivers/reset/stm32/stm32-reset-mp1.c +++ b/drivers/reset/stm32/stm32-reset-mp1.c @@ -46,7 +46,7 @@ static int stm32_reset_probe(struct udevice *dev) return stm32_reset_core_probe(dev, &stm32mp1_reset_data); } -U_BOOT_DRIVER(stm32mp25_rcc_reset) = { +U_BOOT_DRIVER(stm32mp1_rcc_reset) = { .name = "stm32mp1_reset", .id = UCLASS_RESET, .probe = stm32_reset_probe, diff --git a/drivers/reset/stm32/stm32-reset-mp21.c b/drivers/reset/stm32/stm32-reset-mp21.c index 7d169d7582f..0e92b0f5d5d 100644 --- a/drivers/reset/stm32/stm32-reset-mp21.c +++ b/drivers/reset/stm32/stm32-reset-mp21.c @@ -5,7 +5,7 @@ */ #include <dm.h> -#include <stm32-reset-core.h> +#include "stm32-reset-core.h" #include <stm32mp21_rcc.h> #include <dt-bindings/reset/st,stm32mp21-rcc.h> |