diff options
Diffstat (limited to 'drivers')
70 files changed, 4778 insertions, 235 deletions
diff --git a/drivers/adc/imx93-adc.c b/drivers/adc/imx93-adc.c index f593fb6447b..d671df79f68 100644 --- a/drivers/adc/imx93-adc.c +++ b/drivers/adc/imx93-adc.c @@ -221,7 +221,7 @@ static int imx93_adc_stop(struct udevice *dev) static int imx93_adc_probe(struct udevice *dev) { struct imx93_adc_priv *adc = dev_get_priv(dev); - unsigned int ret; + int ret; ret = imx93_adc_calibration(adc); if (ret < 0) @@ -238,7 +238,7 @@ static int imx93_adc_of_to_plat(struct udevice *dev) { struct adc_uclass_plat *uc_pdata = dev_get_uclass_plat(dev); struct imx93_adc_priv *adc = dev_get_priv(dev); - unsigned int ret; + int ret; adc->regs = dev_read_addr_ptr(dev); if (adc->regs == (struct imx93_adc *)FDT_ADDR_T_NONE) { diff --git a/drivers/block/Kconfig b/drivers/block/Kconfig index 750b0bd2082..c6c148ebd17 100644 --- a/drivers/block/Kconfig +++ b/drivers/block/Kconfig @@ -96,7 +96,7 @@ config TPL_BLOCK_CACHE config EFI_MEDIA bool "Support EFI media drivers" - default y if EFI || SANDBOX + default y if EFI_CLIENT || SANDBOX select BLK help Enable this to support media devices on top of UEFI. This enables diff --git a/drivers/block/blk-uclass.c b/drivers/block/blk-uclass.c index f3ac8db9464..73c24fd9176 100644 --- a/drivers/block/blk-uclass.c +++ b/drivers/block/blk-uclass.c @@ -611,30 +611,6 @@ static int blk_flags_check(struct udevice *dev, enum blk_flag_t req_flags) return flags & req_flags ? 0 : 1; } -int blk_find_first(enum blk_flag_t flags, struct udevice **devp) -{ - int ret; - - for (ret = uclass_find_first_device(UCLASS_BLK, devp); - *devp && !blk_flags_check(*devp, flags); - ret = uclass_find_next_device(devp)) - return 0; - - return -ENODEV; -} - -int blk_find_next(enum blk_flag_t flags, struct udevice **devp) -{ - int ret; - - for (ret = uclass_find_next_device(devp); - *devp && !blk_flags_check(*devp, flags); - ret = uclass_find_next_device(devp)) - return 0; - - return -ENODEV; -} - int blk_first_device_err(enum blk_flag_t flags, struct udevice **devp) { for (uclass_first_device(UCLASS_BLK, devp); diff --git a/drivers/clk/at91/Makefile b/drivers/clk/at91/Makefile index 6cca861f81c..96cc2bc3abc 100644 --- a/drivers/clk/at91/Makefile +++ b/drivers/clk/at91/Makefile @@ -11,6 +11,7 @@ obj-$(CONFIG_AT91_UTMI) += clk-utmi.o obj-$(CONFIG_AT91_SAM9X60_PLL) += clk-sam9x60-pll.o obj-$(CONFIG_AT91_SAM9X60_USB) += clk-sam9x60-usb.o obj-$(CONFIG_SAMA7G5) += sama7g5.o +obj-$(CONFIG_SAMA7D65) += sama7d65.o obj-$(CONFIG_SAM9X60) += sam9x60.o obj-$(CONFIG_SAM9X7) += sam9x7.o else diff --git a/drivers/clk/at91/clk-master.c b/drivers/clk/at91/clk-master.c index d28775d64d3..cdc5271fa83 100644 --- a/drivers/clk/at91/clk-master.c +++ b/drivers/clk/at91/clk-master.c @@ -37,7 +37,7 @@ #define PMC_MCR_ID(x) ((x) & PMC_MCR_ID_MSK) -#define MASTER_MAX_ID 4 +#define MASTER_MAX_ID 10 struct clk_master { void __iomem *base; diff --git a/drivers/clk/at91/clk-sam9x60-pll.c b/drivers/clk/at91/clk-sam9x60-pll.c index df8172bccac..65be2775ac3 100644 --- a/drivers/clk/at91/clk-sam9x60-pll.c +++ b/drivers/clk/at91/clk-sam9x60-pll.c @@ -32,7 +32,7 @@ #define UPLL_DIV 2 #define PLL_MUL_MAX (FIELD_GET(PMC_PLL_CTRL1_MUL_MSK, UINT_MAX) + 1) -#define PLL_MAX_ID 7 +#define PLL_MAX_ID 8 struct sam9x60_pll { void __iomem *base; diff --git a/drivers/clk/at91/sama7d65.c b/drivers/clk/at91/sama7d65.c new file mode 100644 index 00000000000..8d2c25e6fa9 --- /dev/null +++ b/drivers/clk/at91/sama7d65.c @@ -0,0 +1,1451 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * SAMA7D65 PMC clock support. + * + * Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries + * + * Author: Ryan Wanner <Ryan.Wanner@microchip.com> + * + */ + +#include <clk-uclass.h> +#include <dm.h> +#include <dt-bindings/clock/at91.h> +#include <linux/clk-provider.h> + +#include "pmc.h" + +/** + * Clock identifiers to be used in conjunction with macros like + * AT91_TO_CLK_ID() + * + * @ID_MD_SLCK: TD slow clock identifier + * @ID_TD_SLCK: MD slow clock identifier + * @ID_MAIN_XTAL: Main Xtal clock identifier + * @ID_MAIN_RC: Main RC clock identifier + * @ID_MAIN_RC_OSC: Main RC Oscillator clock identifier + * @ID_MAIN_OSC: Main Oscillator clock identifier + * @ID_MAINCK: MAINCK clock identifier + * @ID_PLL_CPU_FRAC: CPU PLL fractional clock identifier + * @ID_PLL_CPU_DIV: CPU PLL divider clock identifier + * @ID_PLL_SYS_FRAC: SYS PLL fractional clock identifier + * @ID_PLL_SYS_DIV: SYS PLL divider clock identifier + * @ID_PLL_DDR_FRAC: DDR PLL fractional clock identifier + * @ID_PLL_DDR_DIV: DDR PLL divider clock identifier + * @ID_PLL_GPU_FRAC: GPU PLL fractional clock identifier + * @ID_PLL_GPU_DIV: GPU PLL divider clock identifier + * @ID_PLL_BAUD_FRAC: Baud PLL fractional clock identifier + * @ID_PLL_BAUD_DIV: Baud PLL divider clock identifier + * @ID_PLL_AUDIO_FRAC: Audio PLL fractional clock identifier + * @ID_PLL_AUDIO_DIVPMC: Audio PLL PMC divider clock identifier + * @ID_PLL_AUDIO_DIVIO: Audio PLL IO divider clock identifier + * @ID_PLL_ETH_FRAC: Ethernet PLL fractional clock identifier + * @ID_PLL_ETH_DIV: Ethernet PLL divider clock identifier + * @ID_PLL_LVDS_FRAC: LVDS PLL fractional clock identifier + * @ID_PLL_LVDS_DIV: LVDS PLL divider clock identifier + * @ID_PLL_USB_FRAC: USB PLL fractional clock identifier + * @ID_PLL_USB_DIV: USB PLL divider clock identifier + + * @ID_MCK0_PRES: MCK0 PRES clock identifier + * @ID_MCK0_DIV: MCK0 DIV clock identifier + * @ID_MCK1: MCK1 clock identifier + * @ID_MCK2: MCK2 clock identifier + * @ID_MCK3: MCK3 clock identifier + * @ID_MCK4: MCK4 clock identifier + + * @ID_UTMI: UTMI clock identifier + + * @ID_PROG0: Programmable 0 clock identifier + * @ID_PROG1: Programmable 1 clock identifier + * @ID_PROG2: Programmable 2 clock identifier + * @ID_PROG3: Programmable 3 clock identifier + * @ID_PROG4: Programmable 4 clock identifier + * @ID_PROG5: Programmable 5 clock identifier + * @ID_PROG6: Programmable 6 clock identifier + * @ID_PROG7: Programmable 7 clock identifier + + * @ID_PCK0: System clock 0 clock identifier + * @ID_PCK1: System clock 1 clock identifier + * @ID_PCK2: System clock 2 clock identifier + * @ID_PCK3: System clock 3 clock identifier + * @ID_PCK4: System clock 4 clock identifier + * @ID_PCK5: System clock 5 clock identifier + * @ID_PCK6: System clock 6 clock identifier + * @ID_PCK7: System clock 7 clock identifier + */ +enum pmc_clk_ids { + ID_MD_SLCK = 0, + ID_TD_SLCK = 1, + ID_MAIN_XTAL = 2, + ID_MAIN_RC = 3, + ID_MAIN_RC_OSC = 4, + ID_MAIN_OSC = 5, + ID_MAINCK = 6, + + ID_PLL_CPU_FRAC = 7, + ID_PLL_CPU_DIV = 8, + ID_PLL_SYS_FRAC = 9, + ID_PLL_SYS_DIV = 10, + ID_PLL_DDR_FRAC = 11, + ID_PLL_DDR_DIV = 12, + ID_PLL_GPU_FRAC = 13, + ID_PLL_GPU_DIV = 14, + ID_PLL_BAUD_FRAC = 15, + ID_PLL_BAUD_DIV = 16, + ID_PLL_AUDIO_FRAC = 17, + ID_PLL_AUDIO_DIVPMC = 18, + ID_PLL_AUDIO_DIVIO = 19, + ID_PLL_ETH_FRAC = 20, + ID_PLL_ETH_DIV = 21, + ID_PLL_LVDS_FRAC = 22, + ID_PLL_LVDS_DIV = 23, + ID_PLL_USB_FRAC = 24, + ID_PLL_USB_DIV = 25, + + ID_MCK0_DIV = 26, + ID_MCK1 = 27, + ID_MCK2 = 28, + ID_MCK3 = 29, + ID_MCK4 = 30, + ID_MCK5 = 31, + ID_MCK6 = 32, + ID_MCK7 = 33, + ID_MCK8 = 34, + ID_MCK9 = 35, + + ID_UTMI = 36, + + ID_PROG0 = 37, + ID_PROG1 = 38, + ID_PROG2 = 39, + ID_PROG3 = 40, + ID_PROG4 = 41, + ID_PROG5 = 42, + ID_PROG6 = 43, + ID_PROG7 = 44, + + ID_PCK0 = 45, + ID_PCK1 = 46, + ID_PCK2 = 47, + ID_PCK3 = 48, + ID_PCK4 = 49, + ID_PCK5 = 50, + ID_PCK6 = 51, + ID_PCK7 = 52, + + ID_MCK0_PRES = 53, + + ID_MAX, +}; + +/** + * PLL type identifiers + * @PLL_TYPE_FRAC: fractional PLL identifier + * @PLL_TYPE_DIV: divider PLL identifier + */ +enum pll_type { + PLL_TYPE_FRAC, + PLL_TYPE_DIV, +}; + +/* Clock names used as parents for multiple clocks. */ +static const char *clk_names[] = { + [ID_MAIN_RC] = "main_rc", + [ID_MAIN_RC_OSC] = "main_rc_osc", + [ID_MAIN_OSC] = "main_osc", + [ID_MAINCK] = "mainck", + [ID_PLL_CPU_DIV] = "cpupll_divpmcck", + [ID_PLL_SYS_DIV] = "syspll_divpmcck", + [ID_PLL_DDR_DIV] = "ddrpll_divpmcck", + [ID_PLL_GPU_DIV] = "gpupll_divpmcck", + [ID_PLL_BAUD_DIV] = "baudpll_divpmcck", + [ID_PLL_AUDIO_DIVPMC] = "audiopll_divpmcck", + [ID_PLL_AUDIO_DIVIO] = "audiopll_diviock", + [ID_PLL_ETH_DIV] = "ethpll_divpmcck", + [ID_PLL_LVDS_DIV] = "lvdspll_divpmcck", + [ID_PLL_USB_DIV] = "usbpll_divpmcck", + [ID_MCK0_DIV] = "mck0_div", + [ID_MCK0_PRES] = "mck0_pres", +}; + +/* Fractional PLL output range. */ +static const struct clk_range pll_outputs[] = { + { .min = 2343750, .max = 1200000000 }, +}; + +/* Fractional PLL core output range. */ +static const struct clk_range core_outputs[] = { + { .min = 600000000, .max = 1200000000 }, +}; + +/* PLL characteristics. */ +static const struct clk_pll_characteristics pll_characteristics = { + .input = { .min = 12000000, .max = 50000000 }, + .num_output = ARRAY_SIZE(pll_outputs), + .output = pll_outputs, + .core_output = core_outputs, +}; + +/* Layout for fractional PLLs. */ +static const struct clk_pll_layout pll_layout_frac = { + .mul_mask = GENMASK(31, 24), + .frac_mask = GENMASK(21, 0), + .mul_shift = 24, + .frac_shift = 0, +}; + +/* Layout for DIVPMC dividers. */ +static const struct clk_pll_layout pll_layout_divpmc = { + .div_mask = GENMASK(7, 0), + .endiv_mask = BIT(29), + .div_shift = 0, + .endiv_shift = 29, +}; + +/* Layout for DIVIO dividers. */ +static const struct clk_pll_layout pll_layout_divio = { + .div_mask = GENMASK(19, 12), + .endiv_mask = BIT(30), + .div_shift = 12, + .endiv_shift = 30, +}; + +/* MCK0 characteristics. */ +static const struct clk_master_characteristics mck0_characteristics = { + .output = { .min = 140000000, .max = 200000000 }, + .divisors = { 1, 2, 4, 3, 5 }, + .have_div3_pres = 1, +}; + +/* MCK0 layout. */ +static const struct clk_master_layout mck0_layout = { + .mask = 0x773, + .pres_shift = 4, + .offset = 0x28, +}; + +/* Programmable clock layout. */ +static const struct clk_programmable_layout programmable_layout = { + .pres_mask = 0xff, + .pres_shift = 8, + .css_mask = 0x1f, + .have_slck_mck = 0, + .is_pres_direct = 1, +}; + +/* Peripheral clock layout. */ +static const struct clk_pcr_layout sama7d65_pcr_layout = { + .offset = 0x88, + .cmd = BIT(31), + .gckcss_mask = GENMASK(12, 8), + .pid_mask = GENMASK(6, 0), +}; + +/** + * PLL clocks description + * @n: clock name + * @p: clock parent + * @l: clock layout + * @t: clock type + * @c: true if clock is critical and cannot be disabled + * @id: clock id corresponding to PLL driver + * @cid: clock id corresponding to clock subsystem + */ +static const struct { + const char *n; + const char *p; + const struct clk_pll_layout *l; + u8 t; + u8 c; + u8 id; + u8 cid; +} sama7d65_plls[] = { + { + .n = "cpupll_fracck", + .p = "mainck", + .l = &pll_layout_frac, + .t = PLL_TYPE_FRAC, + .c = 1, + .id = 0, + .cid = ID_PLL_CPU_FRAC, + }, + + { + .n = "cpupll_divpmcck", + .p = "cpupll_fracck", + .l = &pll_layout_divpmc, + .t = PLL_TYPE_DIV, + .c = 1, + .id = 0, + .cid = ID_PLL_CPU_DIV, + }, + + { + .n = "syspll_fracck", + .p = "mainck", + .l = &pll_layout_frac, + .t = PLL_TYPE_FRAC, + .c = 1, + .id = 1, + .cid = ID_PLL_SYS_FRAC, + }, + + { + .n = "syspll_divpmcck", + .p = "syspll_fracck", + .l = &pll_layout_divpmc, + .t = PLL_TYPE_DIV, + .c = 1, + .id = 1, + .cid = ID_PLL_SYS_DIV, + }, + + { + .n = "ddrpll_fracck", + .p = "mainck", + .l = &pll_layout_frac, + .t = PLL_TYPE_FRAC, + .c = 1, + .id = 2, + .cid = ID_PLL_DDR_FRAC, + }, + + { + .n = "ddrpll_divpmcck", + .p = "ddrpll_fracck", + .l = &pll_layout_divpmc, + .t = PLL_TYPE_DIV, + .c = 1, + .id = 2, + .cid = ID_PLL_DDR_DIV, + }, + + { + .n = "gpupll_fracck", + .p = "mainck", + .l = &pll_layout_frac, + .t = PLL_TYPE_FRAC, + .id = 3, + .cid = ID_PLL_GPU_FRAC, + }, + + { + .n = "gpupll_divpmcck", + .p = "gpupll_fracck", + .l = &pll_layout_divpmc, + .t = PLL_TYPE_DIV, + .id = 3, + .cid = ID_PLL_GPU_DIV + }, + + { + .n = "baudpll_fracck", + .p = "mainck", + .l = &pll_layout_frac, + .t = PLL_TYPE_FRAC, + .id = 4, + .cid = ID_PLL_BAUD_FRAC, + }, + + { + .n = "baudpll_divpmcck", + .p = "baudpll_fracck", + .l = &pll_layout_divpmc, + .t = PLL_TYPE_DIV, + .id = 4, + .cid = ID_PLL_BAUD_DIV, + }, + + { + .n = "audiopll_fracck", + .p = "main_osc", + .l = &pll_layout_frac, + .t = PLL_TYPE_FRAC, + .id = 5, + .cid = ID_PLL_AUDIO_FRAC, + }, + + { + .n = "audiopll_divpmcck", + .p = "audiopll_fracck", + .l = &pll_layout_divpmc, + .t = PLL_TYPE_DIV, + .id = 5, + .cid = ID_PLL_AUDIO_DIVPMC, + }, + + { + .n = "audiopll_diviock", + .p = "audiopll_fracck", + .l = &pll_layout_divio, + .t = PLL_TYPE_DIV, + .id = 5, + .cid = ID_PLL_AUDIO_DIVIO, + }, + + { + .n = "ethpll_fracck", + .p = "main_osc", + .l = &pll_layout_frac, + .t = PLL_TYPE_FRAC, + .id = 6, + .cid = ID_PLL_ETH_FRAC, + }, + + { + .n = "ethpll_divpmcck", + .p = "ethpll_fracck", + .l = &pll_layout_divpmc, + .t = PLL_TYPE_DIV, + .id = 6, + .cid = ID_PLL_ETH_DIV, + }, + { + .n = "lvdspll_fracck", + .p = "main_osc", + .l = &pll_layout_frac, + .t = PLL_TYPE_FRAC, + .id = 7, + .cid = ID_PLL_LVDS_FRAC, + }, + { + .n = "lvdspll_divpmcck", + .p = "lvdspll_fracck", + .l = &pll_layout_divpmc, + .t = PLL_TYPE_DIV, + .id = 7, + .cid = ID_PLL_LVDS_DIV, + }, + { + .n = "usbpll_fracck", + .p = "main_osc", + .l = &pll_layout_frac, + .t = PLL_TYPE_FRAC, + .id = 8, + .cid = ID_PLL_USB_FRAC, + }, + { + .n = "usbpll_divmpcck", + .p = "usbpll_fracck", + .l = &pll_layout_divpmc, + .t = PLL_TYPE_DIV, + .id = 8, + .cid = ID_PLL_USB_DIV, + }, +}; + +/** + * Master clock (MCK[1..9]) description + * @n: clock name + * @ep: extra parents names array + * @ep_chg_chg_id: index in parents array that specifies the changeable + * parent + * @ep_count: extra parents count + * @ep_mux_table: mux table for extra parents + * @ep_clk_mux_table: mux table to deal with subsystem clock ids + * @id: clock id corresponding to MCK driver + * @cid: clock id corresponding to clock subsystem + * @c: true if clock is critical and cannot be disabled + */ +static const struct { + const char *n; + const char *ep[4]; + u8 ep_count; + u8 ep_mux_table[4]; + u8 ep_clk_mux_table[4]; + u8 id; + u8 cid; + u8 c; +} sama7d65_mckx[] = { + { + .n = "mck1", + .id = 1, + .cid = ID_MCK1, + .ep = { "syspll_divpmcck", }, + .ep_mux_table = { 5, }, + .ep_clk_mux_table = { ID_PLL_SYS_DIV, }, + .ep_count = 1, + .c = 1, + }, + + { + .n = "mck2", + .id = 2, + .cid = ID_MCK2, + .ep = { "syspll_divpmcck", "ddrpll_divpmcck", }, + .ep_mux_table = { 5, 6, }, + .ep_clk_mux_table = { ID_PLL_SYS_DIV, ID_PLL_DDR_DIV, }, + .ep_count = 2, + .c = 1, + }, + + { + .n = "mck3", + .id = 3, + .cid = ID_MCK3, + .ep = { "syspll_divpmcck", "ddrpll_divpmcck", }, + .ep_mux_table = { 5, 6, }, + .ep_clk_mux_table = { ID_PLL_SYS_DIV, ID_PLL_DDR_DIV, }, + .ep_count = 2, + }, + + { + .n = "mck4", + .id = 4, + .cid = ID_MCK4, + .ep = { "syspll_divpmcck", }, + .ep_mux_table = { 5, }, + .ep_clk_mux_table = { ID_PLL_SYS_DIV, }, + .ep_count = 1, + .c = 1, + }, + + { + .n = "mck5", + .id = 5, + .cid = ID_MCK5, + .ep = { "syspll_divpmcck", }, + .ep_mux_table = { 5, }, + .ep_clk_mux_table = { ID_PLL_SYS_DIV, }, + .ep_count = 1, + }, + + { + .n = "mck6", + .id = 6, + .cid = ID_MCK6, + .ep = { "syspll_divpmcck", }, + .ep_mux_table = { 5, }, + .ep_clk_mux_table = { ID_PLL_SYS_DIV, }, + .ep_count = 1, + .c = 1, + }, + + { + .n = "mck7", + .id = 7, + .cid = ID_MCK7, + .ep = { "syspll_divpmcck", }, + .ep_mux_table = { 5, }, + .ep_clk_mux_table = { ID_PLL_SYS_DIV, }, + .ep_count = 1, + .c = 1, + }, + + { + .n = "mck8", + .id = 8, + .cid = ID_MCK8, + .ep = { "syspll_divpmcck", }, + .ep_mux_table = { 5, }, + .ep_clk_mux_table = { ID_PLL_SYS_DIV, }, + .ep_count = 1, + .c = 1, + }, + + { + .n = "mck9", + .id = 9, + .cid = ID_MCK9, + .ep = { "syspll_divpmcck", }, + .ep_mux_table = { 5, }, + .ep_clk_mux_table = { ID_PLL_SYS_DIV, }, + .ep_count = 1, + }, + +}; + +/** + * Programmable clock description + * @n: clock name + * @cid: clock id corresponding to clock subsystem + */ +static const struct { + const char *n; + u8 cid; +} sama7d65_prog[] = { + { .n = "prog0", .cid = ID_PROG0, }, + { .n = "prog1", .cid = ID_PROG1, }, + { .n = "prog2", .cid = ID_PROG2, }, + { .n = "prog3", .cid = ID_PROG3, }, + { .n = "prog4", .cid = ID_PROG4, }, + { .n = "prog5", .cid = ID_PROG5, }, + { .n = "prog6", .cid = ID_PROG6, }, + { .n = "prog7", .cid = ID_PROG7, }, +}; + +/* Mux table for programmable clocks. */ +static u32 sama7d65_prog_mux_table[] = { 0, 1, 2, 3, 5, 7, 8, 9, 10, 12, }; + +/** + * System clock description + * @n: clock name + * @p: parent clock name + * @id: clock id corresponding to system clock driver + * @cid: clock id corresponding to clock subsystem + */ +static const struct { + const char *n; + const char *p; + u8 id; + u8 cid; +} sama7d65_systemck[] = { + { .n = "pck0", .p = "prog0", .id = 8, .cid = ID_PCK0, }, + { .n = "pck1", .p = "prog1", .id = 9, .cid = ID_PCK1, }, + { .n = "pck2", .p = "prog2", .id = 10, .cid = ID_PCK2, }, + { .n = "pck3", .p = "prog3", .id = 11, .cid = ID_PCK3, }, + { .n = "pck4", .p = "prog4", .id = 12, .cid = ID_PCK4, }, + { .n = "pck5", .p = "prog5", .id = 13, .cid = ID_PCK5, }, + { .n = "pck6", .p = "prog6", .id = 14, .cid = ID_PCK6, }, + { .n = "pck7", .p = "prog7", .id = 15, .cid = ID_PCK7, }, +}; + +/** + * Peripheral clock description + * @n: clock name + * @p: clock parent name + * @r: clock range values + * @id: clock id + */ +static const struct { + const char *n; + const char *p; + struct clk_range r; + u8 id; +} sama7d65_periphck[] = { + { .n = "pioA_clk", .p = "mck0_div", .id = 10, }, + { .n = "sfr_clk", .p = "mck7", .id = 18, }, + { .n = "hsmc_clk", .p = "mck5", .id = 20, }, + { .n = "xdmac0_clk", .p = "mck6", .id = 21, }, + { .n = "xdmac1_clk", .p = "mck6", .id = 22, }, + { .n = "xdmac2_clk", .p = "mck1", .id = 23, }, + { .n = "acc_clk", .p = "mck7", .id = 24, }, + { .n = "aes_clk", .p = "mck6", .id = 26, }, + { .n = "tzaesbasc_clk", .p = "mck8", .id = 27, }, + { .n = "asrc_clk", .p = "mck9", .id = 29, .r = { .max = 200000000, }, }, + { .n = "cpkcc_clk", .p = "mck0_div", .id = 30, }, + { .n = "eic_clk", .p = "mck7", .id = 33, }, + { .n = "flex0_clk", .p = "mck7", .id = 34, }, + { .n = "flex1_clk", .p = "mck7", .id = 35, }, + { .n = "flex2_clk", .p = "mck7", .id = 36, }, + { .n = "flex3_clk", .p = "mck7", .id = 37, }, + { .n = "flex4_clk", .p = "mck8", .id = 38, }, + { .n = "flex5_clk", .p = "mck8", .id = 39, }, + { .n = "flex6_clk", .p = "mck8", .id = 40, }, + { .n = "flex7_clk", .p = "mck8", .id = 41, }, + { .n = "flex8_clk", .p = "mck9", .id = 42, }, + { .n = "flex9_clk", .p = "mck9", .id = 43, }, + { .n = "flex10_clk", .p = "mck9", .id = 44, }, + { .n = "gmac0_clk", .p = "mck6", .id = 46, }, + { .n = "gmac1_clk", .p = "mck6", .id = 47, }, + { .n = "gmac0_tsu_clk", .p = "mck1", .id = 49, }, + { .n = "gmac1_tsu_clk", .p = "mck1", .id = 50, }, + { .n = "icm_clk", .p = "mck5", .id = 53, }, + { .n = "i2smcc0_clk", .p = "mck9", .id = 54, .r = { .max = 200000000, }, }, + { .n = "i2smcc1_clk", .p = "mck9", .id = 55, .r = { .max = 200000000, }, }, + { .n = "matrix_clk", .p = "mck5", .id = 57, }, + { .n = "mcan0_clk", .p = "mck5", .id = 58, .r = { .max = 200000000, }, }, + { .n = "mcan1_clk", .p = "mck5", .id = 59, .r = { .max = 200000000, }, }, + { .n = "mcan2_clk", .p = "mck5", .id = 60, .r = { .max = 200000000, }, }, + { .n = "mcan3_clk", .p = "mck5", .id = 61, .r = { .max = 200000000, }, }, + { .n = "mcan4_clk", .p = "mck5", .id = 62, .r = { .max = 200000000, }, }, + { .n = "pdmc0_clk", .p = "mck9", .id = 64, .r = { .max = 200000000, }, }, + { .n = "pdmc1_clk", .p = "mck9", .id = 65, .r = { .max = 200000000, }, }, + { .n = "pit64b0_clk", .p = "mck7", .id = 66, }, + { .n = "pit64b1_clk", .p = "mck7", .id = 67, }, + { .n = "pit64b2_clk", .p = "mck7", .id = 68, }, + { .n = "pit64b3_clk", .p = "mck8", .id = 69, }, + { .n = "pit64b4_clk", .p = "mck8", .id = 70, }, + { .n = "pit64b5_clk", .p = "mck8", .id = 71, }, + { .n = "pwm_clk", .p = "mck7", .id = 72, }, + { .n = "qspi0_clk", .p = "mck5", .id = 73, }, + { .n = "qspi1_clk", .p = "mck5", .id = 74, }, + { .n = "sdmmc0_clk", .p = "mck1", .id = 75, }, + { .n = "sdmmc1_clk", .p = "mck1", .id = 76, }, + { .n = "sdmmc2_clk", .p = "mck1", .id = 77, }, + { .n = "sha_clk", .p = "mck6", .id = 78, }, + { .n = "spdifrx_clk", .p = "mck9", .id = 79, .r = { .max = 200000000, }, }, + { .n = "spdiftx_clk", .p = "mck9", .id = 80, .r = { .max = 200000000, }, }, + { .n = "ssc0_clk", .p = "mck7", .id = 81, .r = { .max = 200000000, }, }, + { .n = "ssc1_clk", .p = "mck8", .id = 82, .r = { .max = 200000000, }, }, + { .n = "tcb0_ch0_clk", .p = "mck8", .id = 83, .r = { .max = 200000000, }, }, + { .n = "tcb0_ch1_clk", .p = "mck8", .id = 84, .r = { .max = 200000000, }, }, + { .n = "tcb0_ch2_clk", .p = "mck8", .id = 85, .r = { .max = 200000000, }, }, + { .n = "tcb1_ch0_clk", .p = "mck5", .id = 86, .r = { .max = 200000000, }, }, + { .n = "tcb1_ch1_clk", .p = "mck5", .id = 87, .r = { .max = 200000000, }, }, + { .n = "tcb1_ch2_clk", .p = "mck5", .id = 88, .r = { .max = 200000000, }, }, + { .n = "tcpca_clk", .p = "mck5", .id = 89, }, + { .n = "tcpcb_clk", .p = "mck5", .id = 90, }, + { .n = "tdes_clk", .p = "mck6", .id = 91, }, + { .n = "trng_clk", .p = "mck6", .id = 92, }, + { .n = "udphsa_clk", .p = "mck5", .id = 99, }, + { .n = "udphsb_clk", .p = "mck5", .id = 100, }, + { .n = "uhphs_clk", .p = "mck5", .id = 101, }, +}; + +/** + * Generic clock description + * @n: clock name + * @ep: extra parents names + * @ep_mux_table: extra parents mux table + * @ep_clk_mux_table: extra parents clock mux table (for CCF) + * @r: clock output range + * @ep_count: extra parents count + * @id: clock id + */ +static const struct { + const char *n; + const char *ep[8]; + const char ep_mux_table[8]; + const char ep_clk_mux_table[8]; + struct clk_range r; + u8 ep_count; + u8 id; +} sama7d65_gck[] = { + { + .n = "adc_gclk", + .id = 25, + .r = { .max = 100000000, }, + .ep = { "baudpll_divpmcck", "audiopll_divpmcck", }, + .ep_mux_table = { 8, 9, }, + .ep_clk_mux_table = { ID_PLL_BAUD_DIV, ID_PLL_AUDIO_DIVPMC, }, + .ep_count = 2, + }, + + { + .n = "asrc_gclk", + .id = 29, + .r = { .max = 200000000 }, + .ep = { "audiopll_divpmcck", }, + .ep_mux_table = { 9, }, + .ep_clk_mux_table = { ID_PLL_AUDIO_DIVPMC, }, + .ep_count = 1, + }, + + { + .n = "flex0_gclk", + .id = 34, + .r = { .max = 34000000 }, + .ep = {"baudpll_divpmcck", }, + .ep_mux_table = { 8, }, + .ep_clk_mux_table = {ID_PLL_BAUD_DIV, }, + .ep_count = 1, + }, + + { + .n = "flex1_gclk", + .id = 35, + .r = { .max = 34000000 }, + .ep = {"baudpll_divpmcck", }, + .ep_mux_table = { 8, }, + .ep_clk_mux_table = { ID_PLL_BAUD_DIV, }, + .ep_count = 1, + }, + + { + .n = "flex2_gclk", + .id = 36, + .r = { .max = 34000000 }, + .ep = { "baudpll_divpmcck", }, + .ep_mux_table = { 8,}, + .ep_clk_mux_table = {ID_PLL_BAUD_DIV, }, + .ep_count = 1, + }, + + { + .n = "flex3_gclk", + .id = 37, + .r = { .max = 34000000 }, + .ep = {"baudpll_divpmcck", }, + .ep_mux_table = { 8,}, + .ep_clk_mux_table = { ID_PLL_BAUD_DIV, }, + .ep_count = 1, + }, + + { + .n = "flex4_gclk", + .id = 38, + .r = { .max = 34000000 }, + .ep = {"baudpll_divpmcck", }, + .ep_mux_table = { 8, }, + .ep_clk_mux_table = { ID_PLL_BAUD_DIV, }, + .ep_count = 1, + }, + + { + .n = "flex5_gclk", + .id = 39, + .r = { .max = 34000000 }, + .ep = { "baudpll_divpmcck", }, + .ep_mux_table = { 8, }, + .ep_clk_mux_table = {ID_PLL_BAUD_DIV, }, + .ep_count = 1, + }, + + { + .n = "flex6_gclk", + .id = 40, + .r = { .max = 34000000 }, + .ep = { "baudpll_divpmcck", }, + .ep_mux_table = { 8, }, + .ep_clk_mux_table = { ID_PLL_BAUD_DIV, }, + .ep_count = 1, + }, + + { + .n = "flex7_gclk", + .id = 41, + .r = { .max = 34000000 }, + .ep = { "baudpll_divpmcck", }, + .ep_mux_table = { 8, }, + .ep_clk_mux_table = {ID_PLL_BAUD_DIV, }, + .ep_count = 1, + }, + + { + .n = "flex8_gclk", + .id = 42, + .r = { .max = 34000000 }, + .ep = { "baudpll_divpmcck", }, + .ep_mux_table = { 8,}, + .ep_clk_mux_table = { ID_PLL_BAUD_DIV, }, + .ep_count = 1, + }, + + { + .n = "flex9_gclk", + .id = 43, + .r = { .max = 34000000 }, + .ep = { "baudpll_divpmcck", }, + .ep_mux_table = { 8,}, + .ep_clk_mux_table = {ID_PLL_BAUD_DIV, }, + .ep_count = 1, + }, + + { + .n = "flex10_gclk", + .id = 44, + .r = { .max = 34000000 }, + .ep = { "baudpll_divpmcck", }, + .ep_mux_table = { 8,}, + .ep_clk_mux_table = {ID_PLL_BAUD_DIV, }, + .ep_count = 1, + }, + + { + .n = "gmac0_gclk", + .id = 46, + .r = { .max = 125000000}, + .ep = { "ethpll_divpmcck", }, + .ep_clk_mux_table = { ID_PLL_ETH_DIV, }, + .ep_mux_table = { 10, }, + .ep_count = 1, + }, + + { + .n = "gmac1_gclk", + .id = 47, + .r = { .max = 125000000}, + .ep = { "ethpll_divpmcck", }, + .ep_mux_table = { 10, }, + .ep_clk_mux_table = { ID_PLL_ETH_DIV, }, + .ep_count = 1, + }, + + { + .n = "gmac0_tsu_gclk", + .id = 49, + .r = { .max = 400000000 }, + .ep = { "syspll_divpmcck", "audiopll_divpmcck", "ethpll_divpmcck", }, + .ep_mux_table = { 5, 9, 10, }, + .ep_clk_mux_table = { ID_PLL_SYS_DIV, ID_PLL_AUDIO_DIVPMC, ID_PLL_ETH_DIV, }, + .ep_count = 3, + }, + + { + .n = "gmac1_tsu_gclk", + .id = 50, + .r = { .max = 400000000 }, + .ep = { "syspll_divpmcck", "audiopll_divpmcck", "ethpll_divpmcck", }, + .ep_mux_table = { 5, 9, 10, }, + .ep_clk_mux_table = { ID_PLL_SYS_DIV, ID_PLL_AUDIO_DIVPMC, ID_PLL_ETH_DIV, }, + .ep_count = 3, + }, + + { + .n = "i2smcc0_gclk", + .id = 54, + .r = { .max = 100000000 }, + .ep = { "audiopll_divpmcck", }, + .ep_mux_table = { 9, }, + .ep_clk_mux_table = {ID_PLL_AUDIO_DIVPMC, }, + .ep_count = 1, + }, + + { + .n = "i2smcc1_gclk", + .id = 55, + .r = { .max = 100000000 }, + .ep = {"audiopll_divpmcck", }, + .ep_mux_table = { 9, }, + .ep_clk_mux_table = {ID_PLL_AUDIO_DIVPMC, }, + .ep_count = 1, + }, + + { + .n = "mcan0_gclk", + .id = 58, + .r = { .max = 80000000 }, + .ep = { "usbpll_divpmcck", }, + .ep_mux_table = { 12, }, + .ep_clk_mux_table = { ID_PLL_USB_DIV }, + .ep_count = 1, + }, + + { + .n = "mcan1_gclk", + .id = 59, + .r = { .max = 80000000 }, + .ep = { "usbpll_divpmcck", }, + .ep_mux_table = { 12, }, + .ep_clk_mux_table = { ID_PLL_USB_DIV, }, + .ep_count = 1, + }, + + { + .n = "mcan2_gclk", + .id = 60, + .r = { .max = 80000000 }, + .ep = { "usbpll_divpmcck", }, + .ep_mux_table = { 12, }, + .ep_clk_mux_table = { ID_PLL_USB_DIV, }, + .ep_count = 1, + }, + + { + .n = "mcan3_gclk", + .id = 61, + .r = { .max = 80000000 }, + .ep = { "usbpll_divpmcck", }, + .ep_mux_table = { 12, }, + .ep_clk_mux_table = { ID_PLL_USB_DIV, }, + .ep_count = 1, + }, + + { + .n = "mcan4_gclk", + .id = 62, + .r = { .max = 80000000 }, + .ep = { "usbpll_divpmcck", }, + .ep_mux_table = { 12, }, + .ep_clk_mux_table = { ID_PLL_USB_DIV, }, + .ep_count = 1, + }, + + { + .n = "pdmc0_gclk", + .id = 64, + .r = { .max = 80000000 }, + .ep = { "audiopll_divpmcck", }, + .ep_mux_table = { 9, }, + .ep_clk_mux_table = { ID_PLL_AUDIO_DIVPMC, }, + .ep_count = 1, + }, + + { + .n = "pdmc1_gclk", + .id = 65, + .r = { .max = 80000000, }, + .ep = { "audiopll_divpmcck",}, + .ep_mux_table = { 9, }, + .ep_clk_mux_table = {ID_PLL_AUDIO_DIVPMC, }, + .ep_count = 1, + }, + + { + .n = "pit64b0_gclk", + .id = 66, + .r = { .max = 34000000 }, + .ep = { "baudpll_divpmcck", "audiopll_divpmcck", "ethpll_divpmcck", }, + .ep_mux_table = {8, 9, 10, }, + .ep_clk_mux_table = { ID_PLL_BAUD_DIV, ID_PLL_AUDIO_DIVPMC, + ID_PLL_ETH_DIV, }, + .ep_count = 3, + }, + + { + .n = "pit64b1_gclk", + .id = 67, + .r = { .max = 34000000 }, + .ep = { "baudpll_divpmcck", "audiopll_divpmcck", "ethpll_divpmcck", }, + .ep_mux_table = {8, 9, 10, }, + .ep_clk_mux_table = { ID_PLL_BAUD_DIV, ID_PLL_AUDIO_DIVPMC, + ID_PLL_ETH_DIV, }, + .ep_count = 3, + }, + + { + .n = "pit64b2_gclk", + .id = 68, + .r = { .max = 34000000 }, + .ep = { "baudpll_divpmcck", "audiopll_divpmcck", "ethpll_divpmcck", }, + .ep_mux_table = { 8, 9, 10, }, + .ep_clk_mux_table = {ID_PLL_BAUD_DIV, ID_PLL_AUDIO_DIVPMC, + ID_PLL_ETH_DIV, }, + .ep_count = 3, + }, + + { + .n = "pit64b3_gclk", + .id = 69, + .r = { .max = 34000000 }, + .ep = {"baudpll_divpmcck", "audiopll_divpmcck", "ethpll_divpmcck", }, + .ep_mux_table = {8, 9, 10, }, + .ep_clk_mux_table = {ID_PLL_BAUD_DIV, ID_PLL_AUDIO_DIVPMC, + ID_PLL_ETH_DIV, }, + .ep_count = 3, + }, + + { + .n = "pit64b4_gclk", + .id = 70, + .r = { .max = 34000000 }, + .ep = {"baudpll_divpmcck", "audiopll_divpmcck", "ethpll_divpmcck", }, + .ep_mux_table = {8, 9, 10, }, + .ep_clk_mux_table = {ID_PLL_BAUD_DIV, ID_PLL_AUDIO_DIVPMC, + ID_PLL_ETH_DIV, }, + .ep_count = 3, + }, + + { + .n = "pit64b5_gclk", + .id = 71, + .r = { .max = 34000000 }, + .ep = {"baudpll_divpmcck", "audiopll_divpmcck", "ethpll_divpmcck", }, + .ep_mux_table = {8, 9, 10, }, + .ep_clk_mux_table = {ID_PLL_BAUD_DIV, ID_PLL_AUDIO_DIVPMC, + ID_PLL_ETH_DIV, }, + .ep_count = 3, + }, + + { + .n = "qspi0_gclk", + .id = 73, + .r = { .max = 400000000 }, + .ep = { "syspll_divpmcck", "baudpll_divpmcck", }, + .ep_mux_table = { 5, 8, }, + .ep_clk_mux_table = { ID_PLL_SYS_DIV, ID_PLL_BAUD_DIV, }, + .ep_count = 2, + }, + + { + .n = "qspi1_gclk", + .id = 74, + .r = { .max = 266000000 }, + .ep = { "syspll_divpmcck", "baudpll_divpmcck", }, + .ep_mux_table = { 5, 8, }, + .ep_clk_mux_table = { ID_PLL_SYS_DIV, ID_PLL_BAUD_DIV, }, + .ep_count = 2, + }, + + { + .n = "sdmmc0_gclk", + .id = 75, + .r = { .max = 208000000 }, + .ep = {"baudpll_divpmcck", "ethpll_divpmcck", }, + .ep_mux_table = {8, 10, }, + .ep_clk_mux_table = {ID_PLL_BAUD_DIV, ID_PLL_ETH_DIV,}, + .ep_count = 2, + }, + + { + .n = "sdmmc1_gclk", + .id = 76, + .r = { .max = 208000000 }, + .ep = { "baudpll_divpmcck", "ethpll_divpmcck", }, + .ep_mux_table = {8, 10,}, + .ep_clk_mux_table = {ID_PLL_BAUD_DIV, ID_PLL_ETH_DIV, }, + .ep_count = 2, + }, + + { + .n = "sdmmc2_gclk", + .id = 77, + .r = { .max = 208000000 }, + .ep = {"baudpll_divpmcck", "ethpll_divpmcck",}, + .ep_mux_table = {8, 10,}, + .ep_clk_mux_table = {ID_PLL_BAUD_DIV, ID_PLL_ETH_DIV,}, + .ep_count = 2, + }, + + { + .n = "spdifrx_gclk", + .id = 79, + .r = { .max = 150000000 }, + .ep = {"audiopll_divpmcck", }, + .ep_mux_table = { 9, }, + .ep_clk_mux_table = { ID_PLL_AUDIO_DIVPMC, }, + .ep_count = 1, + }, + + { + .n = "spdiftx_gclk", + .id = 80, + .r = { .max = 25000000 }, + .ep = { "audiopll_divpmcck", }, + .ep_mux_table = {9, }, + .ep_clk_mux_table = {ID_PLL_AUDIO_DIVPMC, }, + .ep_count = 1, + }, + + { + .n = "tcb0_ch0_gclk", + .id = 83, + .r = { .max = 34000000 }, + .ep = {"baudpll_divpmcck", "audiopll_divpmcck", "ethpll_divpmcck", }, + .ep_mux_table = { 8, 9, 10, }, + .ep_clk_mux_table = {ID_PLL_BAUD_DIV, ID_PLL_AUDIO_DIVPMC, + ID_PLL_ETH_DIV, }, + .ep_count = 3, + }, + + { + .n = "tcb1_ch0_gclk", + .id = 86, + .r = { .max = 67000000 }, + .ep = {"baudpll_divpmcck", "audiopll_divpmcck", "ethpll_divpmcck", }, + .ep_mux_table = {8, 9, 10, }, + .ep_clk_mux_table = {ID_PLL_BAUD_DIV, ID_PLL_AUDIO_DIVPMC, + ID_PLL_ETH_DIV, }, + .ep_count = 3, + }, + + { + .n = "DSI_gclk", + .id = 103, + .r = {.max = 27000000}, + .ep = {"syspll_divpmcck"}, + .ep_mux_table = {5}, + .ep_clk_mux_table = {ID_PLL_SYS_DIV}, + .ep_count = 1, + }, + + { + .n = "I3CC_gclk", + .id = 105, + .r = {.max = 125000000}, + .ep = {"baudpll_divpmcck", "audiopll_divpmcck", "ethpll_divpmcck", }, + .ep_mux_table = {8, 9, 10, }, + .ep_clk_mux_table = {ID_PLL_BAUD_DIV, ID_PLL_AUDIO_DIVPMC, + ID_PLL_ETH_DIV, }, + .ep_count = 3, + }, +}; + +/* Clock setup description */ +static const struct pmc_clk_setup sama7d65_clk_setup[] = { + { + .cid = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_PLL_ETH_FRAC), + .rate = 625000000, + }, + + { + .cid = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_PLL_ETH_DIV), + .rate = 625000000, + }, +}; + +#define SAMA7D65_MAX_MUX_ALLOCS (64) + +#define prepare_mux_table(_allocs, _index, _dst, _src, _num, _label) \ + do { \ + int _i; \ + if ((_index) >= SAMA7D65_MAX_MUX_ALLOCS) { \ + debug("%s(): AT91: MUX: insufficient space\n", \ + __func__); \ + goto _label; \ + } \ + (_dst) = kzalloc(sizeof(*(_dst)) * (_num), GFP_KERNEL); \ + if (!(_dst)) \ + goto _label; \ + (_allocs)[(_index)++] = (_dst); \ + for (_i = 0; _i < (_num); _i++) \ + (_dst)[_i] = (_src)[_i]; \ + } while (0) + +static int sama7d65_clk_probe(struct udevice *dev) +{ + void __iomem *base = (void *)devfdt_get_addr(dev); + unsigned int *clkmuxallocs[SAMA7D65_MAX_MUX_ALLOCS]; + unsigned int *muxallocs[SAMA7D65_MAX_MUX_ALLOCS]; + const char *p[12]; + unsigned int cm[12], m[12], *tmpclkmux, *tmpmux; + struct clk clk, *c; + bool main_osc_bypass; + int ret, muxallocindex = 0, clkmuxallocindex = 0, i, j; + + if (IS_ERR(base)) + return PTR_ERR(base); + + memset(muxallocs, 0, ARRAY_SIZE(muxallocs)); + memset(clkmuxallocs, 0, ARRAY_SIZE(clkmuxallocs)); + + ret = clk_get_by_index(dev, 0, &clk); + if (ret) + return ret; + ret = clk_get_by_id(clk.id, &c); + if (ret) + return ret; + clk_names[ID_TD_SLCK] = kmemdup(clk_hw_get_name(c), + strlen(clk_hw_get_name(c)) + 1, + GFP_KERNEL); + if (!clk_names[ID_TD_SLCK]) + return -ENOMEM; + + ret = clk_get_by_index(dev, 1, &clk); + if (ret) + return ret; + ret = clk_get_by_id(clk.id, &c); + if (ret) + return ret; + clk_names[ID_MD_SLCK] = kmemdup(clk_hw_get_name(c), + strlen(clk_hw_get_name(c)) + 1, + GFP_KERNEL); + if (!clk_names[ID_MD_SLCK]) + return -ENOMEM; + + ret = clk_get_by_index(dev, 2, &clk); + if (ret) + return ret; + clk_names[ID_MAIN_XTAL] = kmemdup(clk_hw_get_name(&clk), + strlen(clk_hw_get_name(&clk)) + 1, + GFP_KERNEL); + if (!clk_names[ID_MAIN_XTAL]) + return -ENOMEM; + + main_osc_bypass = dev_read_bool(dev, "atmel,main-osc-bypass"); + + /* Register main rc oscillator. */ + clk_dm(AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MAIN_RC_OSC), + at91_clk_main_rc(base, clk_names[ID_MAIN_RC_OSC], + NULL)); + + /* Register main oscillator. */ + clk_dm(AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MAIN_OSC), + at91_clk_main_osc(base, clk_names[ID_MAIN_OSC], + clk_names[ID_MAIN_XTAL], main_osc_bypass)); + + /* Register mainck. */ + p[0] = clk_names[ID_MAIN_RC_OSC]; + p[1] = clk_names[ID_MAIN_OSC]; + cm[0] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MAIN_RC_OSC); + cm[1] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MAIN_OSC); + prepare_mux_table(clkmuxallocs, clkmuxallocindex, tmpclkmux, cm, 2, + fail); + clk_dm(AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MAINCK), + at91_clk_sam9x5_main(base, clk_names[ID_MAINCK], p, 2, + tmpclkmux, PMC_TYPE_CORE)); + + /* Register PLL fracs clocks. */ + for (i = 0; i < ARRAY_SIZE(sama7d65_plls); i++) { + if (sama7d65_plls[i].t != PLL_TYPE_FRAC) + continue; + + clk_dm(AT91_TO_CLK_ID(PMC_TYPE_CORE, sama7d65_plls[i].cid), + sam9x60_clk_register_frac_pll(base, sama7d65_plls[i].n, + sama7d65_plls[i].p, + sama7d65_plls[i].id, + &pll_characteristics, + sama7d65_plls[i].l, + sama7d65_plls[i].c)); + } + + /* Register PLL div clocks. */ + for (i = 0; i < ARRAY_SIZE(sama7d65_plls); i++) { + if (sama7d65_plls[i].t != PLL_TYPE_DIV) + continue; + + clk_dm(AT91_TO_CLK_ID(PMC_TYPE_CORE, sama7d65_plls[i].cid), + sam9x60_clk_register_div_pll(base, sama7d65_plls[i].n, + sama7d65_plls[i].p, + sama7d65_plls[i].id, + &pll_characteristics, + sama7d65_plls[i].l, + sama7d65_plls[i].c)); + } + + /* Register MCK0_PRES clock. */ + p[0] = clk_names[ID_MD_SLCK]; + p[1] = clk_names[ID_MAINCK]; + p[2] = clk_names[ID_PLL_CPU_DIV]; + p[3] = clk_names[ID_PLL_SYS_DIV]; + cm[0] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MD_SLCK); + cm[1] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MAINCK); + cm[2] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_PLL_CPU_DIV); + cm[3] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_PLL_SYS_DIV); + prepare_mux_table(clkmuxallocs, clkmuxallocindex, tmpclkmux, cm, 2, + fail); + clk_dm(AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MCK0_PRES), + at91_clk_register_master_pres(base, clk_names[ID_MCK0_PRES], + p, 4, &mck0_layout, + &mck0_characteristics, + tmpclkmux)); + + clk_dm(AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MCK0_DIV), + at91_clk_register_master_div(base, clk_names[ID_MCK0_DIV], + clk_names[ID_MCK0_PRES], + &mck0_layout, + &mck0_characteristics)); + + /* Register MCK1-9 clocks. */ + p[0] = clk_names[ID_MD_SLCK]; + p[1] = clk_names[ID_TD_SLCK]; + p[2] = clk_names[ID_MAINCK]; + p[3] = clk_names[ID_MCK0_DIV]; + m[0] = 0; + m[1] = 1; + m[2] = 2; + m[3] = 3; + cm[0] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MD_SLCK); + cm[1] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_TD_SLCK); + cm[2] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MAINCK); + cm[3] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MCK0_DIV); + for (i = 0; i < ARRAY_SIZE(sama7d65_mckx); i++) { + for (j = 0; j < sama7d65_mckx[i].ep_count; j++) { + p[4 + j] = sama7d65_mckx[i].ep[j]; + m[4 + j] = sama7d65_mckx[i].ep_mux_table[j]; + cm[4 + j] = AT91_TO_CLK_ID(PMC_TYPE_CORE, + sama7d65_mckx[i].ep_clk_mux_table[j]); + } + + prepare_mux_table(clkmuxallocs, clkmuxallocindex, tmpclkmux, cm, + 4 + sama7d65_mckx[i].ep_count, fail); + prepare_mux_table(muxallocs, muxallocindex, tmpmux, m, + 4 + sama7d65_mckx[i].ep_count, fail); + + clk_dm(AT91_TO_CLK_ID(PMC_TYPE_CORE, sama7d65_mckx[i].cid), + at91_clk_sama7g5_register_master(base, sama7d65_mckx[i].n, p, + 4 + sama7d65_mckx[i].ep_count, + tmpmux, tmpclkmux, + sama7d65_mckx[i].c, + sama7d65_mckx[i].id)); + } + + /* Register programmable clocks. */ + p[0] = clk_names[ID_MD_SLCK]; + p[1] = clk_names[ID_TD_SLCK]; + p[2] = clk_names[ID_MAINCK]; + p[3] = clk_names[ID_MCK0_DIV]; + p[4] = clk_names[ID_PLL_SYS_DIV]; + p[5] = clk_names[ID_PLL_GPU_DIV]; + p[6] = clk_names[ID_PLL_BAUD_DIV]; + p[7] = clk_names[ID_PLL_AUDIO_DIVPMC]; + p[8] = clk_names[ID_PLL_ETH_DIV]; + p[9] = clk_names[ID_PLL_USB_DIV]; + cm[0] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MD_SLCK); + cm[1] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_TD_SLCK); + cm[2] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MAINCK); + cm[3] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MCK0_DIV); + cm[4] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_PLL_SYS_DIV); + cm[5] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_PLL_GPU_DIV); + cm[6] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_PLL_BAUD_DIV); + cm[7] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_PLL_AUDIO_DIVPMC); + cm[8] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_PLL_ETH_DIV); + cm[9] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_PLL_USB_DIV); + + for (i = 0; i < ARRAY_SIZE(sama7d65_prog); i++) { + prepare_mux_table(clkmuxallocs, clkmuxallocindex, tmpclkmux, cm, + 10, fail); + + clk_dm(AT91_TO_CLK_ID(PMC_TYPE_CORE, sama7d65_prog[i].cid), + at91_clk_register_programmable(base, sama7d65_prog[i].n, + p, 10, i, + &programmable_layout, + tmpclkmux, + sama7d65_prog_mux_table)); + } + + /* System clocks. */ + for (i = 0; i < ARRAY_SIZE(sama7d65_systemck); i++) { + clk_dm(AT91_TO_CLK_ID(PMC_TYPE_SYSTEM, sama7d65_systemck[i].cid), + at91_clk_register_system(base, sama7d65_systemck[i].n, + sama7d65_systemck[i].p, + sama7d65_systemck[i].id)); + } + + /* Peripheral clocks. */ + for (i = 0; i < ARRAY_SIZE(sama7d65_periphck); i++) { + clk_dm(AT91_TO_CLK_ID(PMC_TYPE_PERIPHERAL, sama7d65_periphck[i].id), + at91_clk_register_sam9x5_peripheral(base, + &sama7d65_pcr_layout, + sama7d65_periphck[i].n, + sama7d65_periphck[i].p, + sama7d65_periphck[i].id, + &sama7d65_periphck[i].r)); + } + + /* Generic clocks. */ + p[0] = clk_names[ID_MD_SLCK]; + p[1] = clk_names[ID_TD_SLCK]; + p[2] = clk_names[ID_MAINCK]; + p[3] = clk_names[ID_MCK1]; + m[0] = 0; + m[1] = 1; + m[2] = 2; + m[3] = 3; + cm[0] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MD_SLCK); + cm[1] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_TD_SLCK); + cm[2] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MAINCK); + cm[3] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MCK1); + for (i = 0; i < ARRAY_SIZE(sama7d65_gck); i++) { + for (j = 0; j < sama7d65_gck[i].ep_count; j++) { + p[4 + j] = sama7d65_gck[i].ep[j]; + m[4 + j] = sama7d65_gck[i].ep_mux_table[j]; + cm[4 + j] = AT91_TO_CLK_ID(PMC_TYPE_CORE, + sama7d65_gck[i].ep_clk_mux_table[j]); + } + + prepare_mux_table(clkmuxallocs, clkmuxallocindex, tmpclkmux, cm, + 4 + sama7d65_gck[i].ep_count, fail); + prepare_mux_table(muxallocs, muxallocindex, tmpmux, m, + 4 + sama7d65_gck[i].ep_count, fail); + + clk_dm(AT91_TO_CLK_ID(PMC_TYPE_GCK, sama7d65_gck[i].id), + at91_clk_register_generic(base, &sama7d65_pcr_layout, + sama7d65_gck[i].n, p, + tmpclkmux, tmpmux, + 4 + sama7d65_gck[i].ep_count, + sama7d65_gck[i].id, + &sama7d65_gck[i].r)); + } + + /* Setup clocks. */ + ret = at91_clk_setup(sama7d65_clk_setup, ARRAY_SIZE(sama7d65_clk_setup)); + if (ret) + goto fail; + + return 0; + +fail: + for (i = 0; i < ARRAY_SIZE(muxallocs); i++) + kfree(muxallocs[i]); + + for (i = 0; i < ARRAY_SIZE(clkmuxallocs); i++) + kfree(clkmuxallocs[i]); + + return -ENOMEM; +} + +static const struct udevice_id sama7d65_clk_ids[] = { + { .compatible = "microchip,sama7d65-pmc" }, + { /* Sentinel. */ }, +}; + +U_BOOT_DRIVER(at91_sama7d65_pmc) = { + .name = "at91-sama7d65-pmc", + .id = UCLASS_CLK, + .of_match = sama7d65_clk_ids, + .ops = &at91_clk_ops, + .probe = sama7d65_clk_probe, + .flags = DM_FLAG_PRE_RELOC, +}; diff --git a/drivers/clk/sunxi/Kconfig b/drivers/clk/sunxi/Kconfig index f44db76c182..1c1cc82719c 100644 --- a/drivers/clk/sunxi/Kconfig +++ b/drivers/clk/sunxi/Kconfig @@ -129,4 +129,18 @@ config CLK_SUN50I_A100 This enables common clock driver support for platforms based on Allwinner A100/A133 SoCs. +config CLK_SUN55I_A523 + bool "Clock driver for Allwinner A523/T527" + default MACH_SUN55I_A523 + help + This enables common clock driver support for platforms based + on Allwinner A523/T527 SoC. + +config CLK_SUN55I_A523_R + bool "Clock driver for Allwinner A523 generation PRCM" + default MACH_SUN55I_A523 + help + This enables common clock driver support for the PRCM + in Allwinner A523/T527 SoCs. + endif # CLK_SUNXI diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile index 7ff71c756e0..93b542cebcd 100644 --- a/drivers/clk/sunxi/Makefile +++ b/drivers/clk/sunxi/Makefile @@ -25,3 +25,5 @@ obj-$(CONFIG_CLK_SUN50I_H6_R) += clk_h6_r.o obj-$(CONFIG_CLK_SUN50I_H616) += clk_h616.o obj-$(CONFIG_CLK_SUN50I_A64) += clk_a64.o obj-$(CONFIG_CLK_SUN50I_A100) += clk_a100.o +obj-$(CONFIG_CLK_SUN55I_A523) += clk_a523.o +obj-$(CONFIG_CLK_SUN55I_A523_R) += clk_a523_r.o diff --git a/drivers/clk/sunxi/clk_a523.c b/drivers/clk/sunxi/clk_a523.c new file mode 100644 index 00000000000..1de95fbaf2f --- /dev/null +++ b/drivers/clk/sunxi/clk_a523.c @@ -0,0 +1,85 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2024 Arm Ltd. + */ + +#include <clk-uclass.h> +#include <dm.h> +#include <errno.h> +#include <clk/sunxi.h> +#include <linux/bitops.h> + +#include <dt-bindings/clock/sun55i-a523-ccu.h> +#include <dt-bindings/reset/sun55i-a523-ccu.h> + +static struct ccu_clk_gate a523_gates[] = { + [CLK_PLL_PERIPH0_200M] = GATE_DUMMY, + [CLK_APB1] = GATE_DUMMY, + + [CLK_BUS_MMC0] = GATE(0x84c, BIT(0)), + [CLK_BUS_MMC1] = GATE(0x84c, BIT(1)), + [CLK_BUS_MMC2] = GATE(0x84c, BIT(2)), + [CLK_BUS_UART0] = GATE(0x90c, BIT(0)), + [CLK_BUS_UART1] = GATE(0x90c, BIT(1)), + [CLK_BUS_UART2] = GATE(0x90c, BIT(2)), + [CLK_BUS_UART3] = GATE(0x90c, BIT(3)), + [CLK_BUS_UART4] = GATE(0x90c, BIT(4)), + [CLK_BUS_UART5] = GATE(0x90c, BIT(5)), + [CLK_BUS_I2C0] = GATE(0x91c, BIT(0)), + [CLK_BUS_I2C1] = GATE(0x91c, BIT(1)), + [CLK_BUS_I2C2] = GATE(0x91c, BIT(2)), + [CLK_BUS_I2C3] = GATE(0x91c, BIT(3)), + [CLK_SPI0] = GATE(0x940, BIT(31)), + [CLK_SPI1] = GATE(0x944, BIT(31)), + [CLK_BUS_SPI0] = GATE(0x96c, BIT(0)), + [CLK_BUS_SPI1] = GATE(0x96c, BIT(1)), + + [CLK_EMAC0_25M] = GATE(0x970, BIT(30) | BIT(31)), + [CLK_EMAC1_25M] = GATE(0x974, BIT(30) | BIT(31)), + [CLK_BUS_EMAC0] = GATE(0x97c, BIT(0)), + [CLK_BUS_EMAC1] = GATE(0x98c, BIT(0)), + + [CLK_USB_OHCI0] = GATE(0xa70, BIT(31)), + [CLK_USB_OHCI1] = GATE(0xa74, BIT(31)), + [CLK_BUS_OHCI0] = GATE(0xa8c, BIT(0)), + [CLK_BUS_OHCI1] = GATE(0xa8c, BIT(1)), + [CLK_BUS_EHCI0] = GATE(0xa8c, BIT(4)), + [CLK_BUS_EHCI1] = GATE(0xa8c, BIT(5)), + [CLK_BUS_OTG] = GATE(0xa8c, BIT(8)), +}; + +static struct ccu_reset a523_resets[] = { + [RST_BUS_MMC0] = RESET(0x84c, BIT(16)), + [RST_BUS_MMC1] = RESET(0x84c, BIT(17)), + [RST_BUS_MMC2] = RESET(0x84c, BIT(18)), + [RST_BUS_UART0] = RESET(0x90c, BIT(16)), + [RST_BUS_UART1] = RESET(0x90c, BIT(17)), + [RST_BUS_UART2] = RESET(0x90c, BIT(18)), + [RST_BUS_UART3] = RESET(0x90c, BIT(19)), + [RST_BUS_UART4] = RESET(0x90c, BIT(20)), + [RST_BUS_UART5] = RESET(0x90c, BIT(21)), + [RST_BUS_I2C0] = RESET(0x91c, BIT(16)), + [RST_BUS_I2C1] = RESET(0x91c, BIT(17)), + [RST_BUS_I2C2] = RESET(0x91c, BIT(18)), + [RST_BUS_I2C3] = RESET(0x91c, BIT(19)), + [RST_BUS_SPI0] = RESET(0x96c, BIT(16)), + [RST_BUS_SPI1] = RESET(0x96c, BIT(17)), + + [RST_BUS_EMAC0] = RESET(0x97c, BIT(16)), + [RST_BUS_EMAC1] = RESET(0x98c, BIT(16) | BIT(17)), + + [RST_USB_PHY0] = RESET(0xa70, BIT(30)), + [RST_USB_PHY1] = RESET(0xa74, BIT(30)), + [RST_BUS_OHCI0] = RESET(0xa8c, BIT(16)), + [RST_BUS_OHCI1] = RESET(0xa8c, BIT(17)), + [RST_BUS_EHCI0] = RESET(0xa8c, BIT(20)), + [RST_BUS_EHCI1] = RESET(0xa8c, BIT(21)), + [RST_BUS_OTG] = RESET(0xa8c, BIT(24)), +}; + +const struct ccu_desc a523_ccu_desc = { + .gates = a523_gates, + .resets = a523_resets, + .num_gates = ARRAY_SIZE(a523_gates), + .num_resets = ARRAY_SIZE(a523_resets), +}; diff --git a/drivers/clk/sunxi/clk_a523_r.c b/drivers/clk/sunxi/clk_a523_r.c new file mode 100644 index 00000000000..01e613d20aa --- /dev/null +++ b/drivers/clk/sunxi/clk_a523_r.c @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2024 Arm Ltd. + */ + +#include <clk-uclass.h> +#include <dm.h> +#include <clk/sunxi.h> +#include <dt-bindings/clock/sun55i-a523-r-ccu.h> +#include <dt-bindings/reset/sun55i-a523-r-ccu.h> +#include <linux/bitops.h> + +static struct ccu_clk_gate a523_r_gates[] = { + [CLK_R_AHB] = GATE_DUMMY, + [CLK_R_APB0] = GATE_DUMMY, + [CLK_R_APB1] = GATE_DUMMY, + [CLK_BUS_R_TWD] = GATE(0x12c, BIT(0)), + [CLK_BUS_R_I2C0] = GATE(0x19c, BIT(0)), + [CLK_BUS_R_I2C1] = GATE(0x19c, BIT(1)), + [CLK_BUS_R_I2C2] = GATE(0x19c, BIT(2)), + [CLK_BUS_R_RTC] = GATE(0x20c, BIT(0)), +}; + +static struct ccu_reset a523_r_resets[] = { + [RST_BUS_R_TWD] = RESET(0x12c, BIT(16)), + [RST_BUS_R_UART0] = RESET(0x18c, BIT(16)), + [RST_BUS_R_I2C0] = RESET(0x19c, BIT(16)), + [RST_BUS_R_I2C1] = RESET(0x19c, BIT(17)), + [RST_BUS_R_I2C2] = RESET(0x19c, BIT(18)), + [RST_BUS_R_PPU1] = RESET(0x1ac, BIT(17)), + [RST_BUS_R_RTC] = RESET(0x20c, BIT(16)), +}; + +const struct ccu_desc a523_r_ccu_desc = { + .gates = a523_r_gates, + .resets = a523_r_resets, + .num_gates = ARRAY_SIZE(a523_r_gates), + .num_resets = ARRAY_SIZE(a523_r_resets), +}; diff --git a/drivers/clk/sunxi/clk_sunxi.c b/drivers/clk/sunxi/clk_sunxi.c index e0765cbc6dc..842a0541bd6 100644 --- a/drivers/clk/sunxi/clk_sunxi.c +++ b/drivers/clk/sunxi/clk_sunxi.c @@ -126,6 +126,8 @@ extern const struct ccu_desc a100_ccu_desc; extern const struct ccu_desc h6_r_ccu_desc; extern const struct ccu_desc r40_ccu_desc; extern const struct ccu_desc v3s_ccu_desc; +extern const struct ccu_desc a523_ccu_desc; +extern const struct ccu_desc a523_r_ccu_desc; static const struct udevice_id sunxi_clk_ids[] = { #ifdef CONFIG_CLK_SUN4I_A10 @@ -224,6 +226,14 @@ static const struct udevice_id sunxi_clk_ids[] = { { .compatible = "allwinner,suniv-f1c100s-ccu", .data = (ulong)&f1c100s_ccu_desc }, #endif +#ifdef CONFIG_CLK_SUN55I_A523 + { .compatible = "allwinner,sun55i-a523-ccu", + .data = (ulong)&a523_ccu_desc }, +#endif +#ifdef CONFIG_CLK_SUN55I_A523_R + { .compatible = "allwinner,sun55i-a523-r-ccu", + .data = (ulong)&a523_r_ccu_desc }, +#endif { } }; diff --git a/drivers/core/uclass.c b/drivers/core/uclass.c index ce5e61bbaa6..5365ac68f9e 100644 --- a/drivers/core/uclass.c +++ b/drivers/core/uclass.c @@ -261,17 +261,14 @@ int uclass_find_first_device(enum uclass_id id, struct udevice **devp) return 0; } -int uclass_find_next_device(struct udevice **devp) +void uclass_find_next_device(struct udevice **devp) { struct udevice *dev = *devp; *devp = NULL; - if (list_is_last(&dev->uclass_node, &dev->uclass->dev_head)) - return 0; - - *devp = list_entry(dev->uclass_node.next, struct udevice, uclass_node); - - return 0; + if (!list_is_last(&dev->uclass_node, &dev->uclass->dev_head)) + *devp = list_entry(dev->uclass_node.next, struct udevice, + uclass_node); } int uclass_find_device_by_namelen(enum uclass_id id, const char *name, int len, @@ -675,11 +672,8 @@ int uclass_first_device_check(enum uclass_id id, struct udevice **devp) int uclass_next_device_check(struct udevice **devp) { - int ret; + uclass_find_next_device(devp); - ret = uclass_find_next_device(devp); - if (ret) - return ret; if (!*devp) return 0; diff --git a/drivers/ddr/marvell/a38x/mv_ddr4_training_calibration.c b/drivers/ddr/marvell/a38x/mv_ddr4_training_calibration.c index 31b6209416b..84156a1e8ad 100644 --- a/drivers/ddr/marvell/a38x/mv_ddr4_training_calibration.c +++ b/drivers/ddr/marvell/a38x/mv_ddr4_training_calibration.c @@ -64,7 +64,7 @@ static u8 center_high_element_get(u8 dir, u8 pbs_element, u16 lambda, u8 pbs_max static int mv_ddr4_centralization(u8 dev_num, u16 (*lambda)[MAX_BUS_NUM][BUS_WIDTH_IN_BITS], u8 (*copt)[MAX_BUS_NUM], u8 (*pbs_result)[MAX_BUS_NUM][BUS_WIDTH_IN_BITS], u8 (*vw_size)[MAX_BUS_NUM], u8 mode, u16 param0, u8 param1); -static int mv_ddr4_dqs_reposition(u8 dir, u16 *lambda, u8 *pbs_result, char delta, u8 *copt, u8 *dqs_pbs); +static int mv_ddr4_dqs_reposition(u8 dir, u16 *lambda, u8 *pbs_result, s8 delta, u8 *copt, u8 *dqs_pbs); static int mv_ddr4_copt_get(u8 dir, u16 *lambda, u8 *vw_l, u8 *vw_h, u8 *pbs_result, u8 *copt); static int mv_ddr4_center_of_mass_calc(u8 dev_num, u8 if_id, u8 subphy_num, u8 mode, u8 *vw_l, u8 *vw_h, u8 *vw_v, u8 vw_num, u8 *v_opt, u8 *t_opt); @@ -659,7 +659,7 @@ static int mv_ddr4_centralization(u8 dev_num, u16 (*lambda)[MAX_BUS_NUM][BUS_WID } /* if_id */ /* restore cs enable value*/ - for (if_id = 0; if_id < MAX_INTERFACE_NUM - 1; if_id++) { + for (if_id = 0; if_id < MAX_INTERFACE_NUM; if_id++) { VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id); status = ddr3_tip_if_write(dev_num, ACCESS_TYPE_UNICAST, if_id, DUAL_DUNIT_CFG_REG, cs_ena_reg_val[if_id], MASK_ALL_BITS); @@ -895,7 +895,7 @@ static int mv_ddr4_copt_get(u8 dir, u16 *lambda, u8 *vw_l, u8 *vw_h, u8 *pbs_res * It provides with a solution for a single subphy (8 bits). * The calling function is responsible for any additional pbs taps for dqs */ -static int mv_ddr4_dqs_reposition(u8 dir, u16 *lambda, u8 *pbs_result, char delta, u8 *copt, u8 *dqs_pbs) +static int mv_ddr4_dqs_reposition(u8 dir, u16 *lambda, u8 *pbs_result, s8 delta, u8 *copt, u8 *dqs_pbs) { u8 dq_idx; u32 pbs_max_val = 0; @@ -952,7 +952,8 @@ static int mv_ddr4_center_of_mass_calc(u8 dev_num, u8 if_id, u8 subphy_num, u8 m int t_opt_temp = 0, v_opt_temp = 0; int vw_avg = 0, v_avg = 0; int s0 = 0, s1 = 0, s2 = 0, slope = 1, r_sq = 0; - u32 d_min = 10000, reg_val = 0; + u32 reg_val = 0; + int d_min = 10000; int status; /* @@ -2189,7 +2190,7 @@ int mv_ddr4_dm_tuning(u32 cs, u16 (*pbs_tap_factor)[MAX_BUS_NUM][BUS_WIDTH_IN_BI for (dq = 0; dq < BUS_WIDTH_IN_BITS; dq++) { idx = dq + subphy * BUS_WIDTH_IN_BITS; reg_val = new_dq_pbs[dq] - dq_pbs_diff; - if (reg_val < 0) { + if (new_dq_pbs[dq] < dq_pbs_diff) { DEBUG_DM_TUNING(DEBUG_LEVEL_ERROR, ("unexpected negative value found\n")); return MV_FAIL; @@ -2267,7 +2268,7 @@ int mv_ddr4_dm_tuning(u32 cs, u16 (*pbs_tap_factor)[MAX_BUS_NUM][BUS_WIDTH_IN_BI idx = dq + subphy * BUS_WIDTH_IN_BITS; pad = dq_map_table[idx]; reg_val = new_dq_pbs[dq] - dq_pbs_diff; - if (reg_val < 0) { + if (new_dq_pbs[dq] < dq_pbs_diff) { DEBUG_DM_TUNING(DEBUG_LEVEL_ERROR, ("unexpected negative value found\n")); return MV_FAIL; diff --git a/drivers/fastboot/Kconfig b/drivers/fastboot/Kconfig index 70207573de2..843171902ae 100644 --- a/drivers/fastboot/Kconfig +++ b/drivers/fastboot/Kconfig @@ -91,7 +91,7 @@ config FASTBOOT_USB_DEV config FASTBOOT_FLASH bool "Enable FASTBOOT FLASH command" default y if ARCH_SUNXI || ARCH_ROCKCHIP - depends on MMC || (MTD_RAW_NAND && CMD_MTDPARTS) + depends on MMC || (MTD_RAW_NAND && CMD_MTDPARTS) || DM_SPI_FLASH select IMAGE_SPARSE help The fastboot protocol includes a "flash" command for writing @@ -119,6 +119,10 @@ config FASTBOOT_FLASH_NAND bool "FASTBOOT on NAND" depends on MTD_RAW_NAND && CMD_MTDPARTS +config FASTBOOT_FLASH_SPI + bool "FASTBOOT on SPI flash" + depends on DM_SPI_FLASH + endchoice config FASTBOOT_FLASH_MMC_DEV diff --git a/drivers/fastboot/Makefile b/drivers/fastboot/Makefile index 048af5aa823..adedba0bf24 100644 --- a/drivers/fastboot/Makefile +++ b/drivers/fastboot/Makefile @@ -5,3 +5,4 @@ obj-y += fb_getvar.o obj-y += fb_command.o obj-$(CONFIG_FASTBOOT_FLASH_MMC) += fb_mmc.o obj-$(CONFIG_FASTBOOT_FLASH_NAND) += fb_nand.o +obj-$(CONFIG_FASTBOOT_FLASH_SPI) += fb_spi_flash.o diff --git a/drivers/fastboot/fb_command.c b/drivers/fastboot/fb_command.c index 2cdbac50ac4..791088bc094 100644 --- a/drivers/fastboot/fb_command.c +++ b/drivers/fastboot/fb_command.c @@ -10,6 +10,7 @@ #include <fastboot-internal.h> #include <fb_mmc.h> #include <fb_nand.h> +#include <fb_spi_flash.h> #include <part.h> #include <stdlib.h> #include <vsprintf.h> @@ -344,6 +345,10 @@ static void __maybe_unused flash(char *cmd_parameter, char *response) if (IS_ENABLED(CONFIG_FASTBOOT_FLASH_NAND)) fastboot_nand_flash_write(cmd_parameter, fastboot_buf_addr, image_size, response); + + if (IS_ENABLED(CONFIG_FASTBOOT_FLASH_SPI)) + fastboot_spi_flash_write(cmd_parameter, fastboot_buf_addr, + image_size, response); } /** @@ -362,6 +367,9 @@ static void __maybe_unused erase(char *cmd_parameter, char *response) if (IS_ENABLED(CONFIG_FASTBOOT_FLASH_NAND)) fastboot_nand_erase(cmd_parameter, response); + + if (IS_ENABLED(CONFIG_FASTBOOT_FLASH_SPI)) + fastboot_spi_flash_erase(cmd_parameter, response); } /** @@ -405,7 +413,7 @@ static void __maybe_unused run_acmd(char *cmd_parameter, char *response) return; } - if (strlen(cmd_parameter) > sizeof(g_a_cmd_buff)) { + if (strlen(cmd_parameter) >= sizeof(g_a_cmd_buff)) { pr_err("too long command\n"); fastboot_fail("too long command", response); return; diff --git a/drivers/fastboot/fb_getvar.c b/drivers/fastboot/fb_getvar.c index 9c2ce65a4e5..6775ea397ab 100644 --- a/drivers/fastboot/fb_getvar.c +++ b/drivers/fastboot/fb_getvar.c @@ -8,6 +8,7 @@ #include <fastboot-internal.h> #include <fb_mmc.h> #include <fb_nand.h> +#include <fb_spi_flash.h> #include <fs.h> #include <part.h> #include <version.h> @@ -123,6 +124,11 @@ static int getvar_get_part_info(const char *part_name, char *response, r = fastboot_nand_get_part_info(part_name, &part_info, response); if (r >= 0 && size) *size = part_info->size; + } else if (IS_ENABLED(CONFIG_FASTBOOT_FLASH_SPI)) { + r = fastboot_spi_flash_get_part_info(part_name, &disk_part, + response); + if (r >= 0 && size) + *size = disk_part.size * disk_part.blksz; } else { fastboot_fail("this storage is not supported in bootloader", response); r = -ENODEV; diff --git a/drivers/fastboot/fb_spi_flash.c b/drivers/fastboot/fb_spi_flash.c new file mode 100644 index 00000000000..691be7c7ef7 --- /dev/null +++ b/drivers/fastboot/fb_spi_flash.c @@ -0,0 +1,251 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2025 Collabora Ltd. + */ + +#include <blk.h> +#include <config.h> +#include <env.h> +#include <fastboot.h> +#include <image-sparse.h> +#include <spi.h> +#include <spi_flash.h> +#include <dm.h> +#include <dm/device-internal.h> + +static struct spi_flash *flash; + +__weak int board_fastboot_spi_flash_write_setup(void) +{ + return 0; +} + +__weak int board_fastboot_spi_flash_erase_setup(void) +{ + return 0; +} + +static int raw_part_get_info_by_name(const char *name, + struct disk_partition *part_info) +{ + /* strlen("fastboot_raw_partition_") + PART_NAME_LEN + 1 */ + char env_desc_name[23 + PART_NAME_LEN + 1]; + char *raw_part_desc; + const char *argv[2]; + const char **parg = argv; + + /* check for raw partition descriptor */ + strcpy(env_desc_name, "fastboot_raw_partition_"); + strlcat(env_desc_name, name, sizeof(env_desc_name)); + raw_part_desc = strdup(env_get(env_desc_name)); + if (!raw_part_desc) + return -ENODEV; + + /* parse partition descriptor: <start> <size> */ + for (; parg < argv + sizeof(argv) / sizeof(*argv); ++parg) { + *parg = strsep(&raw_part_desc, " "); + if (!*parg) { + pr_err("Invalid number of arguments.\n"); + return -ENODEV; + } + } + + part_info->start = simple_strtoul(argv[0], NULL, 0); + part_info->size = simple_strtoul(argv[1], NULL, 0); + strlcpy((char *)part_info->name, name, PART_NAME_LEN); + + return 0; +} + +static int fastboot_spi_flash_probe(void) +{ + unsigned int bus = CONFIG_SF_DEFAULT_BUS; + unsigned int cs = CONFIG_SF_DEFAULT_CS; + struct udevice *new, *bus_dev; + int ret; + + /* Remove the old device, otherwise probe will just be a nop */ + ret = spi_find_bus_and_cs(bus, cs, &bus_dev, &new); + if (!ret) + device_remove(new, DM_REMOVE_NORMAL); + + spi_flash_probe_bus_cs(bus, cs, &new); + flash = dev_get_uclass_priv(new); + if (!flash) { + printf("Failed to initialize SPI flash at %u:%u (error %d)\n", + bus, cs, ret); + return 1; + } + + return 0; +} + +static int fastboot_spi_flash_unlock(struct spi_flash *flash, + struct disk_partition *part_info) +{ + int ret = spi_flash_protect(flash, part_info->start, part_info->size, + false); + + if (ret && ret != -EOPNOTSUPP) { + printf("Failed to unlock SPI flash (%d)\n", ret); + return ret; + } + + return 0; +} + +static lbaint_t fb_spi_flash_sparse_write(struct sparse_storage *info, + lbaint_t blk, lbaint_t blkcnt, + const void *buffer) +{ + size_t len = blkcnt * info->blksz; + u32 offset = blk * info->blksz; + int ret; + + ret = spi_flash_erase(flash, offset, ROUND(len, flash->erase_size)); + if (ret < 0) { + printf("Failed to erase sparse chunk (%d)\n", ret); + return ret; + } + + ret = spi_flash_write(flash, offset, len, buffer); + if (ret < 0) { + printf("Failed to write sparse chunk (%d)\n", ret); + return ret; + } + + return blkcnt; +} + +static lbaint_t fb_spi_flash_sparse_reserve(struct sparse_storage *info, + lbaint_t blk, lbaint_t blkcnt) +{ + return blkcnt; +} + +/** + * fastboot_spi_flash_get_part_info() - Lookup SPI partition by name + * + * @part_name: Named device to lookup + * @part_info: Pointer to returned struct disk_partition + * @response: Pointer to fastboot response buffer + * Return: 0 if OK, -ENOENT if no partition name was given, -ENODEV on invalid + * raw partition descriptor + */ +int fastboot_spi_flash_get_part_info(const char *part_name, + struct disk_partition *part_info, + char *response) +{ + int ret; + + if (!part_name || !strcmp(part_name, "")) { + fastboot_fail("partition not given", response); + return -ENOENT; + } + + /* TODO: Support partitions on the device */ + ret = raw_part_get_info_by_name(part_name, part_info); + if (ret < 0) + fastboot_fail("invalid partition or device", response); + + return ret; +} + +/** + * fastboot_spi_flash_write() - Write image to SPI for fastboot + * + * @cmd: Named device to write image to + * @download_buffer: Pointer to image data + * @download_bytes: Size of image data + * @response: Pointer to fastboot response buffer + */ +void fastboot_spi_flash_write(const char *cmd, void *download_buffer, + u32 download_bytes, char *response) +{ + struct disk_partition part_info; + int ret; + + if (fastboot_spi_flash_get_part_info(cmd, &part_info, response)) + return; + + if (fastboot_spi_flash_probe()) + return; + + if (board_fastboot_spi_flash_write_setup()) + return; + + if (fastboot_spi_flash_unlock(flash, &part_info)) + return; + + if (is_sparse_image(download_buffer)) { + struct sparse_storage sparse; + + sparse.blksz = flash->sector_size; + sparse.start = part_info.start / sparse.blksz; + sparse.size = part_info.size / sparse.blksz; + sparse.write = fb_spi_flash_sparse_write; + sparse.reserve = fb_spi_flash_sparse_reserve; + sparse.mssg = fastboot_fail; + + printf("Flashing sparse image at offset " LBAFU "\n", + sparse.start); + + ret = write_sparse_image(&sparse, cmd, download_buffer, + response); + } else { + printf("Flashing raw image at offset " LBAFU "\n", + part_info.start); + + ret = spi_flash_erase(flash, part_info.start, + ROUND(download_bytes, flash->erase_size)); + if (ret < 0) { + printf("Failed to erase raw image (%d)\n", ret); + return; + } + ret = spi_flash_write(flash, part_info.start, download_bytes, + download_buffer); + if (ret < 0) { + printf("Failed to write raw image (%d)\n", ret); + return; + } + printf("........ wrote %u bytes\n", download_bytes); + } + + if (ret) + fastboot_fail("error writing the image", response); + else + fastboot_okay(NULL, response); +} + +/** + * fastboot_spi_flash_erase() - Erase SPI for fastboot + * + * @cmd: Named device to erase + * @response: Pointer to fastboot response buffer + */ +void fastboot_spi_flash_erase(const char *cmd, char *response) +{ + struct disk_partition part_info; + int ret; + + if (fastboot_spi_flash_get_part_info(cmd, &part_info, response)) + return; + + if (fastboot_spi_flash_probe()) + return; + + if (board_fastboot_spi_flash_erase_setup()) + return; + + if (fastboot_spi_flash_unlock(flash, &part_info)) + return; + + ret = spi_flash_erase(flash, part_info.start, part_info.size); + if (ret < 0) { + pr_err("failed erasing from SPI flash"); + fastboot_fail("failed erasing from SPI flash", response); + return; + } + + fastboot_okay(NULL, response); +} diff --git a/drivers/firmware/firmware-zynqmp.c b/drivers/firmware/firmware-zynqmp.c index d18ae523b6b..e07ec3929b2 100644 --- a/drivers/firmware/firmware-zynqmp.c +++ b/drivers/firmware/firmware-zynqmp.c @@ -500,11 +500,8 @@ static int zynqmp_firmware_bind(struct udevice *dev) if (!smc_call_handler) return -EINVAL; - if ((IS_ENABLED(CONFIG_XPL_BUILD) && - IS_ENABLED(CONFIG_SPL_POWER_DOMAIN) && - IS_ENABLED(CONFIG_ZYNQMP_POWER_DOMAIN)) || - (!IS_ENABLED(CONFIG_XPL_BUILD) && - IS_ENABLED(CONFIG_ZYNQMP_POWER_DOMAIN))) { + if (CONFIG_IS_ENABLED(POWER_DOMAIN) && + IS_ENABLED(CONFIG_ZYNQMP_POWER_DOMAIN)) { ret = device_bind_driver_to_node(dev, "zynqmp_power_domain", "zynqmp_power_domain", dev_ofnode(dev), &child); diff --git a/drivers/fpga/ACEX1K.c b/drivers/fpga/ACEX1K.c index 3de9011ac06..e1514fc56d0 100644 --- a/drivers/fpga/ACEX1K.c +++ b/drivers/fpga/ACEX1K.c @@ -14,6 +14,7 @@ #include <log.h> #include <ACEX1K.h> /* ACEX device family */ #include <linux/delay.h> +#include <time.h> /* Note: The assumption is that we cannot possibly run fast enough to * overrun the device (the Slave Parallel mode can free run at 50MHz). diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig index 62cb77b098c..9456ca3149a 100644 --- a/drivers/fpga/Kconfig +++ b/drivers/fpga/Kconfig @@ -15,6 +15,7 @@ config FPGA_ALTERA config FPGA_SOCFPGA bool "Enable Gen5 and Arria10 common FPGA drivers" + depends on ARCH_SOCFPGA select FPGA_ALTERA help Say Y here to enable the Gen5 and Arria10 common FPGA driver diff --git a/drivers/fpga/fpga.c b/drivers/fpga/fpga.c index f88267e01b6..2297fefd149 100644 --- a/drivers/fpga/fpga.c +++ b/drivers/fpga/fpga.c @@ -16,20 +16,6 @@ static int next_desc = FPGA_INVALID_DEVICE; static fpga_desc desc_table[CONFIG_MAX_FPGA_DEVICES]; -/* - * fpga_no_sup - * 'no support' message function - */ -static void fpga_no_sup(char *fn, char *msg) -{ - if (fn && msg) - printf("%s: No support for %s.\n", fn, msg); - else if (msg) - printf("No support for %s.\n", msg); - else - printf("No FPGA support!\n"); -} - /* fpga_get_desc * map a device number to a descriptor */ @@ -39,8 +25,8 @@ const fpga_desc *fpga_get_desc(int devnum) if ((devnum >= 0) && (devnum < next_desc)) { desc = &desc_table[devnum]; - debug("%s: found fpga descriptor #%d @ 0x%p\n", - __func__, devnum, desc); + log_debug("found fpga descriptor #%d @ 0x%p\n", + devnum, desc); } return desc; @@ -51,15 +37,15 @@ const fpga_desc *fpga_get_desc(int devnum) * generic parameter checking code */ const fpga_desc *fpga_validate(int devnum, const void *buf, - size_t bsize, char *fn) + size_t bsize) { const fpga_desc *desc = fpga_get_desc(devnum); if (!desc) - printf("%s: Invalid device number %d\n", fn, devnum); + log_err("Invalid device number %d\n", devnum); if (!buf) { - printf("%s: Null buffer.\n", fn); + log_err("Null buffer.\n"); return NULL; } return desc; @@ -75,40 +61,40 @@ static int fpga_dev_info(int devnum) const fpga_desc *desc = fpga_get_desc(devnum); if (desc) { - debug("%s: Device Descriptor @ 0x%p\n", - __func__, desc->devdesc); + log_info("Device Descriptor @ 0x%p\n", + desc->devdesc); switch (desc->devtype) { case fpga_xilinx: #if defined(CONFIG_FPGA_XILINX) - printf("Xilinx Device\nDescriptor @ 0x%p\n", desc); + log_info("Xilinx Device\nDescriptor @ 0x%p\n", desc); ret_val = xilinx_info(desc->devdesc); #else - fpga_no_sup((char *)__func__, "Xilinx devices"); + log_err("No support for Xilinx devices.\n"); #endif break; case fpga_altera: #if defined(CONFIG_FPGA_ALTERA) - printf("Altera Device\nDescriptor @ 0x%p\n", desc); + log_info("Altera Device\nDescriptor @ 0x%p\n", desc); ret_val = altera_info(desc->devdesc); #else - fpga_no_sup((char *)__func__, "Altera devices"); + log_err("No support for Altera devices.\n"); #endif break; case fpga_lattice: #if defined(CONFIG_FPGA_LATTICE) - printf("Lattice Device\nDescriptor @ 0x%p\n", desc); + log_info("Lattice Device\nDescriptor @ 0x%p\n", desc); ret_val = lattice_info(desc->devdesc); #else - fpga_no_sup((char *)__func__, "Lattice devices"); + log_err("No support for Lattice devices.\n"); #endif break; default: - printf("%s: Invalid or unsupported device type %d\n", - __func__, desc->devtype); + log_err("Invalid or unsupported device type %d\n", + desc->devtype); } } else { - printf("%s: Invalid device number %d\n", __func__, devnum); + log_err("Invalid device number %d\n", devnum); } return ret_val; @@ -144,23 +130,22 @@ int fpga_add(fpga_type devtype, void *desc) int devnum = FPGA_INVALID_DEVICE; if (!desc) { - printf("%s: NULL device descriptor\n", __func__); + log_err("NULL device descriptor\n"); return devnum; } if (next_desc < 0) { - printf("%s: FPGA support not initialized!\n", __func__); + log_err("FPGA support not initialized!\n"); } else if ((devtype > fpga_min_type) && (devtype < fpga_undefined)) { if (next_desc < CONFIG_MAX_FPGA_DEVICES) { devnum = next_desc; desc_table[next_desc].devtype = devtype; desc_table[next_desc++].devdesc = desc; } else { - printf("%s: Exceeded Max FPGA device count\n", - __func__); + log_err("Exceeded Max FPGA device count\n"); } } else { - printf("%s: Unsupported FPGA type %d\n", __func__, devtype); + log_err("Unsupported FPGA type %d\n", devtype); } return devnum; @@ -181,7 +166,7 @@ int __weak fpga_is_partial_data(int devnum, size_t img_len) int __weak fpga_loadbitstream(int devnum, char *fpgadata, size_t size, bitstream_type bstype) { - printf("Bitstream support not implemented for this FPGA device\n"); + log_err("Bitstream support not implemented for this FPGA device\n"); return FPGA_FAIL; } @@ -190,8 +175,7 @@ int fpga_fsload(int devnum, const void *buf, size_t size, fpga_fs_info *fpga_fsinfo) { int ret_val = FPGA_FAIL; /* assume failure */ - const fpga_desc *desc = fpga_validate(devnum, buf, size, - (char *)__func__); + const fpga_desc *desc = fpga_validate(devnum, buf, size); if (desc) { switch (desc->devtype) { @@ -200,12 +184,12 @@ int fpga_fsload(int devnum, const void *buf, size_t size, ret_val = xilinx_loadfs(desc->devdesc, buf, size, fpga_fsinfo); #else - fpga_no_sup((char *)__func__, "Xilinx devices"); + log_err("No support for Xilinx devices.\n"); #endif break; default: - printf("%s: Invalid or unsupported device type %d\n", - __func__, desc->devtype); + log_err("Invalid or unsupported device type %d\n", + desc->devtype); } } @@ -219,8 +203,7 @@ int fpga_loads(int devnum, const void *buf, size_t size, { int ret_val = FPGA_FAIL; - const fpga_desc *desc = fpga_validate(devnum, buf, size, - (char *)__func__); + const fpga_desc *desc = fpga_validate(devnum, buf, size); if (desc) { switch (desc->devtype) { @@ -229,12 +212,12 @@ int fpga_loads(int devnum, const void *buf, size_t size, ret_val = xilinx_loads(desc->devdesc, buf, size, fpga_sec_info); #else - fpga_no_sup((char *)__func__, "Xilinx devices"); + log_err("No support for Xilinx devices.\n"); #endif break; default: - printf("%s: Invalid or unsupported device type %d\n", - __func__, desc->devtype); + log_err("Invalid or unsupported device type %d\n", + desc->devtype); } } @@ -265,8 +248,7 @@ int fpga_load(int devnum, const void *buf, size_t bsize, bitstream_type bstype, { int ret_val = FPGA_FAIL; /* assume failure */ int ret_notify; - const fpga_desc *desc = fpga_validate(devnum, buf, bsize, - (char *)__func__); + const fpga_desc *desc = fpga_validate(devnum, buf, bsize); if (desc) { switch (desc->devtype) { @@ -275,26 +257,26 @@ int fpga_load(int devnum, const void *buf, size_t bsize, bitstream_type bstype, ret_val = xilinx_load(desc->devdesc, buf, bsize, bstype, flags); #else - fpga_no_sup((char *)__func__, "Xilinx devices"); + log_err("No support for Xilinx devices.\n"); #endif break; case fpga_altera: #if defined(CONFIG_FPGA_ALTERA) ret_val = altera_load(desc->devdesc, buf, bsize); #else - fpga_no_sup((char *)__func__, "Altera devices"); + log_err("No support for Altera devices.\n"); #endif break; case fpga_lattice: #if defined(CONFIG_FPGA_LATTICE) ret_val = lattice_load(desc->devdesc, buf, bsize); #else - fpga_no_sup((char *)__func__, "Lattice devices"); + log_err("No support for Lattice devices.\n"); #endif break; default: - printf("%s: Invalid or unsupported device type %d\n", - __func__, desc->devtype); + log_err("Invalid or unsupported device type %d\n", + desc->devtype); } } @@ -312,8 +294,7 @@ int fpga_load(int devnum, const void *buf, size_t bsize, bitstream_type bstype, int fpga_dump(int devnum, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; /* assume failure */ - const fpga_desc *desc = fpga_validate(devnum, buf, bsize, - (char *)__func__); + const fpga_desc *desc = fpga_validate(devnum, buf, bsize); if (desc) { switch (desc->devtype) { @@ -321,26 +302,26 @@ int fpga_dump(int devnum, const void *buf, size_t bsize) #if defined(CONFIG_FPGA_XILINX) ret_val = xilinx_dump(desc->devdesc, buf, bsize); #else - fpga_no_sup((char *)__func__, "Xilinx devices"); + log_err("No support for Xilinx devices.\n"); #endif break; case fpga_altera: #if defined(CONFIG_FPGA_ALTERA) ret_val = altera_dump(desc->devdesc, buf, bsize); #else - fpga_no_sup((char *)__func__, "Altera devices"); + log_err("No support for Altera devices.\n"); #endif break; case fpga_lattice: #if defined(CONFIG_FPGA_LATTICE) ret_val = lattice_dump(desc->devdesc, buf, bsize); #else - fpga_no_sup((char *)__func__, "Lattice devices"); + log_err("No support for Lattice devices.\n"); #endif break; default: - printf("%s: Invalid or unsupported device type %d\n", - __func__, desc->devtype); + log_err("Invalid or unsupported device type %d\n", + desc->devtype); } } @@ -363,7 +344,7 @@ int fpga_info(int devnum) return FPGA_SUCCESS; } else { - printf("%s: No FPGA devices available.\n", __func__); + log_err("No FPGA devices available.\n"); return FPGA_FAIL; } } diff --git a/drivers/fpga/ivm_core.c b/drivers/fpga/ivm_core.c index 3c9a01e5110..37d5c5ec9ec 100644 --- a/drivers/fpga/ivm_core.c +++ b/drivers/fpga/ivm_core.c @@ -33,6 +33,7 @@ #include <linux/string.h> #include <malloc.h> #include <lattice.h> +#include <vsprintf.h> #define vme_out_char(c) printf("%c", c) #define vme_out_hex(c) printf("%x", c) @@ -291,7 +292,7 @@ unsigned short g_usLVDSPairCount; */ static signed char ispVMDataCode(void); -static long int ispVMDataSize(void); +static long ispVMDataSize(void); static void ispVMData(unsigned char *Data); static signed char ispVMShift(signed char Code); static signed char ispVMAmble(signed char Code); @@ -589,7 +590,7 @@ void ispVMFreeMem(void) * */ -long int ispVMDataSize() +long ispVMDataSize(void) { /* 09/11/07 NN added local variables initialization */ long int iSize = 0; @@ -614,7 +615,7 @@ long int ispVMDataSize() * */ -signed char ispVMCode() +signed char ispVMCode(void) { /* 09/11/07 NN added local variables initialization */ unsigned short iRepeatSize = 0; @@ -1113,7 +1114,7 @@ signed char ispVMCode() * */ -signed char ispVMDataCode() +signed char ispVMDataCode(void) { /* 09/11/07 NN added local variables initialization */ signed char cDataByte = 0; @@ -2475,7 +2476,7 @@ void ispVMStateMachine(signed char cNextJTAGState) * */ -void ispVMStart() +void ispVMStart(void) { #ifdef DEBUG printf("// ISPVM EMBEDDED ADDED\n"); @@ -2504,7 +2505,7 @@ void ispVMStart() * */ -void ispVMEnd() +void ispVMEnd(void) { #ifdef DEBUG printf("// ISPVM EMBEDDED ADDED\n"); diff --git a/drivers/fpga/lattice.c b/drivers/fpga/lattice.c index 3f481e38565..29cf2f60974 100644 --- a/drivers/fpga/lattice.c +++ b/drivers/fpga/lattice.c @@ -350,8 +350,8 @@ int lattice_info(Lattice_desc *desc) printf("Unsupported interface type, %d\n", desc->iface); } - printf("Device Size: \t%d bytes\n", - desc->size); + printf("Device Size: \t%zu bytes\n", + desc->size); if (desc->iface_fns) { printf("Device Function Table @ 0x%p\n", diff --git a/drivers/fpga/spartan2.c b/drivers/fpga/spartan2.c index 906649ea181..792e4033428 100644 --- a/drivers/fpga/spartan2.c +++ b/drivers/fpga/spartan2.c @@ -9,6 +9,7 @@ #include <config.h> /* core U-Boot definitions */ #include <log.h> #include <spartan2.h> /* Spartan-II device family */ +#include <time.h> /* Note: The assumption is that we cannot possibly run fast enough to * overrun the device (the Slave Parallel mode can free run at 50MHz). diff --git a/drivers/fpga/stratixII.c b/drivers/fpga/stratixII.c index 73fecd9dca5..3f984385316 100644 --- a/drivers/fpga/stratixII.c +++ b/drivers/fpga/stratixII.c @@ -5,92 +5,41 @@ */ #include <altera.h> +#include <stratixII.h> #include <linux/delay.h> -int StratixII_ps_fpp_load (Altera_desc * desc, void *buf, size_t bsize, - int isSerial, int isSecure); -int StratixII_ps_fpp_dump (Altera_desc * desc, void *buf, size_t bsize); - /****************************************************************/ /* Stratix II Generic Implementation */ -int StratixII_load (Altera_desc * desc, void *buf, size_t bsize) -{ - int ret_val = FPGA_FAIL; - - switch (desc->iface) { - case passive_serial: - ret_val = StratixII_ps_fpp_load (desc, buf, bsize, 1, 0); - break; - case fast_passive_parallel: - ret_val = StratixII_ps_fpp_load (desc, buf, bsize, 0, 0); - break; - case fast_passive_parallel_security: - ret_val = StratixII_ps_fpp_load (desc, buf, bsize, 0, 1); - break; - - /* Add new interface types here */ - default: - printf ("%s: Unsupported interface type, %d\n", __FUNCTION__, - desc->iface); - } - return ret_val; -} - -int StratixII_dump (Altera_desc * desc, void *buf, size_t bsize) -{ - int ret_val = FPGA_FAIL; - - switch (desc->iface) { - case passive_serial: - case fast_passive_parallel: - case fast_passive_parallel_security: - ret_val = StratixII_ps_fpp_dump (desc, buf, bsize); - break; - /* Add new interface types here */ - default: - printf ("%s: Unsupported interface type, %d\n", __FUNCTION__, - desc->iface); - } - return ret_val; -} - -int StratixII_info (Altera_desc * desc) -{ - return FPGA_SUCCESS; -} - -int StratixII_ps_fpp_dump (Altera_desc * desc, void *buf, size_t bsize) +int StratixII_ps_fpp_dump(Altera_desc *desc, const void *buf, size_t bsize) { - printf ("Stratix II Fast Passive Parallel dump is not implemented\n"); + printf("Stratix II Fast Passive Parallel dump is not implemented\n"); return FPGA_FAIL; } -int StratixII_ps_fpp_load (Altera_desc * desc, void *buf, size_t bsize, - int isSerial, int isSecure) +int StratixII_ps_fpp_load(Altera_desc *desc, const void *buf, size_t bsize, + int isSerial, int isSecure) { altera_board_specific_func *fns; int cookie; int ret_val = FPGA_FAIL; int bytecount; - char *buff = buf; + const char *buff = buf; int i; if (!desc) { - printf ("%s(%d) Altera_desc missing\n", __FUNCTION__, __LINE__); + log_err("Altera_desc missing\n"); return FPGA_FAIL; } if (!buff) { - printf ("%s(%d) buffer is missing\n", __FUNCTION__, __LINE__); + log_err("buffer is missing\n"); return FPGA_FAIL; } if (!bsize) { - printf ("%s(%d) size is zero\n", __FUNCTION__, __LINE__); + log_err("size is zero\n"); return FPGA_FAIL; } if (!desc->iface_fns) { - printf - ("%s(%d) Altera_desc function interface table is missing\n", - __FUNCTION__, __LINE__); + log_err("Altera_desc function interface table is missing\n"); return FPGA_FAIL; } fns = (altera_board_specific_func *) (desc->iface_fns); @@ -99,9 +48,7 @@ int StratixII_ps_fpp_load (Altera_desc * desc, void *buf, size_t bsize, if (! (fns->config && fns->status && fns->done && fns->data && fns->abort)) { - printf - ("%s(%d) Missing some function in the function interface table\n", - __FUNCTION__, __LINE__); + log_err("Missing some function in the function interface table\n"); return FPGA_FAIL; } @@ -124,13 +71,12 @@ int StratixII_ps_fpp_load (Altera_desc * desc, void *buf, size_t bsize, bytecount = 0; fns->clk (0, 1, cookie); - printf ("loading to fpga "); + printf("loading to fpga "); while (bytecount < bsize) { /* 3.1 check stratix has not signaled us an error */ if (fns->status (cookie) != 1) { - printf - ("\n%s(%d) Stratix failed (byte transferred till failure 0x%x)\n", - __FUNCTION__, __LINE__, bytecount); + log_err("\nStratix failed (byte transferred till failure 0x%x)\n", + bytecount); fns->abort (cookie); return FPGA_FAIL; } @@ -162,7 +108,7 @@ int StratixII_ps_fpp_load (Altera_desc * desc, void *buf, size_t bsize, /* 3.5 while clk is deasserted it is safe to print some progress indication */ if ((bytecount % (bsize / 100)) == 0) { - printf ("\b\b\b%02d\%", bytecount * 100 / bsize); + printf("\b\b\b%02zu\%%", bytecount * 100 / bsize); } } @@ -170,11 +116,11 @@ int StratixII_ps_fpp_load (Altera_desc * desc, void *buf, size_t bsize, fns->clk (1, 1, cookie); udelay(100); if (!fns->done (cookie)) { - printf (" error!.\n"); + printf(" error!.\n"); fns->abort (cookie); return FPGA_FAIL; } else { - printf ("\b\b\b done.\n"); + printf("\b\b\b done.\n"); } /* 5. call lower layer post configuration */ @@ -187,3 +133,47 @@ int StratixII_ps_fpp_load (Altera_desc * desc, void *buf, size_t bsize, return FPGA_SUCCESS; } + +int StratixII_load(Altera_desc *desc, const void *buf, size_t size) +{ + int ret_val = FPGA_FAIL; + + switch (desc->iface) { + case passive_serial: + ret_val = StratixII_ps_fpp_load(desc, buf, size, 1, 0); + break; + case fast_passive_parallel: + ret_val = StratixII_ps_fpp_load(desc, buf, size, 0, 0); + break; + case fast_passive_parallel_security: + ret_val = StratixII_ps_fpp_load(desc, buf, size, 0, 1); + break; + + /* Add new interface types here */ + default: + log_err("Unsupported interface type, %d\n", desc->iface); + } + return ret_val; +} + +int StratixII_dump(Altera_desc *desc, const void *buf, size_t bsize) +{ + int ret_val = FPGA_FAIL; + + switch (desc->iface) { + case passive_serial: + case fast_passive_parallel: + case fast_passive_parallel_security: + ret_val = StratixII_ps_fpp_dump(desc, buf, bsize); + break; + /* Add new interface types here */ + default: + log_err("Unsupported interface type, %d\n", desc->iface); + } + return ret_val; +} + +int StratixII_info(Altera_desc *desc) +{ + return FPGA_SUCCESS; +} diff --git a/drivers/fpga/stratixv.c b/drivers/fpga/stratixv.c index 372f16d92d1..4b251994598 100644 --- a/drivers/fpga/stratixv.c +++ b/drivers/fpga/stratixv.c @@ -48,7 +48,7 @@ int stratixv_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size) int spi_dev; int ret = 0; - if ((u32)rbf_data & 0x3) { + if ((size_t)rbf_data & 0x3) { puts("FPGA: Unaligned data, realign to 32bit boundary.\n"); return -EINVAL; } diff --git a/drivers/fpga/versalpl.c b/drivers/fpga/versalpl.c index d691f135e89..624493ad838 100644 --- a/drivers/fpga/versalpl.c +++ b/drivers/fpga/versalpl.c @@ -6,7 +6,6 @@ #include <cpu_func.h> #include <log.h> -#include <asm/arch/sys_proto.h> #include <memalign.h> #include <versalpl.h> #include <zynqmp_firmware.h> diff --git a/drivers/fpga/virtex2.c b/drivers/fpga/virtex2.c index 8e2c12bb58b..805cbac8082 100644 --- a/drivers/fpga/virtex2.c +++ b/drivers/fpga/virtex2.c @@ -19,6 +19,7 @@ #include <log.h> #include <virtex2.h> #include <linux/delay.h> +#include <time.h> /* * If the SelectMap interface can be overrun by the processor, enable @@ -301,6 +302,7 @@ static int virtex2_ssm_load(xilinx_desc *desc, const void *buf, size_t bsize) size_t bytecount = 0; unsigned char *data = (unsigned char *)buf; int cookie = desc->cookie; + unsigned long ts; ret_val = virtex2_slave_pre(fn, cookie); if (ret_val != FPGA_SUCCESS) diff --git a/drivers/fpga/xilinx.c b/drivers/fpga/xilinx.c index c46513226d9..28c68faba55 100644 --- a/drivers/fpga/xilinx.c +++ b/drivers/fpga/xilinx.c @@ -49,7 +49,7 @@ int fpga_loadbitstream(int devnum, char *fpgadata, size_t size, dataptr = (unsigned char *)fpgadata; /* Find out fpga_description */ - desc = fpga_validate(devnum, dataptr, 0, (char *)__func__); + desc = fpga_validate(devnum, dataptr, 0); /* Assign xilinx device description */ xdesc = desc->devdesc; diff --git a/drivers/fpga/zynqmppl.c b/drivers/fpga/zynqmppl.c index 2b62bbbe3cf..1199b249e36 100644 --- a/drivers/fpga/zynqmppl.c +++ b/drivers/fpga/zynqmppl.c @@ -191,8 +191,8 @@ static int zynqmp_validate_bitstream(xilinx_desc *desc, const void *buf, } if ((ulong)buf < SZ_1M) { - printf("%s: Bitstream has to be placed up to 1MB (%px)\n", - __func__, buf); + log_err("Bitstream has to be placed above 1MB (%px)\n", + buf); return FPGA_FAIL; } diff --git a/drivers/fpga/zynqpl.c b/drivers/fpga/zynqpl.c index 3e86d854a01..5a37a33b0a7 100644 --- a/drivers/fpga/zynqpl.c +++ b/drivers/fpga/zynqpl.c @@ -360,8 +360,8 @@ static int zynq_validate_bitstream(xilinx_desc *desc, const void *buf, } if ((u32)buf < SZ_1M) { - printf("%s: Bitstream has to be placed up to 1MB (%x)\n", - __func__, (u32)buf); + log_err("Bitstream has to be placed above 1MB (%x)\n", + (u32)buf); return FPGA_FAIL; } diff --git a/drivers/gpio/zynq_gpio.c b/drivers/gpio/zynq_gpio.c index 7db58c70663..ef4f33f84e9 100644 --- a/drivers/gpio/zynq_gpio.c +++ b/drivers/gpio/zynq_gpio.c @@ -184,6 +184,7 @@ static const struct zynq_platform_data zynq_gpio_def = { * pin * @bank_pin_num: an output parameter used to return pin number within a bank * for the given gpio pin + * @dev: Pointer to our device structure. * * Returns the bank number and pin offset within the bank. */ diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig index 775b2b4e9af..108b24b3dd2 100644 --- a/drivers/i2c/Kconfig +++ b/drivers/i2c/Kconfig @@ -181,6 +181,7 @@ config SYS_I2C_IPROC config SYS_I2C_FSL bool "Freescale I2C bus driver" + depends on M68K || PPC help Add support for Freescale I2C busses as used on MPC8240, MPC8245, and MPC85xx processors. @@ -240,7 +241,7 @@ config SYS_I2C_DW config SYS_I2C_DW_PCI bool "Designware PCI I2C Controller" - depends on SYS_I2C_DW && PCI && ACPIGEN + depends on SYS_I2C_DW && PCI && ACPIGEN && X86 default y help Say yes here to select the Designware PCI I2C Host Controller. @@ -277,6 +278,7 @@ config SYS_I2C_INTEL config SYS_I2C_IMX_LPI2C bool "NXP i.MX LPI2C driver" + depends on MACH_IMX help Add support for the NXP i.MX LPI2C driver. @@ -314,6 +316,7 @@ config SYS_I2C_MICROCHIP config SYS_I2C_MXC bool "NXP MXC I2C driver" + depends on ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3 || MACH_IMX help Add support for the NXP I2C driver. This supports up to four bus channels and operating on standard mode up to 100 kbits/s and fast @@ -485,7 +488,7 @@ endif config SYS_I2C_NEXELL bool "Nexell I2C driver" - depends on DM_I2C + depends on DM_I2C && ARCH_NEXELL help Add support for the Nexell I2C driver. This is used with various Nexell parts such as S5Pxx18 series SoCs. All chips @@ -494,6 +497,7 @@ config SYS_I2C_NEXELL config SYS_I2C_NPCM bool "Nuvoton NPCM I2C driver" + depends on ARCH_NPCM help Support for Nuvoton I2C controller driver. @@ -533,7 +537,7 @@ config SYS_I2C_RCAR_IIC config SYS_I2C_ROCKCHIP bool "Rockchip I2C driver" - depends on DM_I2C + depends on DM_I2C && ARCH_ROCKCHIP help Add support for the Rockchip I2C driver. This is used with various Rockchip parts such as RK3126, RK3128, RK3036 and RK3288. All chips @@ -751,6 +755,7 @@ config SYS_I2C_MV config SYS_I2C_MVTWSI bool "Marvell I2C driver" + depends on ARCH_KIRKWOOD || ARCH_MVEBU || ARCH_SUNXI help Support for Marvell I2C controllers as used on the orion5x and kirkwood SoC families. diff --git a/drivers/i2c/iproc_i2c.c b/drivers/i2c/iproc_i2c.c index 6570f64fe77..8f94dfe117e 100644 --- a/drivers/i2c/iproc_i2c.c +++ b/drivers/i2c/iproc_i2c.c @@ -8,6 +8,7 @@ #include <asm/io.h> #include <config.h> #include <dm.h> +#include <linux/delay.h> #include <linux/printk.h> #include "errno.h" #include <i2c.h> diff --git a/drivers/i2c/muxes/Kconfig b/drivers/i2c/muxes/Kconfig index cd5579aa55a..65319bb6fd8 100644 --- a/drivers/i2c/muxes/Kconfig +++ b/drivers/i2c/muxes/Kconfig @@ -25,6 +25,13 @@ config I2C_ARB_GPIO_CHALLENGE response mechanism where masters have to claim the bus by asserting a GPIO. +config I2C_MUX_PCA9541 + tristate "NXP PCA9541 I2C Master Selector" + depends on I2C_MUX + help + If you say yes here you get support for the NXP PCA9541 + I2C Master Selector. + config I2C_MUX_PCA954x tristate "TI PCA954x I2C Mux/switches" depends on I2C_MUX diff --git a/drivers/i2c/muxes/Makefile b/drivers/i2c/muxes/Makefile index b690821199f..844d4520e43 100644 --- a/drivers/i2c/muxes/Makefile +++ b/drivers/i2c/muxes/Makefile @@ -3,5 +3,6 @@ # Copyright (c) 2015 Google, Inc obj-$(CONFIG_I2C_ARB_GPIO_CHALLENGE) += i2c-arb-gpio-challenge.o obj-$(CONFIG_I2C_MUX) += i2c-mux-uclass.o +obj-$(CONFIG_I2C_MUX_PCA9541) += pca9541.o obj-$(CONFIG_I2C_MUX_PCA954x) += pca954x.o obj-$(CONFIG_I2C_MUX_GPIO) += i2c-mux-gpio.o diff --git a/drivers/i2c/muxes/pca9541.c b/drivers/i2c/muxes/pca9541.c new file mode 100644 index 00000000000..021088acaee --- /dev/null +++ b/drivers/i2c/muxes/pca9541.c @@ -0,0 +1,297 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2008-2009 Rodolfo Giometti <giometti@linux.it> + * Copyright (c) 2008-2009 Eurotech S.p.A. <info@eurotech.it> + * Copyright (c) 2010 Ericsson AB. + * Copyright (c) 2025 Advanced Micro Devices, Inc. + */ + +#include <dm.h> +#include <errno.h> +#include <i2c.h> +#include <log.h> +#include <malloc.h> +#include <linux/delay.h> + +/* + * The PCA9541 is a bus master selector. It supports two I2C masters connected + * to a single slave bus. + * + * Before each bus transaction, a master has to acquire bus ownership. After the + * transaction is complete, bus ownership has to be released. This fits well + * into the I2C multiplexer framework, which provides select and release + * functions for this purpose. For this reason, this driver is modeled as + * single-channel I2C bus multiplexer. + * + * This driver assumes that the two bus masters are controlled by two different + * hosts. If a single host controls both masters, platform code has to ensure + * that only one of the masters is instantiated at any given time. + */ + +#define PCA9541_CONTROL 0x01 +#define PCA9541_ISTAT 0x02 + +#define PCA9541_CTL_MYBUS BIT(0) +#define PCA9541_CTL_NMYBUS BIT(1) +#define PCA9541_CTL_BUSON BIT(2) +#define PCA9541_CTL_NBUSON BIT(3) +#define PCA9541_CTL_BUSINIT BIT(4) +#define PCA9541_CTL_TESTON BIT(6) +#define PCA9541_CTL_NTESTON BIT(7) + +#define PCA9541_ISTAT_INTIN BIT(0) +#define PCA9541_ISTAT_BUSINIT BIT(1) +#define PCA9541_ISTAT_BUSOK BIT(2) +#define PCA9541_ISTAT_BUSLOST BIT(3) +#define PCA9541_ISTAT_MYTEST BIT(6) +#define PCA9541_ISTAT_NMYTEST BIT(7) + +#define BUSON (PCA9541_CTL_BUSON | PCA9541_CTL_NBUSON) +#define MYBUS (PCA9541_CTL_MYBUS | PCA9541_CTL_NMYBUS) + +/* arbitration timeouts, in jiffies */ +#define ARB_TIMEOUT_US 125000 /* 125 ms until forcing bus ownership */ +#define ARB2_TIMEOUT_US 250000 /* 250 ms until acquisition failure */ + +/* arbitration retry delays, in us */ +#define SELECT_DELAY_SHORT 50 +#define SELECT_DELAY_LONG 1000 + +struct pca9541_plat { + u32 addr; +}; + +struct pca9541_priv { + u32 addr; + unsigned long select_timeout; + long arb_timeout; +}; + +static inline int mybus(int x) +{ + return !(x & MYBUS) || ((x & MYBUS) == MYBUS); +} + +static inline int busoff(int x) +{ + return !(x & BUSON) || ((x & BUSON) == BUSON); +} + +static int pca9541_reg_write(struct udevice *mux, struct pca9541_priv *client, + u8 command, u8 val) +{ + return dm_i2c_write(mux, command, &val, 1); +} + +static int pca9541_reg_read(struct udevice *mux, struct pca9541_priv *client, + u8 command) +{ + int ret; + uchar byte; + + ret = dm_i2c_read(mux, command, &byte, 1); + + return ret ?: byte; +} + +/* + * Arbitration management functions + */ + +/* Release bus. Also reset NTESTON and BUSINIT if it was set. */ +static void pca9541_release_bus(struct udevice *mux, struct pca9541_priv *client) +{ + int reg; + + reg = pca9541_reg_read(mux, client, PCA9541_CONTROL); + if (reg >= 0 && !busoff(reg) && mybus(reg)) + pca9541_reg_write(mux, client, PCA9541_CONTROL, + (reg & PCA9541_CTL_NBUSON) >> 1); +} + +/* + * Arbitration is defined as a two-step process. A bus master can only activate + * the slave bus if it owns it; otherwise it has to request ownership first. + * This multi-step process ensures that access contention is resolved + * gracefully. + * + * Bus Ownership Other master Action + * state requested access + * ---------------------------------------------------- + * off - yes wait for arbitration timeout or + * for other master to drop request + * off no no take ownership + * off yes no turn on bus + * on yes - done + * on no - wait for arbitration timeout or + * for other master to release bus + * + * The main contention point occurs if the slave bus is off and both masters + * request ownership at the same time. In this case, one master will turn on + * the slave bus, believing that it owns it. The other master will request + * bus ownership. Result is that the bus is turned on, and master which did + * _not_ own the slave bus before ends up owning it. + */ + +/* Control commands per PCA9541 datasheet */ +static const u8 pca9541_control[16] = { + 4, 0, 1, 5, 4, 4, 5, 5, 0, 0, 1, 1, 0, 4, 5, 1 +}; + +/* + * Channel arbitration + * + * Return values: + * <0: error + * 0 : bus not acquired + * 1 : bus acquired + */ +static int pca9541_arbitrate(struct udevice *mux, struct pca9541_priv *client) +{ + int reg, ret = 0; + + reg = pca9541_reg_read(mux, client, PCA9541_CONTROL); + if (reg < 0) + return reg; + + if (busoff(reg)) { + int istat; + + /* + * Bus is off. Request ownership or turn it on unless + * other master requested ownership. + */ + istat = pca9541_reg_read(mux, client, PCA9541_ISTAT); + if (!(istat & PCA9541_ISTAT_NMYTEST) || + client->arb_timeout <= 0) { + /* + * Other master did not request ownership, + * or arbitration timeout expired. Take the bus. + */ + pca9541_reg_write(mux, client, PCA9541_CONTROL, + pca9541_control[reg & 0x0f] + | PCA9541_CTL_NTESTON); + client->select_timeout = SELECT_DELAY_SHORT; + } else { + /* + * Other master requested ownership. + * Set extra long timeout to give it time to acquire it. + */ + client->select_timeout = SELECT_DELAY_LONG * 2; + } + } else if (mybus(reg)) { + /* + * Bus is on, and we own it. We are done with acquisition. + * Reset NTESTON and BUSINIT, then return success. + */ + if (reg & (PCA9541_CTL_NTESTON | PCA9541_CTL_BUSINIT)) + pca9541_reg_write(mux, client, PCA9541_CONTROL, + reg & ~(PCA9541_CTL_NTESTON + | PCA9541_CTL_BUSINIT)); + ret = 1; + } else { + /* + * Other master owns the bus. + * If arbitration timeout has expired, force ownership. + * Otherwise request it. + */ + client->select_timeout = SELECT_DELAY_LONG; + if (client->arb_timeout <= 0) { + /* Time is up, take the bus and reset it. */ + pca9541_reg_write(mux, client, PCA9541_CONTROL, + pca9541_control[reg & 0x0f] + | PCA9541_CTL_BUSINIT + | PCA9541_CTL_NTESTON); + } else { + /* Request bus ownership if needed */ + if (!(reg & PCA9541_CTL_NTESTON)) + pca9541_reg_write(mux, client, PCA9541_CONTROL, + reg | PCA9541_CTL_NTESTON); + } + } + + return ret; +} + +static int pca9541_select_chan(struct udevice *mux, struct udevice *bus, + uint channel) +{ + struct pca9541_priv *priv = dev_get_priv(mux); + int ret; + long timeout = ARB2_TIMEOUT_US; /* Give up after this time */ + + /* Force bus ownership after this time */ + priv->arb_timeout = ARB_TIMEOUT_US; + do { + ret = pca9541_arbitrate(mux, priv); + if (ret) + return ret < 0 ? ret : 0; + + udelay(priv->select_timeout); + timeout -= priv->select_timeout; + priv->arb_timeout -= priv->select_timeout; + } while (timeout > 0); + + debug("I2C Arbitration select timeout\n"); + + return -ETIMEDOUT; +} + +static int pca9541_release_chan(struct udevice *mux, struct udevice *bus, + uint channel) +{ + struct pca9541_priv *priv = dev_get_priv(mux); + + pca9541_release_bus(mux, priv); + + return 0; +} + +/* + * I2C init/probing/exit functions + */ +static int pca9541_of_to_plat(struct udevice *dev) +{ + struct pca9541_plat *plat = dev_get_plat(dev); + + plat->addr = dev_read_u32_default(dev, "reg", 0); + if (!plat->addr) { + debug("Reg property is not found\n"); + return -ENODEV; + } + + debug("Device %s at 0x%x\n", dev->name, plat->addr); + + return 0; +} + +static int pca9541_probe(struct udevice *dev) +{ + struct pca9541_plat *plat = dev_get_plat(dev); + struct pca9541_priv *priv = dev_get_priv(dev); + + priv->addr = plat->addr; + + return 0; +} + +static const struct i2c_mux_ops pca9541_ops = { + .select = pca9541_select_chan, + .deselect = pca9541_release_chan, +}; + +static const struct udevice_id pca9541_ids[] = { + { .compatible = "nxp,pca9541", }, + { } +}; + +U_BOOT_DRIVER(pca9541) = { + .name = "pca9541", + .id = UCLASS_I2C_MUX, + .of_match = pca9541_ids, + .probe = pca9541_probe, + .ops = &pca9541_ops, + .of_to_plat = pca9541_of_to_plat, + .plat_auto = sizeof(struct pca9541_plat), + .priv_auto = sizeof(struct pca9541_priv), +}; diff --git a/drivers/i2c/muxes/pca954x.c b/drivers/i2c/muxes/pca954x.c index 9dd26972703..d13947a0d9c 100644 --- a/drivers/i2c/muxes/pca954x.c +++ b/drivers/i2c/muxes/pca954x.c @@ -22,6 +22,7 @@ enum pca_type { MAX7369, PCA9543, PCA9544, + PCA9545, PCA9546, PCA9547, PCA9548, @@ -79,6 +80,10 @@ static const struct chip_desc chips[] = { .muxtype = pca954x_ismux, .width = 4, }, + [PCA9545] = { + .muxtype = pca954x_isswi, + .width = 4, + }, [PCA9546] = { .muxtype = pca954x_isswi, .width = 4, @@ -141,6 +146,7 @@ static const struct udevice_id pca954x_ids[] = { { .compatible = "maxim,max7369", .data = MAX7369 }, { .compatible = "nxp,pca9543", .data = PCA9543 }, { .compatible = "nxp,pca9544", .data = PCA9544 }, + { .compatible = "nxp,pca9545", .data = PCA9545 }, { .compatible = "nxp,pca9546", .data = PCA9546 }, { .compatible = "nxp,pca9547", .data = PCA9547 }, { .compatible = "nxp,pca9548", .data = PCA9548 }, diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index 966783e4b62..0f753b9dbb9 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -641,6 +641,14 @@ config ESM_K3 help Support ESM (Error Signaling Module) on TI K3 SoCs. +config K3_BIST + bool "Enable K3 BIST driver" + depends on ARCH_K3 + help + Support BIST (Built-In Self Test) module on TI K3 SoCs. This driver + supports running both PBIST (Memory BIST) and LBIST (Logic BIST) on + a region or IP in the SoC. + config MICROCHIP_FLEXCOM bool "Enable Microchip Flexcom driver" depends on MISC diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index 09dfd8072db..f7422c8e95a 100644 --- a/drivers/misc/Makefile +++ b/drivers/misc/Makefile @@ -88,6 +88,7 @@ obj-$(CONFIG_JZ4780_EFUSE) += jz4780_efuse.o obj-$(CONFIG_MICROCHIP_FLEXCOM) += microchip_flexcom.o obj-$(CONFIG_K3_AVS0) += k3_avs.o obj-$(CONFIG_ESM_K3) += k3_esm.o +obj-$(CONFIG_K3_BIST) += k3_bist.o obj-$(CONFIG_ESM_PMIC) += esm_pmic.o obj-$(CONFIG_SL28CPLD) += sl28cpld.o obj-$(CONFIG_SPL_SOCFPGA_DT_REG) += socfpga_dtreg.o diff --git a/drivers/misc/k3_bist.c b/drivers/misc/k3_bist.c new file mode 100644 index 00000000000..3acb1a1ac1f --- /dev/null +++ b/drivers/misc/k3_bist.c @@ -0,0 +1,807 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Texas Instruments' BIST (Built-In Self-Test) driver + * + * Copyright (C) 2025 Texas Instruments Incorporated - https://www.ti.com/ + * Neha Malcom Francis <n-francis@ti.com> + * + */ + +#include <dm.h> +#include <errno.h> +#include <clk.h> +#include <asm/io.h> +#include <dm/device_compat.h> +#include <linux/bitops.h> +#include <linux/delay.h> +#include <asm/arch/hardware.h> +#include <linux/soc/ti/ti_sci_protocol.h> +#include <remoteproc.h> +#include <power-domain.h> +#include <k3_bist.h> + +#include "k3_bist_static_data.h" + +/* PBIST Timeout Value */ +#define PBIST_MAX_TIMEOUT_VALUE 100000000 + +/** + * struct k3_bist_privdata - K3 BIST structure + * @dev: device pointer + * @pbist_base: base of register set for PBIST + * @instance: PBIST instance number + * @intr_num: corresponding interrupt ID of the PBIST instance + * @lbist_ctrl_mmr: base of CTRL MMR register set for LBIST + */ +struct k3_bist_privdata { + struct udevice *dev; + void *pbist_base; + u32 instance; + u32 intr_num; + void *lbist_ctrl_mmr; + struct pbist_inst_info *pbist_info; + struct lbist_inst_info *lbist_info; +}; + +static struct k3_bist_privdata *k3_bist_priv; + +/** + * check_post_pbist_result() - Check POST results + * + * Function to check whether HW Power-On Self Test, i.e. POST has run + * successfully on the MCU domain. + * + * Return: 0 if all went fine, else corresponding error. + */ +static int check_post_pbist_result(void) +{ + bool is_done, timed_out; + u32 mask; + u32 post_reg_val, shift; + + /* Read HW POST status register */ + post_reg_val = readl(WKUP_CTRL_MMR0_BASE + WKUP_CTRL_MMR_CFG0_WKUP_POST_STAT); + + /* Check if HW POST PBIST was performed */ + shift = WKUP_CTRL_MMR_CFG0_WKUP_POST_STAT_POST_MCU_PBIST_DONE_SHIFT; + is_done = (((post_reg_val >> shift) & 0x1u) == 0x1u) ? (bool)true : (bool)false; + + if (!is_done) { + /* HW POST: PBIST not completed, check if it timed out */ + shift = WKUP_CTRL_MMR_CFG0_WKUP_POST_STAT_POST_MCU_PBIST_TIMEOUT_SHIFT; + timed_out = (((post_reg_val >> shift) & 0x1u) == 0x1u) ? (bool)true : (bool)false; + + if (!timed_out) { + printf("%s: PBIST was not performed at all on this device for this core\n", + __func__); + return -EINVAL; + } + printf("%s: PBIST was attempted but timed out for this section\n", + __func__); + return -ETIMEDOUT; + + } else { + /* HW POST: PBIST was completed on this device, check the result */ + mask = WKUP_CTRL_MMR_CFG0_WKUP_POST_STAT_POST_MCU_PBIST_FAIL_MASK; + + if ((post_reg_val & mask) != 0) { + printf("%s: PBIST was completed, but the test failed\n", __func__); + return -EINVAL; + } + debug("%s: HW POST PBIST completed, test passed\n", __func__); + } + + return 0; +} + +/** + * check_post_lbist_result() - Check POST results + * + * Function to check whether HW Power-On Self Test, i.e. POST has run + * successfully on the MCU domain. + * + * Return: 0 if all went fine, else corresponding error. + */ +static int check_post_lbist_result(void) +{ + bool is_done, timed_out; + u32 post_reg_val, shift; + u32 calculated_misr, expected_misr; + + /* Read HW POST status register */ + post_reg_val = readl(WKUP_CTRL_MMR0_BASE + WKUP_CTRL_MMR_CFG0_WKUP_POST_STAT); + + /* Check if HW POST LBIST was performed */ + shift = WKUP_CTRL_MMR_CFG0_WKUP_POST_STAT_POST_MCU_LBIST_DONE_SHIFT; + is_done = (((post_reg_val >> shift) & 0x1u) == 0x1u) ? (bool)true : (bool)false; + + if (!is_done) { + /* HW POST: PBIST not completed, check if it timed out */ + shift = WKUP_CTRL_MMR_CFG0_WKUP_POST_STAT_POST_MCU_LBIST_TIMEOUT_SHIFT; + timed_out = (((post_reg_val >> shift) & 0x1u) == 0x1u) ? (bool)true : (bool)false; + + if (!timed_out) { + printf("%s: PBIST was not performed at all on this device for this core\n", + __func__); + return -EINVAL; + } + printf("%s: PBIST was attempted but timed out for this section\n", + __func__); + return -ETIMEDOUT; + + } else { + /* Get the output MISR and the expected MISR which 0 for MCU domain */ + lbist_get_misr((void *)MCU_LBIST_BASE, &calculated_misr); + expected_misr = readl(MCU_CTRL_MMR0_CFG0_BASE + MCU_CTRL_MMR_CFG0_MCU_LBIST_SIG); + + if (calculated_misr != expected_misr) { + /* HW POST: LBIST was completed, but the test failed for this core */ + printf("%s: calculated MISR != expected MISR\n", __func__); + debug("%s: calculated MISR = %x\n", __func__, calculated_misr); + debug("%s: expected MISR = %x\n", __func__, expected_misr); + return -EINVAL; + } + debug("%s: HW POST LBIST completed, test passed\n", __func__); + } + + return 0; +} + +/** + * pbist_self_test() - Run PBIST_TEST on specified cores + * @config: pbist_config structure for PBIST test + * + * Function to run PBIST_TEST + * + * Return: 0 if all went fine, else corresponding error. + */ +static int pbist_self_test(struct pbist_config *config) +{ + void *base = k3_bist_priv->pbist_base; + + /* Turns on PBIST clock in PBIST ACTivate register */ + writel(PBIST_PACT_PACT_MASK, base + PBIST_PACT); + + /* Set Margin mode register for Test mode */ + writel(PBIST_TEST_MODE, base + PBIST_MARGIN_MODE); + + /* Zero out Loop counter 0 */ + writel(0x0, base + PBIST_L0); + + /* Set algorithm bitmap */ + writel(config->algorithms_bit_map, base + PBIST_ALGO); + + /* Set Memory group bitmap */ + writel(config->memory_groups_bit_map, base + PBIST_RINFO); + + /* Zero out override register */ + writel(config->override, base + PBIST_OVER); + + /* Set Scramble value - 64 bit*/ + writel(config->scramble_value_lo, base + PBIST_SCR_LO); + writel(config->scramble_value_hi, base + PBIST_SCR_HI); + + /* Set DLR register for ROM based testing and Config Access */ + writel(PBIST_DLR_DLR0_ROM_MASK + | PBIST_DLR_DLR0_CAM_MASK, base + PBIST_DLR); + + /* Allow time for completion of test*/ + udelay(1000); + + if (readl(base + PBIST_FSRF)) { + printf("%s: test failed\n", __func__); + return -EINVAL; + } + + return 0; +} + +/** + * pbist_neg_self_test() - Run PBIST_negTEST on specified cores + * @config: pbist_config_neg structure for PBIST negative test + * + * Function to run PBIST failure insertion test + * + * Return: 0 if all went fine, else corresponding error. + */ +static int pbist_neg_self_test(struct pbist_config_neg *config) +{ + void *base = k3_bist_priv->pbist_base; + + /* Turns on PBIST clock in PBIST ACTivate register */ + writel(PBIST_PACT_PACT_MASK, base + PBIST_PACT); + + /* Set Margin mode register for Test mode */ + writel(PBIST_FAILURE_INSERTION_TEST_MODE, base + PBIST_MARGIN_MODE); + + /* Zero out Loop counter 0 */ + writel(0x0, base + PBIST_L0); + + /* Set DLR register */ + writel(0x10, base + PBIST_DLR); + + /* Set Registers*/ + writel(0x00000001, base + PBIST_RF0L); + writel(0x00003123, base + PBIST_RF0U); + writel(0x0513FC02, base + PBIST_RF1L); + writel(0x00000002, base + PBIST_RF1U); + writel(0x00000003, base + PBIST_RF2L); + writel(0x00000000, base + PBIST_RF2U); + writel(0x00000004, base + PBIST_RF3L); + writel(0x00000028, base + PBIST_RF3U); + writel(0x64000044, base + PBIST_RF4L); + writel(0x00000000, base + PBIST_RF4U); + writel(0x0006A006, base + PBIST_RF5L); + writel(0x00000000, base + PBIST_RF5U); + writel(0x00000007, base + PBIST_RF6L); + writel(0x0000A0A0, base + PBIST_RF6U); + writel(0x00000008, base + PBIST_RF7L); + writel(0x00000064, base + PBIST_RF7U); + writel(0x00000009, base + PBIST_RF8L); + writel(0x0000A5A5, base + PBIST_RF8U); + writel(0x0000000A, base + PBIST_RF9L); + writel(0x00000079, base + PBIST_RF9U); + writel(0x00000000, base + PBIST_RF10L); + writel(0x00000001, base + PBIST_RF10U); + writel(0xAAAAAAAA, base + PBIST_D); + writel(0xAAAAAAAA, base + PBIST_E); + + writel(config->CA2, base + PBIST_CA2); + writel(config->CL0, base + PBIST_CL0); + writel(config->CA3, base + PBIST_CA3); + writel(config->I0, base + PBIST_I0); + writel(config->CL1, base + PBIST_CL1); + writel(config->I3, base + PBIST_I3); + writel(config->I2, base + PBIST_I2); + writel(config->CL2, base + PBIST_CL2); + writel(config->CA1, base + PBIST_CA1); + writel(config->CA0, base + PBIST_CA0); + writel(config->CL3, base + PBIST_CL3); + writel(config->I1, base + PBIST_I1); + writel(config->RAMT, base + PBIST_RAMT); + writel(config->CSR, base + PBIST_CSR); + writel(config->CMS, base + PBIST_CMS); + + writel(0x00000009, base + PBIST_STR); + + /* Start PBIST */ + writel(0x00000001, base + PBIST_STR); + + /* Allow time for completion of test*/ + udelay(1000); + + if (readl(base + PBIST_FSRF) == 0) { + printf("%s: test failed\n", __func__); + return -EINVAL; + } + + return 0; +} + +/** + * pbist_rom_self_test() - Run PBIST_ROM_TEST on specified cores + * @config: pbist_config_rom structure for PBIST negative test + * + * Function to run PBIST test of ROM + * + * Return: 0 if all went fine, else corresponding error. + */ +static int pbist_rom_self_test(struct pbist_config_rom *config) +{ + void *base = k3_bist_priv->pbist_base; + + /* Turns on PBIST clock in PBIST ACTivate register */ + writel(0x1, base + PBIST_PACT); + + /* Set Margin mode register for Test mode */ + writel(0xf, base + PBIST_MARGIN_MODE); + + /* Zero out Loop counter 0 */ + writel(0x0, base + PBIST_L0); + + /* Set DLR register */ + writel(0x310, base + PBIST_DLR); + + /* Set Registers*/ + writel(0x00000001, base + PBIST_RF0L); + writel(0x00003123, base + PBIST_RF0U); + writel(0x7A400183, base + PBIST_RF1L); + writel(0x00000060, base + PBIST_RF1U); + writel(0x00000184, base + PBIST_RF2L); + writel(0x00000000, base + PBIST_RF2U); + writel(0x7B600181, base + PBIST_RF3L); + writel(0x00000061, base + PBIST_RF3U); + writel(0x00000000, base + PBIST_RF4L); + writel(0x00000000, base + PBIST_RF4U); + + writel(config->D, base + PBIST_D); + writel(config->E, base + PBIST_E); + writel(config->CA2, base + PBIST_CA2); + writel(config->CL0, base + PBIST_CL0); + writel(config->CA3, base + PBIST_CA3); + writel(config->I0, base + PBIST_I0); + writel(config->CL1, base + PBIST_CL1); + writel(config->I3, base + PBIST_I3); + writel(config->I2, base + PBIST_I2); + writel(config->CL2, base + PBIST_CL2); + writel(config->CA1, base + PBIST_CA1); + writel(config->CA0, base + PBIST_CA0); + writel(config->CL3, base + PBIST_CL3); + writel(config->I1, base + PBIST_I1); + writel(config->RAMT, base + PBIST_RAMT); + writel(config->CSR, base + PBIST_CSR); + writel(config->CMS, base + PBIST_CMS); + + writel(0x00000009, base + PBIST_STR); + + /* Start PBIST */ + writel(0x00000001, base + PBIST_STR); + + /* Allow time for completion of test*/ + udelay(1000); + + if (readl(base + PBIST_FSRF)) { + printf("%s: test failed\n", __func__); + return -EINVAL; + } + + return 0; +} + +/** + * lbist_program_config() - Program LBIST config + * @config: lbist_config structure for LBIST test + */ +static void lbist_program_config(struct lbist_config *config) +{ + void *base = k3_bist_priv->lbist_ctrl_mmr; + + lbist_set_clock_delay(base, config->dc_def); + lbist_set_divide_ratio(base, config->divide_ratio); + lbist_clear_load_div(base); + lbist_set_load_div(base); + lbist_set_num_stuck_at_patterns(base, config->static_pc_def); + lbist_set_num_set_patterns(base, config->set_pc_def); + lbist_set_num_reset_patterns(base, config->reset_pc_def); + lbist_set_num_chain_test_patterns(base, config->scan_pc_def); + lbist_set_seed(base, config->prpg_def_l, config->prpg_def_u); +} + +/** + * lbist_enable_isolation() - LBIST Enable Isolation + * @config: lbist_config structure for LBIST test + */ +void lbist_enable_isolation(void) +{ + void *base = k3_bist_priv->lbist_ctrl_mmr; + u32 reg_val; + + reg_val = readl(base + LBIST_SPARE0); + writel(reg_val | (LBIST_SPARE0_LBIST_SELFTEST_EN_MASK), base + LBIST_SPARE0); +} + +/** + * lbist_disable_isolation() - LBIST Disable Isolation + * @config: lbist_config structure for LBIST test + */ +void lbist_disable_isolation(void) +{ + void *base = k3_bist_priv->lbist_ctrl_mmr; + u32 reg_val; + + reg_val = readl(base + LBIST_SPARE0); + writel(reg_val & (~(LBIST_SPARE0_LBIST_SELFTEST_EN_MASK)), base + LBIST_SPARE0); +} + +/** + * lbist_enable_run_bist_mode() - LBIST Enable run BIST mode + * @config: lbist_config structure for LBIST test + */ +static void lbist_enable_run_bist_mode(struct lbist_config *config) +{ + void *base = k3_bist_priv->lbist_ctrl_mmr; + u32 reg_val; + + reg_val = readl(base + LBIST_CTRL); + writel(reg_val | (LBIST_CTRL_RUNBIST_MODE_MAX << LBIST_CTRL_RUNBIST_MODE_SHIFT), + base + LBIST_CTRL); +} + +/** + * lbist_start() - Start LBIST test + * @config: lbist_config structure for LBIST test + */ +static void lbist_start(struct lbist_config *config) +{ + struct udevice *dev = k3_bist_priv->dev; + void *base = k3_bist_priv->lbist_ctrl_mmr; + u32 reg_val; + u32 timeout_count = 0; + + reg_val = readl(base + LBIST_CTRL); + writel(reg_val | (LBIST_CTRL_BIST_RESET_MAX << LBIST_CTRL_BIST_RESET_SHIFT), + base + LBIST_CTRL); + + reg_val = readl(base + LBIST_CTRL); + writel(reg_val | (LBIST_CTRL_BIST_RUN_MAX << LBIST_CTRL_BIST_RUN_SHIFT), + base + LBIST_CTRL); + + reg_val = readl(base + LBIST_STAT); + if ((reg_val & LBIST_STAT_BIST_RUNNING_MASK) != 0) + debug("%s(dev=%p): LBIST is running\n", __func__, dev); + + while (((!(readl(base + LBIST_STAT) & LBIST_STAT_BIST_DONE_MASK))) && + (timeout_count++ < PBIST_MAX_TIMEOUT_VALUE)) { + } + + if (!(readl(base + LBIST_STAT) & LBIST_STAT_BIST_DONE_MASK)) + printf("%s(dev=%p): test failed\n", __func__, dev); +} + +/** + * lbist_check_result() - Check LBIST test result + * @config: lbist_config structure for LBIST test + * + * Return: 0 if all went fine, else corresponding error. + */ +static int lbist_check_result(struct lbist_config *config) +{ + void *base = k3_bist_priv->lbist_ctrl_mmr; + struct lbist_inst_info *info = k3_bist_priv->lbist_info; + u32 calculated_misr; + u32 expected_misr; + + lbist_get_misr(base, &calculated_misr); + expected_misr = info->expected_misr; + lbist_clear_run_bist_mode(base); + lbist_stop(base); + lbist_reset(base); + + if (calculated_misr != expected_misr) { + printf("calculated_misr != expected_misr\n %x %x\n", + calculated_misr, expected_misr); + return -EINVAL; + } + + return 0; +} + +static int k3_run_lbist(void) +{ + /* Check whether HW POST successfully completely LBIST on the MCU domain */ + struct lbist_inst_info *info_lbist = k3_bist_priv->lbist_info; + + lbist_program_config(&info_lbist->lbist_conf); + lbist_enable_isolation(); + lbist_reset(&info_lbist->lbist_conf); + lbist_enable_run_bist_mode(&info_lbist->lbist_conf); + lbist_start(&info_lbist->lbist_conf); + if (lbist_check_result(&info_lbist->lbist_conf)) { + printf("%s: test failed\n", __func__); + return -EINVAL; + } + + return 0; +} + +static int k3_run_lbist_post(void) +{ + if (check_post_lbist_result()) { + printf("HW POST LBIST failed to run successfully\n"); + return -EINVAL; + } + + return 0; +} + +static int k3_run_pbist_post(void) +{ + /* Check whether HW POST successfully completely PBIST on the MCU domain */ + if (check_post_pbist_result()) { + printf("HW POST failed to run successfully\n"); + return -EINVAL; + } + + return 0; +} + +static int k3_run_pbist(void) +{ + /* Run PBIST test */ + struct pbist_inst_info *info = k3_bist_priv->pbist_info; + int num_runs = info->num_pbist_runs; + + for (int j = 0; j < num_runs; j++) { + if (pbist_self_test(&info->pbist_config_run[j])) { + printf("failed to run PBIST test\n"); + return -EINVAL; + } + } + + return 0; +} + +static int k3_run_pbist_neg(void) +{ + /* Run PBIST failure insertion test */ + struct pbist_inst_info *info = k3_bist_priv->pbist_info; + + if (pbist_neg_self_test(&info->pbist_neg_config_run)) { + printf("failed to run PBIST negative test\n"); + return -EINVAL; + } + + return 0; +} + +static int k3_run_pbist_rom(void) +{ + /* Run PBIST test on ROM */ + struct pbist_inst_info *info = k3_bist_priv->pbist_info; + int num_runs = info->num_pbist_rom_test_runs; + + for (int j = 0; j < num_runs; j++) { + if (pbist_rom_self_test(&info->pbist_rom_test_config_run[j])) { + printf("failed to run ROM PBIST test\n"); + return -EINVAL; + } + } + + return 0; +} + +int prepare_pbist(struct ti_sci_handle *handle) +{ + struct ti_sci_proc_ops *proc_ops = &handle->ops.proc_ops; + struct ti_sci_dev_ops *dev_ops = &handle->ops.dev_ops; + struct pbist_inst_info *info_pbist = k3_bist_priv->pbist_info; + struct core_under_test *cut = info_pbist->cut; + + if (proc_ops->proc_request(handle, cut[0].proc_id)) { + printf("%s: requesting primary core failed\n", __func__); + return -EINVAL; + } + + if (proc_ops->proc_request(handle, cut[1].proc_id)) { + printf("%s: requesting secondary core failed\n", __func__); + return -EINVAL; + } + + if (dev_ops->set_device_resets(handle, cut[0].dev_id, 0x1)) { + printf("%s: local reset primary core failed\n", __func__); + return -EINVAL; + } + + if (dev_ops->set_device_resets(handle, cut[1].dev_id, 0x1)) { + printf("%s: local reset secondary core failed\n", __func__); + return -EINVAL; + } + + if (dev_ops->get_device(handle, cut[0].dev_id)) { + printf("%s: power on primary core failed\n", __func__); + return -EINVAL; + } + + if (dev_ops->get_device(handle, cut[1].dev_id)) { + printf("%s: power on secondary core failed\n", __func__); + return -EINVAL; + } + + if (dev_ops->get_device(handle, info_pbist->dev_id)) { + printf("%s: power on PBIST failed\n", __func__); + return -EINVAL; + } + + return 0; +} + +int deprepare_pbist(struct ti_sci_handle *handle) +{ + struct ti_sci_proc_ops *proc_ops = &handle->ops.proc_ops; + struct ti_sci_dev_ops *dev_ops = &handle->ops.dev_ops; + struct pbist_inst_info *info_pbist = k3_bist_priv->pbist_info; + struct core_under_test *cut = info_pbist->cut; + + if (dev_ops->put_device(handle, info_pbist->dev_id)) { + printf("%s: power off PBIST failed\n", __func__); + return -EINVAL; + } + + if (dev_ops->put_device(handle, cut[1].dev_id)) { + printf("%s: power off secondary core failed\n", __func__); + return -EINVAL; + } + + if (dev_ops->put_device(handle, cut[0].dev_id)) { + printf("%s: power off primary core failed\n", __func__); + return -EINVAL; + } + + if (dev_ops->set_device_resets(handle, cut[0].dev_id, 0)) { + printf("%s: putting primary core out of local reset failed\n", __func__); + return -EINVAL; + } + + if (dev_ops->set_device_resets(handle, cut[1].dev_id, 0)) { + printf("%s: putting secondary core out of local reset failed\n", __func__); + return -EINVAL; + } + + if (dev_ops->put_device(handle, cut[0].dev_id)) { + printf("%s: power off primary core failed\n", __func__); + return -EINVAL; + } + + if (dev_ops->put_device(handle, cut[1].dev_id)) { + printf("%s: power off secondary core failed\n", __func__); + return -EINVAL; + } + + if (proc_ops->proc_release(handle, cut[0].proc_id)) { + printf("%s: release primary core failed\n", __func__); + return -EINVAL; + } + + if (proc_ops->proc_release(handle, cut[1].proc_id)) { + printf("%s: release secondary core failed\n", __func__); + return -EINVAL; + } + + return 0; +} + +int prepare_lbist(struct ti_sci_handle *handle) +{ + struct ti_sci_proc_ops *proc_ops = &handle->ops.proc_ops; + struct ti_sci_dev_ops *dev_ops = &handle->ops.dev_ops; + struct lbist_inst_info *info_lbist = k3_bist_priv->lbist_info; + struct core_under_test *cut = &info_lbist->cut; + + if (proc_ops->proc_request(handle, cut->proc_id)) { + printf("%s: requesting primary core failed\n", __func__); + return -EINVAL; + } + + if (dev_ops->set_device_resets(handle, cut->dev_id, 0x3)) { + printf("%s: module and local reset primary core failed\n", __func__); + return -EINVAL; + } + + if (dev_ops->idle_device(handle, cut->dev_id)) { + printf("%s: putting primary core into retention failed\n", __func__); + return -EINVAL; + } + + return 0; +} + +int deprepare_lbist(struct ti_sci_handle *handle) +{ + struct ti_sci_proc_ops *proc_ops = &handle->ops.proc_ops; + struct ti_sci_dev_ops *dev_ops = &handle->ops.dev_ops; + struct lbist_inst_info *info_lbist = k3_bist_priv->lbist_info; + struct core_under_test *cut = &info_lbist->cut; + + if (dev_ops->put_device(handle, 0)) { + printf("%s: power off secondary core failed\n", __func__); + return -EINVAL; + } + + if (dev_ops->put_device(handle, cut->dev_id)) { + printf("%s: power off primary core failed\n", __func__); + return -EINVAL; + } + + lbist_disable_isolation(); + + if (dev_ops->idle_device(handle, cut->dev_id)) { + printf("%s: retention primary core failed\n", __func__); + return -EINVAL; + } + + if (dev_ops->idle_device(handle, 0)) { + printf("%s: retention secondary core failed\n", __func__); + return -EINVAL; + } + + if (dev_ops->put_device(handle, 0)) { + printf("%s: power off secondary core failed\n", __func__); + return -EINVAL; + } + + if (dev_ops->put_device(handle, cut->dev_id)) { + printf("%s: power off primary core failed\n", __func__); + return -EINVAL; + } + + if (dev_ops->set_device_resets(handle, cut->dev_id, 0)) { + printf("%s: putting primary core out of local reset failed\n", __func__); + return -EINVAL; + } + + if (proc_ops->proc_release(handle, cut->proc_id)) { + printf("%s: release primary core failed\n", __func__); + return -EINVAL; + } + + return 0; +} + +/** + * k3_bist_probe() - Basic probe + * @dev: corresponding BIST device + * + * Parses BIST info from device tree, and configures the module accordingly. + * Return: 0 if all goes good, else appropriate error message. + */ +static int k3_bist_probe(struct udevice *dev) +{ + int ret = 0; + struct k3_bist_privdata *priv = dev_get_priv(dev); + struct pbist_inst_info *info; + struct lbist_inst_info *info_lbist; + void *reg; + + debug("%s(dev=%p)\n", __func__, dev); + + priv = dev_get_priv(dev); + priv->dev = dev; + + k3_bist_priv = priv; + + reg = dev_read_addr_name_ptr(dev, "cfg"); + if (!reg) { + dev_err(dev, "No reg property for BIST\n"); + return -EINVAL; + } + priv->pbist_base = reg; + + reg = dev_read_addr_name_ptr(dev, "ctrl_mmr"); + if (!reg) { + dev_err(dev, "No reg property for CTRL MMR\n"); + return -EINVAL; + } + priv->lbist_ctrl_mmr = reg; + + ret = dev_read_u32(dev, "ti,sci-dev-id", &priv->instance); + if (!priv->instance) + return -ENODEV; + + switch (priv->instance) { + case PBIST14_DEV_ID: + priv->pbist_info = &pbist14_inst_info; + priv->lbist_info = &lbist_inst_info_main_r5f2_x; + info = priv->pbist_info; + info_lbist = priv->lbist_info; + priv->intr_num = info->intr_num; + break; + default: + dev_err(dev, "%s: PBIST instance %d not supported\n", __func__, priv->instance); + return -ENODEV; + }; + + return 0; +} + +static const struct bist_ops k3_bist_ops = { + .run_lbist = k3_run_lbist, + .run_lbist_post = k3_run_lbist_post, + .run_pbist = k3_run_pbist, + .run_pbist_post = k3_run_pbist_post, + .run_pbist_neg = k3_run_pbist_neg, + .run_pbist_rom = k3_run_pbist_rom, +}; + +static const struct udevice_id k3_bist_ids[] = { + { .compatible = "ti,j784s4-bist" }, + {} +}; + +U_BOOT_DRIVER(k3_bist) = { + .name = "k3_bist", + .of_match = k3_bist_ids, + .id = UCLASS_MISC, + .ops = &k3_bist_ops, + .probe = k3_bist_probe, + .priv_auto = sizeof(struct k3_bist_privdata), +}; diff --git a/drivers/misc/k3_bist_static_data.h b/drivers/misc/k3_bist_static_data.h new file mode 100644 index 00000000000..af371d83724 --- /dev/null +++ b/drivers/misc/k3_bist_static_data.h @@ -0,0 +1,673 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Static Data for Texas Instruments' BIST (Built-In Self-Test) driver + * + * Copyright (C) 2025 Texas Instruments Incorporated - https://www.ti.com/ + * + */ + +#ifndef __K3_BIST_STATIC_DATA_H +#define __K3_BIST_STATIC_DATA_H + +/* + * Registers and functions related to PBIST + */ + +#define PBIST_MAX_NUM_RUNS 2 +#define NUM_MAX_PBIST_TEST_ROM_RUNS 13 +#define PBIST14_DFT_PBIST_CPU_0_INTR_NUM 311 + +/* VIM Registers */ +#define VIM_STS_BASE 0x40f80404 +#define VIM_RAW_BASE 0x40f80400 + +#define VIM_STS(i) (VIM_STS_BASE + (i) / 32 * 0x20) +#define VIM_RAW(i) (VIM_RAW_BASE + (i) / 32 * 0x20) +#define VIM_RAW_MASK(i) (BIT((i) % 32)) + +/* PBIST Registers and Flags*/ +#define PBIST_RF0L 0x00000000 +#define PBIST_RF1L 0x00000004 +#define PBIST_RF2L 0x00000008 +#define PBIST_RF3L 0x0000000C +#define PBIST_RF4L 0x0000010 +#define PBIST_RF5L 0x0000014 +#define PBIST_RF6L 0x0000018 +#define PBIST_RF7L 0x000001C +#define PBIST_RF8L 0x0000020 +#define PBIST_RF9L 0x0000024 +#define PBIST_RF10L 0x0000028 +#define PBIST_RF11L 0x000002C +#define PBIST_RF12L 0x0000030 +#define PBIST_RF13L 0x0000034 +#define PBIST_RF14L 0x0000038 +#define PBIST_RF15L 0x000003C +#define PBIST_RF0U 0x0000040 +#define PBIST_RF1U 0x0000044 +#define PBIST_RF2U 0x0000048 +#define PBIST_RF3U 0x000004C +#define PBIST_RF4U 0x0000050 +#define PBIST_RF5U 0x0000054 +#define PBIST_RF6U 0x0000058 +#define PBIST_RF7U 0x000005C +#define PBIST_RF8U 0x0000060 +#define PBIST_RF9U 0x0000064 +#define PBIST_RF10U 0x0000068 +#define PBIST_RF11U 0x000006C +#define PBIST_RF12U 0x0000070 +#define PBIST_RF13U 0x0000074 +#define PBIST_RF14U 0x0000078 +#define PBIST_RF15U 0x000007C +#define PBIST_A0 0x0000100 +#define PBIST_A1 0x0000104 +#define PBIST_A2 0x0000108 +#define PBIST_A3 0x000010C +#define PBIST_L0 0x0000110 +#define PBIST_L1 0x0000114 +#define PBIST_L2 0x0000118 +#define PBIST_L3 0x000011C +#define PBIST_D 0x0000120 +#define PBIST_E 0x0000124 +#define PBIST_CA0 0x0000130 +#define PBIST_CA1 0x0000134 +#define PBIST_CA2 0x0000138 +#define PBIST_CA3 0x000013C +#define PBIST_CL0 0x0000140 +#define PBIST_CL1 0x0000144 +#define PBIST_CL2 0x0000148 +#define PBIST_CL3 0x000014C +#define PBIST_I0 0x0000150 +#define PBIST_I1 0x0000154 +#define PBIST_I2 0x0000158 +#define PBIST_I3 0x000015C +#define PBIST_RAMT 0x0000160 +#define PBIST_DLR 0x0000164 +#define PBIST_CMS 0x0000168 +#define PBIST_STR 0x000016C +#define PBIST_SCR 0x0000170 +#define PBIST_SCR_LO 0x0000170 +#define PBIST_SCR_HI 0x0000174 +#define PBIST_CSR 0x0000178 +#define PBIST_FDLY 0x000017C +#define PBIST_PACT 0x0000180 +#define PBIST_PID 0x0000184 +#define PBIST_OVER 0x0000188 +#define PBIST_FSRF 0x0000190 +#define PBIST_FSRC 0x0000198 +#define PBIST_FSRA 0x00001A0 +#define PBIST_FSRDL0 0x00001A8 +#define PBIST_FSRDL1 0x00001B0 +#define PBIST_MARGIN_MODE 0x00001B4 +#define PBIST_WRENZ 0x00001B8 +#define PBIST_PAGE_PGS 0x00001BC +#define PBIST_ROM 0x00001C0 +#define PBIST_ALGO 0x00001C4 +#define PBIST_RINFO 0x00001C8 + +#define PBIST_MARGIN_MODE_PBIST_DFT_WRITE_MASK 0x00000003 +#define PBIST_MARGIN_MODE_PBIST_DFT_READ_SHIFT 0x00000002 +#define PBIST_MARGIN_MODE_PBIST_DFT_READ_MASK 0x0000000C +#define PBIST_PACT_PACT_MASK 0x00000001 +#define PBIST_DLR_DLR0_ROM_MASK 0x00000004 +#define PBIST_DLR_DLR0_CAM_MASK 0x00000010 +#define PBIST_NOT_DONE 0 +#define PBIST_DONE 1 + +/* PBIST test mode */ +#define PBIST_TEST_MODE (PBIST_MARGIN_MODE_PBIST_DFT_WRITE_MASK \ + | (1 << PBIST_MARGIN_MODE_PBIST_DFT_READ_SHIFT)) + +/* PBIST Failure Insertion test mode */ +#define PBIST_FAILURE_INSERTION_TEST_MODE (PBIST_MARGIN_MODE_PBIST_DFT_WRITE_MASK \ + | PBIST_MARGIN_MODE_PBIST_DFT_READ_MASK) + +/** + * struct core_under_test - structure for a core under a BIST test + * @dev_id: Device ID of the core + * @proc_id: Processor ID of the core + */ +struct core_under_test { + u32 dev_id; + u32 proc_id; +}; + +/* + * struct pbist_config - Structure for different configuration used for PBIST + * @override: Override value for memory configuration + * @algorithms_bit_map: Bitmap to select algorithms to use for test + * @memory_groups_bit_map: Bitmap to select memory groups to run test on + * @scramble_value_lo: Lower scramble value to be used for test + * @scramble_value_hi: Higher scramble value to be used for test + */ +struct pbist_config { + u32 override; + u32 algorithms_bit_map; + u64 memory_groups_bit_map; + u32 scramble_value_lo; + u32 scramble_value_hi; +}; + +/* + * struct pbist_config_neg - Structure for different configuration used for PBIST + * for the failure insertion test to generate negative result + * @CA0: Failure insertion value for CA0 + * @CA1: Failure insertion value for CA1 + * @CA2: Failure insertion value for CA2 + * @CA3: Failure insertion value for CA3 + * @CL0: Failure insertion value for CL0 + * @CL1: Failure insertion value for CL1 + * @CL2: Failure insertion value for CL2 + * @CL3: Failure insertion value for CL3 + * @CMS: Failure insertion value for CMS + * @CSR: Failure insertion value for CSR + * @I0: Failure insertion value for I0 + * @I1: Failure insertion value for I1 + * @I2: Failure insertion value for I2 + * @I3: Failure insertion value for I3 + * @RAMT: Failure insertion value for RAMT + */ +struct pbist_config_neg { + u32 CA0; + u32 CA1; + u32 CA2; + u32 CA3; + u32 CL0; + u32 CL1; + u32 CL2; + u32 CL3; + u32 CMS; + u32 CSR; + u32 I0; + u32 I1; + u32 I2; + u32 I3; + u32 RAMT; +}; + +/* + * struct pbist_config_neg - Structure for different configuration used for PBIST + * test of ROM + * @D: ROM test value for D + * @E: ROM test value for E + * @CA2: ROM test value for CA2 + * @CL0: ROM test value for CL0 + * @CA3: ROM test value for CA3 + * @I0: ROM test value for I0 + * @CL1: ROM test value for CL1 + * @I3: ROM test value for I3 + * @I2: ROM test value for I2 + * @CL2: ROM test value for CL2 + * @CA1: ROM test value for CA1 + * @CA0: ROM test value for CA0 + * @CL3: ROM test value for CL3 + * @I1: ROM test value for I1 + * @RAMT: ROM test value for RAMT + * @CSR: ROM test value for CSR + * @CMS: ROM test value for CMS + */ +struct pbist_config_rom { + u32 D; + u32 E; + u32 CA2; + u32 CL0; + u32 CA3; + u32 I0; + u32 CL1; + u32 I3; + u32 I2; + u32 CL2; + u32 CA1; + u32 CA0; + u32 CL3; + u32 I1; + u32 RAMT; + u32 CSR; + u32 CMS; +}; + +/* + * struct pbist_inst_info - Structure for different configuration used for PBIST + * @num_pbist_runs: Number of runs of PBIST test + * @intr_num: Interrupt number triggered by this PBIST instance to MCU R5 VIM + * @pbist_config_run: Configuration for PBIST test + * @pbist_neg_config_run: Configuration for PBIST negative test + * @num_pbist_rom_test_runs: Number of runs of PBIST test on ROM + * @pbist_rom_test_config_run: Configuration for PBIST test on ROM + */ +struct pbist_inst_info { + u32 num_pbist_runs; + u32 intr_num; + u32 dev_id; + struct core_under_test cut[2]; + struct pbist_config pbist_config_run[PBIST_MAX_NUM_RUNS]; + struct pbist_config_neg pbist_neg_config_run; + u32 num_pbist_rom_test_runs; + struct pbist_config_rom pbist_rom_test_config_run[NUM_MAX_PBIST_TEST_ROM_RUNS]; +}; + +/* + * Registers and functions related to LBIST + */ + +#define LBIST_CTRL_DIVIDE_RATIO_MASK 0x0000001F +#define LBIST_CTRL_DIVIDE_RATIO_SHIFT 0x00000000 +#define LBIST_CTRL_DIVIDE_RATIO_MAX 0x0000001F + +#define LBIST_CTRL_LOAD_DIV_MASK 0x00000080 +#define LBIST_CTRL_LOAD_DIV_SHIFT 0x00000007 +#define LBIST_CTRL_LOAD_DIV_MAX 0x00000001 + +#define LBIST_CTRL_DC_DEF_MASK 0x00000300 +#define LBIST_CTRL_DC_DEF_SHIFT 0x00000008 +#define LBIST_CTRL_DC_DEF_MAX 0x00000003 + +#define LBIST_CTRL_RUNBIST_MODE_MASK 0x0000F000 +#define LBIST_CTRL_RUNBIST_MODE_SHIFT 0x0000000C +#define LBIST_CTRL_RUNBIST_MODE_MAX 0x0000000F + +#define LBIST_CTRL_BIST_RUN_MASK 0x0F000000 +#define LBIST_CTRL_BIST_RUN_SHIFT 0x00000018 +#define LBIST_CTRL_BIST_RUN_MAX 0x0000000F + +#define LBIST_CTRL_BIST_RESET_MASK 0x80000000 +#define LBIST_CTRL_BIST_RESET_SHIFT 0x0000001F +#define LBIST_CTRL_BIST_RESET_MAX 0x00000001 + +/* LBIST_PATCOUNT */ + +#define LBIST_PATCOUNT_SCAN_PC_DEF_MASK 0x0000000F +#define LBIST_PATCOUNT_SCAN_PC_DEF_SHIFT 0x00000000 +#define LBIST_PATCOUNT_SCAN_PC_DEF_MAX 0x0000000F + +#define LBIST_PATCOUNT_RESET_PC_DEF_MASK 0x000000F0 +#define LBIST_PATCOUNT_RESET_PC_DEF_SHIFT 0x00000004 +#define LBIST_PATCOUNT_RESET_PC_DEF_MAX 0x0000000F + +#define LBIST_PATCOUNT_SET_PC_DEF_MASK 0x00000F00 +#define LBIST_PATCOUNT_SET_PC_DEF_SHIFT 0x00000008 +#define LBIST_PATCOUNT_SET_PC_DEF_MAX 0x0000000F + +#define LBIST_PATCOUNT_STATIC_PC_DEF_MASK 0x3FFF0000 +#define LBIST_PATCOUNT_STATIC_PC_DEF_SHIFT 0x00000010 +#define LBIST_PATCOUNT_STATIC_PC_DEF_MAX 0x00003FFF + +/* LBIST_SEED0 */ + +#define LBIST_SEED0_PRPG_DEF_MASK 0xFFFFFFFF +#define LBIST_SEED0_PRPG_DEF_SHIFT 0x00000000 +#define LBIST_SEED0_PRPG_DEF_MAX 0xFFFFFFFF + +/* LBIST_SEED1 */ + +#define LBIST_SEED1_PRPG_DEF_MASK 0x001FFFFF +#define LBIST_SEED1_PRPG_DEF_SHIFT 0x00000000 +#define LBIST_SEED1_PRPG_DEF_MAX 0x001FFFFF + +/* LBIST_SPARE0 */ + +#define LBIST_SPARE0_LBIST_SELFTEST_EN_MASK 0x00000001 +#define LBIST_SPARE0_LBIST_SELFTEST_EN_SHIFT 0x00000000 +#define LBIST_SPARE0_LBIST_SELFTEST_EN_MAX 0x00000001 + +#define LBIST_SPARE0_PBIST_SELFTEST_EN_MASK 0x00000002 +#define LBIST_SPARE0_PBIST_SELFTEST_EN_SHIFT 0x00000001 +#define LBIST_SPARE0_PBIST_SELFTEST_EN_MAX 0x00000001 + +#define LBIST_SPARE0_SPARE0_MASK 0xFFFFFFFC +#define LBIST_SPARE0_SPARE0_SHIFT 0x00000002 +#define LBIST_SPARE0_SPARE0_MAX 0x3FFFFFFF + +/* LBIST_SPARE1 */ + +#define LBIST_SPARE1_SPARE1_MASK 0xFFFFFFFF +#define LBIST_SPARE1_SPARE1_SHIFT 0x00000000 +#define LBIST_SPARE1_SPARE1_MAX 0xFFFFFFFF + +/* LBIST_STAT */ + +#define LBIST_STAT_MISR_MUX_CTL_MASK 0x000000FF +#define LBIST_STAT_MISR_MUX_CTL_SHIFT 0x00000000 +#define LBIST_STAT_MISR_MUX_CTL_MAX 0x000000FF + +#define LBIST_STAT_OUT_MUX_CTL_MASK 0x00000300 +#define LBIST_STAT_OUT_MUX_CTL_SHIFT 0x00000008 +#define LBIST_STAT_OUT_MUX_CTL_MAX 0x00000003 + +#define LBIST_STAT_BIST_RUNNING_MASK 0x00008000 +#define LBIST_STAT_BIST_RUNNING_SHIFT 0x0000000F +#define LBIST_STAT_BIST_RUNNING_MAX 0x00000001 + +#define LBIST_STAT_BIST_DONE_MASK 0x80000000 +#define LBIST_STAT_BIST_DONE_SHIFT 0x0000001F +#define LBIST_STAT_BIST_DONE_MAX 0x00000001 + +/* LBIST_MISR */ + +#define LBIST_MISR_MISR_RESULT_MASK 0xFFFFFFFF +#define LBIST_MISR_MISR_RESULT_SHIFT 0x00000000 +#define LBIST_MISR_MISR_RESULT_MAX 0xFFFFFFFF + +#define CTRL_MMR0_CFG0_BASE 0x00100000 +#define MAIN_CTRL_MMR_CFG0_MCU2_LBIST_CTRL 0x0000C1A0 +#define MAIN_R5F2_LBIST_BASE (CTRL_MMR0_CFG0_BASE +\ + MAIN_CTRL_MMR_CFG0_MCU2_LBIST_CTRL) + +#define LBIST_CTRL 0x00000000 +#define LBIST_PATCOUNT 0x00000004 +#define LBIST_SEED0 0x00000008 +#define LBIST_SEED1 0x0000000C +#define LBIST_SPARE0 0x00000010 +#define LBIST_SPARE1 0x00000014 +#define LBIST_STAT 0x00000018 +#define LBIST_MISR 0x0000001C + +#define MAIN_CTRL_MMR_CFG0_MCU2_LBIST_SIG 0x0000C2C0 +#define MAIN_R5F2_LBIST_SIG (CTRL_MMR0_CFG0_BASE +\ + MAIN_CTRL_MMR_CFG0_MCU2_LBIST_SIG) +#define MCU_R5FSS0_CORE0_INTR_LBIST_BIST_DONE_0 284 + +/* Lbist Parameters */ +#define LBIST_DC_DEF 0x3 +#define LBIST_DIVIDE_RATIO 0x02 +#define LBIST_STATIC_PC_DEF 0x3ac0 +#define LBIST_RESET_PC_DEF 0x0f +#define LBIST_SET_PC_DEF 0x00 +#define LBIST_SCAN_PC_DEF 0x04 +#define LBIST_PRPG_DEF_L 0xFFFFFFFF +#define LBIST_PRPG_DEF_U 0x1FFFFF + +/* + * LBIST setup parameters for each core + */ + +#define LBIST_MAIN_R5_STATIC_PC_DEF LBIST_STATIC_PC_DEF +#define LBIST_C7X_STATIC_PC_DEF 0x3fc0 +#define LBIST_A72_STATIC_PC_DEF 0x3fc0 +#define LBIST_DMPAC_STATIC_PC_DEF 0x1880 +#define LBIST_VPAC_STATIC_PC_DEF 0x3fc0 +#define LBIST_A72SS_STATIC_PC_DEF 0x13c0 + +/* + * LBIST expected MISR's (using parameters above) + */ + +#define MAIN_R5_MISR_EXP_VAL 0x71d66f87 +#define A72_MISR_EXP_VAL 0x14df0200 +#define C7X_MISR_EXP_VAL 0x57b0478f +#define VPAC_MISR_EXP_VAL 0xec6abe22 +#define VPAC0_MISR_EXP_VAL 0x5c43b468 +#define DMPAC_MISR_EXP_VAL 0x53e1ef7b +#define A72SS_MISR_EXP_VAL 0x87da5a92 + +/** + * lbist_set_clock_delay() - Set seed for LBIST + * @ctrl_mmr_base: CTRL MMR base + * @clock_delay: clock delay + * + * Return: 0 if all went fine, else corresponding error. + */ +static void lbist_set_clock_delay(void *ctrl_mmr_base, u32 clock_delay) +{ + u32 reg_val; + + reg_val = readl(ctrl_mmr_base); + writel(reg_val & LBIST_CTRL_DC_DEF_MASK, ctrl_mmr_base); + + reg_val = readl(ctrl_mmr_base); + writel(reg_val | ((clock_delay & LBIST_CTRL_DC_DEF_MAX) + << LBIST_CTRL_DC_DEF_SHIFT), ctrl_mmr_base); +} + +/** + * lbist_set_seed() - Set seed for LBIST + * @config: lbist_config structure for LBIST test + * @seed: seed + * + * Return: 0 if all went fine, else corresponding error. + */ +static void lbist_set_seed(void *ctrl_mmr_base, u32 seed_l, u32 seed_u) +{ + writel(seed_l & LBIST_SEED0_PRPG_DEF_MASK, ctrl_mmr_base + LBIST_SEED0); + writel(seed_u & LBIST_SEED1_PRPG_DEF_MASK, ctrl_mmr_base + LBIST_SEED1); +} + +/** + * set_num_chain_test_patterns() - Set chain test patterns + * @ctrl_mmr_base: CTRL MMR base + * @chain_test_patterns: chain test patterns + * + * Return: 0 if all went fine, else corresponding error. + */ +static void lbist_set_num_chain_test_patterns(void *ctrl_mmr_base, u32 chain_test_patterns) +{ + u32 reg_val; + + reg_val = readl(ctrl_mmr_base + LBIST_PATCOUNT); + writel(reg_val & (~(LBIST_PATCOUNT_SCAN_PC_DEF_MASK)), + ctrl_mmr_base + LBIST_PATCOUNT); + + reg_val = readl(ctrl_mmr_base + LBIST_PATCOUNT); + writel(reg_val | ((chain_test_patterns & LBIST_PATCOUNT_SCAN_PC_DEF_MAX) + << LBIST_PATCOUNT_SCAN_PC_DEF_SHIFT), ctrl_mmr_base + LBIST_PATCOUNT); +} + +/** + * set_num_reset_patterns() - Set reset patterns + * @ctrl_mmr_base: CTRL MMR base + * @reset_patterns: reset patterns + * + * Return: 0 if all went fine, else corresponding error. + */ +static void lbist_set_num_reset_patterns(void *ctrl_mmr_base, u32 reset_patterns) +{ + u32 reg_val; + + reg_val = readl(ctrl_mmr_base + LBIST_PATCOUNT); + writel(reg_val & (~(LBIST_PATCOUNT_RESET_PC_DEF_MASK)), + ctrl_mmr_base + LBIST_PATCOUNT); + + reg_val = readl(ctrl_mmr_base + LBIST_PATCOUNT); + writel(reg_val | ((reset_patterns & LBIST_PATCOUNT_RESET_PC_DEF_MAX) + << LBIST_PATCOUNT_RESET_PC_DEF_SHIFT), ctrl_mmr_base + LBIST_PATCOUNT); +} + +/** + * set_num_set_patterns() - Set patterns + * @ctrl_mmr_base: CTRL MMR base + * @set_patterns: set patterns + * + * Return: 0 if all went fine, else corresponding error. + */ +static void lbist_set_num_set_patterns(void *ctrl_mmr_base, u32 set_patterns) +{ + u32 reg_val; + + reg_val = readl(ctrl_mmr_base + LBIST_PATCOUNT); + writel(reg_val & (~(LBIST_PATCOUNT_SET_PC_DEF_MASK)), + ctrl_mmr_base + LBIST_PATCOUNT); + + reg_val = readl(ctrl_mmr_base + LBIST_PATCOUNT); + writel(reg_val | ((set_patterns & LBIST_PATCOUNT_RESET_PC_DEF_MAX) + << LBIST_PATCOUNT_SET_PC_DEF_SHIFT), ctrl_mmr_base + LBIST_PATCOUNT); +} + +/** + * set_num_stuck_at_patterns() - Set + * @ctrl_mmr_base: CTRL MMR base + * @stuck_at_patterns: set patterns + * + * Return: 0 if all went fine, else corresponding error. + */ +static void lbist_set_num_stuck_at_patterns(void *ctrl_mmr_base, u32 stuck_at_patterns) +{ + u32 reg_val; + + reg_val = readl(ctrl_mmr_base + LBIST_PATCOUNT); + writel(reg_val & (~(LBIST_PATCOUNT_STATIC_PC_DEF_MASK)), + ctrl_mmr_base + LBIST_PATCOUNT); + + reg_val = readl(ctrl_mmr_base + LBIST_PATCOUNT); + writel(reg_val | ((stuck_at_patterns & LBIST_PATCOUNT_STATIC_PC_DEF_MAX) + << LBIST_PATCOUNT_STATIC_PC_DEF_SHIFT), ctrl_mmr_base + LBIST_PATCOUNT); +} + +/** + * set_divide_ratio() - Set divide ratio + * @ctrl_mmr_base: CTRL MMR base + * @divide_ratio: divide ratio + * + * Return: 0 if all went fine, else corresponding error. + */ +static void lbist_set_divide_ratio(void *ctrl_mmr_base, u32 divide_ratio) +{ + u32 reg_val; + + reg_val = readl(ctrl_mmr_base + LBIST_CTRL); + writel(reg_val & (~(LBIST_CTRL_DIVIDE_RATIO_MASK)), ctrl_mmr_base + LBIST_CTRL); + + reg_val = readl(ctrl_mmr_base + LBIST_CTRL); + writel(reg_val | (divide_ratio & LBIST_CTRL_DIVIDE_RATIO_MASK), + ctrl_mmr_base + LBIST_CTRL); +} + +/** + * clear_load_div() - Clear load div + * @ctrl_mmr_base: CTRL MMR base + * + * Return: 0 if all went fine, else corresponding error. + */ +static void lbist_clear_load_div(void *ctrl_mmr_base) +{ + u32 reg_val; + + reg_val = readl(ctrl_mmr_base + LBIST_CTRL); + writel(reg_val & (~(LBIST_CTRL_LOAD_DIV_MASK)), ctrl_mmr_base + LBIST_CTRL); +} + +/** + * set_load_div() - Set load div + * @ctrl_mmr_base: CTRL MMR base + * + * Return: 0 if all went fine, else corresponding error. + */ +static void lbist_set_load_div(void *ctrl_mmr_base) +{ + u32 reg_val; + + reg_val = readl(ctrl_mmr_base + LBIST_CTRL); + writel(reg_val | (LBIST_CTRL_LOAD_DIV_MASK), ctrl_mmr_base + LBIST_CTRL); +} + +/* MACRO DEFINES */ +#define LBIST_STAT_MISR_MUX_CTL_COMPACT_MISR 0x0 + +#define LBIST_STAT_OUT_MUX_CTL_CTRLMMR_PID 0x0 +#define LBIST_STAT_OUT_MUX_CTL_CTRL_ID 0x1 +#define LBIST_STAT_OUT_MUX_CTL_MISR_VALUE_1 0x2 +#define LBIST_STAT_OUT_MUX_CTL_MISR_VALUE_2 0x3 + +/** + * lbist_get_misr() - Get MISR + * @ctrl_mmr_base: CTRL MMR base + * + * Return: 0 if all went fine, else corresponding error. + */ +static void lbist_get_misr(void *ctrl_mmr_base, u32 *p_misr_val) +{ + u32 reg_val; + u32 mux_val; + + reg_val = LBIST_STAT_MISR_MUX_CTL_COMPACT_MISR; + mux_val = LBIST_STAT_OUT_MUX_CTL_MISR_VALUE_1; + reg_val |= (mux_val << LBIST_STAT_OUT_MUX_CTL_SHIFT); + writel(reg_val, ctrl_mmr_base + LBIST_STAT); + *p_misr_val = readl(ctrl_mmr_base + LBIST_MISR); +} + +/** + * lbist_clear_run_bist_mode() - Clear RUN_BIST_MODE + * @ctrl_mmr_base: CTRL MMR base + * + * Return: 0 if all went fine, else corresponding error. + */ +static void lbist_clear_run_bist_mode(void *ctrl_mmr_base) +{ + u32 reg_val; + + reg_val = readl(ctrl_mmr_base + LBIST_CTRL); + writel(reg_val & (~(LBIST_CTRL_RUNBIST_MODE_MAX << LBIST_CTRL_RUNBIST_MODE_SHIFT)), + ctrl_mmr_base + LBIST_CTRL); +} + +/** + * lbist_stop() - Stop running LBIST + * @ctrl_mmr_base: CTRL MMR base + * + * Return: 0 if all went fine, else corresponding error. + */ +static void lbist_stop(void *ctrl_mmr_base) +{ + u32 reg_val; + + reg_val = readl(ctrl_mmr_base + LBIST_CTRL); + writel(reg_val & (~(LBIST_CTRL_BIST_RUN_MAX << LBIST_CTRL_BIST_RUN_SHIFT)), + ctrl_mmr_base + LBIST_CTRL); +} + +/** + * lbist_reset() - Reset LBIST + * @ctrl_mmr_base: CTRL MMR base + * + * Return: 0 if all went fine, else corresponding error. + */ +static void lbist_reset(void *ctrl_mmr_base) +{ + u32 reg_val; + + reg_val = readl(ctrl_mmr_base + LBIST_CTRL); + writel(reg_val & (~(LBIST_CTRL_BIST_RESET_MAX << LBIST_CTRL_BIST_RESET_SHIFT)), + ctrl_mmr_base + LBIST_CTRL); +} + +/* + * struct lbist_config - Structure containing different configuration used for LBIST + * @dc_def: Clock delay after scan_enable switching + * @divide_ratio: LBIST clock divide ratio + * @static_pc_def: Bitmap of stuck-at patterns to run + * @set_pc_def: Bitmap of set patterns to run + * @reset_pc_def: Bitmap of reset patterns to run + * @scan_pc_def: Bitmap of chain test patterns to run + * @prpg_def: Initial seed for Pseudo Random Pattern generator (PRPG) + */ +struct lbist_config { + u32 dc_def; + u32 divide_ratio; + u32 static_pc_def; + u32 set_pc_def; + u32 reset_pc_def; + u32 scan_pc_def; + u32 prpg_def_l; + u32 prpg_def_u; +}; + +/* + * struct lbist_inst_info - Structure for different configuration used for LBIST + * @lbist_signature: Pointer to LBIST signature + * @intr_num: Interrupt number triggered by this LBIST instance to MCU R5 VIM + * @expected_misr: Expected signature + * @lbist_config: Configuration for LBIST test + */ +struct lbist_inst_info { + u32 *lbist_signature; + u32 intr_num; + u32 expected_misr; + struct lbist_config lbist_conf; + struct core_under_test cut; +}; + +#if IS_ENABLED(CONFIG_SOC_K3_J784S4) + +#include "k3_j784s4_bist_static_data.h" + +#endif /* CONFIG_SOC_K3_J784S4 */ +#endif /* __K3_BIST_STATIC_DATA_H */ diff --git a/drivers/misc/k3_j784s4_bist_static_data.h b/drivers/misc/k3_j784s4_bist_static_data.h new file mode 100644 index 00000000000..7f9378e917f --- /dev/null +++ b/drivers/misc/k3_j784s4_bist_static_data.h @@ -0,0 +1,370 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Static Data for Texas Instruments' BIST logic for J784S4 + * + * Copyright (C) 2025 Texas Instruments Incorporated - https://www.ti.com/ + * + */ + +/* Device IDs of IPs that can be tested under BIST */ +#define TISCI_DEV_MCU_R5FSS2_CORE0 343 +#define TISCI_DEV_MCU_R5FSS2_CORE1 344 +#define TISCI_DEV_RTI32 365 +#define TISCI_DEV_RTI33 366 + +/* WKUP CTRL MMR Registers */ +#define WKUP_CTRL_MMR_CFG0_WKUP_POST_STAT 0x0000C2C0 +#define WKUP_CTRL_MMR_CFG0_WKUP_POST_STAT_POST_MCU_PBIST_DONE_SHIFT 0x00000008 +#define WKUP_CTRL_MMR_CFG0_WKUP_POST_STAT_POST_MCU_LBIST_DONE_SHIFT 0x00000001 +#define WKUP_CTRL_MMR_CFG0_WKUP_POST_STAT_POST_MCU_PBIST_TIMEOUT_SHIFT 0x00000009 +#define WKUP_CTRL_MMR_CFG0_WKUP_POST_STAT_POST_MCU_LBIST_TIMEOUT_SHIFT 0x00000005 +#define WKUP_CTRL_MMR_CFG0_WKUP_POST_STAT_POST_MCU_PBIST_FAIL_MASK 0x00008000 + +/* MCU CTRL MMR Register */ +#define MCU_CTRL_MMR0_CFG0_BASE 0x40f00000 +#define MCU_CTRL_MMR_CFG0_MCU_LBIST_CTRL 0x0000c000 +#define MCU_CTRL_MMR_CFG0_MCU_LBIST_SIG 0x0000c280 +#define MCU_LBIST_BASE (MCU_CTRL_MMR0_CFG0_BASE + \ + MCU_CTRL_MMR_CFG0_MCU_LBIST_CTRL) + +/* Properties of PBIST instances in: PBIST14 */ +#define PBIST14_DEV_ID 234 +#define PBIST14_NUM_TEST_VECTORS 0x1 +#define PBIST14_ALGO_BITMAP_0 0x00000003 +#define PBIST14_MEM_BITMAP_0 0x000CCCCC +#define PBIST14_FAIL_INSERTION_TEST_VECTOR_CA0 0x00000000 +#define PBIST14_FAIL_INSERTION_TEST_VECTOR_CA1 0x000001FF +#define PBIST14_FAIL_INSERTION_TEST_VECTOR_CA2 0x000001FF +#define PBIST14_FAIL_INSERTION_TEST_VECTOR_CA3 0x00000000 +#define PBIST14_FAIL_INSERTION_TEST_VECTOR_CL0 0x0000007F +#define PBIST14_FAIL_INSERTION_TEST_VECTOR_CL1 0x00000003 +#define PBIST14_FAIL_INSERTION_TEST_VECTOR_CL2 0x00000008 +#define PBIST14_FAIL_INSERTION_TEST_VECTOR_CL3 0x000001FF +#define PBIST14_FAIL_INSERTION_TEST_VECTOR_CMS 0x00000000 +#define PBIST14_FAIL_INSERTION_TEST_VECTOR_CSR 0x20000000 +#define PBIST14_FAIL_INSERTION_TEST_VECTOR_I0 0x00000001 +#define PBIST14_FAIL_INSERTION_TEST_VECTOR_I1 0x00000004 +#define PBIST14_FAIL_INSERTION_TEST_VECTOR_I2 0x00000008 +#define PBIST14_FAIL_INSERTION_TEST_VECTOR_I3 0x00000000 +#define PBIST14_FAIL_INSERTION_TEST_VECTOR_RAMT 0x011D2528 + +static struct pbist_inst_info pbist14_inst_info = { + /* Main Pulsar 2 Instance 1 or MAIN_R52_x */ + .num_pbist_runs = 1, + .intr_num = PBIST14_DFT_PBIST_CPU_0_INTR_NUM, + .dev_id = TISCI_DEV_PBIST14, + .cut = { + { + .dev_id = TISCI_DEV_R5FSS2_CORE0, + .proc_id = PROC_ID_MCU_R5FSS2_CORE0, + }, + { + .dev_id = TISCI_DEV_R5FSS2_CORE1, + .proc_id = PROC_ID_MCU_R5FSS2_CORE1, + } + }, + .pbist_config_run = { + { + .override = 0, + .algorithms_bit_map = PBIST14_ALGO_BITMAP_0, + .memory_groups_bit_map = PBIST14_MEM_BITMAP_0, + .scramble_value_lo = 0x76543210, + .scramble_value_hi = 0xFEDCBA98, + }, + { + .override = 0, + .algorithms_bit_map = 0, + .memory_groups_bit_map = 0, + .scramble_value_lo = 0, + .scramble_value_hi = 0, + }, + }, + .pbist_neg_config_run = { + .CA0 = PBIST14_FAIL_INSERTION_TEST_VECTOR_CA0, + .CA1 = PBIST14_FAIL_INSERTION_TEST_VECTOR_CA1, + .CA2 = PBIST14_FAIL_INSERTION_TEST_VECTOR_CA2, + .CA3 = PBIST14_FAIL_INSERTION_TEST_VECTOR_CA3, + .CL0 = PBIST14_FAIL_INSERTION_TEST_VECTOR_CL0, + .CL1 = PBIST14_FAIL_INSERTION_TEST_VECTOR_CL1, + .CL2 = PBIST14_FAIL_INSERTION_TEST_VECTOR_CL2, + .CL3 = PBIST14_FAIL_INSERTION_TEST_VECTOR_CL3, + .CMS = PBIST14_FAIL_INSERTION_TEST_VECTOR_CMS, + .CSR = PBIST14_FAIL_INSERTION_TEST_VECTOR_CSR, + .I0 = PBIST14_FAIL_INSERTION_TEST_VECTOR_I0, + .I1 = PBIST14_FAIL_INSERTION_TEST_VECTOR_I1, + .I2 = PBIST14_FAIL_INSERTION_TEST_VECTOR_I2, + .I3 = PBIST14_FAIL_INSERTION_TEST_VECTOR_I3, + .RAMT = PBIST14_FAIL_INSERTION_TEST_VECTOR_RAMT + }, + .num_pbist_rom_test_runs = 1, + .pbist_rom_test_config_run = { + { + .D = 0xF412605Eu, + .E = 0xF412605Eu, + .CA2 = 0x7FFFu, + .CL0 = 0x3FFu, + .CA3 = 0x0u, + .I0 = 0x1u, + .CL1 = 0x1Fu, + .I3 = 0x0u, + .I2 = 0xEu, + .CL2 = 0xEu, + .CA1 = 0x7FFFu, + .CA0 = 0x0u, + .CL3 = 0x7FFFu, + .I1 = 0x20u, + .RAMT = 0x08002020u, + .CSR = 0x00000001u, + .CMS = 0x01u + }, + { + .D = 0x0u, + .E = 0x0u, + .CA2 = 0x0u, + .CL0 = 0x0u, + .CA3 = 0x0u, + .I0 = 0x0u, + .CL1 = 0x0u, + .I3 = 0x0u, + .I2 = 0x0u, + .CL2 = 0x0u, + .CA1 = 0x0u, + .CA0 = 0x0u, + .CL3 = 0x0u, + .I1 = 0x0u, + .RAMT = 0x0u, + .CSR = 0x0u, + .CMS = 0x0u + }, + { + .D = 0x0u, + .E = 0x0u, + .CA2 = 0x0u, + .CL0 = 0x0u, + .CA3 = 0x0u, + .I0 = 0x0u, + .CL1 = 0x0u, + .I3 = 0x0u, + .I2 = 0x0u, + .CL2 = 0x0u, + .CA1 = 0x0u, + .CA0 = 0x0u, + .CL3 = 0x0u, + .I1 = 0x0u, + .RAMT = 0x0u, + .CSR = 0x0u, + .CMS = 0x0u + }, + { + .D = 0x0u, + .E = 0x0u, + .CA2 = 0x0u, + .CL0 = 0x0u, + .CA3 = 0x0u, + .I0 = 0x0u, + .CL1 = 0x0u, + .I3 = 0x0u, + .I2 = 0x0u, + .CL2 = 0x0u, + .CA1 = 0x0u, + .CA0 = 0x0u, + .CL3 = 0x0u, + .I1 = 0x0u, + .RAMT = 0x0u, + .CSR = 0x0u, + .CMS = 0x0u + }, + { + .D = 0x0u, + .E = 0x0u, + .CA2 = 0x0u, + .CL0 = 0x0u, + .CA3 = 0x0u, + .I0 = 0x0u, + .CL1 = 0x0u, + .I3 = 0x0u, + .I2 = 0x0u, + .CL2 = 0x0u, + .CA1 = 0x0u, + .CA0 = 0x0u, + .CL3 = 0x0u, + .I1 = 0x0u, + .RAMT = 0x0u, + .CSR = 0x0u, + .CMS = 0x0u + }, + { + .D = 0x0u, + .E = 0x0u, + .CA2 = 0x0u, + .CL0 = 0x0u, + .CA3 = 0x0u, + .I0 = 0x0u, + .CL1 = 0x0u, + .I3 = 0x0u, + .I2 = 0x0u, + .CL2 = 0x0u, + .CA1 = 0x0u, + .CA0 = 0x0u, + .CL3 = 0x0u, + .I1 = 0x0u, + .RAMT = 0x0u, + .CSR = 0x0u, + .CMS = 0x0u + }, + { + .D = 0x0u, + .E = 0x0u, + .CA2 = 0x0u, + .CL0 = 0x0u, + .CA3 = 0x0u, + .I0 = 0x0u, + .CL1 = 0x0u, + .I3 = 0x0u, + .I2 = 0x0u, + .CL2 = 0x0u, + .CA1 = 0x0u, + .CA0 = 0x0u, + .CL3 = 0x0u, + .I1 = 0x0u, + .RAMT = 0x0u, + .CSR = 0x0u, + .CMS = 0x0u + }, + { + .D = 0x0u, + .E = 0x0u, + .CA2 = 0x0u, + .CL0 = 0x0u, + .CA3 = 0x0u, + .I0 = 0x0u, + .CL1 = 0x0u, + .I3 = 0x0u, + .I2 = 0x0u, + .CL2 = 0x0u, + .CA1 = 0x0u, + .CA0 = 0x0u, + .CL3 = 0x0u, + .I1 = 0x0u, + .RAMT = 0x0u, + .CSR = 0x0u, + .CMS = 0x0u + }, + { + .D = 0x0u, + .E = 0x0u, + .CA2 = 0x0u, + .CL0 = 0x0u, + .CA3 = 0x0u, + .I0 = 0x0u, + .CL1 = 0x0u, + .I3 = 0x0u, + .I2 = 0x0u, + .CL2 = 0x0u, + .CA1 = 0x0u, + .CA0 = 0x0u, + .CL3 = 0x0u, + .I1 = 0x0u, + .RAMT = 0x0u, + .CSR = 0x0u, + .CMS = 0x0u + }, + { + .D = 0x0u, + .E = 0x0u, + .CA2 = 0x0u, + .CL0 = 0x0u, + .CA3 = 0x0u, + .I0 = 0x0u, + .CL1 = 0x0u, + .I3 = 0x0u, + .I2 = 0x0u, + .CL2 = 0x0u, + .CA1 = 0x0u, + .CA0 = 0x0u, + .CL3 = 0x0u, + .I1 = 0x0u, + .RAMT = 0x0u, + .CSR = 0x0u, + .CMS = 0x0u + }, + { + .D = 0x0u, + .E = 0x0u, + .CA2 = 0x0u, + .CL0 = 0x0u, + .CA3 = 0x0u, + .I0 = 0x0u, + .CL1 = 0x0u, + .I3 = 0x0u, + .I2 = 0x0u, + .CL2 = 0x0u, + .CA1 = 0x0u, + .CA0 = 0x0u, + .CL3 = 0x0u, + .I1 = 0x0u, + .RAMT = 0x0u, + .CSR = 0x0u, + .CMS = 0x0u + }, + { + .D = 0x0u, + .E = 0x0u, + .CA2 = 0x0u, + .CL0 = 0x0u, + .CA3 = 0x0u, + .I0 = 0x0u, + .CL1 = 0x0u, + .I3 = 0x0u, + .I2 = 0x0u, + .CL2 = 0x0u, + .CA1 = 0x0u, + .CA0 = 0x0u, + .CL3 = 0x0u, + .I1 = 0x0u, + .RAMT = 0x0u, + .CSR = 0x0u, + .CMS = 0x0u + }, + { + .D = 0x0u, + .E = 0x0u, + .CA2 = 0x0u, + .CL0 = 0x0u, + .CA3 = 0x0u, + .I0 = 0x0u, + .CL1 = 0x0u, + .I3 = 0x0u, + .I2 = 0x0u, + .CL2 = 0x0u, + .CA1 = 0x0u, + .CA0 = 0x0u, + .CL3 = 0x0u, + .I1 = 0x0u, + .RAMT = 0x0u, + .CSR = 0x0u, + .CMS = 0x0u + }, + }, +}; + +static struct lbist_inst_info lbist_inst_info_main_r5f2_x = { + /* Main Pulsar 2 Instance 1 or MAIN_R52_x */ + .lbist_signature = (u32 *)(MAIN_R5F2_LBIST_SIG), + .intr_num = MCU_R5FSS0_CORE0_INTR_LBIST_BIST_DONE_0, + .expected_misr = MAIN_R5_MISR_EXP_VAL, + .lbist_conf = { + .dc_def = LBIST_DC_DEF, + .divide_ratio = LBIST_DIVIDE_RATIO, + .static_pc_def = LBIST_MAIN_R5_STATIC_PC_DEF, + .set_pc_def = LBIST_SET_PC_DEF, + .reset_pc_def = LBIST_RESET_PC_DEF, + .scan_pc_def = LBIST_SCAN_PC_DEF, + .prpg_def_l = LBIST_PRPG_DEF_L, + .prpg_def_u = LBIST_PRPG_DEF_U, + }, + .cut = { + .dev_id = TISCI_DEV_R5FSS2_CORE0, + .proc_id = PROC_ID_MCU_R5FSS2_CORE0, + }, +}; diff --git a/drivers/mmc/exynos_dw_mmc.c b/drivers/mmc/exynos_dw_mmc.c index c8bf89d6d35..12e37cb4b78 100644 --- a/drivers/mmc/exynos_dw_mmc.c +++ b/drivers/mmc/exynos_dw_mmc.c @@ -373,6 +373,12 @@ static const struct udevice_id exynos_dwmmc_ids[] = { .compatible = "samsung,exynos4412-dw-mshc", .data = (ulong)&exynos4_drv_data, }, { + .compatible = "samsung,exynos5420-dw-mshc-smu", + .data = (ulong)&exynos5_drv_data, + }, { + .compatible = "samsung,exynos5420-dw-mshc", + .data = (ulong)&exynos5_drv_data, + }, { .compatible = "samsung,exynos-dwmmc", .data = (ulong)&exynos5_drv_data, }, { diff --git a/drivers/mmc/mmc_write.c b/drivers/mmc/mmc_write.c index 90fcf2679bb..928c05872ca 100644 --- a/drivers/mmc/mmc_write.c +++ b/drivers/mmc/mmc_write.c @@ -155,6 +155,7 @@ static ulong mmc_write_blocks(struct mmc *mmc, lbaint_t start, struct mmc_cmd cmd; struct mmc_data data; int timeout_ms = 1000; + int err; if ((start + blkcnt) > mmc_get_blk_desc(mmc)->lba) { printf("MMC: block number 0x" LBAF " exceeds max(0x" LBAF ")\n", @@ -181,9 +182,13 @@ static ulong mmc_write_blocks(struct mmc *mmc, lbaint_t start, data.blocksize = mmc->write_bl_len; data.flags = MMC_DATA_WRITE; - if (mmc_send_cmd(mmc, &cmd, &data)) { + err = mmc_send_cmd(mmc, &cmd, &data); + if (err) { printf("mmc write failed\n"); - return 0; + /* + * Don't return 0 here since the emmc will still be in data + * transfer mode continue to send the STOP_TRANSMISSION command + */ } /* SPI multiblock writes terminate using a special @@ -203,6 +208,9 @@ static ulong mmc_write_blocks(struct mmc *mmc, lbaint_t start, if (mmc_poll_for_busy(mmc, timeout_ms)) return 0; + if (err) + return 0; + return blkcnt; } diff --git a/drivers/mmc/s5p_sdhci.c b/drivers/mmc/s5p_sdhci.c index 278019f02ab..c80033d8752 100644 --- a/drivers/mmc/s5p_sdhci.c +++ b/drivers/mmc/s5p_sdhci.c @@ -141,14 +141,6 @@ static int do_sdhci_init(struct sdhci_host *host) } } - if (dm_gpio_is_valid(&host->cd_gpio)) { - ret = dm_gpio_get_value(&host->cd_gpio); - if (ret) { - debug("no SD card detected (%d)\n", ret); - return -ENODEV; - } - } - return s5p_sdhci_core_init(host); } @@ -183,8 +175,6 @@ static int sdhci_get_config(const void *blob, int node, struct sdhci_host *host) gpio_request_by_name_nodev(offset_to_ofnode(node), "pwr-gpios", 0, &host->pwr_gpio, GPIOD_IS_OUT); - gpio_request_by_name_nodev(offset_to_ofnode(node), "cd-gpios", 0, - &host->cd_gpio, GPIOD_IS_IN); return 0; } @@ -236,6 +226,7 @@ static int s5p_sdhci_bind(struct udevice *dev) static const struct udevice_id s5p_sdhci_ids[] = { { .compatible = "samsung,exynos4412-sdhci"}, + { .compatible = "samsung,exynos4210-sdhci"}, { } }; diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c index 06c1e09bf26..e28c81afffe 100644 --- a/drivers/mmc/sunxi_mmc.c +++ b/drivers/mmc/sunxi_mmc.c @@ -99,6 +99,19 @@ static int mmc_set_mod_clk(struct sunxi_mmc_priv *priv, unsigned int hz) */ if (IS_ENABLED(CONFIG_MACH_SUN8I_R528)) pll_hz /= 2; + + /* + * The A523/T527 uses PERIPH0_400M as the MMC0/1 input clock, + * and PERIPH0_800M for MMC2. There is also the hidden divider + * of 2. The clock code reports 600 MHz for PERIPH0. + * Adjust the calculation accordingly: 600 * hidden2 / 3 for + * MMC0/1, and 600 * hidden2 / 3 * 2 for MMC2. + */ + if (IS_ENABLED(CONFIG_MACH_SUN55I_A523)) { + pll_hz /= 3; + if (priv->mmc_no == 2) + pll_hz *= 2; + } } div = pll_hz / hz; @@ -153,6 +166,10 @@ static int mmc_set_mod_clk(struct sunxi_mmc_priv *priv, unsigned int hz) CCM_MMC_CTRL_SCLK_DLY(sclk_dly); } + /* The A523 has a second divider, not a shift. */ + if (IS_ENABLED(CONFIG_MACH_SUN55I_A523)) + n = (1U << n) - 1; + writel(CCM_MMC_CTRL_ENABLE| pll | CCM_MMC_CTRL_N(n) | CCM_MMC_CTRL_M(div) | val, priv->mclkreg); @@ -559,7 +576,8 @@ struct mmc *sunxi_mmc_init(int sdc_no) cfg->host_caps = MMC_MODE_4BIT; if ((IS_ENABLED(CONFIG_MACH_SUN50I) || IS_ENABLED(CONFIG_MACH_SUN8I) || - IS_ENABLED(CONFIG_SUN50I_GEN_H6)) && (sdc_no == 2)) + IS_ENABLED(CONFIG_SUN50I_GEN_H6) || IS_ENABLED(CONFIG_MACH_SUN55I_A523)) && + (sdc_no == 2)) cfg->host_caps = MMC_MODE_8BIT; cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS; diff --git a/drivers/net/sandbox-raw-bus.c b/drivers/net/sandbox-raw-bus.c index 15670d6d24a..c698a07c784 100644 --- a/drivers/net/sandbox-raw-bus.c +++ b/drivers/net/sandbox-raw-bus.c @@ -42,7 +42,7 @@ static int eth_raw_bus_post_bind(struct udevice *dev) device_probe(child); priv = dev_get_priv(child); if (priv) { - strcpy(priv->host_ifname, i->if_name); + strlcpy(priv->host_ifname, i->if_name, IFNAMSIZ); priv->host_ifindex = i->if_index; priv->local = local; } diff --git a/drivers/net/xilinx_axi_mrmac.c b/drivers/net/xilinx_axi_mrmac.c index 555651937f8..56f877c20a6 100644 --- a/drivers/net/xilinx_axi_mrmac.c +++ b/drivers/net/xilinx_axi_mrmac.c @@ -346,7 +346,7 @@ static bool isrxready(struct axi_mrmac_priv *priv) * axi_mrmac_recv - MRMAC Rx function * @dev: udevice structure * @flags: flags from network stack - * @packetp pointer to received data + * @packetp: pointer to received data * * Return: received data length on success, negative value on errors * @@ -399,7 +399,7 @@ static int axi_mrmac_recv(struct udevice *dev, int flags, uchar **packetp) * axi_mrmac_free_pkt - MRMAC free packet function * @dev: udevice structure * @packet: receive buffer pointer - * @length received data length + * @length: received data length * * Return: 0 on success, negative value on errors * diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index d3fe90d939e..c297fa03ea7 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -259,6 +259,15 @@ config MT76X8_USB_PHY This PHY is found on MT76x8 devices supporting USB. +config PHY_EXYNOS_USBDRD + bool "Exynos SoC series USB DRD PHY driver" + depends on PHY && CLK + depends on ARCH_EXYNOS + select REGMAP + select SYSCON + help + Enable USB DRD PHY support for Exynos SoC series. + config PHY_MTK_TPHY bool "MediaTek T-PHY Driver" depends on PHY diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile index b4d01fc700d..98c1ef8683b 100644 --- a/drivers/phy/Makefile +++ b/drivers/phy/Makefile @@ -35,6 +35,7 @@ obj-$(CONFIG_KEYSTONE_USB_PHY) += keystone-usb-phy.o obj-$(CONFIG_MT7620_USB_PHY) += mt7620-usb-phy.o obj-$(CONFIG_MT76X8_USB_PHY) += mt76x8-usb-phy.o obj-$(CONFIG_PHY_DA8XX_USB) += phy-da8xx-usb.o +obj-$(CONFIG_PHY_EXYNOS_USBDRD) += phy-exynos-usbdrd.o obj-$(CONFIG_PHY_MTK_TPHY) += phy-mtk-tphy.o obj-$(CONFIG_PHY_NPCM_USB) += phy-npcm-usb.o obj-$(CONFIG_PHY_IMX8MQ_USB) += phy-imx8mq-usb.o diff --git a/drivers/phy/phy-exynos-usbdrd.c b/drivers/phy/phy-exynos-usbdrd.c new file mode 100644 index 00000000000..db5815ed184 --- /dev/null +++ b/drivers/phy/phy-exynos-usbdrd.c @@ -0,0 +1,386 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2025 Linaro Ltd. + * Sam Protsenko <semen.protsenko@linaro.org> + * + * Samsung Exynos SoC series USB DRD PHY driver. + * Based on Linux kernel PHY driver: drivers/phy/samsung/phy-exynos5-usbdrd.c + */ + +#include <clk.h> +#include <dm.h> +#include <generic-phy.h> +#include <regmap.h> +#include <syscon.h> +#include <asm/io.h> +#include <dm/device_compat.h> +#include <linux/bitfield.h> +#include <linux/bitops.h> +#include <linux/delay.h> + +/* Offset of PMU register controlling USB PHY output isolation */ +#define EXYNOS_USBDRD_PHY_CONTROL 0x0704 +#define EXYNOS_PHY_ENABLE BIT(0) + +/* Exynos USB PHY registers */ +#define EXYNOS5_FSEL_9MHZ6 0x0 +#define EXYNOS5_FSEL_10MHZ 0x1 +#define EXYNOS5_FSEL_12MHZ 0x2 +#define EXYNOS5_FSEL_19MHZ2 0x3 +#define EXYNOS5_FSEL_20MHZ 0x4 +#define EXYNOS5_FSEL_24MHZ 0x5 +#define EXYNOS5_FSEL_26MHZ 0x6 +#define EXYNOS5_FSEL_50MHZ 0x7 + +/* Exynos850: USB DRD PHY registers */ +#define EXYNOS850_DRD_LINKCTRL 0x04 +#define LINKCTRL_FORCE_QACT BIT(8) +#define LINKCTRL_BUS_FILTER_BYPASS GENMASK(7, 4) + +#define EXYNOS850_DRD_CLKRST 0x20 +#define CLKRST_LINK_SW_RST BIT(0) +#define CLKRST_PORT_RST BIT(1) +#define CLKRST_PHY_SW_RST BIT(3) + +#define EXYNOS850_DRD_SSPPLLCTL 0x30 +#define SSPPLLCTL_FSEL GENMASK(2, 0) + +#define EXYNOS850_DRD_UTMI 0x50 +#define UTMI_FORCE_SLEEP BIT(0) +#define UTMI_FORCE_SUSPEND BIT(1) +#define UTMI_DM_PULLDOWN BIT(2) +#define UTMI_DP_PULLDOWN BIT(3) +#define UTMI_FORCE_BVALID BIT(4) +#define UTMI_FORCE_VBUSVALID BIT(5) + +#define EXYNOS850_DRD_HSP 0x54 +#define HSP_COMMONONN BIT(8) +#define HSP_EN_UTMISUSPEND BIT(9) +#define HSP_VBUSVLDEXT BIT(12) +#define HSP_VBUSVLDEXTSEL BIT(13) +#define HSP_FSV_OUT_EN BIT(24) + +#define EXYNOS850_DRD_HSP_TEST 0x5c +#define HSP_TEST_SIDDQ BIT(24) + +#define KHZ 1000 +#define MHZ (KHZ * KHZ) + +/** + * struct exynos_usbdrd_phy - driver data for Exynos USB PHY + * @reg_phy: USB PHY controller register memory base + * @clk: clock for register access + * @core_clk: core clock for phy (ref clock) + * @reg_pmu: regmap for PMU block + * @extrefclk: frequency select settings when using 'separate reference clocks' + */ +struct exynos_usbdrd_phy { + void __iomem *reg_phy; + struct clk *clk; + struct clk *core_clk; + struct regmap *reg_pmu; + u32 extrefclk; +}; + +static void exynos_usbdrd_phy_isol(struct regmap *reg_pmu, bool isolate) +{ + unsigned int val; + + if (!reg_pmu) + return; + + val = isolate ? 0 : EXYNOS_PHY_ENABLE; + regmap_update_bits(reg_pmu, EXYNOS_USBDRD_PHY_CONTROL, + EXYNOS_PHY_ENABLE, val); +} + +/* + * Convert the supplied clock rate to the value that can be written to the PHY + * register. + */ +static unsigned int exynos_rate_to_clk(unsigned long rate, u32 *reg) +{ + switch (rate) { + case 9600 * KHZ: + *reg = EXYNOS5_FSEL_9MHZ6; + break; + case 10 * MHZ: + *reg = EXYNOS5_FSEL_10MHZ; + break; + case 12 * MHZ: + *reg = EXYNOS5_FSEL_12MHZ; + break; + case 19200 * KHZ: + *reg = EXYNOS5_FSEL_19MHZ2; + break; + case 20 * MHZ: + *reg = EXYNOS5_FSEL_20MHZ; + break; + case 24 * MHZ: + *reg = EXYNOS5_FSEL_24MHZ; + break; + case 26 * MHZ: + *reg = EXYNOS5_FSEL_26MHZ; + break; + case 50 * MHZ: + *reg = EXYNOS5_FSEL_50MHZ; + break; + default: + return -EINVAL; + } + + return 0; +} + +static void exynos850_usbdrd_utmi_init(struct phy *phy) +{ + struct exynos_usbdrd_phy *phy_drd = dev_get_priv(phy->dev); + void __iomem *regs_base = phy_drd->reg_phy; + u32 reg; + + /* + * Disable HWACG (hardware auto clock gating control). This will force + * QACTIVE signal in Q-Channel interface to HIGH level, to make sure + * the PHY clock is not gated by the hardware. + */ + reg = readl(regs_base + EXYNOS850_DRD_LINKCTRL); + reg |= LINKCTRL_FORCE_QACT; + writel(reg, regs_base + EXYNOS850_DRD_LINKCTRL); + + /* Start PHY Reset (POR=high) */ + reg = readl(regs_base + EXYNOS850_DRD_CLKRST); + reg |= CLKRST_PHY_SW_RST; + writel(reg, regs_base + EXYNOS850_DRD_CLKRST); + + /* Enable UTMI+ */ + reg = readl(regs_base + EXYNOS850_DRD_UTMI); + reg &= ~(UTMI_FORCE_SUSPEND | UTMI_FORCE_SLEEP | UTMI_DP_PULLDOWN | + UTMI_DM_PULLDOWN); + writel(reg, regs_base + EXYNOS850_DRD_UTMI); + + /* Set PHY clock and control HS PHY */ + reg = readl(regs_base + EXYNOS850_DRD_HSP); + reg |= HSP_EN_UTMISUSPEND | HSP_COMMONONN; + writel(reg, regs_base + EXYNOS850_DRD_HSP); + + /* Set VBUS Valid and D+ pull-up control by VBUS pad usage */ + reg = readl(regs_base + EXYNOS850_DRD_LINKCTRL); + reg |= FIELD_PREP(LINKCTRL_BUS_FILTER_BYPASS, 0xf); + writel(reg, regs_base + EXYNOS850_DRD_LINKCTRL); + + reg = readl(regs_base + EXYNOS850_DRD_UTMI); + reg |= UTMI_FORCE_BVALID | UTMI_FORCE_VBUSVALID; + writel(reg, regs_base + EXYNOS850_DRD_UTMI); + + reg = readl(regs_base + EXYNOS850_DRD_HSP); + reg |= HSP_VBUSVLDEXT | HSP_VBUSVLDEXTSEL; + writel(reg, regs_base + EXYNOS850_DRD_HSP); + + reg = readl(regs_base + EXYNOS850_DRD_SSPPLLCTL); + reg &= ~SSPPLLCTL_FSEL; + switch (phy_drd->extrefclk) { + case EXYNOS5_FSEL_50MHZ: + reg |= FIELD_PREP(SSPPLLCTL_FSEL, 7); + break; + case EXYNOS5_FSEL_26MHZ: + reg |= FIELD_PREP(SSPPLLCTL_FSEL, 6); + break; + case EXYNOS5_FSEL_24MHZ: + reg |= FIELD_PREP(SSPPLLCTL_FSEL, 2); + break; + case EXYNOS5_FSEL_20MHZ: + reg |= FIELD_PREP(SSPPLLCTL_FSEL, 1); + break; + case EXYNOS5_FSEL_19MHZ2: + reg |= FIELD_PREP(SSPPLLCTL_FSEL, 0); + break; + default: + dev_warn(phy->dev, "unsupported ref clk: %#.2x\n", + phy_drd->extrefclk); + break; + } + writel(reg, regs_base + EXYNOS850_DRD_SSPPLLCTL); + + /* Power up PHY analog blocks */ + reg = readl(regs_base + EXYNOS850_DRD_HSP_TEST); + reg &= ~HSP_TEST_SIDDQ; + writel(reg, regs_base + EXYNOS850_DRD_HSP_TEST); + + /* Finish PHY reset (POR=low) */ + udelay(10); /* required before doing POR=low */ + reg = readl(regs_base + EXYNOS850_DRD_CLKRST); + reg &= ~(CLKRST_PHY_SW_RST | CLKRST_PORT_RST); + writel(reg, regs_base + EXYNOS850_DRD_CLKRST); + udelay(75); /* required after POR=low for guaranteed PHY clock */ + + /* Disable single ended signal out */ + reg = readl(regs_base + EXYNOS850_DRD_HSP); + reg &= ~HSP_FSV_OUT_EN; + writel(reg, regs_base + EXYNOS850_DRD_HSP); +} + +static void exynos850_usbdrd_utmi_exit(struct phy *phy) +{ + struct exynos_usbdrd_phy *phy_drd = dev_get_priv(phy->dev); + void __iomem *regs_base = phy_drd->reg_phy; + u32 reg; + + /* Set PHY clock and control HS PHY */ + reg = readl(regs_base + EXYNOS850_DRD_UTMI); + reg &= ~(UTMI_DP_PULLDOWN | UTMI_DM_PULLDOWN); + reg |= UTMI_FORCE_SUSPEND | UTMI_FORCE_SLEEP; + writel(reg, regs_base + EXYNOS850_DRD_UTMI); + + /* Power down PHY analog blocks */ + reg = readl(regs_base + EXYNOS850_DRD_HSP_TEST); + reg |= HSP_TEST_SIDDQ; + writel(reg, regs_base + EXYNOS850_DRD_HSP_TEST); + + /* Link reset */ + reg = readl(regs_base + EXYNOS850_DRD_CLKRST); + reg |= CLKRST_LINK_SW_RST; + writel(reg, regs_base + EXYNOS850_DRD_CLKRST); + udelay(10); /* required before doing POR=low */ + reg &= ~CLKRST_LINK_SW_RST; + writel(reg, regs_base + EXYNOS850_DRD_CLKRST); +} + +static int exynos_usbdrd_phy_init(struct phy *phy) +{ + struct exynos_usbdrd_phy *phy_drd = dev_get_priv(phy->dev); + int ret; + + ret = clk_prepare_enable(phy_drd->clk); + if (ret) + return ret; + + exynos850_usbdrd_utmi_init(phy); + + clk_disable_unprepare(phy_drd->clk); + + return 0; +} + +static int exynos_usbdrd_phy_exit(struct phy *phy) +{ + struct exynos_usbdrd_phy *phy_drd = dev_get_priv(phy->dev); + int ret; + + ret = clk_prepare_enable(phy_drd->clk); + if (ret) + return ret; + + exynos850_usbdrd_utmi_exit(phy); + + clk_disable_unprepare(phy_drd->clk); + + return 0; +} + +static int exynos_usbdrd_phy_power_on(struct phy *phy) +{ + struct exynos_usbdrd_phy *phy_drd = dev_get_priv(phy->dev); + int ret; + + dev_dbg(phy->dev, "Request to power_on usbdrd_phy phy\n"); + + ret = clk_prepare_enable(phy_drd->core_clk); + if (ret) + return ret; + + /* Power-on PHY */ + exynos_usbdrd_phy_isol(phy_drd->reg_pmu, false); + + return 0; +} + +static int exynos_usbdrd_phy_power_off(struct phy *phy) +{ + struct exynos_usbdrd_phy *phy_drd = dev_get_priv(phy->dev); + + dev_dbg(phy->dev, "Request to power_off usbdrd_phy phy\n"); + + /* Power-off the PHY */ + exynos_usbdrd_phy_isol(phy_drd->reg_pmu, true); + + clk_disable_unprepare(phy_drd->core_clk); + + return 0; +} + +static int exynos_usbdrd_phy_init_clk(struct udevice *dev) +{ + struct exynos_usbdrd_phy *phy_drd = dev_get_priv(dev); + unsigned long ref_rate; + int err; + + phy_drd->clk = devm_clk_get(dev, "phy"); + if (IS_ERR(phy_drd->clk)) { + err = PTR_ERR(phy_drd->clk); + dev_err(dev, "Failed to get phy clock (err=%d)\n", err); + return err; + } + + phy_drd->core_clk = devm_clk_get(dev, "ref"); + if (IS_ERR(phy_drd->core_clk)) { + err = PTR_ERR(phy_drd->core_clk); + dev_err(dev, "Failed to get ref clock (err=%d)\n", err); + return err; + } + + ref_rate = clk_get_rate(phy_drd->core_clk); + err = exynos_rate_to_clk(ref_rate, &phy_drd->extrefclk); + if (err) { + dev_err(dev, "Clock rate %lu not supported\n", ref_rate); + return err; + } + + return 0; +} + +static int exynos_usbdrd_phy_probe(struct udevice *dev) +{ + struct exynos_usbdrd_phy *phy_drd = dev_get_priv(dev); + int err; + + phy_drd->reg_phy = dev_read_addr_ptr(dev); + if (!phy_drd->reg_phy) + return -EINVAL; + + err = exynos_usbdrd_phy_init_clk(dev); + if (err) + return err; + + phy_drd->reg_pmu = syscon_regmap_lookup_by_phandle(dev, + "samsung,pmu-syscon"); + if (IS_ERR(phy_drd->reg_pmu)) { + err = PTR_ERR(phy_drd->reg_pmu); + dev_err(dev, "Failed to lookup PMU regmap\n"); + return err; + } + + return 0; +} + +static const struct phy_ops exynos_usbdrd_phy_ops = { + .init = exynos_usbdrd_phy_init, + .exit = exynos_usbdrd_phy_exit, + .power_on = exynos_usbdrd_phy_power_on, + .power_off = exynos_usbdrd_phy_power_off, +}; + +static const struct udevice_id exynos_usbdrd_phy_of_match[] = { + { + .compatible = "samsung,exynos850-usbdrd-phy", + }, + { } +}; + +U_BOOT_DRIVER(exynos_usbdrd_phy) = { + .name = "exynos-usbdrd-phy", + .id = UCLASS_PHY, + .of_match = exynos_usbdrd_phy_of_match, + .probe = exynos_usbdrd_phy_probe, + .ops = &exynos_usbdrd_phy_ops, + .priv_auto = sizeof(struct exynos_usbdrd_phy), +}; diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig index 65e8192a99a..54314992299 100644 --- a/drivers/pinctrl/sunxi/Kconfig +++ b/drivers/pinctrl/sunxi/Kconfig @@ -139,4 +139,14 @@ config PINCTRL_SUN20I_D1 default MACH_SUN8I_R528 select PINCTRL_SUNXI +config PINCTRL_SUN55I_A523 + bool "Support for the Allwinner A523 PIO" + default MACH_SUN55I_A523 + select PINCTRL_SUNXI + +config PINCTRL_SUN55I_A523_R + bool "Support for the Allwinner A523 R-PIO" + default MACH_SUN55I_A523 + select PINCTRL_SUNXI + endif diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c index c38edf7d4f5..03cfe23aaf8 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c @@ -759,6 +759,29 @@ static const struct sunxi_pinctrl_desc __maybe_unused sun50i_h616_pinctrl_desc = .num_banks = 9, }; +static const struct sunxi_pinctrl_function sun55i_a523_pinctrl_functions[] = { + { "emac0", 5 }, /* PI0-PI16 */ + { "gpio_in", 0 }, + { "gpio_out", 1 }, + { "mmc0", 2 }, /* PF0-PF5 */ + { "mmc1", 2 }, /* PG0-PG5 */ + { "mmc2", 3 }, /* PC0-PC16 */ + { "spi0", 4 }, /* PC0-PC7, PC15-PC16 */ +#if IS_ENABLED(CONFIG_UART0_PORT_F) + { "uart0", 3 }, /* PF2-PF4 */ +#else + { "uart0", 2 }, /* PH0-PH1 */ +#endif + { "uart1", 2 }, /* PG6-PG7 */ +}; + +static const struct sunxi_pinctrl_desc __maybe_unused sun55i_a523_pinctrl_desc = { + .functions = sun55i_a523_pinctrl_functions, + .num_functions = ARRAY_SIZE(sun55i_a523_pinctrl_functions), + .first_bank = SUNXI_GPIO_A, + .num_banks = 11, +}; + static const struct sunxi_pinctrl_function sun50i_h616_r_pinctrl_functions[] = { { "gpio_in", 0 }, { "gpio_out", 1 }, @@ -809,6 +832,21 @@ static const struct sunxi_pinctrl_desc __maybe_unused sun50i_a100_r_pinctrl_desc .num_banks = 1, }; +static const struct sunxi_pinctrl_function sun55i_a523_r_pinctrl_functions[] = { + { "gpio_in", 0 }, + { "gpio_out", 1 }, + { "r_i2c0", 2 }, /* PL0-PL1 */ + { "r_spi", 6 }, /* PL10-PL13 */ + { "r_uart", 2 }, /* PL2-PL3 */ +}; + +static const struct sunxi_pinctrl_desc __maybe_unused sun55i_a523_r_pinctrl_desc = { + .functions = sun55i_a523_r_pinctrl_functions, + .num_functions = ARRAY_SIZE(sun55i_a523_r_pinctrl_functions), + .first_bank = SUNXI_GPIO_L, + .num_banks = 2, +}; + static const struct udevice_id sunxi_pinctrl_ids[] = { #ifdef CONFIG_PINCTRL_SUNIV_F1C100S { @@ -984,6 +1022,18 @@ static const struct udevice_id sunxi_pinctrl_ids[] = { .data = (ulong)&sun50i_a100_r_pinctrl_desc, }, #endif +#ifdef CONFIG_PINCTRL_SUN55I_A523 + { + .compatible = "allwinner,sun55i-a523-pinctrl", + .data = (ulong)&sun55i_a523_pinctrl_desc, + }, +#endif +#ifdef CONFIG_PINCTRL_SUN55I_A523_R + { + .compatible = "allwinner,sun55i-a523-r-pinctrl", + .data = (ulong)&sun55i_a523_r_pinctrl_desc, + }, +#endif {} }; diff --git a/drivers/power/domain/imx8m-power-domain.c b/drivers/power/domain/imx8m-power-domain.c index b44aae78e6d..a7e64971a2a 100644 --- a/drivers/power/domain/imx8m-power-domain.c +++ b/drivers/power/domain/imx8m-power-domain.c @@ -468,6 +468,8 @@ out_clk_disable: static int imx8m_power_domain_of_xlate(struct power_domain *power_domain, struct ofnode_phandle_args *args) { + power_domain->id = 0; + return 0; } diff --git a/drivers/power/pmic/axp.c b/drivers/power/pmic/axp.c index c300fd2bbc2..1204ec00f8d 100644 --- a/drivers/power/pmic/axp.c +++ b/drivers/power/pmic/axp.c @@ -89,6 +89,7 @@ static const struct udevice_id axp_pmic_ids[] = { { .compatible = "x-powers,axp221", .data = AXP221_ID }, { .compatible = "x-powers,axp223", .data = AXP223_ID }, { .compatible = "x-powers,axp313a", .data = AXP313_ID }, + { .compatible = "x-powers,axp323", .data = AXP323_ID }, { .compatible = "x-powers,axp717", .data = AXP717_ID }, { .compatible = "x-powers,axp803", .data = AXP803_ID }, { .compatible = "x-powers,axp806", .data = AXP806_ID }, diff --git a/drivers/power/regulator/axp_regulator.c b/drivers/power/regulator/axp_regulator.c index 75cdbca30f6..7794a4f5d92 100644 --- a/drivers/power/regulator/axp_regulator.c +++ b/drivers/power/regulator/axp_regulator.c @@ -318,6 +318,7 @@ static const struct axp_regulator_plat *const axp_regulators[] = { [AXP221_ID] = axp22x_regulators, [AXP223_ID] = axp22x_regulators, [AXP313_ID] = axp313_regulators, + [AXP323_ID] = axp313_regulators, [AXP717_ID] = axp717_regulators, [AXP803_ID] = axp803_regulators, [AXP806_ID] = axp806_regulators, diff --git a/drivers/power/regulator/regulator-uclass.c b/drivers/power/regulator/regulator-uclass.c index 09567eb9dbb..2a59a1b79c2 100644 --- a/drivers/power/regulator/regulator-uclass.c +++ b/drivers/power/regulator/regulator-uclass.c @@ -260,13 +260,13 @@ int regulator_get_by_platname(const char *plat_name, struct udevice **devp) *devp = NULL; - for (ret = uclass_find_first_device(UCLASS_REGULATOR, &dev); dev; - ret = uclass_find_next_device(&dev)) { - if (ret) { - dev_dbg(dev, "ret=%d\n", ret); - continue; - } + ret = uclass_find_first_device(UCLASS_REGULATOR, &dev); + if (ret) { + dev_dbg(dev, "ret=%d\n", ret); + return ret; + } + for (; dev; uclass_find_next_device(&dev)) { uc_pdata = dev_get_uclass_plat(dev); if (!uc_pdata || strcmp(plat_name, uc_pdata->name)) continue; @@ -410,9 +410,12 @@ static bool regulator_name_is_unique(struct udevice *check_dev, int ret; int len; - for (ret = uclass_find_first_device(UCLASS_REGULATOR, &dev); dev; - ret = uclass_find_next_device(&dev)) { - if (ret || dev == check_dev) + ret = uclass_find_first_device(UCLASS_REGULATOR, &dev); + if (ret) + return true; + + for (; dev; uclass_find_next_device(&dev)) { + if (dev == check_dev) continue; uc_pdata = dev_get_uclass_plat(dev); diff --git a/drivers/remoteproc/rproc-uclass.c b/drivers/remoteproc/rproc-uclass.c index 3233ff80419..2dbd3a21cea 100644 --- a/drivers/remoteproc/rproc-uclass.c +++ b/drivers/remoteproc/rproc-uclass.c @@ -55,9 +55,12 @@ static int for_each_remoteproc_device(int (*fn) (struct udevice *dev, struct dm_rproc_uclass_pdata *uc_pdata; int ret; - for (ret = uclass_find_first_device(UCLASS_REMOTEPROC, &dev); dev; - ret = uclass_find_next_device(&dev)) { - if (ret || dev == skip_dev) + ret = uclass_find_first_device(UCLASS_REMOTEPROC, &dev); + if (ret) + return ret; + + for (; dev; uclass_find_next_device(&dev)) { + if (dev == skip_dev) continue; uc_pdata = dev_get_uclass_plat(dev); ret = fn(dev, uc_pdata, data); diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index a3513f0a3ef..1ae36b5a348 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -351,6 +351,8 @@ config MTK_SPIM config MVEBU_A3700_SPI bool "Marvell Armada 3700 SPI driver" + depends on ARCH_MVEBU && ARM64 + select CLK_MVEBU select CLK_ARMADA_3720 help Enable the Marvell Armada 3700 SPI driver. This driver can be diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c index 6f89d3add5d..4696c09f754 100644 --- a/drivers/spi/cadence_qspi_apb.c +++ b/drivers/spi/cadence_qspi_apb.c @@ -559,9 +559,6 @@ int cadence_qspi_apb_command_write(struct cadence_spi_priv *priv, u8 opcode; if (priv->dtr) - txlen += txlen & 1; - - if (priv->dtr) opcode = op->cmd.opcode >> 8; else opcode = op->cmd.opcode; diff --git a/drivers/sysreset/Kconfig b/drivers/sysreset/Kconfig index aa83073c96a..67edf004205 100644 --- a/drivers/sysreset/Kconfig +++ b/drivers/sysreset/Kconfig @@ -176,7 +176,7 @@ config SYSRESET_PALMAS config SYSRESET_PSCI bool "Enable support for PSCI System Reset" depends on ARM_PSCI_FW - select SPL_ARM_PSCI_FW if SPL + select SPL_ARM_PSCI_FW if SPL_SYSRESET help Enable PSCI SYSTEM_RESET function call. To use this, PSCI firmware must be running on your system. diff --git a/drivers/usb/Kconfig b/drivers/usb/Kconfig index 99c6649e417..daf2240ffd9 100644 --- a/drivers/usb/Kconfig +++ b/drivers/usb/Kconfig @@ -112,6 +112,7 @@ config USB_KEYBOARD config USB_ONBOARD_HUB bool "Onboard USB hub support" depends on DM_USB + select DEVRES ---help--- Say Y here if you want to support discrete onboard USB hubs that don't require an additional control bus for initialization, but diff --git a/drivers/usb/dwc3/dwc3-generic.c b/drivers/usb/dwc3/dwc3-generic.c index 21452ad1569..3cda2b74b7e 100644 --- a/drivers/usb/dwc3/dwc3-generic.c +++ b/drivers/usb/dwc3/dwc3-generic.c @@ -704,6 +704,7 @@ static const struct udevice_id dwc3_glue_ids[] = { { .compatible = "fsl,imx8mp-dwc3", .data = (ulong)&imx8mp_ops }, { .compatible = "fsl,imx8mq-dwc3" }, { .compatible = "intel,tangier-dwc3" }, + { .compatible = "samsung,exynos850-dwusb3" }, { } }; diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index e9ea874d0e3..56290b32bd9 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -15,6 +15,7 @@ config WATCHDOG_AUTOSTART bool "Automatically start watchdog timer" depends on WDT default n if ARCH_SUNXI + default n if ARCH_STM32MP default y help Automatically start watchdog timer and start servicing it during diff --git a/drivers/watchdog/arm_smc_wdt.c b/drivers/watchdog/arm_smc_wdt.c index 0ea44445700..f6854aa9ac9 100644 --- a/drivers/watchdog/arm_smc_wdt.c +++ b/drivers/watchdog/arm_smc_wdt.c @@ -46,6 +46,8 @@ static int smcwd_call(struct udevice *dev, enum smcwd_call call, return -ENODEV; if (res->a0 == PSCI_RET_INVALID_PARAMS) return -EINVAL; + if (res->a0 == PSCI_RET_DISABLED) + return -ENODATA; if (res->a0 != PSCI_RET_SUCCESS) return -EIO; @@ -99,6 +101,21 @@ static int smcwd_probe(struct udevice *dev) priv->min_timeout = res.a1; priv->max_timeout = res.a2; + /* If already started, then force u-boot to use it */ + err = smcwd_call(dev, SMCWD_GET_TIMELEFT, 0, NULL); + switch (err) { + case 0: + dev_dbg(dev, "Already started\n"); + wdt_set_force_autostart(dev); + break; + case -ENODATA: + dev_dbg(dev, "Not already started\n"); + break; + default: + /* Optional SMCWD_GET_TIMELEFT not implemented */ + break; + } + return 0; } diff --git a/drivers/watchdog/stm32mp_wdt.c b/drivers/watchdog/stm32mp_wdt.c index 97ab8cfe7ab..0712524b4a8 100644 --- a/drivers/watchdog/stm32mp_wdt.c +++ b/drivers/watchdog/stm32mp_wdt.c @@ -21,11 +21,13 @@ #define IWDG_PR 0x04 /* Prescaler Register */ #define IWDG_RLR 0x08 /* ReLoad Register */ #define IWDG_SR 0x0C /* Status Register */ +#define IWDG_VERR 0x3F4 /* Version Register */ /* IWDG_KR register bit mask */ #define KR_KEY_RELOAD 0xAAAA /* Reload counter enable */ #define KR_KEY_ENABLE 0xCCCC /* Peripheral enable */ #define KR_KEY_EWA 0x5555 /* Write access enable */ +#define KR_KEY_DWA 0x0000 /* Write access disable*/ /* IWDG_PR register bit values */ #define PR_256 0x06 /* Prescaler set to 256 */ @@ -36,10 +38,17 @@ /* IWDG_SR register bit values */ #define SR_PVU BIT(0) /* Watchdog prescaler value update */ #define SR_RVU BIT(1) /* Watchdog counter reload value update */ +#define SR_ONF BIT(8) /* Watchdog enable status bit */ + +/* IWDG Compatibility */ +#define ONF_MIN_VER 0x31 + +#define TIMEOUT_US 10000 struct stm32mp_wdt_priv { fdt_addr_t base; /* registers addr in physical memory */ unsigned long wdt_clk_rate; /* Watchdog dedicated clock rate */ + unsigned int hw_version; /* Peripheral version */ }; static int stm32mp_wdt_reset(struct udevice *dev) @@ -90,6 +99,7 @@ static int stm32mp_wdt_start(struct udevice *dev, u64 timeout_ms, ulong flags) static int stm32mp_wdt_probe(struct udevice *dev) { struct stm32mp_wdt_priv *priv = dev_get_priv(dev); + u32 rlr, sr; struct clk clk; int ret; @@ -115,6 +125,29 @@ static int stm32mp_wdt_probe(struct udevice *dev) priv->wdt_clk_rate = clk_get_rate(&clk); + priv->hw_version = readl(priv->base + IWDG_VERR); + + if (priv->hw_version >= ONF_MIN_VER) { + if (readl(priv->base + IWDG_SR) & SR_ONF) + wdt_set_force_autostart(dev); + } else { + /* + * Workaround for old versions without IWDG_SR_ONF bit: + * - write in IWDG_RLR_OFFSET + * - wait for sync + * - if sync succeeds, then iwdg is running + */ + writel(KR_KEY_EWA, priv->base + IWDG_KR); + rlr = readl(priv->base + IWDG_RLR); + writel(rlr, priv->base + IWDG_RLR); + ret = readl_poll_timeout(priv->base + IWDG_SR, sr, sr & SR_RVU, + TIMEOUT_US); + if (!ret) + wdt_set_force_autostart(dev); + + writel(KR_KEY_DWA, priv->base + IWDG_KR); + } + dev_dbg(dev, "IWDG init done\n"); return 0; diff --git a/drivers/watchdog/wdt-uclass.c b/drivers/watchdog/wdt-uclass.c index 10be334e9ed..b32590069d9 100644 --- a/drivers/watchdog/wdt-uclass.c +++ b/drivers/watchdog/wdt-uclass.c @@ -46,6 +46,15 @@ struct wdt_priv { struct cyclic_info cyclic; }; +int wdt_set_force_autostart(struct udevice *dev) +{ + struct wdt_priv *priv = dev_get_uclass_priv(dev); + + priv->autostart = true; + + return 0; +} + static void wdt_cyclic(struct cyclic_info *c) { struct wdt_priv *priv = container_of(c, struct wdt_priv, cyclic); |