diff options
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/gpio/Kconfig | 6 | ||||
| -rw-r--r-- | drivers/gpio/Makefile | 1 | ||||
| -rw-r--r-- | drivers/gpio/ftgpio010.c | 110 | ||||
| -rw-r--r-- | drivers/net/ti/am65-cpsw-nuss.c | 35 | ||||
| -rw-r--r-- | drivers/timer/Kconfig | 2 |
5 files changed, 22 insertions, 132 deletions
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 58e464106a3..db077e472a8 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -695,12 +695,6 @@ config SLG7XL45106_I2C_GPO 8-bit gpo expander, all gpo lines are controlled by writing value into data register. -config FTGPIO010 - bool "Faraday Technology FTGPIO010 driver" - depends on DM_GPIO - help - Support for GPIOs on Faraday Technology's FTGPIO010 controller. - config ADP5585_GPIO bool "ADP5585 GPIO driver" depends on DM_GPIO && DM_I2C diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index 83e10c79b91..73c94329e36 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -77,7 +77,6 @@ obj-$(CONFIG_SL28CPLD_GPIO) += sl28cpld-gpio.o obj-$(CONFIG_ADP5588_GPIO) += adp5588_gpio.o obj-$(CONFIG_ZYNQMP_GPIO_MODEPIN) += zynqmp_gpio_modepin.o obj-$(CONFIG_SLG7XL45106_I2C_GPO) += gpio_slg7xl45106.o -obj-$(CONFIG_FTGPIO010) += ftgpio010.o obj-$(CONFIG_$(PHASE_)ADP5585_GPIO) += adp5585_gpio.o obj-$(CONFIG_RZG2L_GPIO) += rzg2l-gpio.o obj-$(CONFIG_MPFS_GPIO) += mpfs_gpio.o diff --git a/drivers/gpio/ftgpio010.c b/drivers/gpio/ftgpio010.c deleted file mode 100644 index 4cb550a540c..00000000000 --- a/drivers/gpio/ftgpio010.c +++ /dev/null @@ -1,110 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Faraday Technology's FTGPIO010 controller. - */ - -#include <dm.h> -#include <asm/io.h> -#include <asm/gpio.h> - -struct ftgpio010_regs { - u32 out; - u32 in; - u32 direction; // 1 - output - u32 reserved; - u32 set; - u32 clear; -}; - -struct ftgpio010_plat { - struct ftgpio010_regs __iomem *regs; -}; - -static int ftgpio010_direction_input(struct udevice *dev, unsigned int pin) -{ - struct ftgpio010_plat *plat = dev_get_plat(dev); - struct ftgpio010_regs *const regs = plat->regs; - - clrbits_le32(®s->direction, 1 << pin); - return 0; -} - -static int ftgpio010_direction_output(struct udevice *dev, unsigned int pin, - int val) -{ - struct ftgpio010_plat *plat = dev_get_plat(dev); - struct ftgpio010_regs *const regs = plat->regs; - - /* change the data first, then the direction. to avoid glitch */ - out_le32(val ? ®s->set : ®s->clear, 1 << pin); - setbits_le32(®s->direction, 1 << pin); - - return 0; -} - -static int ftgpio010_get_value(struct udevice *dev, unsigned int pin) -{ - struct ftgpio010_plat *plat = dev_get_plat(dev); - struct ftgpio010_regs *const regs = plat->regs; - - return in_le32(®s->in) >> pin & 1; -} - -static int ftgpio010_set_value(struct udevice *dev, unsigned int pin, int val) -{ - struct ftgpio010_plat *plat = dev_get_plat(dev); - struct ftgpio010_regs *const regs = plat->regs; - - out_le32(val ? ®s->set : ®s->clear, 1 << pin); - return 0; -} - -static int ftgpio010_get_function(struct udevice *dev, unsigned int pin) -{ - struct ftgpio010_plat *plat = dev_get_plat(dev); - struct ftgpio010_regs *const regs = plat->regs; - - if (in_le32(®s->direction) >> pin & 1) - return GPIOF_OUTPUT; - return GPIOF_INPUT; -} - -static int ftgpio010_probe(struct udevice *dev) -{ - struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); - - uc_priv->gpio_count = ofnode_read_u32_default(dev_ofnode(dev), - "nr-gpios", 32); - return 0; -} - -static int ftgpio010_of_to_plat(struct udevice *dev) -{ - struct ftgpio010_plat *plat = dev_get_plat(dev); - - plat->regs = dev_read_addr_ptr(dev); - return 0; -} - -static const struct dm_gpio_ops ftgpio010_ops = { - .direction_input = ftgpio010_direction_input, - .direction_output = ftgpio010_direction_output, - .get_value = ftgpio010_get_value, - .set_value = ftgpio010_set_value, - .get_function = ftgpio010_get_function, -}; - -static const struct udevice_id ftgpio010_ids[] = { - { .compatible = "faraday,ftgpio010" }, - { } -}; - -U_BOOT_DRIVER(ftgpio010) = { - .name = "ftgpio010", - .id = UCLASS_GPIO, - .of_match = ftgpio010_ids, - .ops = &ftgpio010_ops, - .of_to_plat = ftgpio010_of_to_plat, - .plat_auto = sizeof(struct ftgpio010_plat), - .probe = ftgpio010_probe, -}; diff --git a/drivers/net/ti/am65-cpsw-nuss.c b/drivers/net/ti/am65-cpsw-nuss.c index 2aa7e5e3a30..7a88f76fd09 100644 --- a/drivers/net/ti/am65-cpsw-nuss.c +++ b/drivers/net/ti/am65-cpsw-nuss.c @@ -234,14 +234,11 @@ out: #define AM65_GMII_SEL_MODE_RGMII 2 #define AM65_GMII_SEL_MODE_SGMII 3 -#define AM65_GMII_SEL_RGMII_IDMODE BIT(4) - static int am65_cpsw_gmii_sel_k3(struct am65_cpsw_priv *priv, phy_interface_t phy_mode) { struct udevice *dev = priv->dev; u32 offset, reg, phandle; - bool rgmii_id = false; fdt_addr_t gmii_sel; u32 mode = 0; ofnode node; @@ -278,12 +275,6 @@ static int am65_cpsw_gmii_sel_k3(struct am65_cpsw_priv *priv, mode = AM65_GMII_SEL_MODE_RGMII; break; - case PHY_INTERFACE_MODE_RGMII_ID: - case PHY_INTERFACE_MODE_RGMII_TXID: - mode = AM65_GMII_SEL_MODE_RGMII; - rgmii_id = true; - break; - case PHY_INTERFACE_MODE_SGMII: mode = AM65_GMII_SEL_MODE_SGMII; break; @@ -298,9 +289,6 @@ static int am65_cpsw_gmii_sel_k3(struct am65_cpsw_priv *priv, break; }; - if (rgmii_id) - mode |= AM65_GMII_SEL_RGMII_IDMODE; - reg = mode; dev_dbg(dev, "gmii_sel PHY mode: %u, new gmii_sel: %08x\n", phy_mode, reg); @@ -630,7 +618,7 @@ static int am65_cpsw_phy_init(struct udevice *dev) u32 supported = PHY_GBIT_FEATURES; int ret = 0; - phydev = dm_eth_phy_connect(dev); + phydev = dm_eth_phy_connect_interface(dev, pdata->phy_interface); if (!phydev) { dev_err(dev, "phy_connect() failed\n"); return -ENODEV; @@ -657,9 +645,28 @@ static int am65_cpsw_ofdata_parse_phy(struct udevice *dev) dev_read_u32(dev, "reg", &priv->port_id); pdata->phy_interface = dev_read_phy_mode(dev); - if (pdata->phy_interface == PHY_INTERFACE_MODE_NA) { + + /* CPSW controllers supported by this driver have a fixed internal TX + * delay in RGMII mode. Fix up PHY mode to account for this and warn + * about Device Trees that claim to have a TX delay on the PCB. + */ + switch (pdata->phy_interface) { + case PHY_INTERFACE_MODE_RGMII_ID: + pdata->phy_interface = PHY_INTERFACE_MODE_RGMII_RXID; + break; + case PHY_INTERFACE_MODE_RGMII_TXID: + pdata->phy_interface = PHY_INTERFACE_MODE_RGMII; + break; + case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_RXID: + dev_warn(dev, + "RGMII mode without internal TX delay unsupported; please fix your Device Tree\n"); + break; + case PHY_INTERFACE_MODE_NA: dev_err(dev, "Invalid PHY mode, port %u\n", priv->port_id); return -EINVAL; + default: + break; } dev_read_u32(dev, "max-speed", (u32 *)&pdata->max_speed); diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig index 5cac1dcf2be..f9511503b02 100644 --- a/drivers/timer/Kconfig +++ b/drivers/timer/Kconfig @@ -312,7 +312,7 @@ config MTK_TIMER config MCHP_PIT64B_TIMER bool "Microchip 64-bit periodic interval timer support" - depends on TIMER + depends on TIMER && ARCH_AT91 help Select this to enable support for Microchip 64-bit periodic interval timer. |