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-rw-r--r--drivers/clk/altera/clk-n5x.c4
-rw-r--r--drivers/clk/clk_scmi.c4
-rw-r--r--drivers/clk/stm32/clk-stm32h7.c4
-rw-r--r--drivers/ddr/altera/sdram_n5x.c8
-rw-r--r--drivers/fpga/socfpga_gen5.c25
-rw-r--r--drivers/misc/socfpga_dtreg.c5
-rw-r--r--drivers/power/domain/Kconfig8
-rw-r--r--drivers/power/domain/Makefile1
-rw-r--r--drivers/power/domain/altr-pmgr-agilex5.c112
-rw-r--r--drivers/pwm/pwm-stm32.c11
-rw-r--r--drivers/reset/stm32/Kconfig2
-rw-r--r--drivers/reset/stm32/stm32-reset-core.c2
-rw-r--r--drivers/reset/stm32/stm32-reset-mp1.c2
-rw-r--r--drivers/reset/stm32/stm32-reset-mp25.c2
-rw-r--r--drivers/reset/stm32/stm32-reset.c4
15 files changed, 155 insertions, 39 deletions
diff --git a/drivers/clk/altera/clk-n5x.c b/drivers/clk/altera/clk-n5x.c
index 09db250ab6d..9e4e7a1d908 100644
--- a/drivers/clk/altera/clk-n5x.c
+++ b/drivers/clk/altera/clk-n5x.c
@@ -386,8 +386,8 @@ static u32 clk_get_emac_clk_hz(struct socfpga_clk_plat *plat, u32 emac_id)
} else {
clock /= 1 + ((CM_REG_READL(plat,
CLKMGR_PERPLL_PLLOUTDIV) &
- CLKMGR_PLLOUTDIV_C3CNT_MASK >>
- CLKMGR_PLLOUTDIV_C3CNT_OFFSET));
+ CLKMGR_PLLOUTDIV_C3CNT_MASK) >>
+ CLKMGR_PLLOUTDIV_C3CNT_OFFSET);
}
break;
diff --git a/drivers/clk/clk_scmi.c b/drivers/clk/clk_scmi.c
index cfb372e6190..0c9a81cabcc 100644
--- a/drivers/clk/clk_scmi.c
+++ b/drivers/clk/clk_scmi.c
@@ -336,8 +336,8 @@ static int scmi_clk_probe(struct udevice *dev)
static int __scmi_clk_set_parent(struct clk *clk, struct clk *parent)
{
struct scmi_clk_parent_set_in in = {
- .clock_id = clk->id,
- .parent_clk = parent->id,
+ .clock_id = clk_get_id(clk),
+ .parent_clk = clk_get_id(parent),
};
struct scmi_clk_parent_set_out out;
struct scmi_msg msg = SCMI_MSG_IN(SCMI_PROTOCOL_ID_CLOCK,
diff --git a/drivers/clk/stm32/clk-stm32h7.c b/drivers/clk/stm32/clk-stm32h7.c
index aa3be414a29..df82db69738 100644
--- a/drivers/clk/stm32/clk-stm32h7.c
+++ b/drivers/clk/stm32/clk-stm32h7.c
@@ -549,8 +549,8 @@ static u32 stm32_get_PLL1_rate(struct stm32_rcc_regs *regs,
divr1 = readl(&regs->pll1divr) & RCC_PLL1DIVR_DIVR1_MASK;
divr1 = (divr1 >> RCC_PLL1DIVR_DIVR1_SHIFT) + 1;
- fracn1 = readl(&regs->pll1fracr) & RCC_PLL1DIVR_DIVR1_MASK;
- fracn1 = fracn1 & RCC_PLL1DIVR_DIVR1_SHIFT;
+ fracn1 = readl(&regs->pll1fracr) & RCC_PLL1FRACR_FRACN1_MASK;
+ fracn1 = (fracn1 >> RCC_PLL1FRACR_FRACN1_SHIFT) + 1;
vco = (pllsrc / divm1) * divn1;
rate = (pllsrc * fracn1) / (divm1 * 8192);
diff --git a/drivers/ddr/altera/sdram_n5x.c b/drivers/ddr/altera/sdram_n5x.c
index d1fc93b6bdd..17ec6afa82b 100644
--- a/drivers/ddr/altera/sdram_n5x.c
+++ b/drivers/ddr/altera/sdram_n5x.c
@@ -346,25 +346,25 @@ struct ddr_handoff {
phys_addr_t cntlr_base;
size_t cntlr_total_length;
enum ddr_type cntlr_t;
- size_t cntlr_handoff_length;
+ int cntlr_handoff_length;
/* Second controller attributes*/
phys_addr_t cntlr2_handoff_base;
phys_addr_t cntlr2_base;
size_t cntlr2_total_length;
enum ddr_type cntlr2_t;
- size_t cntlr2_handoff_length;
+ int cntlr2_handoff_length;
/* PHY attributes */
phys_addr_t phy_handoff_base;
phys_addr_t phy_base;
size_t phy_total_length;
- size_t phy_handoff_length;
+ int phy_handoff_length;
/* PHY engine attributes */
phys_addr_t phy_engine_handoff_base;
size_t phy_engine_total_length;
- size_t phy_engine_handoff_length;
+ int phy_engine_handoff_length;
/* Calibration attributes */
phys_addr_t train_imem_base;
diff --git a/drivers/fpga/socfpga_gen5.c b/drivers/fpga/socfpga_gen5.c
index 9473f057328..964a5cc8789 100644
--- a/drivers/fpga/socfpga_gen5.c
+++ b/drivers/fpga/socfpga_gen5.c
@@ -119,27 +119,14 @@ static int fpgamgr_program_poll_cd(void)
{
const uint32_t mask = FPGAMGRREGS_MON_GPIO_EXT_PORTA_NS_MASK |
FPGAMGRREGS_MON_GPIO_EXT_PORTA_CD_MASK;
- unsigned long reg, i;
+ unsigned long reg;
- /* (3) wait until full config done */
- for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
- reg = readl(&fpgamgr_regs->gpio_ext_porta);
-
- /* Config error */
- if (!(reg & mask)) {
- printf("FPGA: Configuration error.\n");
- return -3;
- }
-
- /* Config done without error */
- if (reg & mask)
- break;
- }
+ reg = readl(&fpgamgr_regs->gpio_ext_porta);
- /* Timeout happened, return error */
- if (i == FPGA_TIMEOUT_CNT) {
- printf("FPGA: Timeout waiting for program.\n");
- return -4;
+ /* Config error */
+ if (!(reg & mask)) {
+ printf("FPGA: Configuration error.\n");
+ return -3;
}
/* Disable AXI configuration */
diff --git a/drivers/misc/socfpga_dtreg.c b/drivers/misc/socfpga_dtreg.c
index ea5d0bcdf51..dd6809433e3 100644
--- a/drivers/misc/socfpga_dtreg.c
+++ b/drivers/misc/socfpga_dtreg.c
@@ -76,16 +76,15 @@ static int socfpga_dtreg_probe(struct udevice *dev)
return -EINVAL;
}
+ reg = base + offset;
+
if (mask != 0) {
if (mask == 0xffffffff) {
- reg = base + offset;
writel(val, (uintptr_t)reg);
} else {
/* Mask the value with the masking bits */
set_mask = val & mask;
- reg = base + offset;
-
/* Clears and sets specific bits in the register */
clrsetbits_le32((uintptr_t)reg, mask, set_mask);
}
diff --git a/drivers/power/domain/Kconfig b/drivers/power/domain/Kconfig
index 5f5218bd8b5..ebf5d828cb0 100644
--- a/drivers/power/domain/Kconfig
+++ b/drivers/power/domain/Kconfig
@@ -18,6 +18,14 @@ config APPLE_PMGR_POWER_DOMAIN
This driver is needed to power on parts of the SoC that have
not been powered on by previous boot stages.
+config AGILEX5_PMGR_POWER_DOMAIN
+ bool "Enable the Agilex5 PMGR power domain driver"
+ depends on SPL_POWER_DOMAIN
+ help
+ Enable support for power gating peripherals' SRAM specified in
+ the handoff data values obtained from the bitstream to reduce
+ power consumption.
+
config BCM6328_POWER_DOMAIN
bool "Enable the BCM6328 power domain driver"
depends on POWER_DOMAIN && ARCH_BMIPS
diff --git a/drivers/power/domain/Makefile b/drivers/power/domain/Makefile
index 4d20c97d26c..8e03f620437 100644
--- a/drivers/power/domain/Makefile
+++ b/drivers/power/domain/Makefile
@@ -5,6 +5,7 @@
obj-$(CONFIG_$(PHASE_)POWER_DOMAIN) += power-domain-uclass.o
obj-$(CONFIG_APPLE_PMGR_POWER_DOMAIN) += apple-pmgr.o
+obj-$(CONFIG_AGILEX5_PMGR_POWER_DOMAIN) += altr-pmgr-agilex5.o
obj-$(CONFIG_BCM6328_POWER_DOMAIN) += bcm6328-power-domain.o
obj-$(CONFIG_IMX8_POWER_DOMAIN) += imx8-power-domain-legacy.o imx8-power-domain.o
obj-$(CONFIG_IMX8M_POWER_DOMAIN) += imx8m-power-domain.o
diff --git a/drivers/power/domain/altr-pmgr-agilex5.c b/drivers/power/domain/altr-pmgr-agilex5.c
new file mode 100644
index 00000000000..257e8b234fd
--- /dev/null
+++ b/drivers/power/domain/altr-pmgr-agilex5.c
@@ -0,0 +1,112 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2025 Altera Corporation <www.altera.com>
+ */
+
+#include <dm.h>
+#include <power-domain-uclass.h>
+#include <asm/io.h>
+#include <asm/arch/handoff_soc64.h>
+#include <linux/bitfield.h>
+#include <linux/delay.h>
+#include <linux/errno.h>
+#include <time.h>
+
+#define PSS_FWENCTL 0x44
+#define PSS_PGENCTL 0x48
+#define PSS_PGSTAT 0x4c
+
+#define DATA_MASK GENMASK(7, 0)
+#define TIMEOUT_MS 1000
+
+static int wait_verify_fsm(u16 timeout_ms, uintptr_t base_addr, u32 peripheral_handoff)
+{
+ u32 data = 0;
+ u32 pgstat = 0;
+ ulong start = get_timer(0);
+
+ /* Wait FSM ready */
+ do {
+ data = FIELD_GET(DATA_MASK, readl(base_addr + PSS_PGSTAT));
+ if (data != 0)
+ break;
+ } while (get_timer(start) < timeout_ms);
+
+ if (get_timer(start) >= timeout_ms)
+ return -ETIMEDOUT;
+
+ /* Verify PSS SRAM power gated */
+ pgstat = FIELD_GET(DATA_MASK, readl(base_addr + PSS_PGSTAT));
+ if (pgstat != FIELD_GET(DATA_MASK, peripheral_handoff))
+ return -EPERM;
+
+ return 0;
+}
+
+static int pss_sram_power_off(uintptr_t base_addr, u32 *handoff_table)
+{
+ u32 peripheral_handoff;
+
+ /* Get PSS SRAM handoff data */
+ peripheral_handoff = handoff_table[0];
+
+ /* Enable firewall for PSS SRAM */
+ setbits_le32(base_addr + PSS_FWENCTL, peripheral_handoff);
+
+ /* Wait */
+ udelay(1);
+
+ /* Power gating PSS SRAM */
+ setbits_le32(base_addr + PSS_PGENCTL, peripheral_handoff);
+
+ return wait_verify_fsm(TIMEOUT_MS, base_addr, peripheral_handoff);
+}
+
+static int altera_pmgr_off(struct power_domain *power_domain)
+{
+ fdt_addr_t base_addr = dev_read_addr(power_domain->dev);
+ u32 handoff_table[SOC64_HANDOFF_PERI_LEN];
+ int ret;
+
+ /* Read handoff data for peripherals configuration */
+ ret = socfpga_handoff_read((void *)SOC64_HANDOFF_PERI, handoff_table,
+ SOC64_HANDOFF_PERI_LEN);
+ if (ret) {
+ debug("%s: handoff data read failed. ret: %d\n", __func__, ret);
+ return ret;
+ }
+
+ pss_sram_power_off(base_addr, handoff_table);
+
+ return 0;
+}
+
+static int altera_pmgr_probe(struct udevice *dev)
+{
+ struct power_domain *power_domain = dev_get_priv(dev);
+
+ if (!power_domain)
+ return -EINVAL;
+
+ power_domain->dev = dev;
+
+ return altera_pmgr_off(power_domain);
+}
+
+static const struct udevice_id altera_pmgr_ids[] = {
+ { .compatible = "altr,pmgr-agilex5" },
+ { /* sentinel */ }
+};
+
+static struct power_domain_ops altera_pmgr_ops = {
+ .off = altera_pmgr_off,
+};
+
+U_BOOT_DRIVER(altr_pmgr) = {
+ .name = "altr_pmgr",
+ .id = UCLASS_POWER_DOMAIN,
+ .of_match = altera_pmgr_ids,
+ .ops = &altera_pmgr_ops,
+ .probe = altera_pmgr_probe,
+ .priv_auto = sizeof(struct power_domain),
+};
diff --git a/drivers/pwm/pwm-stm32.c b/drivers/pwm/pwm-stm32.c
index 5fa649b5903..a691f75e4a7 100644
--- a/drivers/pwm/pwm-stm32.c
+++ b/drivers/pwm/pwm-stm32.c
@@ -12,6 +12,7 @@
#include <asm/io.h>
#include <asm/arch/timers.h>
#include <dm/device_compat.h>
+#include <linux/bitfield.h>
#include <linux/time.h>
#define CCMR_CHANNEL_SHIFT 8
@@ -157,7 +158,14 @@ static void stm32_pwm_detect_complementary(struct udevice *dev)
{
struct stm32_timers_plat *plat = dev_get_plat(dev_get_parent(dev));
struct stm32_pwm_priv *priv = dev_get_priv(dev);
- u32 ccer;
+ u32 ccer, val;
+
+ if (plat->ipidr) {
+ /* Simply read from HWCFGR the number of complementary outputs (MP25). */
+ val = readl(plat->base + TIM_HWCFGR1);
+ priv->have_complementary_output = !!FIELD_GET(TIM_HWCFGR1_NB_OF_DT, val);
+ return;
+ }
/*
* If complementary bit doesn't exist writing 1 will have no
@@ -192,6 +200,7 @@ static const struct pwm_ops stm32_pwm_ops = {
static const struct udevice_id stm32_pwm_ids[] = {
{ .compatible = "st,stm32-pwm" },
+ { .compatible = "st,stm32mp25-pwm" },
{ }
};
diff --git a/drivers/reset/stm32/Kconfig b/drivers/reset/stm32/Kconfig
index 39dcfa0a9ca..fdd88a6bfae 100644
--- a/drivers/reset/stm32/Kconfig
+++ b/drivers/reset/stm32/Kconfig
@@ -16,7 +16,7 @@ config RESET_STM32MP1
config RESET_STM32MP25
bool "Enable the STM32MP25 reset"
- depends on STM32MP25X
+ depends on STM32MP23X || STM32MP25X
default y
help
Support for reset controllers on STMicroelectronics STM32MP2 family SoCs.
diff --git a/drivers/reset/stm32/stm32-reset-core.c b/drivers/reset/stm32/stm32-reset-core.c
index 7dd92e07e1a..9eeed6536e0 100644
--- a/drivers/reset/stm32/stm32-reset-core.c
+++ b/drivers/reset/stm32/stm32-reset-core.c
@@ -6,7 +6,7 @@
#include <dm.h>
#include <reset-uclass.h>
-#include <stm32-reset-core.h>
+#include "stm32-reset-core.h"
#include <stm32_rcc.h>
#include <dm/device_compat.h>
#include <linux/iopoll.h>
diff --git a/drivers/reset/stm32/stm32-reset-mp1.c b/drivers/reset/stm32/stm32-reset-mp1.c
index 6863f6e64b7..ce4532561e5 100644
--- a/drivers/reset/stm32/stm32-reset-mp1.c
+++ b/drivers/reset/stm32/stm32-reset-mp1.c
@@ -5,7 +5,7 @@
*/
#include <dm.h>
-#include <stm32-reset-core.h>
+#include "stm32-reset-core.h"
/* Reset clear offset for STM32MP RCC */
#define RCC_CLR_OFFSET 0x4
diff --git a/drivers/reset/stm32/stm32-reset-mp25.c b/drivers/reset/stm32/stm32-reset-mp25.c
index 91c0336bc58..1cbe5c7f3d5 100644
--- a/drivers/reset/stm32/stm32-reset-mp25.c
+++ b/drivers/reset/stm32/stm32-reset-mp25.c
@@ -5,7 +5,7 @@
*/
#include <dm.h>
-#include <stm32-reset-core.h>
+#include "stm32-reset-core.h"
#include <stm32mp25_rcc.h>
#include <dt-bindings/reset/st,stm32mp25-rcc.h>
diff --git a/drivers/reset/stm32/stm32-reset.c b/drivers/reset/stm32/stm32-reset.c
index 975f67f712a..024f15cb25e 100644
--- a/drivers/reset/stm32/stm32-reset.c
+++ b/drivers/reset/stm32/stm32-reset.c
@@ -5,7 +5,7 @@
*/
#include <dm.h>
-#include <stm32-reset-core.h>
+#include "stm32-reset-core.h"
/* Timeout for deassert */
#define STM32_DEASSERT_TIMEOUT_US 10000
@@ -19,7 +19,7 @@ static const struct stm32_reset_cfg *stm32_get_reset_line(struct reset_ctl *rese
ptr_line->offset = bank;
ptr_line->bit_idx = offset;
- ptr_line->set_clr = true;
+ ptr_line->set_clr = false;
return ptr_line;
}
generated by cgit v1.2.3 (git 2.0.4) at 2025-08-01 16:29:05 +0000