summaryrefslogtreecommitdiff
path: root/drivers
diff options
context:
space:
mode:
Diffstat (limited to 'drivers')
-rw-r--r--drivers/adc/Kconfig4
-rw-r--r--drivers/ata/Kconfig3
-rw-r--r--drivers/block/sandbox.c8
-rw-r--r--drivers/crypto/Kconfig2
-rw-r--r--drivers/crypto/Makefile1
-rw-r--r--drivers/crypto/aes/Kconfig12
-rw-r--r--drivers/crypto/aes/Makefile4
-rw-r--r--drivers/crypto/aes/aes-sw.c167
-rw-r--r--drivers/crypto/aes/aes-uclass.c192
-rw-r--r--drivers/crypto/aspeed/Kconfig4
-rw-r--r--drivers/crypto/fsl/Kconfig4
-rw-r--r--drivers/crypto/hash/Kconfig2
-rw-r--r--drivers/crypto/nuvoton/Kconfig1
-rw-r--r--drivers/dma/Kconfig1
-rw-r--r--drivers/gpio/Kconfig40
-rw-r--r--drivers/i2c/Kconfig1
-rw-r--r--drivers/misc/Kconfig2
-rw-r--r--drivers/net/phy/micrel_ksz90x1.c12
-rw-r--r--drivers/net/sh_eth.c183
-rw-r--r--drivers/net/sh_eth.h28
-rw-r--r--drivers/net/ti/icssg_prueth.c54
-rw-r--r--drivers/net/ti/icssg_prueth.h7
-rw-r--r--drivers/nvme/nvme.c6
-rw-r--r--drivers/serial/Kconfig2
-rw-r--r--drivers/w1/Kconfig2
-rw-r--r--drivers/watchdog/Kconfig2
26 files changed, 555 insertions, 189 deletions
diff --git a/drivers/adc/Kconfig b/drivers/adc/Kconfig
index 37235f557a3..2b45f9e5eba 100644
--- a/drivers/adc/Kconfig
+++ b/drivers/adc/Kconfig
@@ -18,7 +18,7 @@ config SPL_ADC
config ADC_EXYNOS
bool "Enable Exynos 54xx ADC driver"
- depends on ADC
+ depends on ADC && ARCH_EXYNOS5
help
This enables basic driver for Exynos ADC compatible with Exynos54xx.
It provides:
@@ -49,7 +49,7 @@ config SARADC_MESON
config SARADC_ROCKCHIP
bool "Enable Rockchip SARADC driver"
- depends on ADC
+ depends on ADC && ARCH_ROCKCHIP
help
This enables driver for Rockchip SARADC.
It provides:
diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig
index 29ceab849c0..da9c72a99d0 100644
--- a/drivers/ata/Kconfig
+++ b/drivers/ata/Kconfig
@@ -131,6 +131,7 @@ config FSL_SATA_V2
config SATA_MV
bool "Enable Marvell SATA controller driver support"
+ depends on ARCH_KIRKWOOD || ARCH_MVEBU
select AHCI
select LIBATA
help
@@ -148,7 +149,7 @@ config SATA_SIL
config SYS_SATA_MAX_DEVICE
int "Maximum number of SATA devices"
- depends on !AHCI || FSL_SATA || SATA_MV
+ depends on !AHCI || FSL_SATA || SATA_MV || API
help
Sets the maximum number of SATA devices which can be supported
by U-Boot.
diff --git a/drivers/block/sandbox.c b/drivers/block/sandbox.c
index 6c74d66037e..9cb27561a97 100644
--- a/drivers/block/sandbox.c
+++ b/drivers/block/sandbox.c
@@ -18,7 +18,7 @@
DECLARE_GLOBAL_DATA_PTR;
static unsigned long host_block_read(struct udevice *dev,
- unsigned long start, lbaint_t blkcnt,
+ lbaint_t start, lbaint_t blkcnt,
void *buffer)
{
struct blk_desc *desc = dev_get_uclass_plat(dev);
@@ -26,7 +26,7 @@ static unsigned long host_block_read(struct udevice *dev,
struct host_sb_plat *plat = dev_get_plat(host_dev);
if (os_lseek(plat->fd, start * desc->blksz, OS_SEEK_SET) < 0) {
- printf("ERROR: Invalid block %lx\n", start);
+ printf("ERROR: Invalid block " LBAF "\n", start);
return -1;
}
ssize_t len = os_read(plat->fd, buffer, blkcnt * desc->blksz);
@@ -37,7 +37,7 @@ static unsigned long host_block_read(struct udevice *dev,
}
static unsigned long host_block_write(struct udevice *dev,
- unsigned long start, lbaint_t blkcnt,
+ lbaint_t start, lbaint_t blkcnt,
const void *buffer)
{
struct blk_desc *desc = dev_get_uclass_plat(dev);
@@ -45,7 +45,7 @@ static unsigned long host_block_write(struct udevice *dev,
struct host_sb_plat *plat = dev_get_plat(host_dev);
if (os_lseek(plat->fd, start * desc->blksz, OS_SEEK_SET) < 0) {
- printf("ERROR: Invalid block %lx\n", start);
+ printf("ERROR: Invalid block " LBAF "\n", start);
return -1;
}
ssize_t len = os_write(plat->fd, buffer, blkcnt * desc->blksz);
diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig
index 8b49997030b..d26f87364f9 100644
--- a/drivers/crypto/Kconfig
+++ b/drivers/crypto/Kconfig
@@ -2,6 +2,8 @@ menu "Hardware crypto devices"
source "drivers/crypto/hash/Kconfig"
+source "drivers/crypto/aes/Kconfig"
+
source "drivers/crypto/fsl/Kconfig"
source "drivers/crypto/aspeed/Kconfig"
diff --git a/drivers/crypto/Makefile b/drivers/crypto/Makefile
index b9105186097..2bd99fc2763 100644
--- a/drivers/crypto/Makefile
+++ b/drivers/crypto/Makefile
@@ -4,6 +4,7 @@
# http://www.samsung.com
obj-$(CONFIG_EXYNOS_ACE_SHA) += ace_sha.o
+obj-y += aes/
obj-y += rsa_mod_exp/
obj-y += fsl/
obj-y += hash/
diff --git a/drivers/crypto/aes/Kconfig b/drivers/crypto/aes/Kconfig
new file mode 100644
index 00000000000..7e1b1b2875d
--- /dev/null
+++ b/drivers/crypto/aes/Kconfig
@@ -0,0 +1,12 @@
+config DM_AES
+ bool "Enable Driver Model for AES crypto operations"
+ depends on DM
+ help
+ If you want to use driver model for AES crypto operations, say Y.
+
+config AES_SOFTWARE
+ bool "Enable driver for AES in software"
+ depends on DM_AES && AES
+ help
+ Enable driver for AES crypto operations in software. Uses U-Boot
+ AES library.
diff --git a/drivers/crypto/aes/Makefile b/drivers/crypto/aes/Makefile
new file mode 100644
index 00000000000..d38a2e1526d
--- /dev/null
+++ b/drivers/crypto/aes/Makefile
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0+
+
+obj-$(CONFIG_$(PHASE_)DM_AES) += aes-uclass.o
+obj-$(CONFIG_$(PHASE_)AES_SOFTWARE) += aes-sw.o
diff --git a/drivers/crypto/aes/aes-sw.c b/drivers/crypto/aes/aes-sw.c
new file mode 100644
index 00000000000..a65200fb79b
--- /dev/null
+++ b/drivers/crypto/aes/aes-sw.c
@@ -0,0 +1,167 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include <config.h>
+#include <dm.h>
+#include <log.h>
+#include <malloc.h>
+#include <uboot_aes.h>
+
+#define SW_KEY_SLOTS 2
+
+struct sw_aes_priv {
+ u8 key_slots[SW_KEY_SLOTS][AES256_KEY_LENGTH];
+ u8 key_schedule[AES256_EXPAND_KEY_LENGTH];
+ u8 selected_slot;
+ u32 selected_key_size;
+ bool key_expanded;
+};
+
+static int prepare_aes(struct sw_aes_priv *priv)
+{
+ if (!priv->selected_key_size) {
+ log_debug("%s: AES key size not set, setup a slot first\n", __func__);
+ return 1;
+ }
+
+ if (priv->key_expanded)
+ return 0;
+
+ priv->key_expanded = 1;
+
+ aes_expand_key(priv->key_slots[priv->selected_slot], priv->selected_key_size,
+ priv->key_schedule);
+
+ return 0;
+}
+
+static int sw_aes_ops_available_key_slots(struct udevice *dev)
+{
+ return SW_KEY_SLOTS;
+}
+
+static int sw_aes_ops_select_key_slot(struct udevice *dev, u32 key_size, u8 slot)
+{
+ struct sw_aes_priv *priv = dev_get_priv(dev);
+
+ if (slot >= SW_KEY_SLOTS)
+ return 1;
+
+ priv->selected_slot = slot;
+ priv->selected_key_size = key_size;
+ priv->key_expanded = 0;
+
+ return 0;
+}
+
+static int sw_aes_ops_set_key_for_key_slot(struct udevice *dev, u32 key_size,
+ u8 *key, u8 slot)
+{
+ struct sw_aes_priv *priv = dev_get_priv(dev);
+
+ if (slot >= SW_KEY_SLOTS)
+ return 1;
+
+ memcpy(priv->key_slots[slot], key, key_size / 8);
+
+ if (priv->selected_slot == slot)
+ priv->selected_key_size = key_size;
+
+ priv->key_expanded = 0;
+
+ return 0;
+}
+
+static int sw_aes_ops_aes_ecb_encrypt(struct udevice *dev, u8 *src, u8 *dst,
+ u32 num_aes_blocks)
+{
+ struct sw_aes_priv *priv = dev_get_priv(dev);
+ int ret;
+
+ ret = prepare_aes(priv);
+ if (ret)
+ return ret;
+
+ while (num_aes_blocks > 0) {
+ aes_encrypt(priv->selected_key_size, src, priv->key_schedule, dst);
+ num_aes_blocks -= 1;
+ src += AES_BLOCK_LENGTH;
+ dst += AES_BLOCK_LENGTH;
+ }
+
+ return 0;
+}
+
+static int sw_aes_ops_aes_ecb_decrypt(struct udevice *dev, u8 *src, u8 *dst,
+ u32 num_aes_blocks)
+{
+ struct sw_aes_priv *priv = dev_get_priv(dev);
+ int ret;
+
+ ret = prepare_aes(priv);
+ if (ret)
+ return ret;
+
+ while (num_aes_blocks > 0) {
+ aes_decrypt(priv->selected_key_size, src, priv->key_schedule, dst);
+ num_aes_blocks -= 1;
+ src += AES_BLOCK_LENGTH;
+ dst += AES_BLOCK_LENGTH;
+ }
+
+ return 0;
+}
+
+static int sw_aes_ops_aes_cbc_encrypt(struct udevice *dev, u8 *iv, u8 *src,
+ u8 *dst, u32 num_aes_blocks)
+{
+ struct sw_aes_priv *priv = dev_get_priv(dev);
+ int ret;
+
+ ret = prepare_aes(priv);
+ if (ret)
+ return ret;
+
+ aes_cbc_encrypt_blocks(priv->selected_key_size, priv->key_schedule, iv,
+ src, dst, num_aes_blocks);
+
+ return 0;
+}
+
+static int sw_aes_ops_aes_cbc_decrypt(struct udevice *dev, u8 *iv, u8 *src,
+ u8 *dst, u32 num_aes_blocks)
+{
+ struct sw_aes_priv *priv = dev_get_priv(dev);
+ int ret;
+
+ ret = prepare_aes(priv);
+ if (ret)
+ return ret;
+
+ aes_cbc_decrypt_blocks(priv->selected_key_size, priv->key_schedule,
+ iv, src, dst, num_aes_blocks);
+
+ return 0;
+}
+
+static const struct aes_ops aes_ops_sw = {
+ .available_key_slots = sw_aes_ops_available_key_slots,
+ .select_key_slot = sw_aes_ops_select_key_slot,
+ .set_key_for_key_slot = sw_aes_ops_set_key_for_key_slot,
+ .aes_ecb_encrypt = sw_aes_ops_aes_ecb_encrypt,
+ .aes_ecb_decrypt = sw_aes_ops_aes_ecb_decrypt,
+ .aes_cbc_encrypt = sw_aes_ops_aes_cbc_encrypt,
+ .aes_cbc_decrypt = sw_aes_ops_aes_cbc_decrypt,
+};
+
+static const struct udevice_id sw_aes_ids[] = {
+ { .compatible = "software-aes-engine" },
+ { }
+};
+
+U_BOOT_DRIVER(aes_sw) = {
+ .name = "aes_sw",
+ .id = UCLASS_AES,
+ .of_match = sw_aes_ids,
+ .ops = &aes_ops_sw,
+ .priv_auto = sizeof(struct sw_aes_priv),
+};
diff --git a/drivers/crypto/aes/aes-uclass.c b/drivers/crypto/aes/aes-uclass.c
new file mode 100644
index 00000000000..745c6ce57a9
--- /dev/null
+++ b/drivers/crypto/aes/aes-uclass.c
@@ -0,0 +1,192 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#define LOG_CATEGORY UCLASS_AES
+
+#include <dm.h>
+#include <malloc.h>
+#include <log.h>
+#include <uboot_aes.h>
+#include <linux/string.h>
+
+int dm_aes_get_available_key_slots(struct udevice *dev)
+{
+ const struct aes_ops *ops;
+
+ if (!dev)
+ return -ENODEV;
+
+ ops = aes_get_ops(dev);
+
+ if (!ops->available_key_slots)
+ return -ENOSYS;
+
+ return ops->available_key_slots(dev);
+}
+
+int dm_aes_select_key_slot(struct udevice *dev, u32 key_size, u8 slot)
+{
+ const struct aes_ops *ops;
+
+ if (!dev)
+ return -ENODEV;
+
+ ops = aes_get_ops(dev);
+
+ if (!ops->select_key_slot)
+ return -ENOSYS;
+
+ return ops->select_key_slot(dev, key_size, slot);
+}
+
+int dm_aes_set_key_for_key_slot(struct udevice *dev, u32 key_size, u8 *key, u8 slot)
+{
+ const struct aes_ops *ops;
+
+ if (!dev)
+ return -ENODEV;
+
+ ops = aes_get_ops(dev);
+
+ if (!ops->set_key_for_key_slot)
+ return -ENOSYS;
+
+ return ops->set_key_for_key_slot(dev, key_size, key, slot);
+}
+
+int dm_aes_ecb_encrypt(struct udevice *dev, u8 *src, u8 *dst, u32 num_aes_blocks)
+{
+ const struct aes_ops *ops;
+
+ if (!dev)
+ return -ENODEV;
+
+ ops = aes_get_ops(dev);
+
+ if (!ops->aes_ecb_encrypt)
+ return -ENOSYS;
+
+ return ops->aes_ecb_encrypt(dev, src, dst, num_aes_blocks);
+}
+
+int dm_aes_ecb_decrypt(struct udevice *dev, u8 *src, u8 *dst, u32 num_aes_blocks)
+{
+ const struct aes_ops *ops;
+
+ if (!dev)
+ return -ENODEV;
+
+ ops = aes_get_ops(dev);
+
+ if (!ops->aes_ecb_decrypt)
+ return -ENOSYS;
+
+ return ops->aes_ecb_decrypt(dev, src, dst, num_aes_blocks);
+}
+
+int dm_aes_cbc_encrypt(struct udevice *dev, u8 *iv, u8 *src, u8 *dst, u32 num_aes_blocks)
+{
+ const struct aes_ops *ops;
+
+ if (!dev)
+ return -ENODEV;
+
+ ops = aes_get_ops(dev);
+
+ if (!ops->aes_cbc_encrypt)
+ return -ENOSYS;
+
+ return ops->aes_cbc_encrypt(dev, iv, src, dst, num_aes_blocks);
+}
+
+int dm_aes_cbc_decrypt(struct udevice *dev, u8 *iv, u8 *src, u8 *dst, u32 num_aes_blocks)
+{
+ const struct aes_ops *ops;
+
+ if (!dev)
+ return -ENODEV;
+
+ ops = aes_get_ops(dev);
+
+ if (!ops->aes_cbc_decrypt)
+ return -ENOSYS;
+
+ return ops->aes_cbc_decrypt(dev, iv, src, dst, num_aes_blocks);
+}
+
+static void left_shift_vector(u8 *in, u8 *out, int size)
+{
+ int carry = 0;
+ int i;
+
+ for (i = size - 1; i >= 0; i--) {
+ out[i] = (in[i] << 1) | carry;
+ carry = in[i] >> 7; /* get most significant bit */
+ }
+}
+
+int dm_aes_cmac(struct udevice *dev, u8 *src, u8 *dst, u32 num_aes_blocks)
+{
+ const u8 AES_CMAC_CONST_RB = 0x87; /* from RFC 4493, Figure 2.2 */
+ const u32 TMP_BUFFER_LEN = 128;
+ u8 tmp_block[AES128_KEY_LENGTH] = { };
+ u8 k1[AES128_KEY_LENGTH];
+ u8 *tmp_buffer;
+ int ret;
+
+ log_debug("%s: 0x%p -> %p blocks %d\n", __func__, src, dst, num_aes_blocks);
+
+ if (!num_aes_blocks) {
+ log_debug("%s: called with 0 blocks!\n", __func__);
+ return -1;
+ }
+
+ /* Compute K1 constant needed by AES-CMAC calculation */
+ ret = dm_aes_cbc_encrypt(dev, (u8 *)AES_ZERO_BLOCK, (u8 *)AES_ZERO_BLOCK, tmp_block, 1);
+ if (ret)
+ return -1;
+
+ left_shift_vector(tmp_block, k1, AES_BLOCK_LENGTH);
+
+ if ((tmp_block[0] >> 7) != 0) /* get MSB of L */
+ k1[AES128_KEY_LENGTH - 1] ^= AES_CMAC_CONST_RB;
+
+ /* Set what will be the initial IV as zero */
+ memset(tmp_block, 0, AES_BLOCK_LENGTH);
+
+ /* Process all blocks except last by calling engine several times per dma buffer size */
+ if (num_aes_blocks > 1) {
+ tmp_buffer = malloc(AES_BLOCK_LENGTH * min(num_aes_blocks - 1, TMP_BUFFER_LEN));
+ while (num_aes_blocks > 1) {
+ u32 blocks = min(num_aes_blocks - 1, TMP_BUFFER_LEN);
+
+ /* Encrypt the current remaining set of blocks that fits in tmp buffer */
+ ret = dm_aes_cbc_encrypt(dev, tmp_block, src, tmp_buffer, blocks);
+ if (ret)
+ return -1;
+
+ num_aes_blocks -= blocks;
+ src += blocks * AES_BLOCK_LENGTH;
+
+ /* Copy the last encrypted block to tmp_block as IV */
+ memcpy(tmp_block, tmp_buffer + ((blocks - 1) * AES_BLOCK_LENGTH),
+ AES_BLOCK_LENGTH);
+ }
+ free(tmp_buffer);
+ }
+
+ if (num_aes_blocks != 1) {
+ log_debug("%s: left with %d blocks! must be 1\n", __func__, num_aes_blocks);
+ return -1;
+ }
+
+ /* XOR last IV with K1 */
+ aes_apply_cbc_chain_data(tmp_block, k1, tmp_block);
+
+ /* Encrypt the last src block already with tmp_block as IV and output to dst */
+ return dm_aes_cbc_encrypt(dev, tmp_block, src, dst, 1);
+}
+
+UCLASS_DRIVER(aes) = {
+ .id = UCLASS_AES,
+ .name = "aes",
+};
diff --git a/drivers/crypto/aspeed/Kconfig b/drivers/crypto/aspeed/Kconfig
index 6efcd7da738..401225b8528 100644
--- a/drivers/crypto/aspeed/Kconfig
+++ b/drivers/crypto/aspeed/Kconfig
@@ -1,3 +1,5 @@
+if ARCH_ASPEED
+
config ASPEED_HACE
bool "ASPEED Hash and Crypto Engine"
depends on DM_HASH
@@ -38,3 +40,5 @@ config ASPEED_CPTRA_ECDSA
Enabling this allows the use of ECDSA384 signature verification in hardware.
Note that only ECDSA384 is supported by Caliptra.
+
+endif
diff --git a/drivers/crypto/fsl/Kconfig b/drivers/crypto/fsl/Kconfig
index 9ed56632fcd..fe694f6022c 100644
--- a/drivers/crypto/fsl/Kconfig
+++ b/drivers/crypto/fsl/Kconfig
@@ -1,3 +1,5 @@
+if ARM || PPC
+
config FSL_CAAM
bool "Freescale Crypto Driver Support"
select SHA_HW_ACCEL
@@ -95,3 +97,5 @@ config FSL_DCP_RNG
module of the DCP. It uses the True Random Number Generator (TRNG)
and a Pseudo-Random Number Generator (PRNG) to achieve a true
randomness and cryptographic strength.
+
+endif
diff --git a/drivers/crypto/hash/Kconfig b/drivers/crypto/hash/Kconfig
index aa355c44be8..72b955ac791 100644
--- a/drivers/crypto/hash/Kconfig
+++ b/drivers/crypto/hash/Kconfig
@@ -18,7 +18,7 @@ config HASH_SOFTWARE
config HASH_ASPEED
bool "Enable Hash with ASPEED hash accelerator"
- depends on DM_HASH
+ depends on DM_HASH && ARCH_ASPEED
select ASPEED_HACE
help
Enable this to support HW-assisted hashing operations using ASPEED Hash
diff --git a/drivers/crypto/nuvoton/Kconfig b/drivers/crypto/nuvoton/Kconfig
index 034fcadfcc8..0eb4396816e 100644
--- a/drivers/crypto/nuvoton/Kconfig
+++ b/drivers/crypto/nuvoton/Kconfig
@@ -1,5 +1,6 @@
config NPCM_AES
bool "Support the NPCM AES algorithm"
+ depends on (ARM && ARCH_NPCM)
select NPCM_OTP
help
This provides a means to encrypt and decrypt data using the NPCM
diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
index e8ef90e2bd6..1fccbc96f07 100644
--- a/drivers/dma/Kconfig
+++ b/drivers/dma/Kconfig
@@ -37,6 +37,7 @@ config BCM6348_IUDMA
config TI_EDMA3
bool "TI EDMA3 driver"
+ depends on ARCH_OMAP2PLUS || ARCH_KEYSTONE
select DMA_LEGACY
help
Enable the TI EDMA3 driver for DRA7xx and AM43xx evms.
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index 5dee00f832e..fd227d46f5a 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -115,7 +115,7 @@ config ALTERA_PIO
config BCM2835_GPIO
bool "BCM2835 GPIO driver"
- depends on DM_GPIO
+ depends on DM_GPIO && ARCH_BCM283X
config BCM6345_GPIO
bool "BCM6345 GPIO driver"
@@ -140,6 +140,7 @@ config DWAPB_GPIO
config AT91_GPIO
bool "AT91 PIO GPIO driver"
+ depends on ARCH_AT91
help
Say yes here to select AT91 PIO GPIO driver. AT91 PIO
controller manages up to 32 fully programmable input/output
@@ -151,7 +152,7 @@ config AT91_GPIO
config ATMEL_PIO4
bool "ATMEL PIO4 driver"
- depends on DM_GPIO
+ depends on DM_GPIO && ARCH_AT91
help
Say yes here to support the Atmel PIO4 driver.
The PIO4 is new version of Atmel PIO controller, which manages
@@ -194,11 +195,11 @@ config FXL6408_GPIO
config HIKEY_GPIO
bool "HI6220 GPIO driver"
- depends on DM_GPIO
+ depends on DM_GPIO && TARGET_HIKEY
config INTEL_BROADWELL_GPIO
bool "Intel Broadwell GPIO driver"
- depends on DM
+ depends on DM_GPIO && X86
help
This driver supports Broadwell U devices which have an expanded
GPIO feature set. The difference is large enough to merit a separate
@@ -207,7 +208,7 @@ config INTEL_BROADWELL_GPIO
config INTEL_GPIO
bool "Intel generic GPIO driver"
- depends on DM_GPIO
+ depends on DM_GPIO && X86
help
Say yes here to select Intel generic GPIO driver. This controller
supports recent chips (e.g. Apollo Lake). It permits basic GPIO
@@ -216,13 +217,13 @@ config INTEL_GPIO
config INTEL_ICH6_GPIO
bool "Intel ICH6 compatible legacy GPIO driver"
- depends on DM_GPIO
+ depends on DM_GPIO && X86
help
Say yes here to select Intel ICH6 compatible legacy GPIO driver.
config IMX_RGPIO2P
bool "i.MX7ULP RGPIO2P driver"
- depends on DM
+ depends on DM && (ARCH_MX7ULP || ARCH_IMX8ULP || ARCH_IMX9)
help
This driver supports i.MX7ULP Rapid GPIO2P controller.
@@ -244,12 +245,13 @@ config HSDK_CREG_GPIO
config KIRKWOOD_GPIO
bool "Kirkwood GPIO driver"
+ depends on ARCH_KIRKWOOD
help
This drdiver supports GPIOs on Kirkwood platforms
config LPC32XX_GPIO
bool "LPC32XX GPIO driver"
- depends on DM
+ depends on DM && ARCH_LPC32XX
help
Support for the LPC32XX GPIO driver.
@@ -296,7 +298,7 @@ config MSCC_SGPIO
config MSM_GPIO
bool "Qualcomm GPIO driver"
- depends on DM_GPIO
+ depends on DM_GPIO && ARCH_SNAPDRAGON
help
Support GPIO controllers on Qualcomm Snapdragon family of SoCs.
This controller have single bank (default name "soc"), every
@@ -309,24 +311,26 @@ config MSM_GPIO
config MXC_GPIO
bool "Freescale/NXP MXC GPIO driver"
+ depends on MACH_IMX
help
Support GPIO controllers on various i.MX platforms
config MXS_GPIO
bool "Freescale/NXP MXS GPIO driver"
+ depends on ARCH_MX23 || ARCH_MX28
help
Support GPIO controllers on i.MX23 and i.MX28 platforms
config NPCM_GPIO
bool "Nuvoton NPCM GPIO driver"
- depends on DM_GPIO
+ depends on DM_GPIO && ARCH_NPCM
help
Support GPIO controllers on Nuvovon NPCM SoCs.
NPCM7xx/NPCM8xx contain 8 GPIO banks, each bank contains 32 pins.
config NPCM_SGPIO
bool "Nuvoton NPCM SGPIO driver"
- depends on DM_GPIO
+ depends on DM_GPIO && ARCH_NPCM
help
Support Nuvoton BMC NPCM7xx/NPCM8xx sgpio driver support.
Nuvoton NPCM SGPIO module is combine serial to parallel IC (HC595)
@@ -380,7 +384,7 @@ config RZA1_GPIO
config ROCKCHIP_GPIO
bool "Rockchip GPIO driver"
- depends on DM_GPIO
+ depends on DM_GPIO && ARCH_ROCKCHIP
help
Support GPIO access on Rockchip SoCs. The GPIOs are arranged into
a number of banks (different for each SoC type) each with 32 GPIOs.
@@ -430,7 +434,7 @@ config XILINX_GPIO
config TEGRA_GPIO
bool "Tegra20..210 GPIO driver"
- depends on DM_GPIO
+ depends on DM_GPIO && ARCH_TEGRA
help
Support for the GPIO controller contained in NVIDIA Tegra20 through
Tegra210.
@@ -451,7 +455,7 @@ config GPIO_UNIPHIER
config VYBRID_GPIO
bool "Vybrid GPIO driver"
- depends on DM
+ depends on DM && MACH_IMX
help
Say yes here to support Vybrid vf610 GPIOs.
@@ -490,7 +494,7 @@ config STM32_GPIO
config SIFIVE_GPIO
bool "SiFive GPIO driver"
- depends on DM_GPIO
+ depends on DM_GPIO && RISCV
help
Device model driver for GPIO controller present in SiFive FU540 SoC. This
driver enables GPIO interface on HiFive Unleashed A00 board.
@@ -577,7 +581,7 @@ config PCA953X
config MPC8XXX_GPIO
bool "Freescale MPC8XXX GPIO driver"
- depends on DM_GPIO
+ depends on DM_GPIO && (PPC || ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3)
help
This driver supports the built-in GPIO controller of MPC8XXX CPUs.
Each GPIO bank is identified by its own entry in the device tree,
@@ -618,7 +622,7 @@ config QE_GPIO
config MPC8XX_GPIO
bool "Freescale MPC8XX GPIO driver"
- depends on DM_GPIO
+ depends on DM_GPIO && PPC
help
This driver supports parallel IO ports from MPC8XX CPUs.
Each GPIO bank is identified by its own entry in the device tree.
@@ -685,7 +689,7 @@ config SL28CPLD_GPIO
config SLG7XL45106_I2C_GPO
bool "slg7xl45106 i2c gpo expander"
- depends on DM_GPIO
+ depends on DM_GPIO && ARCH_ZYNQMP
help
Support for slg7xl45106 i2c gpo expander. It is an i2c based
8-bit gpo expander, all gpo lines are controlled by writing
diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig
index 146bc621c7e..775b2b4e9af 100644
--- a/drivers/i2c/Kconfig
+++ b/drivers/i2c/Kconfig
@@ -615,6 +615,7 @@ endif
config SYS_I2C_SOFT
bool "Legacy software I2C interface"
+ depends on !COMPILE_TEST
help
Enable the legacy software defined I2C interface
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index 8b8f6309ada..515d3668395 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -300,7 +300,7 @@ config DS4510
config FSL_IIM
bool "Enable FSL IC Identification Module (IIM) driver"
- depends on ARCH_MX31 || ARCH_MX5
+ depends on ARCH_MX5
config FSL_SEC_MON
bool "Enable FSL SEC_MON Driver"
diff --git a/drivers/net/phy/micrel_ksz90x1.c b/drivers/net/phy/micrel_ksz90x1.c
index ee8eae1efd9..a02dbe900b8 100644
--- a/drivers/net/phy/micrel_ksz90x1.c
+++ b/drivers/net/phy/micrel_ksz90x1.c
@@ -7,6 +7,7 @@
* (C) 2012 NetModule AG, David Andrey, added KSZ9031
* (C) Copyright 2017 Adaptrum, Inc.
* Written by Alexandru Gagniuc <alex.g@adaptrum.com> for Adaptrum, Inc.
+ * Copyright (C) 2025 Altera Corporation <www.altera.com>
*/
#include <dm.h>
#include <env.h>
@@ -110,6 +111,7 @@ static int ksz90x1_of_config_group(struct phy_device *phydev,
{
struct udevice *dev = phydev->dev;
struct phy_driver *drv = phydev->drv;
+ struct ofnode_phandle_args phandle;
int val[4];
int i, changed = 0, offset, max;
u16 regval = 0;
@@ -126,8 +128,14 @@ static int ksz90x1_of_config_group(struct phy_device *phydev,
}
if (!ofnode_valid(node)) {
- /* No node found, look in the Ethernet node */
- node = dev_ofnode(dev);
+ if (dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0,
+ &phandle)) {
+ /* No phy-handle found, look in the Ethernet node */
+ node = dev_ofnode(dev);
+ } else {
+ /* phy-handle found */
+ node = phandle.node;
+ }
}
for (i = 0; i < ofcfg->grpsz; i++) {
diff --git a/drivers/net/sh_eth.c b/drivers/net/sh_eth.c
index f695a3a41d2..1160c1d6cfa 100644
--- a/drivers/net/sh_eth.c
+++ b/drivers/net/sh_eth.c
@@ -29,45 +29,30 @@
#include "sh_eth.h"
-#ifndef CFG_SH_ETHER_USE_PORT
-# error "Please define CFG_SH_ETHER_USE_PORT"
-#endif
-#ifndef CFG_SH_ETHER_PHY_ADDR
-# error "Please define CFG_SH_ETHER_PHY_ADDR"
-#endif
+static void flush_cache_wback(void *addr, unsigned long len)
+{
+ flush_dcache_range((unsigned long)addr,
+ (unsigned long)(addr + ALIGN(len, SH_ETHER_ALIGN_SIZE)));
+}
-#if defined(CFG_SH_ETHER_CACHE_WRITEBACK) && \
- !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
-#define flush_cache_wback(addr, len) \
- flush_dcache_range((unsigned long)addr, \
- (unsigned long)(addr + ALIGN(len, CFG_SH_ETHER_ALIGNE_SIZE)))
-#else
-#define flush_cache_wback(...)
-#endif
+static void invalidate_cache(void *addr, unsigned long len)
+{
+ unsigned long line_size = SH_ETHER_ALIGN_SIZE;
+ unsigned long start, end;
-#if defined(CFG_SH_ETHER_CACHE_INVALIDATE) && defined(CONFIG_ARM)
-#define invalidate_cache(addr, len) \
- { \
- unsigned long line_size = CFG_SH_ETHER_ALIGNE_SIZE; \
- unsigned long start, end; \
- \
- start = (unsigned long)addr; \
- end = start + len; \
- start &= ~(line_size - 1); \
- end = ((end + line_size - 1) & ~(line_size - 1)); \
- \
- invalidate_dcache_range(start, end); \
- }
-#else
-#define invalidate_cache(...)
-#endif
+ start = (unsigned long)addr;
+ end = start + len;
+ start &= ~(line_size - 1);
+ end = (end + line_size - 1) & ~(line_size - 1);
+
+ invalidate_dcache_range(start, end);
+}
#define TIMEOUT_CNT 1000
-static int sh_eth_send_common(struct sh_eth_dev *eth, void *packet, int len)
+static int sh_eth_send_common(struct sh_eth_info *port_info, void *packet, int len)
{
int ret = 0, timeout;
- struct sh_eth_info *port_info = &eth->port_info[eth->port];
if (!packet || len > 0xffff) {
printf(SHETHER_NAME ": %s: Invalid argument\n", __func__);
@@ -121,10 +106,8 @@ err:
return ret;
}
-static int sh_eth_recv_start(struct sh_eth_dev *eth)
+static int sh_eth_recv_start(struct sh_eth_info *port_info)
{
- struct sh_eth_info *port_info = &eth->port_info[eth->port];
-
/* Check if the rx descriptor is ready */
invalidate_cache(port_info->rx_desc_cur, sizeof(struct rx_desc_s));
if (port_info->rx_desc_cur->rd0 & RD_RACT)
@@ -137,11 +120,9 @@ static int sh_eth_recv_start(struct sh_eth_dev *eth)
return port_info->rx_desc_cur->rd1 & 0xffff;
}
-static void sh_eth_recv_finish(struct sh_eth_dev *eth)
+static void sh_eth_recv_finish(struct sh_eth_info *port_info)
{
- struct sh_eth_info *port_info = &eth->port_info[eth->port];
-
- invalidate_cache(ADDR_TO_P2(port_info->rx_desc_cur->rd2), MAX_BUF_SIZE);
+ invalidate_cache((void *)ADDR_TO_P2((uintptr_t)port_info->rx_desc_cur->rd2), MAX_BUF_SIZE);
/* Make current descriptor available again */
if (port_info->rx_desc_cur->rd0 & RD_RDLE)
@@ -159,9 +140,8 @@ static void sh_eth_recv_finish(struct sh_eth_dev *eth)
port_info->rx_desc_cur = port_info->rx_desc_base;
}
-static int sh_eth_reset(struct sh_eth_dev *eth)
+static int sh_eth_reset(struct sh_eth_info *port_info)
{
- struct sh_eth_info *port_info = &eth->port_info[eth->port];
#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
int ret = 0, i;
@@ -192,12 +172,11 @@ static int sh_eth_reset(struct sh_eth_dev *eth)
#endif
}
-static int sh_eth_tx_desc_init(struct sh_eth_dev *eth)
+static int sh_eth_tx_desc_init(struct sh_eth_info *port_info)
{
- int i, ret = 0;
u32 alloc_desc_size = NUM_TX_DESC * sizeof(struct tx_desc_s);
- struct sh_eth_info *port_info = &eth->port_info[eth->port];
struct tx_desc_s *cur_tx_desc;
+ int i, ret = 0;
/*
* Allocate rx descriptors. They must be aligned to size of struct
@@ -244,11 +223,10 @@ err:
return ret;
}
-static int sh_eth_rx_desc_init(struct sh_eth_dev *eth)
+static int sh_eth_rx_desc_init(struct sh_eth_info *port_info)
{
int i, ret = 0;
u32 alloc_desc_size = NUM_RX_DESC * sizeof(struct rx_desc_s);
- struct sh_eth_info *port_info = &eth->port_info[eth->port];
struct rx_desc_s *cur_rx_desc;
u8 *rx_buf;
@@ -318,20 +296,16 @@ err:
return ret;
}
-static void sh_eth_tx_desc_free(struct sh_eth_dev *eth)
+static void sh_eth_tx_desc_free(struct sh_eth_info *port_info)
{
- struct sh_eth_info *port_info = &eth->port_info[eth->port];
-
if (port_info->tx_desc_alloc) {
free(port_info->tx_desc_alloc);
port_info->tx_desc_alloc = NULL;
}
}
-static void sh_eth_rx_desc_free(struct sh_eth_dev *eth)
+static void sh_eth_rx_desc_free(struct sh_eth_info *port_info)
{
- struct sh_eth_info *port_info = &eth->port_info[eth->port];
-
if (port_info->rx_desc_alloc) {
free(port_info->rx_desc_alloc);
port_info->rx_desc_alloc = NULL;
@@ -343,21 +317,21 @@ static void sh_eth_rx_desc_free(struct sh_eth_dev *eth)
}
}
-static int sh_eth_desc_init(struct sh_eth_dev *eth)
+static int sh_eth_desc_init(struct sh_eth_info *port_info)
{
int ret = 0;
- ret = sh_eth_tx_desc_init(eth);
+ ret = sh_eth_tx_desc_init(port_info);
if (ret)
goto err_tx_init;
- ret = sh_eth_rx_desc_init(eth);
+ ret = sh_eth_rx_desc_init(port_info);
if (ret)
goto err_rx_init;
return ret;
err_rx_init:
- sh_eth_tx_desc_free(eth);
+ sh_eth_tx_desc_free(port_info);
err_tx_init:
return ret;
@@ -375,9 +349,8 @@ static void sh_eth_write_hwaddr(struct sh_eth_info *port_info,
sh_eth_write(port_info, val, MALR);
}
-static void sh_eth_mac_regs_config(struct sh_eth_dev *eth, unsigned char *mac)
+static void sh_eth_mac_regs_config(struct sh_eth_info *port_info, unsigned char *mac)
{
- struct sh_eth_info *port_info = &eth->port_info[eth->port];
unsigned long edmr;
/* Configure e-dmac registers */
@@ -422,9 +395,8 @@ static void sh_eth_mac_regs_config(struct sh_eth_dev *eth, unsigned char *mac)
#endif
}
-static int sh_eth_phy_regs_config(struct sh_eth_dev *eth)
+static int sh_eth_phy_regs_config(struct sh_eth_info *port_info)
{
- struct sh_eth_info *port_info = &eth->port_info[eth->port];
struct phy_device *phy = port_info->phydev;
int ret = 0;
u32 val = 0;
@@ -470,10 +442,8 @@ static int sh_eth_phy_regs_config(struct sh_eth_dev *eth)
return ret;
}
-static void sh_eth_start(struct sh_eth_dev *eth)
+static void sh_eth_start(struct sh_eth_info *port_info)
{
- struct sh_eth_info *port_info = &eth->port_info[eth->port];
-
/*
* Enable the e-dmac receiver only. The transmitter will be enabled when
* we have something to transmit
@@ -481,33 +451,30 @@ static void sh_eth_start(struct sh_eth_dev *eth)
sh_eth_write(port_info, EDRRR_R, EDRRR);
}
-static void sh_eth_stop(struct sh_eth_dev *eth)
+static void sh_eth_stop(struct sh_eth_info *port_info)
{
- struct sh_eth_info *port_info = &eth->port_info[eth->port];
-
sh_eth_write(port_info, ~EDRRR_R, EDRRR);
}
-static int sh_eth_init_common(struct sh_eth_dev *eth, unsigned char *mac)
+static int sh_eth_init_common(struct sh_eth_info *port_info, unsigned char *mac)
{
int ret = 0;
- ret = sh_eth_reset(eth);
+ ret = sh_eth_reset(port_info);
if (ret)
return ret;
- ret = sh_eth_desc_init(eth);
+ ret = sh_eth_desc_init(port_info);
if (ret)
return ret;
- sh_eth_mac_regs_config(eth, mac);
+ sh_eth_mac_regs_config(port_info, mac);
return 0;
}
-static int sh_eth_start_common(struct sh_eth_dev *eth)
+static int sh_eth_start_common(struct sh_eth_info *port_info)
{
- struct sh_eth_info *port_info = &eth->port_info[eth->port];
int ret;
ret = phy_startup(port_info->phydev);
@@ -516,17 +483,17 @@ static int sh_eth_start_common(struct sh_eth_dev *eth)
return ret;
}
- ret = sh_eth_phy_regs_config(eth);
+ ret = sh_eth_phy_regs_config(port_info);
if (ret)
return ret;
- sh_eth_start(eth);
+ sh_eth_start(port_info);
return 0;
}
struct sh_ether_priv {
- struct sh_eth_dev shdev;
+ struct sh_eth_info port_info;
struct mii_dev *bus;
phys_addr_t iobase;
@@ -536,20 +503,19 @@ struct sh_ether_priv {
static int sh_ether_send(struct udevice *dev, void *packet, int len)
{
struct sh_ether_priv *priv = dev_get_priv(dev);
- struct sh_eth_dev *eth = &priv->shdev;
+ struct sh_eth_info *port_info = &priv->port_info;
- return sh_eth_send_common(eth, packet, len);
+ return sh_eth_send_common(port_info, packet, len);
}
static int sh_ether_recv(struct udevice *dev, int flags, uchar **packetp)
{
struct sh_ether_priv *priv = dev_get_priv(dev);
- struct sh_eth_dev *eth = &priv->shdev;
- struct sh_eth_info *port_info = &eth->port_info[eth->port];
+ struct sh_eth_info *port_info = &priv->port_info;
uchar *packet = (uchar *)ADDR_TO_P2((uintptr_t)port_info->rx_desc_cur->rd2);
int len;
- len = sh_eth_recv_start(eth);
+ len = sh_eth_recv_start(port_info);
if (len > 0) {
invalidate_cache(packet, len);
*packetp = packet;
@@ -567,10 +533,9 @@ static int sh_ether_recv(struct udevice *dev, int flags, uchar **packetp)
static int sh_ether_free_pkt(struct udevice *dev, uchar *packet, int length)
{
struct sh_ether_priv *priv = dev_get_priv(dev);
- struct sh_eth_dev *eth = &priv->shdev;
- struct sh_eth_info *port_info = &eth->port_info[eth->port];
+ struct sh_eth_info *port_info = &priv->port_info;
- sh_eth_recv_finish(eth);
+ sh_eth_recv_finish(port_info);
/* Restart the receiver if disabled */
if (!(sh_eth_read(port_info, EDRRR) & EDRRR_R))
@@ -582,8 +547,7 @@ static int sh_ether_free_pkt(struct udevice *dev, uchar *packet, int length)
static int sh_ether_write_hwaddr(struct udevice *dev)
{
struct sh_ether_priv *priv = dev_get_priv(dev);
- struct sh_eth_dev *eth = &priv->shdev;
- struct sh_eth_info *port_info = &eth->port_info[eth->port];
+ struct sh_eth_info *port_info = &priv->port_info;
struct eth_pdata *pdata = dev_get_plat(dev);
sh_eth_write_hwaddr(port_info, pdata->enetaddr);
@@ -595,10 +559,9 @@ static int sh_eth_phy_config(struct udevice *dev)
{
struct sh_ether_priv *priv = dev_get_priv(dev);
struct eth_pdata *pdata = dev_get_plat(dev);
- struct sh_eth_dev *eth = &priv->shdev;
- int ret = 0;
- struct sh_eth_info *port_info = &eth->port_info[eth->port];
+ struct sh_eth_info *port_info = &priv->port_info;
struct phy_device *phydev;
+ int ret = 0;
phydev = phy_connect(priv->bus, -1, dev, pdata->phy_interface);
if (!phydev)
@@ -614,40 +577,38 @@ static int sh_ether_start(struct udevice *dev)
{
struct sh_ether_priv *priv = dev_get_priv(dev);
struct eth_pdata *pdata = dev_get_plat(dev);
- struct sh_eth_dev *eth = &priv->shdev;
+ struct sh_eth_info *port_info = &priv->port_info;
int ret;
- ret = sh_eth_init_common(eth, pdata->enetaddr);
+ ret = sh_eth_init_common(port_info, pdata->enetaddr);
if (ret)
return ret;
- ret = sh_eth_start_common(eth);
+ ret = sh_eth_start_common(port_info);
if (ret)
goto err_start;
return 0;
err_start:
- sh_eth_tx_desc_free(eth);
- sh_eth_rx_desc_free(eth);
+ sh_eth_tx_desc_free(port_info);
+ sh_eth_rx_desc_free(port_info);
return ret;
}
static void sh_ether_stop(struct udevice *dev)
{
struct sh_ether_priv *priv = dev_get_priv(dev);
- struct sh_eth_dev *eth = &priv->shdev;
- struct sh_eth_info *port_info = &eth->port_info[eth->port];
+ struct sh_eth_info *port_info = &priv->port_info;
phy_shutdown(port_info->phydev);
- sh_eth_stop(&priv->shdev);
+ sh_eth_stop(port_info);
}
/******* for bb_miiphy *******/
static int sh_eth_bb_mdio_active(struct mii_dev *miidev)
{
- struct sh_eth_dev *eth = miidev->priv;
- struct sh_eth_info *port_info = &eth->port_info[eth->port];
+ struct sh_eth_info *port_info = miidev->priv;
sh_eth_write(port_info, sh_eth_read(port_info, PIR) | PIR_MMD, PIR);
@@ -656,8 +617,7 @@ static int sh_eth_bb_mdio_active(struct mii_dev *miidev)
static int sh_eth_bb_mdio_tristate(struct mii_dev *miidev)
{
- struct sh_eth_dev *eth = miidev->priv;
- struct sh_eth_info *port_info = &eth->port_info[eth->port];
+ struct sh_eth_info *port_info = miidev->priv;
sh_eth_write(port_info, sh_eth_read(port_info, PIR) & ~PIR_MMD, PIR);
@@ -666,8 +626,7 @@ static int sh_eth_bb_mdio_tristate(struct mii_dev *miidev)
static int sh_eth_bb_set_mdio(struct mii_dev *miidev, int v)
{
- struct sh_eth_dev *eth = miidev->priv;
- struct sh_eth_info *port_info = &eth->port_info[eth->port];
+ struct sh_eth_info *port_info = miidev->priv;
if (v)
sh_eth_write(port_info,
@@ -681,8 +640,7 @@ static int sh_eth_bb_set_mdio(struct mii_dev *miidev, int v)
static int sh_eth_bb_get_mdio(struct mii_dev *miidev, int *v)
{
- struct sh_eth_dev *eth = miidev->priv;
- struct sh_eth_info *port_info = &eth->port_info[eth->port];
+ struct sh_eth_info *port_info = miidev->priv;
*v = (sh_eth_read(port_info, PIR) & PIR_MDI) >> 3;
@@ -691,8 +649,7 @@ static int sh_eth_bb_get_mdio(struct mii_dev *miidev, int *v)
static int sh_eth_bb_set_mdc(struct mii_dev *miidev, int v)
{
- struct sh_eth_dev *eth = miidev->priv;
- struct sh_eth_info *port_info = &eth->port_info[eth->port];
+ struct sh_eth_info *port_info = miidev->priv;
if (v)
sh_eth_write(port_info,
@@ -738,7 +695,7 @@ static int sh_ether_probe(struct udevice *udev)
{
struct eth_pdata *pdata = dev_get_plat(udev);
struct sh_ether_priv *priv = dev_get_priv(udev);
- struct sh_eth_dev *eth = &priv->shdev;
+ struct sh_eth_info *port_info = &priv->port_info;
struct mii_dev *mdiodev;
int ret;
@@ -757,7 +714,7 @@ static int sh_ether_probe(struct udevice *udev)
mdiodev->read = sh_eth_bb_miiphy_read;
mdiodev->write = sh_eth_bb_miiphy_write;
- mdiodev->priv = eth;
+ mdiodev->priv = port_info;
snprintf(mdiodev->name, sizeof(mdiodev->name), udev->name);
ret = mdio_register(mdiodev);
@@ -766,10 +723,7 @@ static int sh_ether_probe(struct udevice *udev)
priv->bus = mdiodev;
- eth->port = CFG_SH_ETHER_USE_PORT;
- eth->port_info[eth->port].phy_addr = CFG_SH_ETHER_PHY_ADDR;
- eth->port_info[eth->port].iobase =
- (void __iomem *)(uintptr_t)(BASE_IO_ADDR + 0x800 * eth->port);
+ port_info->iobase = (void __iomem *)(uintptr_t)BASE_IO_ADDR;
#if CONFIG_IS_ENABLED(CLK)
ret = clk_enable(&priv->clk);
@@ -777,7 +731,7 @@ static int sh_ether_probe(struct udevice *udev)
goto err_mdio_register;
#endif
- ret = sh_eth_init_common(eth, pdata->enetaddr);
+ ret = sh_eth_init_common(port_info, pdata->enetaddr);
if (ret)
goto err_phy_config;
@@ -801,8 +755,7 @@ err_mdio_register:
static int sh_ether_remove(struct udevice *udev)
{
struct sh_ether_priv *priv = dev_get_priv(udev);
- struct sh_eth_dev *eth = &priv->shdev;
- struct sh_eth_info *port_info = &eth->port_info[eth->port];
+ struct sh_eth_info *port_info = &priv->port_info;
#if CONFIG_IS_ENABLED(CLK)
clk_disable(&priv->clk);
diff --git a/drivers/net/sh_eth.h b/drivers/net/sh_eth.h
index ecf4a697e27..c395e6e8fc7 100644
--- a/drivers/net/sh_eth.h
+++ b/drivers/net/sh_eth.h
@@ -19,23 +19,17 @@
/* The ethernet controller needs to use physical addresses */
#define ADDR_TO_PHY(addr) ((uintptr_t)(addr) & ~0xe0000000)
+#define SH_ETHER_ALIGN_SIZE 16
#elif defined(CONFIG_ARM)
#ifndef inl
#define inl readl
#define outl writel
+#define SH_ETHER_ALIGN_SIZE 64
#endif
#define ADDR_TO_PHY(addr) ((uintptr_t)(addr))
#define ADDR_TO_P2(addr) (addr)
#endif /* defined(CONFIG_SH) */
-/* base padding size is 16 */
-#ifndef CFG_SH_ETHER_ALIGNE_SIZE
-#define CFG_SH_ETHER_ALIGNE_SIZE 16
-#endif
-
-/* Number of supported ports */
-#define MAX_PORT_NUM 2
-
/* Buffers must be big enough to hold the largest ethernet frame. Also, rx
buffers must be a multiple of 32 bytes */
#define MAX_BUF_SIZE (48 * 32)
@@ -47,7 +41,7 @@
/* The size of the tx descriptor is determined by how much padding is used.
4, 20, or 52 bytes of padding can be used */
-#define TX_DESC_PADDING (CFG_SH_ETHER_ALIGNE_SIZE - 12)
+#define TX_DESC_PADDING (SH_ETHER_ALIGN_SIZE - 12)
/* Tx descriptor. We always use 3 bytes of padding */
struct tx_desc_s {
@@ -62,9 +56,9 @@ struct tx_desc_s {
/* The size of the rx descriptor is determined by how much padding is used.
4, 20, or 52 bytes of padding can be used */
-#define RX_DESC_PADDING (CFG_SH_ETHER_ALIGNE_SIZE - 12)
+#define RX_DESC_PADDING (SH_ETHER_ALIGN_SIZE - 12)
/* aligned cache line size */
-#define RX_BUF_ALIGNE_SIZE (CFG_SH_ETHER_ALIGNE_SIZE > 32 ? 64 : 32)
+#define RX_BUF_ALIGNE_SIZE (SH_ETHER_ALIGN_SIZE > 32 ? 64 : 32)
/* Rx descriptor. We always use 4 bytes of padding */
struct rx_desc_s {
@@ -84,17 +78,11 @@ struct sh_eth_info {
u8 *rx_buf_alloc;
u8 *rx_buf_base;
u8 mac_addr[6];
- u8 phy_addr;
struct eth_device *dev;
struct phy_device *phydev;
void __iomem *iobase;
};
-struct sh_eth_dev {
- int port;
- struct sh_eth_info port_info[MAX_PORT_NUM];
-};
-
/* from linux/drivers/net/ethernet/renesas/sh_eth.h */
enum {
/* E-DMAC registers */
@@ -388,11 +376,11 @@ enum DMAC_M_BIT {
#endif
};
-#if CFG_SH_ETHER_ALIGNE_SIZE == 64
+#if SH_ETHER_ALIGN_SIZE == 64
# define EMDR_DESC EDMR_DL1
-#elif CFG_SH_ETHER_ALIGNE_SIZE == 32
+#elif SH_ETHER_ALIGN_SIZE == 32
# define EMDR_DESC EDMR_DL0
-#elif CFG_SH_ETHER_ALIGNE_SIZE == 16 /* Default */
+#elif SH_ETHER_ALIGN_SIZE == 16 /* Default */
# define EMDR_DESC 0
#endif
diff --git a/drivers/net/ti/icssg_prueth.c b/drivers/net/ti/icssg_prueth.c
index 2639f960631..d8df3c9afb0 100644
--- a/drivers/net/ti/icssg_prueth.c
+++ b/drivers/net/ti/icssg_prueth.c
@@ -63,6 +63,7 @@
/* Number of PRU Cores per Slice */
#define ICSSG_NUM_PRU_CORES 3
+#define ICSSG_NUM_FIRMWARES 6
static int icssg_gmii_select(struct prueth_priv *priv)
{
@@ -192,25 +193,6 @@ static int icssg_update_link(struct prueth_priv *priv)
return phy->link;
}
-struct icssg_firmwares {
- char *pru;
- char *rtu;
- char *txpru;
-};
-
-static struct icssg_firmwares icssg_emac_firmwares[] = {
- {
- .pru = "/lib/firmware/ti-pruss/am65x-sr2-pru0-prueth-fw.elf",
- .rtu = "/lib/firmware/ti-pruss/am65x-sr2-rtu0-prueth-fw.elf",
- .txpru = "/lib/firmware/ti-pruss/am65x-sr2-txpru0-prueth-fw.elf",
- },
- {
- .pru = "/lib/firmware/ti-pruss/am65x-sr2-pru1-prueth-fw.elf",
- .rtu = "/lib/firmware/ti-pruss/am65x-sr2-rtu1-prueth-fw.elf",
- .txpru = "/lib/firmware/ti-pruss/am65x-sr2-txpru1-prueth-fw.elf",
- }
-};
-
static int icssg_start_pru_cores(struct udevice *dev)
{
struct prueth_priv *priv = dev_get_priv(dev);
@@ -223,7 +205,7 @@ static int icssg_start_pru_cores(struct udevice *dev)
slice = priv->port_id;
index = slice * ICSSG_NUM_PRU_CORES;
- firmwares = icssg_emac_firmwares;
+ firmwares = prueth->firmwares;
ofnode_read_u32_index(dev_ofnode(prueth->dev), "ti,prus", index, &phandle);
ret = uclass_get_device_by_phandle_id(UCLASS_REMOTEPROC, phandle, &rproc_dev);
@@ -476,6 +458,24 @@ static const struct eth_ops prueth_ops = {
.stop = prueth_stop,
};
+static char *prepend_fw_path(const char *fw_name)
+{
+ static const char fw_dir[] = "/lib/firmware/";
+ char *result;
+ int len;
+
+ if (!fw_name)
+ return NULL;
+
+ len = strlen(fw_dir) + strlen(fw_name) + 1;
+ result = malloc(len);
+ if (!result)
+ return NULL;
+
+ sprintf(result, "%s%s", fw_dir, fw_name);
+ return result;
+}
+
static int icssg_ofdata_parse_phy(struct udevice *dev)
{
struct prueth_priv *priv = dev_get_priv(dev);
@@ -534,6 +534,8 @@ static int prueth_probe(struct udevice *dev)
struct udevice **prussdev = NULL;
ofnode eth_ports_node, eth_node;
struct udevice *port_dev;
+ const char **fw_names;
+ int fw_count, i;
int ret = 0;
prueth->dev = dev;
@@ -659,6 +661,18 @@ static int prueth_probe(struct udevice *dev)
}
}
+ /* Parse firmware-name property from DT */
+ fw_count = dev_read_string_list(dev, "firmware-name", &fw_names);
+ if (fw_count != ICSSG_NUM_FIRMWARES) {
+ dev_err(dev, "Expected %d firmware names, got %d\n", ICSSG_NUM_FIRMWARES, fw_count);
+ return -EINVAL;
+ }
+ for (i = 0; i < 2; i++) {
+ prueth->firmwares[i].pru = prepend_fw_path(fw_names[i * 3 + 0]);
+ prueth->firmwares[i].rtu = prepend_fw_path(fw_names[i * 3 + 1]);
+ prueth->firmwares[i].txpru = prepend_fw_path(fw_names[i * 3 + 2]);
+ }
+
return 0;
out:
clk_disable(&prueth->mdiofck);
diff --git a/drivers/net/ti/icssg_prueth.h b/drivers/net/ti/icssg_prueth.h
index c69cfd4f162..d88b6fa88e7 100644
--- a/drivers/net/ti/icssg_prueth.h
+++ b/drivers/net/ti/icssg_prueth.h
@@ -38,6 +38,12 @@ enum prueth_port {
PRUETH_PORT_MII1, /* physical port MII 1 */
};
+struct icssg_firmwares {
+ char *pru;
+ char *rtu;
+ char *txpru;
+};
+
struct prueth {
struct udevice *dev;
struct udevice *pruss;
@@ -66,6 +72,7 @@ struct prueth {
u8 rtu_core_id;
u8 txpru_core_id;
u8 icssg_hwcmdseq;
+ struct icssg_firmwares firmwares[PRUETH_NUM_MACS];
};
struct prueth_priv {
diff --git a/drivers/nvme/nvme.c b/drivers/nvme/nvme.c
index 7c58ceb78f5..2b14437f69c 100644
--- a/drivers/nvme/nvme.c
+++ b/drivers/nvme/nvme.c
@@ -912,8 +912,10 @@ int nvme_init(struct udevice *udev)
goto free_id;
ret = bootdev_setup_for_sibling_blk(ns_udev, "nvme_bootdev");
- if (ret)
- return log_msg_ret("bootdev", ret);
+ if (ret) {
+ log_err("bootdev: returning err=%d\n", ret);
+ goto free_id;
+ }
ret = blk_probe_or_unbind(ns_udev);
if (ret)
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index 589b526381f..1f2f2468eb0 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -762,7 +762,7 @@ config MCFUART
config MXC_UART
bool "IMX serial port support"
- depends on ARCH_MX31 || MX5 || MX6 || MX7 || IMX8M
+ depends on MX5 || MX6 || MX7 || IMX8M
help
If you have a machine based on a Motorola IMX CPU you
can enable its onboard serial port by enabling this option.
diff --git a/drivers/w1/Kconfig b/drivers/w1/Kconfig
index 0ffc1b6444b..9e52ba8905c 100644
--- a/drivers/w1/Kconfig
+++ b/drivers/w1/Kconfig
@@ -20,7 +20,7 @@ config W1_GPIO
config W1_MXC
bool "Enable 1-wire controller on i.MX processors"
- depends on ARCH_MX31 || ARCH_MX5
+ depends on ARCH_MX5
help
Support the one wire controller found in some members of the NXP
i.MX SoC family.
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index 45eb9b4d3f9..e9ea874d0e3 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -27,7 +27,7 @@ config WATCHDOG_AUTOSTART
config WATCHDOG_TIMEOUT_MSECS
int "Watchdog timeout in msec"
- default 128000 if ARCH_MX31 || ARCH_MX5 || ARCH_MX6
+ default 128000 if ARCH_MX5 || ARCH_MX6
default 128000 if ARCH_MX7 || ARCH_VF610
default 30000 if ARCH_SNAPDRAGON
default 30000 if ARCH_SOCFPGA
generated by cgit v1.2.3 (git 2.0.4) at 2025-07-13 05:21:33 +0000