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-rw-r--r--drivers/dma/dma-uclass.c17
-rw-r--r--drivers/dma/sandbox-dma-test.c4
-rw-r--r--drivers/dma/ti-edma3.c33
-rw-r--r--drivers/dma/ti/k3-udma.c4
-rw-r--r--drivers/phy/ti/phy-j721e-wiz.c75
-rw-r--r--drivers/watchdog/omap_wdt.c2
6 files changed, 116 insertions, 19 deletions
diff --git a/drivers/dma/dma-uclass.c b/drivers/dma/dma-uclass.c
index 012609bb537..81dbb4da107 100644
--- a/drivers/dma/dma-uclass.c
+++ b/drivers/dma/dma-uclass.c
@@ -19,6 +19,7 @@
#include <asm/cache.h>
#include <dm/read.h>
#include <dma-uclass.h>
+#include <linux/dma-mapping.h>
#include <dt-structs.h>
#include <errno.h>
@@ -235,6 +236,8 @@ int dma_memcpy(void *dst, void *src, size_t len)
{
struct udevice *dev;
const struct dma_ops *ops;
+ dma_addr_t destination;
+ dma_addr_t source;
int ret;
ret = dma_get_device(DMA_SUPPORTS_MEM_TO_MEM, &dev);
@@ -245,11 +248,17 @@ int dma_memcpy(void *dst, void *src, size_t len)
if (!ops->transfer)
return -ENOSYS;
- /* Invalidate the area, so no writeback into the RAM races with DMA */
- invalidate_dcache_range((unsigned long)dst, (unsigned long)dst +
- roundup(len, ARCH_DMA_MINALIGN));
+ /* Clean the areas, so no writeback into the RAM races with DMA */
+ destination = dma_map_single(dst, len, DMA_FROM_DEVICE);
+ source = dma_map_single(src, len, DMA_TO_DEVICE);
- return ops->transfer(dev, DMA_MEM_TO_MEM, dst, src, len);
+ ret = ops->transfer(dev, DMA_MEM_TO_MEM, destination, source, len);
+
+ /* Clean+Invalidate the areas after, so we can see DMA'd data */
+ dma_unmap_single(destination, len, DMA_FROM_DEVICE);
+ dma_unmap_single(source, len, DMA_TO_DEVICE);
+
+ return ret;
}
UCLASS_DRIVER(dma) = {
diff --git a/drivers/dma/sandbox-dma-test.c b/drivers/dma/sandbox-dma-test.c
index aebf3eef966..2b8259a35b4 100644
--- a/drivers/dma/sandbox-dma-test.c
+++ b/drivers/dma/sandbox-dma-test.c
@@ -39,9 +39,9 @@ struct sandbox_dma_dev {
};
static int sandbox_dma_transfer(struct udevice *dev, int direction,
- void *dst, void *src, size_t len)
+ dma_addr_t dst, dma_addr_t src, size_t len)
{
- memcpy(dst, src, len);
+ memcpy((void *)dst, (void *)src, len);
return 0;
}
diff --git a/drivers/dma/ti-edma3.c b/drivers/dma/ti-edma3.c
index ec3dc62d2f3..1ad3b92dbf4 100644
--- a/drivers/dma/ti-edma3.c
+++ b/drivers/dma/ti-edma3.c
@@ -13,6 +13,7 @@
#include <common.h>
#include <dm.h>
#include <dma-uclass.h>
+#include <linux/dma-mapping.h>
#include <asm/omap_common.h>
#include <asm/ti-common/ti-edma3.h>
@@ -395,7 +396,7 @@ void qedma3_stop(u32 base, struct edma3_channel_config *cfg)
}
void __edma3_transfer(unsigned long edma3_base_addr, unsigned int edma_slot_num,
- void *dst, void *src, size_t len, size_t s_len)
+ dma_addr_t dst, dma_addr_t src, size_t len, size_t s_len)
{
struct edma3_slot_config slot;
struct edma3_channel_config edma_channel;
@@ -483,12 +484,14 @@ void __edma3_transfer(unsigned long edma3_base_addr, unsigned int edma_slot_num,
}
void __edma3_fill(unsigned long edma3_base_addr, unsigned int edma_slot_num,
- void *dst, u8 val, size_t len)
+ dma_addr_t dst, u8 val, size_t len)
{
int xfer_len;
int max_xfer = EDMA_FILL_BUFFER_SIZE * 65535;
+ dma_addr_t source;
memset((void *)edma_fill_buffer, val, sizeof(edma_fill_buffer));
+ source = dma_map_single(edma_fill_buffer, len, DMA_TO_DEVICE);
while (len) {
xfer_len = len;
@@ -496,11 +499,13 @@ void __edma3_fill(unsigned long edma3_base_addr, unsigned int edma_slot_num,
xfer_len = max_xfer;
__edma3_transfer(edma3_base_addr, edma_slot_num, dst,
- edma_fill_buffer, xfer_len,
+ source, xfer_len,
EDMA_FILL_BUFFER_SIZE);
len -= xfer_len;
dst += xfer_len;
}
+
+ dma_unmap_single(source, len, DMA_FROM_DEVICE);
}
#ifndef CONFIG_DMA
@@ -508,19 +513,33 @@ void __edma3_fill(unsigned long edma3_base_addr, unsigned int edma_slot_num,
void edma3_transfer(unsigned long edma3_base_addr, unsigned int edma_slot_num,
void *dst, void *src, size_t len)
{
- __edma3_transfer(edma3_base_addr, edma_slot_num, dst, src, len, len);
+ /* Clean the areas, so no writeback into the RAM races with DMA */
+ dma_addr_t destination = dma_map_single(dst, len, DMA_FROM_DEVICE);
+ dma_addr_t source = dma_map_single(src, len, DMA_TO_DEVICE);
+
+ __edma3_transfer(edma3_base_addr, edma_slot_num, destination, source, len, len);
+
+ /* Clean+Invalidate the areas after, so we can see DMA'd data */
+ dma_unmap_single(destination, len, DMA_FROM_DEVICE);
+ dma_unmap_single(source, len, DMA_TO_DEVICE);
}
void edma3_fill(unsigned long edma3_base_addr, unsigned int edma_slot_num,
void *dst, u8 val, size_t len)
{
- __edma3_fill(edma3_base_addr, edma_slot_num, dst, val, len);
+ /* Clean the area, so no writeback into the RAM races with DMA */
+ dma_addr_t destination = dma_map_single(dst, len, DMA_FROM_DEVICE);
+
+ __edma3_fill(edma3_base_addr, edma_slot_num, destination, val, len);
+
+ /* Clean+Invalidate the area after, so we can see DMA'd data */
+ dma_unmap_single(destination, len, DMA_FROM_DEVICE);
}
#else
-static int ti_edma3_transfer(struct udevice *dev, int direction, void *dst,
- void *src, size_t len)
+static int ti_edma3_transfer(struct udevice *dev, int direction,
+ dma_addr_t dst, dma_addr_t src, size_t len)
{
struct ti_edma3_priv *priv = dev_get_priv(dev);
diff --git a/drivers/dma/ti/k3-udma.c b/drivers/dma/ti/k3-udma.c
index 1a9197bfc82..d92b9644369 100644
--- a/drivers/dma/ti/k3-udma.c
+++ b/drivers/dma/ti/k3-udma.c
@@ -2305,7 +2305,7 @@ err_res_free:
}
static int udma_transfer(struct udevice *dev, int direction,
- void *dst, void *src, size_t len)
+ dma_addr_t dst, dma_addr_t src, size_t len)
{
struct udma_dev *ud = dev_get_priv(dev);
/* Channel0 is reserved for memcpy */
@@ -2326,7 +2326,7 @@ static int udma_transfer(struct udevice *dev, int direction,
if (ret)
return ret;
- udma_prep_dma_memcpy(uc, (dma_addr_t)dst, (dma_addr_t)src, len);
+ udma_prep_dma_memcpy(uc, dst, src, len);
udma_start(uc);
udma_poll_completion(uc, &paddr);
udma_stop(uc);
diff --git a/drivers/phy/ti/phy-j721e-wiz.c b/drivers/phy/ti/phy-j721e-wiz.c
index fb6b6cf3fff..6646b15d410 100644
--- a/drivers/phy/ti/phy-j721e-wiz.c
+++ b/drivers/phy/ti/phy-j721e-wiz.c
@@ -69,14 +69,20 @@ static const struct reg_field por_en = REG_FIELD(WIZ_SERDES_CTRL, 31, 31);
static const struct reg_field phy_reset_n = REG_FIELD(WIZ_SERDES_RST, 31, 31);
static const struct reg_field pll1_refclk_mux_sel =
REG_FIELD(WIZ_SERDES_RST, 29, 29);
+static const struct reg_field pll1_refclk_mux_sel_2 =
+ REG_FIELD(WIZ_SERDES_RST, 22, 23);
static const struct reg_field pll0_refclk_mux_sel =
REG_FIELD(WIZ_SERDES_RST, 28, 28);
+static const struct reg_field pll0_refclk_mux_sel_2 =
+ REG_FIELD(WIZ_SERDES_RST, 28, 29);
static const struct reg_field refclk_dig_sel_16g =
REG_FIELD(WIZ_SERDES_RST, 24, 25);
static const struct reg_field refclk_dig_sel_10g =
REG_FIELD(WIZ_SERDES_RST, 24, 24);
static const struct reg_field pma_cmn_refclk_int_mode =
REG_FIELD(WIZ_SERDES_TOP_CTRL, 28, 29);
+static const struct reg_field pma_cmn_refclk1_int_mode =
+ REG_FIELD(WIZ_SERDES_TOP_CTRL, 20, 21);
static const struct reg_field pma_cmn_refclk_mode =
REG_FIELD(WIZ_SERDES_TOP_CTRL, 30, 31);
static const struct reg_field pma_cmn_refclk_dig_div =
@@ -204,6 +210,27 @@ static struct wiz_clk_mux_sel clk_mux_sel_10g[] = {
},
};
+static const struct wiz_clk_mux_sel clk_mux_sel_10g_2_refclk[] = {
+ {
+ .num_parents = 3,
+ .parents = { WIZ_CORE_REFCLK, WIZ_CORE_REFCLK1, WIZ_EXT_REFCLK },
+ .table = { 2, 3, 0 },
+ .node_name = "pll0-refclk",
+ },
+ {
+ .num_parents = 3,
+ .parents = { WIZ_CORE_REFCLK, WIZ_CORE_REFCLK1, WIZ_EXT_REFCLK },
+ .table = { 2, 3, 0 },
+ .node_name = "pll1-refclk",
+ },
+ {
+ .num_parents = 3,
+ .parents = { WIZ_CORE_REFCLK, WIZ_CORE_REFCLK1, WIZ_EXT_REFCLK },
+ .table = { 2, 3, 0 },
+ .node_name = "refclk-dig",
+ },
+};
+
static struct wiz_clk_div_sel clk_div_sel[] = {
{
.div_sel = CMN_REFCLK,
@@ -219,6 +246,7 @@ enum wiz_type {
J721E_WIZ_16G,
J721E_WIZ_10G,
AM64_WIZ_10G,
+ J784S4_WIZ_10G,
};
struct wiz_data {
@@ -227,6 +255,7 @@ struct wiz_data {
const struct reg_field *pll1_refclk_mux_sel;
const struct reg_field *refclk_dig_sel;
const struct reg_field *pma_cmn_refclk1_dig_div;
+ const struct reg_field *pma_cmn_refclk1_int_mode;
const struct wiz_clk_mux_sel *clk_mux_sel;
unsigned int clk_div_sel_num;
};
@@ -259,6 +288,16 @@ static struct wiz_data am64_10g_data = {
.clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_10G,
};
+static struct wiz_data j784s4_wiz_10g = {
+ .type = J784S4_WIZ_10G,
+ .pll0_refclk_mux_sel = &pll0_refclk_mux_sel_2,
+ .pll1_refclk_mux_sel = &pll1_refclk_mux_sel_2,
+ .refclk_dig_sel = &refclk_dig_sel_16g,
+ .pma_cmn_refclk1_int_mode = &pma_cmn_refclk1_int_mode,
+ .clk_mux_sel = clk_mux_sel_10g_2_refclk,
+ .clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_10G,
+};
+
#define WIZ_TYPEC_DIR_DEBOUNCE_MIN 100 /* ms */
#define WIZ_TYPEC_DIR_DEBOUNCE_MAX 1000
@@ -279,6 +318,7 @@ struct wiz {
struct regmap_field *p_mac_div_sel1[WIZ_MAX_LANES];
struct regmap_field *p0_fullrt_div[WIZ_MAX_LANES];
struct regmap_field *pma_cmn_refclk_int_mode;
+ struct regmap_field *pma_cmn_refclk1_int_mode;
struct regmap_field *pma_cmn_refclk_mode;
struct regmap_field *pma_cmn_refclk_dig_div;
struct regmap_field *pma_cmn_refclk1_dig_div;
@@ -729,6 +769,15 @@ static int wiz_regfield_init(struct wiz *wiz)
return PTR_ERR(wiz->pma_cmn_refclk_int_mode);
}
+ if (data->pma_cmn_refclk1_int_mode) {
+ wiz->pma_cmn_refclk1_int_mode =
+ devm_regmap_field_alloc(dev, regmap, *data->pma_cmn_refclk1_int_mode);
+ if (IS_ERR(wiz->pma_cmn_refclk1_int_mode)) {
+ dev_err(dev, "PMA_CMN_REFCLK1_INT_MODE reg field init failed\n");
+ return PTR_ERR(wiz->pma_cmn_refclk1_int_mode);
+ }
+ }
+
wiz->pma_cmn_refclk_mode =
devm_regmap_field_alloc(dev, regmap, pma_cmn_refclk_mode);
if (IS_ERR(wiz->pma_cmn_refclk_mode)) {
@@ -844,8 +893,6 @@ static int wiz_clock_init(struct wiz *wiz)
return ret;
}
wiz->input_clks[WIZ_CORE_REFCLK] = clk;
- /* Initialize CORE_REFCLK1 to the same clock reference to maintain old DT compatibility */
- wiz->input_clks[WIZ_CORE_REFCLK1] = clk;
rate = clk_get_rate(clk);
if (rate >= 100000000)
@@ -853,6 +900,25 @@ static int wiz_clock_init(struct wiz *wiz)
else
regmap_field_write(wiz->pma_cmn_refclk_int_mode, 0x3);
+ if (wiz->data->pma_cmn_refclk1_int_mode) {
+ clk = devm_clk_get(dev, "core_ref1_clk");
+ if (IS_ERR(clk)) {
+ dev_err(dev, "core_ref1_clk clock not found\n");
+ ret = PTR_ERR(clk);
+ return ret;
+ }
+ wiz->input_clks[WIZ_CORE_REFCLK1] = clk;
+
+ rate = clk_get_rate(clk);
+ if (rate >= 100000000)
+ regmap_field_write(wiz->pma_cmn_refclk1_int_mode, 0x1);
+ else
+ regmap_field_write(wiz->pma_cmn_refclk1_int_mode, 0x3);
+ } else {
+ /* Initialize CORE_REFCLK1 to the same clock reference to maintain old DT compatibility */
+ wiz->input_clks[WIZ_CORE_REFCLK1] = clk;
+ }
+
clk = devm_clk_get(dev, "ext_ref_clk");
if (IS_ERR(clk)) {
dev_err(dev, "ext_ref_clk clock not found\n");
@@ -933,7 +999,7 @@ static int j721e_wiz_bind_of_clocks(struct wiz *wiz)
ofnode node;
int i, rc;
- if (type == AM64_WIZ_10G)
+ if (type == AM64_WIZ_10G || type == J784S4_WIZ_10G)
return j721e_wiz_bind_clocks(wiz);
div_clk_drv = lists_driver_lookup_name("wiz_div_clk");
@@ -1173,6 +1239,9 @@ static const struct udevice_id j721e_wiz_ids[] = {
{
.compatible = "ti,am64-wiz-10g", .data = (ulong)&am64_10g_data,
},
+ {
+ .compatible = "ti,j784s4-wiz-10g", .data = (ulong)&j784s4_wiz_10g,
+ },
{}
};
diff --git a/drivers/watchdog/omap_wdt.c b/drivers/watchdog/omap_wdt.c
index ca2bc7cfb59..f0e57b4f728 100644
--- a/drivers/watchdog/omap_wdt.c
+++ b/drivers/watchdog/omap_wdt.c
@@ -39,7 +39,7 @@
#include <common.h>
#include <log.h>
#include <watchdog.h>
-#include <asm/arch/hardware.h>
+#include <asm/ti-common/omap_wdt.h>
#include <asm/io.h>
#include <asm/processor.h>
#include <asm/arch/cpu.h>
generated by cgit v1.2.3 (git 2.0.4) at 2025-10-31 06:55:29 +0000