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-rw-r--r--drivers/clk/clk-uclass.c11
-rw-r--r--drivers/clk/kendryte/clk.c26
-rw-r--r--drivers/clk/kendryte/pll.c26
-rw-r--r--drivers/pwm/pwm-sifive.c21
4 files changed, 36 insertions, 48 deletions
diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c
index 4ab3c402ed8..53e7be764d3 100644
--- a/drivers/clk/clk-uclass.c
+++ b/drivers/clk/clk-uclass.c
@@ -14,6 +14,7 @@
#include <errno.h>
#include <log.h>
#include <malloc.h>
+#include <dm/device_compat.h>
#include <dm/device-internal.h>
#include <dm/devres.h>
#include <dm/read.h>
@@ -309,8 +310,9 @@ static int clk_set_default_rates(struct udevice *dev, int stage)
ret = clk_get_by_indexed_prop(dev, "assigned-clocks",
index, &clk);
if (ret) {
- debug("%s: could not get assigned clock %d for %s\n",
- __func__, index, dev_read_name(dev));
+ dev_dbg(dev,
+ "could not get assigned clock %d (err = %d)\n",
+ index, ret);
continue;
}
@@ -332,8 +334,9 @@ static int clk_set_default_rates(struct udevice *dev, int stage)
ret = clk_set_rate(c, rates[index]);
if (ret < 0) {
- debug("%s: failed to set rate on clock index %d (%ld) for %s\n",
- __func__, index, clk.id, dev_read_name(dev));
+ dev_warn(dev,
+ "failed to set rate on clock index %d (%ld) (error = %d)\n",
+ index, clk.id, ret);
break;
}
}
diff --git a/drivers/clk/kendryte/clk.c b/drivers/clk/kendryte/clk.c
index 3b674a998e3..2d6ac03693a 100644
--- a/drivers/clk/kendryte/clk.c
+++ b/drivers/clk/kendryte/clk.c
@@ -347,9 +347,7 @@ static const struct k210_comp_params k210_comps[] = {
#undef COMP_NOMUX_ID
#undef COMP_LIST
-static struct clk *k210_bypass_children = {
- NULL,
-};
+static struct clk *k210_bypass_children __section(.data);
/* Helper functions to create sub-clocks */
static struct clk_mux *k210_create_mux(const struct k210_mux_params *params,
@@ -475,7 +473,14 @@ cleanup_mux:
return comp;
}
-static bool probed;
+static bool __section(.data) probed;
+
+/* reset probed so we will probe again post-relocation */
+static int k210_clk_bind(struct udevice *dev)
+{
+ probed = false;
+ return 0;
+}
static int k210_clk_probe(struct udevice *dev)
{
@@ -528,14 +533,10 @@ static int k210_clk_probe(struct udevice *dev)
return -ENOMEM;
}
- {
- const struct k210_pll_params *params = &k210_plls[1];
-
+ pll = k210_create_pll(&k210_plls[1], base);
+ if (pll)
clk_dm(K210_CLK_PLL1,
- k210_register_pll("pll1", in0, base + params->off,
- base + params->lock_off, params->shift,
- params->width));
- }
+ k210_register_pll_struct("pll1", in0, pll));
/* PLL2 is muxed, so set up a composite clock */
mux = k210_create_mux(&k210_muxes[MUXIFY(K210_CLK_PLL2)], base);
@@ -647,7 +648,7 @@ static int k210_clk_probe(struct udevice *dev)
/* The MTIME register in CLINT runs at one 50th the CPU clock speed */
clk_dm(K210_CLK_CLINT,
- clk_register_fixed_factor(NULL, "clint", "cpu", 0, 1, 50));
+ clk_register_fixed_factor(NULL, "clint", "aclk", 0, 1, 50));
return 0;
}
@@ -662,5 +663,6 @@ U_BOOT_DRIVER(k210_clk) = {
.id = UCLASS_CLK,
.of_match = k210_clk_ids,
.ops = &k210_clk_ops,
+ .bind = k210_clk_bind,
.probe = k210_clk_probe,
};
diff --git a/drivers/clk/kendryte/pll.c b/drivers/clk/kendryte/pll.c
index ab6d75d585a..184f37aaf20 100644
--- a/drivers/clk/kendryte/pll.c
+++ b/drivers/clk/kendryte/pll.c
@@ -512,7 +512,8 @@ static int k210_pll_enable(struct clk *clk)
struct k210_pll *pll = to_k210_pll(clk);
u32 reg = readl(pll->reg);
- if ((reg | K210_PLL_PWRD) && !(reg | K210_PLL_RESET))
+ if ((reg & K210_PLL_PWRD) && (reg & K210_PLL_EN) &&
+ !(reg & K210_PLL_RESET))
return 0;
reg |= K210_PLL_PWRD;
@@ -531,6 +532,7 @@ static int k210_pll_enable(struct clk *clk)
k210_pll_waitfor_lock(pll);
reg &= ~K210_PLL_BYPASS;
+ reg |= K210_PLL_EN;
writel(reg, pll->reg);
return 0;
@@ -550,6 +552,7 @@ static int k210_pll_disable(struct clk *clk)
writel(reg, pll->reg);
reg &= ~K210_PLL_PWRD;
+ reg &= ~K210_PLL_EN;
writel(reg, pll->reg);
return 0;
}
@@ -575,27 +578,6 @@ struct clk *k210_register_pll_struct(const char *name, const char *parent_name,
return clk;
}
-struct clk *k210_register_pll(const char *name, const char *parent_name,
- void __iomem *reg, void __iomem *lock, u8 shift,
- u8 width)
-{
- struct clk *clk;
- struct k210_pll *pll;
-
- pll = kzalloc(sizeof(*pll), GFP_KERNEL);
- if (!pll)
- return ERR_PTR(-ENOMEM);
- pll->reg = reg;
- pll->lock = lock;
- pll->shift = shift;
- pll->width = width;
-
- clk = k210_register_pll_struct(name, parent_name, pll);
- if (IS_ERR(clk))
- kfree(pll);
- return clk;
-}
-
U_BOOT_DRIVER(k210_pll) = {
.name = CLK_K210_PLL,
.id = UCLASS_CLK,
diff --git a/drivers/pwm/pwm-sifive.c b/drivers/pwm/pwm-sifive.c
index 01212d630a9..b9813a3b6bb 100644
--- a/drivers/pwm/pwm-sifive.c
+++ b/drivers/pwm/pwm-sifive.c
@@ -38,6 +38,9 @@
#define PWM_SIFIVE_SIZE_PWMCMP 4
#define PWM_SIFIVE_CMPWIDTH 16
+#define PWM_SIFIVE_CHANNEL_ENABLE_VAL 0
+#define PWM_SIFIVE_CHANNEL_DISABLE_VAL 0xffff
+
DECLARE_GLOBAL_DATA_PTR;
struct pwm_sifive_regs {
@@ -77,7 +80,7 @@ static int pwm_sifive_set_config(struct udevice *dev, uint channel,
*/
scale_pow = lldiv((uint64_t)priv->freq * period_ns, 1000000000);
scale = clamp(ilog2(scale_pow) - PWM_SIFIVE_CMPWIDTH, 0, 0xf);
- val |= FIELD_PREP(PWM_SIFIVE_PWMCFG_SCALE, scale);
+ val |= (FIELD_PREP(PWM_SIFIVE_PWMCFG_SCALE, scale) | PWM_SIFIVE_PWMCFG_EN_ALWAYS);
/*
* The problem of output producing mixed setting as mentioned at top,
@@ -88,6 +91,7 @@ static int pwm_sifive_set_config(struct udevice *dev, uint channel,
num = (u64)duty_ns * (1U << PWM_SIFIVE_CMPWIDTH);
frac = DIV_ROUND_CLOSEST_ULL(num, period_ns);
frac = min(frac, (1U << PWM_SIFIVE_CMPWIDTH) - 1);
+ frac = (1U << PWM_SIFIVE_CMPWIDTH) - 1 - frac;
writel(val, priv->base + regs->cfg);
writel(frac, priv->base + regs->cmp0 + channel *
@@ -100,18 +104,15 @@ static int pwm_sifive_set_enable(struct udevice *dev, uint channel, bool enable)
{
struct pwm_sifive_priv *priv = dev_get_priv(dev);
const struct pwm_sifive_regs *regs = &priv->data->regs;
- u32 val;
debug("%s: Enable '%s'\n", __func__, dev->name);
- if (enable) {
- val = readl(priv->base + regs->cfg);
- val |= PWM_SIFIVE_PWMCFG_EN_ALWAYS;
- writel(val, priv->base + regs->cfg);
- } else {
- writel(0, priv->base + regs->cmp0 + channel *
- PWM_SIFIVE_SIZE_PWMCMP);
- }
+ if (enable)
+ writel(PWM_SIFIVE_CHANNEL_ENABLE_VAL, priv->base +
+ regs->cmp0 + channel * PWM_SIFIVE_SIZE_PWMCMP);
+ else
+ writel(PWM_SIFIVE_CHANNEL_DISABLE_VAL, priv->base +
+ regs->cmp0 + channel * PWM_SIFIVE_SIZE_PWMCMP);
return 0;
}
generated by cgit v1.2.3 (git 2.0.4) at 2025-08-04 09:46:27 +0000