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-rw-r--r--drivers/Makefile3
-rw-r--r--drivers/clk/clk_fixed_rate.c1
-rw-r--r--drivers/clk/clk_zynqmp.c2
-rw-r--r--drivers/firmware/firmware-zynqmp.c2
-rw-r--r--drivers/fpga/zynqmppl.c10
-rw-r--r--drivers/i2c/i2c-cdns.c2
-rw-r--r--drivers/mailbox/zynqmp-ipi.c2
-rw-r--r--drivers/mmc/zynq_sdhci.c2
-rw-r--r--drivers/mtd/nand/raw/Kconfig2
-rw-r--r--drivers/mtd/nand/raw/arasan_nfc.c2
-rw-r--r--drivers/mtd/nand/raw/zynq_nand.c2
-rw-r--r--drivers/net/xilinx_axi_emac.c48
-rw-r--r--drivers/net/zynq_gem.c10
-rw-r--r--drivers/serial/Kconfig4
-rw-r--r--drivers/serial/serial_xuartlite.c64
-rw-r--r--drivers/spi/Kconfig3
-rw-r--r--drivers/usb/host/Kconfig3
17 files changed, 106 insertions, 56 deletions
diff --git a/drivers/Makefile b/drivers/Makefile
index 33126b2da7b..9eb51453e57 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -30,6 +30,7 @@ obj-$(CONFIG_$(SPL_TPL_)TPM) += tpm/
obj-$(CONFIG_$(SPL_TPL_)ACPI_PMC) += power/acpi_pmc/
obj-$(CONFIG_$(SPL_)BOARD) += board/
obj-$(CONFIG_XEN) += xen/
+obj-$(CONFIG_$(SPL_)FPGA) += fpga/
ifndef CONFIG_TPL_BUILD
ifdef CONFIG_SPL_BUILD
@@ -60,7 +61,6 @@ obj-$(CONFIG_SPL_USB_HOST_SUPPORT) += usb/host/
obj-$(CONFIG_OMAP_USB_PHY) += usb/phy/
obj-$(CONFIG_SPL_SATA_SUPPORT) += ata/ scsi/
obj-$(CONFIG_HAVE_BLOCK_DEVICE) += block/
-obj-$(CONFIG_SPL_FPGA_SUPPORT) += fpga/
obj-$(CONFIG_SPL_THERMAL) += thermal/
endif
@@ -85,7 +85,6 @@ obj-y += cache/
obj-$(CONFIG_CPU) += cpu/
obj-y += crypto/
obj-$(CONFIG_FASTBOOT) += fastboot/
-obj-$(CONFIG_FPGA) += fpga/
obj-y += misc/
obj-$(CONFIG_MMC) += mmc/
obj-$(CONFIG_NVME) += nvme/
diff --git a/drivers/clk/clk_fixed_rate.c b/drivers/clk/clk_fixed_rate.c
index 2c20eddb0b5..55e1f8caa52 100644
--- a/drivers/clk/clk_fixed_rate.c
+++ b/drivers/clk/clk_fixed_rate.c
@@ -53,4 +53,5 @@ U_BOOT_DRIVER(clk_fixed_rate) = {
.ofdata_to_platdata = clk_fixed_rate_ofdata_to_platdata,
.platdata_auto_alloc_size = sizeof(struct clk_fixed_rate),
.ops = &clk_fixed_rate_ops,
+ .flags = DM_FLAG_PRE_RELOC,
};
diff --git a/drivers/clk/clk_zynqmp.c b/drivers/clk/clk_zynqmp.c
index 2313ac0bc04..77951197566 100644
--- a/drivers/clk/clk_zynqmp.c
+++ b/drivers/clk/clk_zynqmp.c
@@ -710,7 +710,7 @@ static const struct udevice_id zynqmp_clk_ids[] = {
};
U_BOOT_DRIVER(zynqmp_clk) = {
- .name = "zynqmp-clk",
+ .name = "zynqmp_clk",
.id = UCLASS_CLK,
.of_match = zynqmp_clk_ids,
.probe = zynqmp_clk_probe,
diff --git a/drivers/firmware/firmware-zynqmp.c b/drivers/firmware/firmware-zynqmp.c
index 903a8f58782..7583f24a200 100644
--- a/drivers/firmware/firmware-zynqmp.c
+++ b/drivers/firmware/firmware-zynqmp.c
@@ -202,6 +202,6 @@ static const struct udevice_id zynqmp_firmware_ids[] = {
U_BOOT_DRIVER(zynqmp_firmware) = {
.id = UCLASS_FIRMWARE,
- .name = "zynqmp-firmware",
+ .name = "zynqmp_firmware",
.of_match = zynqmp_firmware_ids,
};
diff --git a/drivers/fpga/zynqmppl.c b/drivers/fpga/zynqmppl.c
index 5b103cfeaf1..8ce140a2e1a 100644
--- a/drivers/fpga/zynqmppl.c
+++ b/drivers/fpga/zynqmppl.c
@@ -231,11 +231,11 @@ static int zynqmp_load(xilinx_desc *desc, const void *buf, size_t bsize,
buf_hi = upper_32_bits(bin_buf);
if (xilfpga_old)
- ret = xilinx_pm_request(ZYNQMP_SIP_SVC_PM_FPGA_LOAD, buf_lo,
+ ret = xilinx_pm_request(PM_FPGA_LOAD, buf_lo,
buf_hi, (u32)(uintptr_t)bsizeptr,
bstype, ret_payload);
else
- ret = xilinx_pm_request(ZYNQMP_SIP_SVC_PM_FPGA_LOAD, buf_lo,
+ ret = xilinx_pm_request(PM_FPGA_LOAD, buf_lo,
buf_hi, (u32)bsize, 0, ret_payload);
if (ret)
@@ -277,7 +277,7 @@ static int zynqmp_loads(xilinx_desc *desc, const void *buf, size_t bsize,
buf_lo = lower_32_bits((ulong)buf);
buf_hi = upper_32_bits((ulong)buf);
- ret = xilinx_pm_request(ZYNQMP_SIP_SVC_PM_FPGA_LOAD, buf_lo,
+ ret = xilinx_pm_request(PM_FPGA_LOAD, buf_lo,
buf_hi,
(u32)(uintptr_t)fpga_sec_info->userkey_addr,
flag, ret_payload);
@@ -295,7 +295,7 @@ static int zynqmp_pcap_info(xilinx_desc *desc)
int ret;
u32 ret_payload[PAYLOAD_ARG_CNT];
- ret = xilinx_pm_request(ZYNQMP_SIP_SVC_PM_FPGA_STATUS, 0, 0, 0,
+ ret = xilinx_pm_request(PM_FPGA_GET_STATUS, 0, 0, 0,
0, ret_payload);
if (!ret)
printf("PCAP status\t0x%x\n", ret_payload[1]);
@@ -305,7 +305,7 @@ static int zynqmp_pcap_info(xilinx_desc *desc)
struct xilinx_fpga_op zynqmp_op = {
.load = zynqmp_load,
-#if defined CONFIG_CMD_FPGA_LOAD_SECURE
+#if defined(CONFIG_CMD_FPGA_LOAD_SECURE) && !defined(CONFIG_SPL_BUILD)
.loads = zynqmp_loads,
#endif
.info = zynqmp_pcap_info,
diff --git a/drivers/i2c/i2c-cdns.c b/drivers/i2c/i2c-cdns.c
index 024c63c4eae..7144d39984e 100644
--- a/drivers/i2c/i2c-cdns.c
+++ b/drivers/i2c/i2c-cdns.c
@@ -500,7 +500,7 @@ static const struct udevice_id cdns_i2c_of_match[] = {
};
U_BOOT_DRIVER(cdns_i2c) = {
- .name = "i2c-cdns",
+ .name = "i2c_cdns",
.id = UCLASS_I2C,
.of_match = cdns_i2c_of_match,
.ofdata_to_platdata = cdns_i2c_ofdata_to_platdata,
diff --git a/drivers/mailbox/zynqmp-ipi.c b/drivers/mailbox/zynqmp-ipi.c
index 746377e557c..9483ed9cefc 100644
--- a/drivers/mailbox/zynqmp-ipi.c
+++ b/drivers/mailbox/zynqmp-ipi.c
@@ -133,7 +133,7 @@ struct mbox_ops zynqmp_ipi_mbox_ops = {
};
U_BOOT_DRIVER(zynqmp_ipi) = {
- .name = "zynqmp-ipi",
+ .name = "zynqmp_ipi",
.id = UCLASS_MAILBOX,
.of_match = zynqmp_ipi_ids,
.probe = zynqmp_ipi_probe,
diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c
index e9381b94930..775c17baac5 100644
--- a/drivers/mmc/zynq_sdhci.c
+++ b/drivers/mmc/zynq_sdhci.c
@@ -191,7 +191,7 @@ static void arasan_sdhci_set_control_reg(struct sdhci_host *host)
#if defined(CONFIG_ARCH_ZYNQMP)
const struct sdhci_ops arasan_ops = {
- .platform_execute_tuning = &arasan_sdhci_execute_tuning,
+ .platform_execute_tuning = &arasan_sdhci_execute_tuning,
.set_delay = &arasan_sdhci_set_tapdelay,
.set_control_reg = &arasan_sdhci_set_control_reg,
};
diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig
index 06b2ff972ca..df4cbd52cf5 100644
--- a/drivers/mtd/nand/raw/Kconfig
+++ b/drivers/mtd/nand/raw/Kconfig
@@ -233,7 +233,7 @@ endif
config NAND_ARASAN
bool "Configure Arasan Nand"
select SYS_NAND_SELF_INIT
- select DM_MTD
+ depends on DM_MTD
imply CMD_NAND
help
This enables Nand driver support for Arasan nand flash
diff --git a/drivers/mtd/nand/raw/arasan_nfc.c b/drivers/mtd/nand/raw/arasan_nfc.c
index 6c1d64054c6..0615e503780 100644
--- a/drivers/mtd/nand/raw/arasan_nfc.c
+++ b/drivers/mtd/nand/raw/arasan_nfc.c
@@ -1306,7 +1306,7 @@ static const struct udevice_id arasan_nand_dt_ids[] = {
};
U_BOOT_DRIVER(arasan_nand) = {
- .name = "arasan-nand",
+ .name = "arasan_nand",
.id = UCLASS_MTD,
.of_match = arasan_nand_dt_ids,
.probe = arasan_probe,
diff --git a/drivers/mtd/nand/raw/zynq_nand.c b/drivers/mtd/nand/raw/zynq_nand.c
index fa594552109..92db2aa19c8 100644
--- a/drivers/mtd/nand/raw/zynq_nand.c
+++ b/drivers/mtd/nand/raw/zynq_nand.c
@@ -1282,7 +1282,7 @@ static const struct udevice_id zynq_nand_dt_ids[] = {
};
U_BOOT_DRIVER(zynq_nand) = {
- .name = "zynq-nand",
+ .name = "zynq_nand",
.id = UCLASS_MTD,
.of_match = zynq_nand_dt_ids,
.probe = zynq_nand_probe,
diff --git a/drivers/net/xilinx_axi_emac.c b/drivers/net/xilinx_axi_emac.c
index 99d4d85c527..8af37112046 100644
--- a/drivers/net/xilinx_axi_emac.c
+++ b/drivers/net/xilinx_axi_emac.c
@@ -101,10 +101,10 @@ struct axidma_priv {
/* BD descriptors */
struct axidma_bd {
- u32 next; /* Next descriptor pointer */
- u32 reserved1;
- u32 phys; /* Buffer address */
- u32 reserved2;
+ u32 next_desc; /* Next descriptor pointer */
+ u32 next_desc_msb;
+ u32 buf_addr; /* Buffer address */
+ u32 buf_addr_msb;
u32 reserved3;
u32 reserved4;
u32 cntrl; /* Control */
@@ -182,7 +182,7 @@ static inline int mdio_wait(struct axi_regs *regs)
static inline void axienet_dma_write(struct axidma_bd *bd, u32 *desc)
{
#if defined(CONFIG_PHYS_64BIT)
- writeq(bd, desc);
+ writeq((unsigned long)bd, desc);
#else
writel((u32)bd, desc);
#endif
@@ -492,15 +492,19 @@ static int axiemac_start(struct udevice *dev)
/* Setup the BD. */
memset(&rx_bd, 0, sizeof(rx_bd));
- rx_bd.next = (u32)&rx_bd;
- rx_bd.phys = (u32)&rxframe;
+ rx_bd.next_desc = lower_32_bits((unsigned long)&rx_bd);
+ rx_bd.buf_addr = lower_32_bits((unsigned long)&rxframe);
+#if defined(CONFIG_PHYS_64BIT)
+ rx_bd.next_desc_msb = upper_32_bits((unsigned long)&rx_bd);
+ rx_bd.buf_addr_msb = upper_32_bits((unsigned long)&rxframe);
+#endif
rx_bd.cntrl = sizeof(rxframe);
/* Flush the last BD so DMA core could see the updates */
- flush_cache((u32)&rx_bd, sizeof(rx_bd));
+ flush_cache((phys_addr_t)&rx_bd, sizeof(rx_bd));
/* It is necessary to flush rxframe because if you don't do it
* then cache can contain uninitialized data */
- flush_cache((u32)&rxframe, sizeof(rxframe));
+ flush_cache((phys_addr_t)&rxframe, sizeof(rxframe));
/* Start the hardware */
temp = readl(&priv->dmarx->control);
@@ -534,19 +538,23 @@ static int axiemac_send(struct udevice *dev, void *ptr, int len)
len = PKTSIZE_ALIGN;
/* Flush packet to main memory to be trasfered by DMA */
- flush_cache((u32)ptr, len);
+ flush_cache((phys_addr_t)ptr, len);
/* Setup Tx BD */
memset(&tx_bd, 0, sizeof(tx_bd));
/* At the end of the ring, link the last BD back to the top */
- tx_bd.next = (u32)&tx_bd;
- tx_bd.phys = (u32)ptr;
+ tx_bd.next_desc = lower_32_bits((unsigned long)&tx_bd);
+ tx_bd.buf_addr = lower_32_bits((unsigned long)ptr);
+#if defined(CONFIG_PHYS_64BIT)
+ tx_bd.next_desc_msb = upper_32_bits((unsigned long)&tx_bd);
+ tx_bd.buf_addr_msb = upper_32_bits((unsigned long)ptr);
+#endif
/* Save len */
tx_bd.cntrl = len | XAXIDMA_BD_CTRL_TXSOF_MASK |
XAXIDMA_BD_CTRL_TXEOF_MASK;
/* Flush the last BD so DMA core could see the updates */
- flush_cache((u32)&tx_bd, sizeof(tx_bd));
+ flush_cache((phys_addr_t)&tx_bd, sizeof(tx_bd));
if (readl(&priv->dmatx->status) & XAXIDMA_HALTED_MASK) {
u32 temp;
@@ -637,16 +645,20 @@ static int axiemac_free_pkt(struct udevice *dev, uchar *packet, int length)
/* Setup RxBD */
/* Clear the whole buffer and setup it again - all flags are cleared */
memset(&rx_bd, 0, sizeof(rx_bd));
- rx_bd.next = (u32)&rx_bd;
- rx_bd.phys = (u32)&rxframe;
+ rx_bd.next_desc = lower_32_bits((unsigned long)&rx_bd);
+ rx_bd.buf_addr = lower_32_bits((unsigned long)&rxframe);
+#if defined(CONFIG_PHYS_64BIT)
+ rx_bd.next_desc_msb = upper_32_bits((unsigned long)&rx_bd);
+ rx_bd.buf_addr_msb = upper_32_bits((unsigned long)&rxframe);
+#endif
rx_bd.cntrl = sizeof(rxframe);
/* Write bd to HW */
- flush_cache((u32)&rx_bd, sizeof(rx_bd));
+ flush_cache((phys_addr_t)&rx_bd, sizeof(rx_bd));
/* It is necessary to flush rxframe because if you don't do it
* then cache will contain previous packet */
- flush_cache((u32)&rxframe, sizeof(rxframe));
+ flush_cache((phys_addr_t)&rxframe, sizeof(rxframe));
/* Rx BD is ready - start again */
axienet_dma_write(&rx_bd, &priv->dmarx->tail);
@@ -738,7 +750,7 @@ static int axi_emac_ofdata_to_platdata(struct udevice *dev)
return -EINVAL;
}
/* RX channel offset is 0x30 */
- priv->dmarx = (struct axidma_reg *)((u32)priv->dmatx + 0x30);
+ priv->dmarx = (struct axidma_reg *)((phys_addr_t)priv->dmatx + 0x30);
priv->phyaddr = -1;
diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c
index da4b6fba9ff..8afec8bbfcf 100644
--- a/drivers/net/zynq_gem.c
+++ b/drivers/net/zynq_gem.c
@@ -758,6 +758,9 @@ static int zynq_gem_ofdata_to_platdata(struct udevice *dev)
if (!dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0,
&phandle_args)) {
+ fdt_addr_t addr;
+ ofnode parent;
+
debug("phy-handle does exist %s\n", dev->name);
priv->phyaddr = ofnode_read_u32_default(phandle_args.node,
"reg", -1);
@@ -765,6 +768,13 @@ static int zynq_gem_ofdata_to_platdata(struct udevice *dev)
priv->max_speed = ofnode_read_u32_default(phandle_args.node,
"max-speed",
SPEED_1000);
+
+ parent = ofnode_get_parent(phandle_args.node);
+ addr = ofnode_get_addr(parent);
+ if (addr != FDT_ADDR_T_NONE) {
+ debug("MDIO bus not found %s\n", dev->name);
+ priv->mdiobase = (struct zynq_gem_regs *)addr;
+ }
}
phy_mode = dev_read_prop(dev, "phy-mode", NULL);
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index e344677f91f..b4805a2e4ea 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -734,7 +734,7 @@ config UNIPHIER_SERIAL
config XILINX_UARTLITE
bool "Xilinx Uarlite support"
- depends on DM_SERIAL && (MICROBLAZE || ARCH_ZYNQ || ARCH_ZYNQMP || 4xx)
+ depends on DM_SERIAL
help
If you have a Xilinx based board and want to use the uartlite
serial ports, say Y to this option. If unsure, say N.
@@ -802,7 +802,7 @@ config STM32_SERIAL
config ZYNQ_SERIAL
bool "Cadence (Xilinx Zynq) UART support"
- depends on DM_SERIAL && (MICROBLAZE || ARCH_ZYNQ || ARCH_ZYNQMP || ARCH_ZYNQMP_R5)
+ depends on DM_SERIAL
help
This driver supports the Cadence UART. It is found e.g. in Xilinx
Zynq/ZynqMP.
diff --git a/drivers/serial/serial_xuartlite.c b/drivers/serial/serial_xuartlite.c
index 5116d13751d..236ab860ad8 100644
--- a/drivers/serial/serial_xuartlite.c
+++ b/drivers/serial/serial_xuartlite.c
@@ -23,6 +23,8 @@
#define ULITE_CONTROL_RST_TX 0x01
#define ULITE_CONTROL_RST_RX 0x02
+static bool little_endian;
+
struct uartlite {
unsigned int rx_fifo;
unsigned int tx_fifo;
@@ -34,15 +36,31 @@ struct uartlite_platdata {
struct uartlite *regs;
};
+static u32 uart_in32(void __iomem *addr)
+{
+ if (little_endian)
+ return in_le32(addr);
+ else
+ return in_be32(addr);
+}
+
+static void uart_out32(void __iomem *addr, u32 val)
+{
+ if (little_endian)
+ out_le32(addr, val);
+ else
+ out_be32(addr, val);
+}
+
static int uartlite_serial_putc(struct udevice *dev, const char ch)
{
struct uartlite_platdata *plat = dev_get_platdata(dev);
struct uartlite *regs = plat->regs;
- if (in_be32(&regs->status) & SR_TX_FIFO_FULL)
+ if (uart_in32(&regs->status) & SR_TX_FIFO_FULL)
return -EAGAIN;
- out_be32(&regs->tx_fifo, ch & 0xff);
+ uart_out32(&regs->tx_fifo, ch & 0xff);
return 0;
}
@@ -52,10 +70,10 @@ static int uartlite_serial_getc(struct udevice *dev)
struct uartlite_platdata *plat = dev_get_platdata(dev);
struct uartlite *regs = plat->regs;
- if (!(in_be32(&regs->status) & SR_RX_FIFO_VALID_DATA))
+ if (!(uart_in32(&regs->status) & SR_RX_FIFO_VALID_DATA))
return -EAGAIN;
- return in_be32(&regs->rx_fifo) & 0xff;
+ return uart_in32(&regs->rx_fifo) & 0xff;
}
static int uartlite_serial_pending(struct udevice *dev, bool input)
@@ -64,19 +82,26 @@ static int uartlite_serial_pending(struct udevice *dev, bool input)
struct uartlite *regs = plat->regs;
if (input)
- return in_be32(&regs->status) & SR_RX_FIFO_VALID_DATA;
+ return uart_in32(&regs->status) & SR_RX_FIFO_VALID_DATA;
- return !(in_be32(&regs->status) & SR_TX_FIFO_EMPTY);
+ return !(uart_in32(&regs->status) & SR_TX_FIFO_EMPTY);
}
static int uartlite_serial_probe(struct udevice *dev)
{
struct uartlite_platdata *plat = dev_get_platdata(dev);
struct uartlite *regs = plat->regs;
-
- out_be32(&regs->control, 0);
- out_be32(&regs->control, ULITE_CONTROL_RST_RX | ULITE_CONTROL_RST_TX);
- in_be32(&regs->control);
+ int ret;
+
+ uart_out32(&regs->control, 0);
+ uart_out32(&regs->control, ULITE_CONTROL_RST_RX | ULITE_CONTROL_RST_TX);
+ ret = uart_in32(&regs->status);
+ /* Endianness detection */
+ if ((ret & SR_TX_FIFO_EMPTY) != SR_TX_FIFO_EMPTY) {
+ little_endian = true;
+ uart_out32(&regs->control, ULITE_CONTROL_RST_RX |
+ ULITE_CONTROL_RST_TX);
+ }
return 0;
}
@@ -119,20 +144,27 @@ U_BOOT_DRIVER(serial_uartlite) = {
static inline void _debug_uart_init(void)
{
struct uartlite *regs = (struct uartlite *)CONFIG_DEBUG_UART_BASE;
-
- out_be32(&regs->control, 0);
- out_be32(&regs->control, ULITE_CONTROL_RST_RX | ULITE_CONTROL_RST_TX);
- in_be32(&regs->control);
+ int ret;
+
+ uart_out32(&regs->control, 0);
+ uart_out32(&regs->control, ULITE_CONTROL_RST_RX | ULITE_CONTROL_RST_TX);
+ uart_in32(&regs->status);
+ /* Endianness detection */
+ if ((ret & SR_TX_FIFO_EMPTY) != SR_TX_FIFO_EMPTY) {
+ little_endian = true;
+ uart_out32(&regs->control, ULITE_CONTROL_RST_RX |
+ ULITE_CONTROL_RST_TX);
+ }
}
static inline void _debug_uart_putc(int ch)
{
struct uartlite *regs = (struct uartlite *)CONFIG_DEBUG_UART_BASE;
- while (in_be32(&regs->status) & SR_TX_FIFO_FULL)
+ while (uart_in32(&regs->status) & SR_TX_FIFO_FULL)
;
- out_be32(&regs->tx_fifo, ch & 0xff);
+ uart_out32(&regs->tx_fifo, ch & 0xff);
}
DEBUG_UART_FUNCS
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 3fc2d0674ae..5df97c80fa5 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -407,7 +407,6 @@ config XILINX_SPI
config ZYNQ_SPI
bool "Zynq SPI driver"
- depends on ARCH_ZYNQ || ARCH_ZYNQMP || ARCH_VERSAL
help
Enable the Zynq SPI driver. This driver can be used to
access the SPI NOR flash on platforms embedding this Zynq
@@ -415,7 +414,6 @@ config ZYNQ_SPI
config ZYNQ_QSPI
bool "Zynq QSPI driver"
- depends on ARCH_ZYNQ
imply SPI_FLASH_BAR
help
Enable the Zynq Quad-SPI (QSPI) driver. This driver can be
@@ -425,7 +423,6 @@ config ZYNQ_QSPI
config ZYNQMP_GQSPI
bool "Configure ZynqMP Generic QSPI"
- depends on ARCH_ZYNQMP || ARCH_VERSAL
help
This option is used to enable ZynqMP QSPI controller driver which
is used to communicate with qspi flash devices.
diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index 1c374a7bd80..4eb7b34e245 100644
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -200,8 +200,7 @@ config USB_EHCI_TEGRA
config USB_EHCI_ZYNQ
bool "Support for Xilinx Zynq on-chip EHCI USB controller"
- depends on ARCH_ZYNQ
- default y
+ default y if ARCH_ZYNQ
---help---
Enable support for Zynq on-chip EHCI USB controller
generated by cgit v1.2.3 (git 2.0.4) at 2025-10-26 16:31:32 +0000