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-rw-r--r--drivers/clk/imx/clk-imx8.c2
-rw-r--r--drivers/clk/imx/clk-imx8qm.c2
-rw-r--r--drivers/clk/imx/clk-imx8qxp.c2
-rw-r--r--drivers/cpu/Kconfig6
-rw-r--r--drivers/cpu/Makefile1
-rw-r--r--drivers/cpu/imx8_cpu.c142
-rw-r--r--drivers/cpu/imx9_cpu.c224
-rw-r--r--drivers/ddr/imx/imx9/Kconfig2
-rw-r--r--drivers/ddr/imx/imx9/ddr_init.c289
-rw-r--r--drivers/ddr/imx/phy/ddrphy_utils.c3
-rw-r--r--drivers/ddr/imx/phy/helper.c5
-rw-r--r--drivers/misc/imx8/fuse.c2
-rw-r--r--drivers/misc/imx8/scu.c2
-rw-r--r--drivers/misc/imx8/scu_api.c2
-rw-r--r--drivers/pinctrl/nxp/pinctrl-scu.c2
-rw-r--r--drivers/power/domain/imx8-power-domain-legacy.c2
-rw-r--r--drivers/power/domain/imx8-power-domain.c2
-rw-r--r--drivers/serial/Kconfig8
-rw-r--r--drivers/serial/Makefile1
-rw-r--r--drivers/serial/serial_mxs.c129
-rw-r--r--drivers/thermal/Kconfig6
-rw-r--r--drivers/thermal/imx_scu_thermal.c2
-rw-r--r--drivers/thermal/imx_tmu.c226
-rw-r--r--drivers/watchdog/ulp_wdog.c2
24 files changed, 994 insertions, 70 deletions
diff --git a/drivers/clk/imx/clk-imx8.c b/drivers/clk/imx/clk-imx8.c
index 24bdab28aa4..ceeead34349 100644
--- a/drivers/clk/imx/clk-imx8.c
+++ b/drivers/clk/imx/clk-imx8.c
@@ -9,7 +9,7 @@
#include <dm.h>
#include <log.h>
#include <malloc.h>
-#include <asm/arch/sci/sci.h>
+#include <firmware/imx/sci/sci.h>
#include <asm/arch/clock.h>
#include <dt-bindings/clock/imx8qxp-clock.h>
#include <dt-bindings/soc/imx_rsrc.h>
diff --git a/drivers/clk/imx/clk-imx8qm.c b/drivers/clk/imx/clk-imx8qm.c
index b874915ba6a..6c05d07c340 100644
--- a/drivers/clk/imx/clk-imx8qm.c
+++ b/drivers/clk/imx/clk-imx8qm.c
@@ -8,7 +8,7 @@
#include <clk-uclass.h>
#include <dm.h>
#include <log.h>
-#include <asm/arch/sci/sci.h>
+#include <firmware/imx/sci/sci.h>
#include <asm/arch/clock.h>
#include <dt-bindings/clock/imx8qm-clock.h>
#include <dt-bindings/soc/imx_rsrc.h>
diff --git a/drivers/clk/imx/clk-imx8qxp.c b/drivers/clk/imx/clk-imx8qxp.c
index d580b437221..8bf7e325481 100644
--- a/drivers/clk/imx/clk-imx8qxp.c
+++ b/drivers/clk/imx/clk-imx8qxp.c
@@ -8,7 +8,7 @@
#include <clk-uclass.h>
#include <dm.h>
#include <log.h>
-#include <asm/arch/sci/sci.h>
+#include <firmware/imx/sci/sci.h>
#include <asm/arch/clock.h>
#include <dt-bindings/clock/imx8qxp-clock.h>
#include <dt-bindings/soc/imx_rsrc.h>
diff --git a/drivers/cpu/Kconfig b/drivers/cpu/Kconfig
index 3bf04105e5e..1c3c810651e 100644
--- a/drivers/cpu/Kconfig
+++ b/drivers/cpu/Kconfig
@@ -7,6 +7,12 @@ config CPU
they can work correctly in the OS. This provides a framework for
finding out information about available CPUs and making changes.
+config CPU_IMX
+ bool "Enable i.MX CPU driver"
+ depends on CPU && ARM64
+ help
+ Support CPU cores for SoCs of the i.MX series.
+
config CPU_MPC83XX
bool "Enable MPC83xx CPU driver"
depends on CPU && MPC83xx
diff --git a/drivers/cpu/Makefile b/drivers/cpu/Makefile
index 3b38ba9c589..d4bbf6fa5e0 100644
--- a/drivers/cpu/Makefile
+++ b/drivers/cpu/Makefile
@@ -10,6 +10,7 @@ obj-$(CONFIG_ARCH_BMIPS) += bmips_cpu.o
obj-$(CONFIG_ARCH_IMX8) += imx8_cpu.o
obj-$(CONFIG_ARCH_AT91) += at91_cpu.o
obj-$(CONFIG_ARCH_MEDIATEK) += mtk_cpu.o
+obj-$(CONFIG_CPU_IMX) += imx8_cpu.o
obj-$(CONFIG_CPU_MPC83XX) += mpc83xx_cpu.o
obj-$(CONFIG_CPU_RISCV) += riscv_cpu.o
obj-$(CONFIG_CPU_MICROBLAZE) += microblaze_cpu.o
diff --git a/drivers/cpu/imx8_cpu.c b/drivers/cpu/imx8_cpu.c
index b8eb2d28006..98ff95f5ff5 100644
--- a/drivers/cpu/imx8_cpu.c
+++ b/drivers/cpu/imx8_cpu.c
@@ -9,11 +9,13 @@
#include <thermal.h>
#include <asm/global_data.h>
#include <asm/system.h>
-#include <asm/arch/sci/sci.h>
+#include <firmware/imx/sci/sci.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch-imx/cpu.h>
#include <asm/armv8/cpu.h>
+#include <imx_thermal.h>
#include <linux/bitops.h>
+#include <linux/clk-provider.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -27,30 +29,57 @@ struct cpu_imx_plat {
u32 mpidr;
};
-const char *get_imx8_type(u32 imxtype)
+static const char *get_imx_type_str(u32 imxtype)
{
switch (imxtype) {
case MXC_CPU_IMX8QXP:
case MXC_CPU_IMX8QXP_A0:
- return "QXP";
+ return "8QXP";
case MXC_CPU_IMX8QM:
- return "QM";
+ return "8QM";
+ case MXC_CPU_IMX93:
+ return "93(52)";/* iMX93 Dual core with NPU */
+ case MXC_CPU_IMX9351:
+ return "93(51)";/* iMX93 Single core with NPU */
+ case MXC_CPU_IMX9332:
+ return "93(32)";/* iMX93 Dual core without NPU */
+ case MXC_CPU_IMX9331:
+ return "93(31)";/* iMX93 Single core without NPU */
+ case MXC_CPU_IMX9322:
+ return "93(22)";/* iMX93 9x9 Dual core */
+ case MXC_CPU_IMX9321:
+ return "93(21)";/* iMX93 9x9 Single core */
+ case MXC_CPU_IMX9312:
+ return "93(12)";/* iMX93 9x9 Dual core without NPU */
+ case MXC_CPU_IMX9311:
+ return "93(11)";/* iMX93 9x9 Single core without NPU */
default:
return "??";
}
}
-const char *get_imx8_rev(u32 rev)
+static const char *get_imx_rev_str(u32 rev)
{
- switch (rev) {
- case CHIP_REV_A:
- return "A";
- case CHIP_REV_B:
- return "B";
- case CHIP_REV_C:
- return "C";
- default:
- return "?";
+ static char revision[4];
+
+ if (IS_ENABLED(CONFIG_IMX8)) {
+ switch (rev) {
+ case CHIP_REV_A:
+ return "A";
+ case CHIP_REV_B:
+ return "B";
+ case CHIP_REV_C:
+ return "C";
+ default:
+ return "?";
+ }
+ } else {
+ revision[0] = '1' + (((rev & 0xf0) - CHIP_REV_1_0) >> 4);
+ revision[1] = '.';
+ revision[2] = '0' + (rev & 0xf);
+ revision[3] = '\0';
+
+ return revision;
}
}
@@ -67,21 +96,27 @@ static void set_core_data(struct udevice *dev)
} else if (device_is_compatible(dev, "arm,cortex-a72")) {
plat->cpu_rsrc = SC_R_A72;
plat->name = "A72";
+ } else if (device_is_compatible(dev, "arm,cortex-a55")) {
+ plat->name = "A55";
} else {
plat->cpu_rsrc = SC_R_A53;
plat->name = "?";
}
}
-#if IS_ENABLED(CONFIG_IMX_SCU_THERMAL)
+#if IS_ENABLED(CONFIG_DM_THERMAL)
static int cpu_imx_get_temp(struct cpu_imx_plat *plat)
{
struct udevice *thermal_dev;
int cpu_tmp, ret;
int idx = 1; /* use "cpu-thermal0" device */
- if (plat->cpu_rsrc == SC_R_A72)
- idx = 2; /* use "cpu-thermal1" device */
+ if (IS_ENABLED(CONFIG_IMX8)) {
+ if (plat->cpu_rsrc == SC_R_A72)
+ idx = 2; /* use "cpu-thermal1" device */
+ } else {
+ idx = 1;
+ }
ret = uclass_get_device(UCLASS_THERMAL, idx, &thermal_dev);
if (!ret) {
@@ -101,18 +136,46 @@ static int cpu_imx_get_temp(struct cpu_imx_plat *plat)
}
#endif
-int cpu_imx_get_desc(const struct udevice *dev, char *buf, int size)
+__weak u32 get_cpu_temp_grade(int *minc, int *maxc)
+{
+ return 0;
+}
+
+static int cpu_imx_get_desc(const struct udevice *dev, char *buf, int size)
{
struct cpu_imx_plat *plat = dev_get_plat(dev);
+ const char *grade;
int ret, temp;
+ int minc, maxc;
if (size < 100)
return -ENOSPC;
- ret = snprintf(buf, size, "NXP i.MX8%s Rev%s %s at %u MHz",
+ ret = snprintf(buf, size, "NXP i.MX%s Rev%s %s at %u MHz",
plat->type, plat->rev, plat->name, plat->freq_mhz);
- if (IS_ENABLED(CONFIG_IMX_SCU_THERMAL)) {
+ if (IS_ENABLED(CONFIG_IMX9)) {
+ switch (get_cpu_temp_grade(&minc, &maxc)) {
+ case TEMP_AUTOMOTIVE:
+ grade = "Automotive temperature grade ";
+ break;
+ case TEMP_INDUSTRIAL:
+ grade = "Industrial temperature grade ";
+ break;
+ case TEMP_EXTCOMMERCIAL:
+ grade = "Extended Consumer temperature grade ";
+ break;
+ default:
+ grade = "Consumer temperature grade ";
+ break;
+ }
+
+ buf = buf + ret;
+ size = size - ret;
+ ret = snprintf(buf, size, "\nCPU: %s (%dC to %dC)", grade, minc, maxc);
+ }
+
+ if (IS_ENABLED(CONFIG_DM_THERMAL)) {
temp = cpu_imx_get_temp(plat);
buf = buf + ret;
size = size - ret;
@@ -174,7 +237,7 @@ static int cpu_imx_is_current(struct udevice *dev)
return 0;
}
-static const struct cpu_ops cpu_imx8_ops = {
+static const struct cpu_ops cpu_imx_ops = {
.get_desc = cpu_imx_get_desc,
.get_info = cpu_imx_get_info,
.get_count = cpu_imx_get_count,
@@ -182,21 +245,32 @@ static const struct cpu_ops cpu_imx8_ops = {
.is_current = cpu_imx_is_current,
};
-static const struct udevice_id cpu_imx8_ids[] = {
+static const struct udevice_id cpu_imx_ids[] = {
{ .compatible = "arm,cortex-a35" },
{ .compatible = "arm,cortex-a53" },
+ { .compatible = "arm,cortex-a55" },
{ .compatible = "arm,cortex-a72" },
{ }
};
-static ulong imx8_get_cpu_rate(struct udevice *dev)
+static ulong imx_get_cpu_rate(struct udevice *dev)
{
struct cpu_imx_plat *plat = dev_get_plat(dev);
+ struct clk clk;
ulong rate;
int ret;
- ret = sc_pm_get_clock_rate(-1, plat->cpu_rsrc, SC_PM_CLK_CPU,
- (sc_pm_clock_rate_t *)&rate);
+ if (IS_ENABLED(CONFIG_IMX8)) {
+ ret = sc_pm_get_clock_rate(-1, plat->cpu_rsrc, SC_PM_CLK_CPU,
+ (sc_pm_clock_rate_t *)&rate);
+ } else {
+ ret = clk_get_by_index(dev, 0, &clk);
+ if (!ret) {
+ rate = clk_get_rate(&clk);
+ if (!rate)
+ ret = -EOPNOTSUPP;
+ }
+ }
if (ret) {
printf("Could not read CPU frequency: %d\n", ret);
return 0;
@@ -205,7 +279,7 @@ static ulong imx8_get_cpu_rate(struct udevice *dev)
return rate;
}
-static int imx8_cpu_probe(struct udevice *dev)
+static int imx_cpu_probe(struct udevice *dev)
{
struct cpu_imx_plat *plat = dev_get_plat(dev);
u32 cpurev;
@@ -213,9 +287,9 @@ static int imx8_cpu_probe(struct udevice *dev)
set_core_data(dev);
cpurev = get_cpu_rev();
plat->cpurev = cpurev;
- plat->rev = get_imx8_rev(cpurev & 0xFFF);
- plat->type = get_imx8_type((cpurev & 0xFF000) >> 12);
- plat->freq_mhz = imx8_get_cpu_rate(dev) / 1000000;
+ plat->rev = get_imx_rev_str(cpurev & 0xFFF);
+ plat->type = get_imx_type_str((cpurev & 0xFF000) >> 12);
+ plat->freq_mhz = imx_get_cpu_rate(dev) / 1000000;
plat->mpidr = dev_read_addr(dev);
if (plat->mpidr == FDT_ADDR_T_NONE) {
printf("%s: Failed to get CPU reg property\n", __func__);
@@ -225,12 +299,12 @@ static int imx8_cpu_probe(struct udevice *dev)
return 0;
}
-U_BOOT_DRIVER(cpu_imx8_drv) = {
- .name = "imx8x_cpu",
+U_BOOT_DRIVER(cpu_imx_drv) = {
+ .name = "imx_cpu",
.id = UCLASS_CPU,
- .of_match = cpu_imx8_ids,
- .ops = &cpu_imx8_ops,
- .probe = imx8_cpu_probe,
+ .of_match = cpu_imx_ids,
+ .ops = &cpu_imx_ops,
+ .probe = imx_cpu_probe,
.plat_auto = sizeof(struct cpu_imx_plat),
.flags = DM_FLAG_PRE_RELOC,
};
diff --git a/drivers/cpu/imx9_cpu.c b/drivers/cpu/imx9_cpu.c
new file mode 100644
index 00000000000..66534fe6d17
--- /dev/null
+++ b/drivers/cpu/imx9_cpu.c
@@ -0,0 +1,224 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ */
+
+#include <common.h>
+#include <cpu.h>
+#include <dm.h>
+#include <thermal.h>
+#include <asm/global_data.h>
+#include <asm/system.h>
+#include <firmware/linux/imx/sci/sci.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch-imx/cpu.h>
+#include <asm/armv8/cpu.h>
+#include <linux/bitops.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct cpu_imx_plat {
+ const char *name;
+ const char *rev;
+ const char *type;
+ u32 cpu_rsrc;
+ u32 cpurev;
+ u32 freq_mhz;
+ u32 mpidr;
+};
+
+const char *get_imx9_type(u32 imxtype)
+{
+ switch (imxtype) {
+ case MXC_CPU_IMX93:
+ return "93";
+ default:
+ return "??";
+ }
+}
+
+const char *get_imx9_rev(u32 rev)
+{
+ switch (rev) {
+ case CHIP_REV_1_0:
+ return "1.";
+ case CHIP_REV_B:
+ return "B";
+ case CHIP_REV_C:
+ return "C";
+ default:
+ return "?";
+ }
+}
+
+static void set_core_data(struct udevice *dev)
+{
+ struct cpu_imx_plat *plat = dev_get_plat(dev);
+
+ if (device_is_compatible(dev, "arm,cortex-a35"))
+ plat->name = "A35";
+ else
+ plat->name = "?";
+}
+
+#if IS_ENABLED(CONFIG_IMX_SCU_THERMAL)
+static int cpu_imx_get_temp(struct cpu_imx_plat *plat)
+{
+ struct udevice *thermal_dev;
+ int cpu_tmp, ret;
+ int idx = 1; /* use "cpu-thermal0" device */
+
+ if (plat->cpu_rsrc == SC_R_A72)
+ idx = 2; /* use "cpu-thermal1" device */
+
+ ret = uclass_get_device(UCLASS_THERMAL, idx, &thermal_dev);
+ if (!ret) {
+ ret = thermal_get_temp(thermal_dev, &cpu_tmp);
+ if (ret)
+ return 0xdeadbeef;
+ } else {
+ return 0xdeadbeef;
+ }
+
+ return cpu_tmp;
+}
+#else
+static int cpu_imx_get_temp(struct cpu_imx_plat *plat)
+{
+ return 0;
+}
+#endif
+
+int cpu_imx_get_desc(const struct udevice *dev, char *buf, int size)
+{
+ struct cpu_imx_plat *plat = dev_get_plat(dev);
+ int ret, temp;
+
+ if (size < 100)
+ return -ENOSPC;
+
+ ret = snprintf(buf, size, "NXP i.MX8%s Rev%s %s at %u MHz",
+ plat->type, plat->rev, plat->name, plat->freq_mhz);
+
+ if (IS_ENABLED(CONFIG_IMX_SCU_THERMAL)) {
+ temp = cpu_imx_get_temp(plat);
+ buf = buf + ret;
+ size = size - ret;
+ if (temp != 0xdeadbeef)
+ ret = snprintf(buf, size, " at %dC", temp);
+ else
+ ret = snprintf(buf, size, " - invalid sensor data");
+ }
+
+ snprintf(buf + ret, size - ret, "\n");
+
+ return 0;
+}
+
+static int cpu_imx_get_info(const struct udevice *dev, struct cpu_info *info)
+{
+ struct cpu_imx_plat *plat = dev_get_plat(dev);
+
+ info->cpu_freq = plat->freq_mhz * 1000;
+ info->features = BIT(CPU_FEAT_L1_CACHE) | BIT(CPU_FEAT_MMU);
+ return 0;
+}
+
+static int cpu_imx_get_count(const struct udevice *dev)
+{
+ ofnode node;
+ int num = 0;
+
+ ofnode_for_each_subnode(node, dev_ofnode(dev->parent)) {
+ const char *device_type;
+
+ if (!ofnode_is_enabled(node))
+ continue;
+
+ device_type = ofnode_read_string(node, "device_type");
+ if (!device_type)
+ continue;
+
+ if (!strcmp(device_type, "cpu"))
+ num++;
+ }
+
+ return num;
+}
+
+static int cpu_imx_get_vendor(const struct udevice *dev, char *buf, int size)
+{
+ snprintf(buf, size, "NXP");
+ return 0;
+}
+
+static int cpu_imx_is_current(struct udevice *dev)
+{
+ struct cpu_imx_plat *plat = dev_get_plat(dev);
+
+ if (plat->mpidr == (read_mpidr() & 0xffff))
+ return 1;
+
+ return 0;
+}
+
+static const struct cpu_ops cpu_imx9_ops = {
+ .get_desc = cpu_imx_get_desc,
+ .get_info = cpu_imx_get_info,
+ .get_count = cpu_imx_get_count,
+ .get_vendor = cpu_imx_get_vendor,
+ .is_current = cpu_imx_is_current,
+};
+
+static const struct udevice_id cpu_imx9_ids[] = {
+ { .compatible = "arm,cortex-a35" },
+ { .compatible = "arm,cortex-a53" },
+ { .compatible = "arm,cortex-a72" },
+ { }
+};
+
+static ulong imx9_get_cpu_rate(struct udevice *dev)
+{
+ struct cpu_imx_plat *plat = dev_get_plat(dev);
+ ulong rate;
+ int ret;
+
+ ret = sc_pm_get_clock_rate(-1, plat->cpu_rsrc, SC_PM_CLK_CPU,
+ (sc_pm_clock_rate_t *)&rate);
+ if (ret) {
+ printf("Could not read CPU frequency: %d\n", ret);
+ return 0;
+ }
+
+ return rate;
+}
+
+static int imx9_cpu_probe(struct udevice *dev)
+{
+ struct cpu_imx_plat *plat = dev_get_plat(dev);
+ u32 cpurev;
+
+ set_core_data(dev);
+ cpurev = get_cpu_rev();
+ plat->cpurev = cpurev;
+ plat->rev = get_imx9_rev(cpurev & 0xFFF);
+ plat->type = get_imx9_type((cpurev & 0xFF000) >> 12);
+ plat->freq_mhz = imx9_get_cpu_rate(dev) / 1000000;
+ plat->mpidr = dev_read_addr(dev);
+ if (plat->mpidr == FDT_ADDR_T_NONE) {
+ printf("%s: Failed to get CPU reg property\n", __func__);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+U_BOOT_DRIVER(cpu_imx9_drv) = {
+ .name = "imx9x_cpu",
+ .id = UCLASS_CPU,
+ .of_match = cpu_imx9_ids,
+ .ops = &cpu_imx9_ops,
+ .probe = imx9_cpu_probe,
+ .plat_auto = sizeof(struct cpu_imx_plat),
+ .flags = DM_FLAG_PRE_RELOC,
+};
diff --git a/drivers/ddr/imx/imx9/Kconfig b/drivers/ddr/imx/imx9/Kconfig
index 123ad173cfc..b1795eec353 100644
--- a/drivers/ddr/imx/imx9/Kconfig
+++ b/drivers/ddr/imx/imx9/Kconfig
@@ -22,6 +22,6 @@ config SAVED_DRAM_TIMING_BASE
help
after DRAM is trained, need to save the dram related timming
info into memory for low power use.
- default 0x204DC000
+ default 0x2051C000
endmenu
diff --git a/drivers/ddr/imx/imx9/ddr_init.c b/drivers/ddr/imx/imx9/ddr_init.c
index 8b8ec7f8de3..7a333880e6b 100644
--- a/drivers/ddr/imx/imx9/ddr_init.c
+++ b/drivers/ddr/imx/imx9/ddr_init.c
@@ -12,6 +12,13 @@
#include <asm/arch/sys_proto.h>
#include <linux/delay.h>
+static unsigned int g_cdd_rr_max[4];
+static unsigned int g_cdd_rw_max[4];
+static unsigned int g_cdd_wr_max[4];
+static unsigned int g_cdd_ww_max[4];
+
+#define MAX(a, b) (((a) > (b)) ? (a) : (b))
+
void ddrphy_coldreset(void)
{
/* dramphy_apb_n default 1 , assert -> 0, de_assert -> 1 */
@@ -64,24 +71,277 @@ void check_dfi_init_complete(void)
setbits_le32(REG_DDRDSR_2, BIT(2));
}
-void ddrc_config(struct dram_cfg_param *ddrc_config, int num)
+void ddrc_config(struct dram_timing_info *dram_timing)
{
+ u32 num = dram_timing->ddrc_cfg_num;
+ struct dram_cfg_param *ddrc_config;
int i = 0;
+ ddrc_config = dram_timing->ddrc_cfg;
for (i = 0; i < num; i++) {
writel(ddrc_config->val, (ulong)ddrc_config->reg);
ddrc_config++;
}
+
+ if (dram_timing->fsp_cfg) {
+ ddrc_config = dram_timing->fsp_cfg[0].ddrc_cfg;
+ while (ddrc_config->reg != 0) {
+ writel(ddrc_config->val, (ulong)ddrc_config->reg);
+ ddrc_config++;
+ }
+ }
+}
+
+static unsigned int look_for_max(unsigned int data[], unsigned int addr_start,
+ unsigned int addr_end)
+{
+ unsigned int i, imax = 0;
+
+ for (i = addr_start; i <= addr_end; i++) {
+ if (((data[i] >> 7) == 0) && data[i] > imax)
+ imax = data[i];
+ }
+
+ return imax;
}
void get_trained_CDD(u32 fsp)
{
+ unsigned int i, tmp;
+ unsigned int cdd_cha[12], cdd_chb[12];
+ unsigned int cdd_cha_rr_max, cdd_cha_rw_max, cdd_cha_wr_max, cdd_cha_ww_max;
+ unsigned int cdd_chb_rr_max, cdd_chb_rw_max, cdd_chb_wr_max, cdd_chb_ww_max;
+
+ for (i = 0; i < 6; i++) {
+ tmp = dwc_ddrphy_apb_rd(0x54013 + i);
+ cdd_cha[i * 2] = tmp & 0xff;
+ cdd_cha[i * 2 + 1] = (tmp >> 8) & 0xff;
+ }
+
+ for (i = 0; i < 7; i++) {
+ tmp = dwc_ddrphy_apb_rd(0x5402c + i);
+
+ if (i == 0) {
+ cdd_chb[0] = (tmp >> 8) & 0xff;
+ } else if (i == 6) {
+ cdd_chb[11] = tmp & 0xff;
+ } else {
+ cdd_chb[i * 2 - 1] = tmp & 0xff;
+ cdd_chb[i * 2] = (tmp >> 8) & 0xff;
+ }
+ }
+
+ cdd_cha_rr_max = look_for_max(cdd_cha, 0, 1);
+ cdd_cha_rw_max = look_for_max(cdd_cha, 2, 5);
+ cdd_cha_wr_max = look_for_max(cdd_cha, 6, 9);
+ cdd_cha_ww_max = look_for_max(cdd_cha, 10, 11);
+ cdd_chb_rr_max = look_for_max(cdd_chb, 0, 1);
+ cdd_chb_rw_max = look_for_max(cdd_chb, 2, 5);
+ cdd_chb_wr_max = look_for_max(cdd_chb, 6, 9);
+ cdd_chb_ww_max = look_for_max(cdd_chb, 10, 11);
+ g_cdd_rr_max[fsp] = cdd_cha_rr_max > cdd_chb_rr_max ? cdd_cha_rr_max : cdd_chb_rr_max;
+ g_cdd_rw_max[fsp] = cdd_cha_rw_max > cdd_chb_rw_max ? cdd_cha_rw_max : cdd_chb_rw_max;
+ g_cdd_wr_max[fsp] = cdd_cha_wr_max > cdd_chb_wr_max ? cdd_cha_wr_max : cdd_chb_wr_max;
+ g_cdd_ww_max[fsp] = cdd_cha_ww_max > cdd_chb_ww_max ? cdd_cha_ww_max : cdd_chb_ww_max;
+}
+
+static u32 ddrc_get_fsp_reg_setting(struct dram_cfg_param *ddrc_cfg, unsigned int cfg_num, u32 reg)
+{
+ unsigned int i;
+
+ for (i = 0; i < cfg_num; i++) {
+ if (reg == ddrc_cfg[i].reg)
+ return ddrc_cfg[i].val;
+ }
+
+ return 0;
+}
+
+static void ddrc_update_fsp_reg_setting(struct dram_cfg_param *ddrc_cfg, int cfg_num,
+ u32 reg, u32 val)
+{
+ unsigned int i;
+
+ for (i = 0; i < cfg_num; i++) {
+ if (reg == ddrc_cfg[i].reg) {
+ ddrc_cfg[i].val = val;
+ return;
+ }
+ }
+}
+
+void update_umctl2_rank_space_setting(struct dram_timing_info *dram_timing, unsigned int pstat_num)
+{
+ u32 tmp, tmp_t;
+ u32 wwt, rrt, wrt, rwt;
+ u32 ext_wwt, ext_rrt, ext_wrt, ext_rwt;
+ u32 max_wwt, max_rrt, max_wrt, max_rwt;
+ u32 i;
+
+ for (i = 0; i < pstat_num; i++) {
+ /* read wwt, rrt, wrt, rwt fields from timing_cfg_0 */
+ if (!dram_timing->fsp_cfg_num) {
+ tmp = ddrc_get_fsp_reg_setting(dram_timing->ddrc_cfg,
+ dram_timing->ddrc_cfg_num,
+ REG_DDR_TIMING_CFG_0);
+ } else {
+ tmp = ddrc_get_fsp_reg_setting(dram_timing->fsp_cfg[i].ddrc_cfg,
+ ARRAY_SIZE(dram_timing->fsp_cfg[i].ddrc_cfg),
+ REG_DDR_TIMING_CFG_0);
+ }
+ wwt = (tmp >> 24) & 0x3;
+ rrt = (tmp >> 26) & 0x3;
+ wrt = (tmp >> 28) & 0x3;
+ rwt = (tmp >> 30) & 0x3;
+
+ /* read rxt_wwt, ext_rrt, ext_wrt, ext_rwt fields from timing_cfg_4 */
+ if (!dram_timing->fsp_cfg_num) {
+ tmp_t = ddrc_get_fsp_reg_setting(dram_timing->ddrc_cfg,
+ dram_timing->ddrc_cfg_num,
+ REG_DDR_TIMING_CFG_4);
+ } else {
+ tmp_t = ddrc_get_fsp_reg_setting(dram_timing->fsp_cfg[i].ddrc_cfg,
+ ARRAY_SIZE(dram_timing->fsp_cfg[i].ddrc_cfg),
+ REG_DDR_TIMING_CFG_4);
+ }
+ ext_wwt = (tmp_t >> 8) & 0x3;
+ ext_rrt = (tmp_t >> 10) & 0x3;
+ ext_wrt = (tmp_t >> 12) & 0x3;
+ ext_rwt = (tmp_t >> 14) & 0x3;
+
+ wwt = (ext_wwt << 2) | wwt;
+ rrt = (ext_rrt << 2) | rrt;
+ wrt = (ext_wrt << 2) | wrt;
+ rwt = (ext_rwt << 2) | rwt;
+
+ max_wwt = MAX(g_cdd_ww_max[0], wwt);
+ max_rrt = MAX(g_cdd_rr_max[0], rrt);
+ max_wrt = MAX(g_cdd_wr_max[0], wrt);
+ max_rwt = MAX(g_cdd_rw_max[0], rwt);
+ /* verify values to see if are bigger then 15 (4 bits) */
+ if (max_wwt > 15)
+ max_wwt = 15;
+ if (max_rrt > 15)
+ max_rrt = 15;
+ if (max_wrt > 15)
+ max_wrt = 15;
+ if (max_rwt > 15)
+ max_rwt = 15;
+
+ /* recalculate timings for controller registers */
+ wwt = max_wwt & 0x3;
+ rrt = max_rrt & 0x3;
+ wrt = max_wrt & 0x3;
+ rwt = max_rwt & 0x3;
+
+ ext_wwt = (max_wwt & 0xC) >> 2;
+ ext_rrt = (max_rrt & 0xC) >> 2;
+ ext_wrt = (max_wrt & 0xC) >> 2;
+ ext_rwt = (max_rwt & 0xC) >> 2;
+
+ /* update timing_cfg_0 and timing_cfg_4 */
+ tmp = (tmp & 0x00ffffff) | (rwt << 30) | (wrt << 28) |
+ (rrt << 26) | (wwt << 24);
+ tmp_t = (tmp_t & 0xFFFF00FF) | (ext_rwt << 14) |
+ (ext_wrt << 12) | (ext_rrt << 10) | (ext_wwt << 8);
+
+ if (!dram_timing->fsp_cfg_num) {
+ ddrc_update_fsp_reg_setting(dram_timing->ddrc_cfg,
+ dram_timing->ddrc_cfg_num,
+ REG_DDR_TIMING_CFG_0, tmp);
+ ddrc_update_fsp_reg_setting(dram_timing->ddrc_cfg,
+ dram_timing->ddrc_cfg_num,
+ REG_DDR_TIMING_CFG_4, tmp_t);
+ } else {
+ ddrc_update_fsp_reg_setting(dram_timing->fsp_cfg[i].ddrc_cfg,
+ ARRAY_SIZE(dram_timing->fsp_cfg[i].ddrc_cfg),
+ REG_DDR_TIMING_CFG_0, tmp);
+ ddrc_update_fsp_reg_setting(dram_timing->fsp_cfg[i].ddrc_cfg,
+ ARRAY_SIZE(dram_timing->fsp_cfg[i].ddrc_cfg),
+ REG_DDR_TIMING_CFG_4, tmp_t);
+ }
+ }
+}
+
+u32 ddrc_mrr(u32 chip_select, u32 mode_reg_num, u32 *mode_reg_val)
+{
+ u32 temp;
+
+ writel(0x80000000, REG_DDR_SDRAM_MD_CNTL_2);
+ temp = 0x80000000 | (chip_select << 28) | (mode_reg_num << 0);
+ writel(temp, REG_DDR_SDRAM_MD_CNTL);
+ while ((readl(REG_DDR_SDRAM_MD_CNTL) & 0x80000000) == 0x80000000)
+ ;
+ while (!(readl(REG_DDR_SDRAM_MPR5)))
+ ;
+ *mode_reg_val = (readl(REG_DDR_SDRAM_MPR4) & 0xFF0000) >> 16;
+ writel(0x0, REG_DDR_SDRAM_MPR5);
+ while ((readl(REG_DDR_SDRAM_MPR5)))
+ ;
+ writel(0x0, REG_DDR_SDRAM_MPR4);
+ writel(0x0, REG_DDR_SDRAM_MD_CNTL_2);
+
+ return 0;
+}
+
+void ddrc_mrs(u32 cs_sel, u32 opcode, u32 mr)
+{
+ u32 regval;
+
+ regval = (cs_sel << 28) | (opcode << 6) | (mr);
+ writel(regval, REG_DDR_SDRAM_MD_CNTL);
+ setbits_le32(REG_DDR_SDRAM_MD_CNTL, BIT(31));
+ check_ddrc_idle();
+}
+
+u32 lpddr4_mr_read(u32 mr_rank, u32 mr_addr)
+{
+ u32 chip_select, regval;
+
+ if (mr_rank == 1)
+ chip_select = 0; /* CS0 */
+ else if (mr_rank == 2)
+ chip_select = 1; /* CS1 */
+ else
+ chip_select = 4; /* CS0 & CS1 */
+
+ ddrc_mrr(chip_select, mr_addr, &regval);
+
+ return regval;
+}
+
+void update_mr_fsp_op0(struct dram_cfg_param *cfg, unsigned int num)
+{
+ int i;
+
+ ddrc_mrs(0x4, 0x88, 13); /* FSP-OP->1, FSP-WR->0, VRCG=1, DMD=0 */
+ for (i = 0; i < num; i++) {
+ if (cfg[i].reg)
+ ddrc_mrs(0x4, cfg[i].val, cfg[i].reg);
+ }
+ ddrc_mrs(0x4, 0xc0, 13); /* FSP-OP->1, FSP-WR->1, VRCG=0, DMD=0 */
+}
+
+void save_trained_mr12_14(struct dram_cfg_param *cfg, u32 cfg_num, u32 mr12, u32 mr14)
+{
+ int i;
+
+ for (i = 0; i < cfg_num; i++) {
+ if (cfg->reg == 12)
+ cfg->val = mr12;
+ else if (cfg->reg == 14)
+ cfg->val = mr14;
+ cfg++;
+ }
}
int ddr_init(struct dram_timing_info *dram_timing)
{
unsigned int initial_drate;
+ struct dram_timing_info *saved_timing;
+ void *fsp;
int ret;
+ u32 mr12, mr14;
u32 regval;
debug("DDRINFO: start DRAM init\n");
@@ -107,9 +367,11 @@ int ddr_init(struct dram_timing_info *dram_timing)
debug("DDRINFO: ddrphy config done\n");
+ update_umctl2_rank_space_setting(dram_timing, dram_timing->fsp_msg_num - 1);
+
/* rogram the ddrc registers */
debug("DDRINFO: ddrc config start\n");
- ddrc_config(dram_timing->ddrc_cfg, dram_timing->ddrc_cfg_num);
+ ddrc_config(dram_timing);
debug("DDRINFO: ddrc config done\n");
#ifdef CONFIG_IMX9_DRAM_PM_COUNTER
@@ -123,8 +385,29 @@ int ddr_init(struct dram_timing_info *dram_timing)
check_ddrc_idle();
+ mr12 = lpddr4_mr_read(1, 12);
+ mr14 = lpddr4_mr_read(1, 14);
+
/* save the dram timing config into memory */
- dram_config_save(dram_timing, CONFIG_SAVED_DRAM_TIMING_BASE);
+ fsp = dram_config_save(dram_timing, CONFIG_SAVED_DRAM_TIMING_BASE);
+
+ saved_timing = (struct dram_timing_info *)CONFIG_SAVED_DRAM_TIMING_BASE;
+ saved_timing->fsp_cfg = fsp;
+ saved_timing->fsp_cfg_num = dram_timing->fsp_cfg_num;
+ if (saved_timing->fsp_cfg_num) {
+ memcpy(saved_timing->fsp_cfg, dram_timing->fsp_cfg,
+ dram_timing->fsp_cfg_num * sizeof(struct dram_fsp_cfg));
+
+ save_trained_mr12_14(saved_timing->fsp_cfg[0].mr_cfg,
+ ARRAY_SIZE(saved_timing->fsp_cfg[0].mr_cfg), mr12, mr14);
+ /*
+ * Configure mode registers in fsp1 to mode register 0 because DDRC
+ * doesn't automatically set.
+ */
+ if (saved_timing->fsp_cfg_num > 1)
+ update_mr_fsp_op0(saved_timing->fsp_cfg[1].mr_cfg,
+ ARRAY_SIZE(saved_timing->fsp_cfg[1].mr_cfg));
+ }
return 0;
}
diff --git a/drivers/ddr/imx/phy/ddrphy_utils.c b/drivers/ddr/imx/phy/ddrphy_utils.c
index 6a8b6be42b2..fd8b4113b7b 100644
--- a/drivers/ddr/imx/phy/ddrphy_utils.c
+++ b/drivers/ddr/imx/phy/ddrphy_utils.c
@@ -148,6 +148,9 @@ void ddrphy_init_set_dfi_clk(unsigned int drate)
dram_pll_init(MHZ(167));
dram_disable_bypass();
break;
+ case 625:
+ dram_enable_bypass(MHZ(625));
+ break;
case 400:
dram_enable_bypass(MHZ(400));
break;
diff --git a/drivers/ddr/imx/phy/helper.c b/drivers/ddr/imx/phy/helper.c
index e9e0294f87d..8cd438791e5 100644
--- a/drivers/ddr/imx/phy/helper.c
+++ b/drivers/ddr/imx/phy/helper.c
@@ -167,8 +167,7 @@ void ddrphy_trained_csr_save(struct dram_cfg_param *ddrphy_csr,
dwc_ddrphy_apb_wr(0xd0000, 0x1);
}
-void dram_config_save(struct dram_timing_info *timing_info,
- unsigned long saved_timing_base)
+void *dram_config_save(struct dram_timing_info *timing_info, unsigned long saved_timing_base)
{
int i = 0;
struct dram_timing_info *saved_timing = (struct dram_timing_info *)saved_timing_base;
@@ -217,4 +216,6 @@ void dram_config_save(struct dram_timing_info *timing_info,
cfg->val = timing_info->ddrphy_pie[i].val;
cfg++;
}
+
+ return (void *)cfg;
}
diff --git a/drivers/misc/imx8/fuse.c b/drivers/misc/imx8/fuse.c
index 38111c52548..b81f73f283f 100644
--- a/drivers/misc/imx8/fuse.c
+++ b/drivers/misc/imx8/fuse.c
@@ -7,7 +7,7 @@
#include <console.h>
#include <errno.h>
#include <fuse.h>
-#include <asm/arch/sci/sci.h>
+#include <firmware/imx/sci/sci.h>
#include <asm/arch/sys_proto.h>
#include <asm/global_data.h>
#include <linux/arm-smccc.h>
diff --git a/drivers/misc/imx8/scu.c b/drivers/misc/imx8/scu.c
index 4ab5cb4bf13..798800aa758 100644
--- a/drivers/misc/imx8/scu.c
+++ b/drivers/misc/imx8/scu.c
@@ -13,7 +13,7 @@
#include <dm/lists.h>
#include <dm/root.h>
#include <dm/device-internal.h>
-#include <asm/arch/sci/sci.h>
+#include <firmware/imx/sci/sci.h>
#include <linux/bitops.h>
#include <linux/iopoll.h>
#include <misc.h>
diff --git a/drivers/misc/imx8/scu_api.c b/drivers/misc/imx8/scu_api.c
index 8f546e9b3fc..dfede7f1d5f 100644
--- a/drivers/misc/imx8/scu_api.c
+++ b/drivers/misc/imx8/scu_api.c
@@ -11,7 +11,7 @@
#include <asm/global_data.h>
#include <asm/io.h>
#include <dm.h>
-#include <asm/arch/sci/sci.h>
+#include <firmware/imx/sci/sci.h>
#include <misc.h>
DECLARE_GLOBAL_DATA_PTR;
diff --git a/drivers/pinctrl/nxp/pinctrl-scu.c b/drivers/pinctrl/nxp/pinctrl-scu.c
index c032be782a1..4959834c0fc 100644
--- a/drivers/pinctrl/nxp/pinctrl-scu.c
+++ b/drivers/pinctrl/nxp/pinctrl-scu.c
@@ -7,7 +7,7 @@
#include <errno.h>
#include <linux/bitops.h>
#include <asm/io.h>
-#include <asm/arch/sci/sci.h>
+#include <firmware/imx/sci/sci.h>
#include <misc.h>
#include "pinctrl-imx.h"
diff --git a/drivers/power/domain/imx8-power-domain-legacy.c b/drivers/power/domain/imx8-power-domain-legacy.c
index bf45891bccd..37b0f95abac 100644
--- a/drivers/power/domain/imx8-power-domain-legacy.c
+++ b/drivers/power/domain/imx8-power-domain-legacy.c
@@ -14,7 +14,7 @@
#include <dm/device-internal.h>
#include <dm/device.h>
#include <dm/uclass-internal.h>
-#include <asm/arch/sci/sci.h>
+#include <firmware/imx/sci/sci.h>
DECLARE_GLOBAL_DATA_PTR;
diff --git a/drivers/power/domain/imx8-power-domain.c b/drivers/power/domain/imx8-power-domain.c
index 17b5d57b19b..b45e468756b 100644
--- a/drivers/power/domain/imx8-power-domain.c
+++ b/drivers/power/domain/imx8-power-domain.c
@@ -10,7 +10,7 @@
#include <malloc.h>
#include <power-domain-uclass.h>
#include <asm/arch/power-domain.h>
-#include <asm/arch/sci/sci.h>
+#include <firmware/imx/sci/sci.h>
static int imx8_power_domain_on(struct power_domain *power_domain)
{
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index f4767c838f9..a1e089962a9 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -966,6 +966,14 @@ config MSM_GENI_SERIAL
Driver works in FIFO mode.
Multiple baudrates supported.
+config MXS_AUART_SERIAL
+ bool "MXS AUART"
+ depends on DM_SERIAL
+ help
+ Support for Freescale i.MX23 / i.MX28 AUART or Application UART IP.
+ This IP is present in the aforementioned SoCs, however this is not
+ the IP used to drive the Debug UART port, for that see PL01X_SERIAL .
+
config OCTEON_SERIAL_BOOTCMD
bool "MIPS Octeon PCI remote bootcmd input"
depends on ARCH_OCTEON
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index 01fef3f323b..403ab1ded68 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -46,6 +46,7 @@ obj-$(CONFIG_BCM283X_MU_SERIAL) += serial_bcm283x_mu.o
obj-$(CONFIG_BCM283X_PL011_SERIAL) += serial_bcm283x_pl011.o
obj-$(CONFIG_MSM_SERIAL) += serial_msm.o
obj-$(CONFIG_MSM_GENI_SERIAL) += serial_msm_geni.o
+obj-$(CONFIG_MXS_AUART_SERIAL) += serial_mxs.o
obj-$(CONFIG_MVEBU_A3700_UART) += serial_mvebu_a3700.o
obj-$(CONFIG_MPC8XX_CONS) += serial_mpc8xx.o
obj-$(CONFIG_NULLDEV_SERIAL) += serial_nulldev.o
diff --git a/drivers/serial/serial_mxs.c b/drivers/serial/serial_mxs.c
new file mode 100644
index 00000000000..3659948b872
--- /dev/null
+++ b/drivers/serial/serial_mxs.c
@@ -0,0 +1,129 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2023 Marek Vasut <marex@denx.de>
+ */
+#include <common.h>
+#include <dm.h>
+#include <malloc.h>
+#include <serial.h>
+#include <wait_bit.h>
+
+#define SET_REG 0x4
+#define CLR_REG 0x8
+
+#define AUART_CTRL0 0x00
+#define AUART_CTRL1 0x10
+#define AUART_CTRL2 0x20
+#define AUART_LINECTRL 0x30
+#define AUART_INTR 0x50
+#define AUART_DATA 0x60
+#define AUART_STAT 0x70
+
+#define AUART_CTRL0_SFTRST BIT(31)
+#define AUART_CTRL0_CLKGATE BIT(30)
+
+#define AUART_CTRL2_UARTEN BIT(0)
+
+#define AUART_LINECTRL_BAUD_DIVINT(v) (((v) & 0xffff) << 16)
+#define AUART_LINECTRL_BAUD_DIVFRAC(v) (((v) & 0x3f) << 8)
+#define AUART_LINECTRL_WLEN(v) ((((v) - 5) & 0x3) << 5)
+
+#define AUART_STAT_TXFE BIT(27)
+#define AUART_STAT_TXFF BIT(25)
+#define AUART_STAT_RXFE BIT(24)
+
+#define AUART_CLK 24000000
+
+struct mxs_auart_uart_priv {
+ void __iomem *base;
+};
+
+static int mxs_auart_uart_setbrg(struct udevice *dev, int baudrate)
+{
+ struct mxs_auart_uart_priv *priv = dev_get_priv(dev);
+ u32 div;
+
+ writel(AUART_CTRL0_CLKGATE, priv->base + AUART_CTRL0 + CLR_REG);
+ writel(AUART_CTRL0_SFTRST, priv->base + AUART_CTRL0 + CLR_REG);
+
+ writel(AUART_CTRL2_UARTEN, priv->base + AUART_CTRL2 + SET_REG);
+
+ writel(0, priv->base + AUART_INTR);
+
+ div = DIV_ROUND_CLOSEST(AUART_CLK * 32, baudrate);
+
+ /* Disable FIFO, baudrate, 8N1. */
+ writel(AUART_LINECTRL_BAUD_DIVFRAC(div & 0x3F) |
+ AUART_LINECTRL_BAUD_DIVINT(div >> 6) |
+ AUART_LINECTRL_WLEN(8),
+ priv->base + AUART_LINECTRL);
+
+ return 0;
+}
+
+static int mxs_auart_uart_pending(struct udevice *dev, bool input)
+{
+ struct mxs_auart_uart_priv *priv = dev_get_priv(dev);
+ u32 stat = readl(priv->base + AUART_STAT);
+
+ if (input)
+ return !(stat & AUART_STAT_RXFE);
+
+ return !!(stat & AUART_STAT_TXFE);
+}
+
+static int mxs_auart_uart_putc(struct udevice *dev, const char ch)
+{
+ struct mxs_auart_uart_priv *priv = dev_get_priv(dev);
+ u32 stat = readl(priv->base + AUART_STAT);
+
+ if (stat & AUART_STAT_TXFF)
+ return -EAGAIN;
+
+ writel(ch, priv->base + AUART_DATA);
+
+ return 0;
+}
+
+static int mxs_auart_uart_getc(struct udevice *dev)
+{
+ struct mxs_auart_uart_priv *priv = dev_get_priv(dev);
+
+ if (!mxs_auart_uart_pending(dev, true))
+ return -EAGAIN;
+
+ return readl(priv->base + AUART_DATA) & 0xff;
+}
+
+static int mxs_auart_uart_probe(struct udevice *dev)
+{
+ struct mxs_auart_uart_priv *priv = dev_get_priv(dev);
+
+ priv->base = dev_read_addr_ptr(dev);
+ if (!priv->base)
+ return -EINVAL;
+
+ return mxs_auart_uart_setbrg(dev, CONFIG_BAUDRATE);
+}
+
+static const struct dm_serial_ops mxs_auart_uart_ops = {
+ .putc = mxs_auart_uart_putc,
+ .pending = mxs_auart_uart_pending,
+ .getc = mxs_auart_uart_getc,
+ .setbrg = mxs_auart_uart_setbrg,
+};
+
+static const struct udevice_id mxs_auart_uart_ids[] = {
+ { .compatible = "fsl,imx23-auart", },
+ { .compatible = "fsl,imx28-auart", },
+ { /* sentinel */ }
+};
+
+U_BOOT_DRIVER(mxs_auart_serial) = {
+ .name = "mxs-auart",
+ .id = UCLASS_SERIAL,
+ .of_match = mxs_auart_uart_ids,
+ .probe = mxs_auart_uart_probe,
+ .ops = &mxs_auart_uart_ops,
+ .priv_auto = sizeof(struct mxs_auart_uart_priv),
+};
diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig
index 97d4163e8ed..681b621760d 100644
--- a/drivers/thermal/Kconfig
+++ b/drivers/thermal/Kconfig
@@ -27,10 +27,10 @@ config IMX_SCU_THERMAL
trip is crossed
config IMX_TMU
- bool "Thermal Management Unit driver for NXP i.MX8M"
- depends on ARCH_IMX8M
+ bool "Thermal Management Unit driver for NXP i.MX8M and iMX93"
+ depends on ARCH_IMX8M || IMX93
help
- Support for Temperature sensors on NXP i.MX8M.
+ Support for Temperature sensors on NXP i.MX8M and iMX93.
It supports one critical trip point and one passive trip point.
The boot is hold to the cool device to throttle CPUs when the
passive trip is crossed
diff --git a/drivers/thermal/imx_scu_thermal.c b/drivers/thermal/imx_scu_thermal.c
index e704bcbea86..3ec131cbc6e 100644
--- a/drivers/thermal/imx_scu_thermal.c
+++ b/drivers/thermal/imx_scu_thermal.c
@@ -12,7 +12,7 @@
#include <asm/global_data.h>
#include <dm/device-internal.h>
#include <dm/device.h>
-#include <asm/arch/sci/sci.h>
+#include <firmware/imx/sci/sci.h>
#include <linux/delay.h>
#include <linux/libfdt.h>
diff --git a/drivers/thermal/imx_tmu.c b/drivers/thermal/imx_tmu.c
index ca45abbb8e1..97efc550443 100644
--- a/drivers/thermal/imx_tmu.c
+++ b/drivers/thermal/imx_tmu.c
@@ -11,6 +11,7 @@
#include <asm/arch/clock.h>
#include <asm/arch/sys_proto.h>
#include <dm.h>
+#include <dm/device_compat.h>
#include <dm/device-internal.h>
#include <dm/device.h>
#include <errno.h>
@@ -24,6 +25,7 @@ DECLARE_GLOBAL_DATA_PTR;
#define SITES_MAX 16
#define FLAGS_VER2 0x1
#define FLAGS_VER3 0x2
+#define FLAGS_VER4 0x4
#define TMR_DISABLE 0x0
#define TMR_ME 0x80000000
@@ -75,6 +77,45 @@ struct imx_tmu_regs {
u32 ttr3cr; /* Temperature Range 3 Control Register */
};
+struct imx_tmu_regs_v4 {
+ u32 tmr; /* Mode Register */
+ u32 tsr; /* Status Register */
+ u32 tmsr; /* Monitor Site Register */
+ u32 tmtmir; /* Temperature measurement interval Register */
+ u8 res0[0x10];
+ u32 tier; /* Interrupt Enable Register */
+ u32 tidr; /* Interrupt Detect Register */
+ u8 res1[0x8];
+ u32 tiiscr; /* Interrupt Immediate Site Capture Register */
+ u32 tiascr; /* Interrupt Average Site Capture Register */
+ u32 ticscr; /* Interrupt Critical Site Capture Register */
+ u8 res2[0x4];
+ u32 tmhtcr; /* Monitor High Temperature Capture Register */
+ u32 tmltcr; /* MonitorLow Temperature Capture Register */
+ u32 tmrtrcr; /* Monitor Rising Temperature Rate Capture Register */
+ u32 tmftrcr; /* Monitor Falling Temperature Rate Capture Register */
+ u32 tmhtitr; /* Monitor High Temperature Immediate Threshold */
+ u32 tmhtatr; /* Monitor High Temperature Average Threshold */
+ u32 tmhtactr; /* Monitor High Temperature Average Crit Threshold */
+ u8 res3[0x4];
+ u32 tmltitr; /* Monitor Low Temperature Immediate Threshold */
+ u32 tmltatr; /* Monitor Low Temperature Average Threshold */
+ u32 tmltactr; /* Monitor Low Temperature Average Crit Threshold */
+ u8 res4[0x4];
+ u32 tmrtrctr; /* Monitor Rising Temperature Rate Critical Threshold Register */
+ u32 tmftrctr; /* Monitor Falling Temperature Rate Critical Threshold Register */
+ u8 res5[0x8];
+ u32 ttcfgr; /* Temperature Configuration Register */
+ u32 tscfgr; /* Sensor Configuration Register */
+ u8 res6[0x78];
+ u32 tritsr0; /* Immediate Temperature Site Register */
+ u32 tratsr0; /* Average Temperature Site Register */
+ u8 res7[0xdf8];
+ u32 tcmcfg; /* Central Module Configuration */
+ u8 res8[0xc];
+ u32 ttrcr[16]; /* Temperature Range Control Register */
+};
+
struct imx_tmu_regs_v2 {
u32 ter; /* TMU enable Register */
u32 tsr; /* Status Register */
@@ -114,6 +155,7 @@ union tmu_regs {
struct imx_tmu_regs regs_v1;
struct imx_tmu_regs_v2 regs_v2;
struct imx_tmu_regs_v3 regs_v3;
+ struct imx_tmu_regs_v4 regs_v4;
};
struct imx_tmu_plat {
@@ -147,6 +189,9 @@ static int read_temperature(struct udevice *dev, int *temp)
* only reflects the RAW uncalibrated data
*/
valid = ((val & 0xff) < 10 || (val & 0xff) > 125) ? 0 : 1;
+ } else if (drv_data & FLAGS_VER4) {
+ val = readl(&pdata->regs->regs_v4.tritsr0);
+ valid = val & 0x80000000;
} else {
val = readl(&pdata->regs->regs_v1.site[pdata->id].tritsr);
valid = val & 0x80000000;
@@ -164,6 +209,13 @@ static int read_temperature(struct udevice *dev, int *temp)
return -EINVAL;
*temp *= 1000;
+ } else if (drv_data & FLAGS_VER4) {
+ *temp = (val & 0x1ff) * 1000;
+ if (val & 0x200)
+ *temp += 500;
+
+ /* Convert Kelvin to Celsius */
+ *temp -= 273000;
} else {
*temp = (val & 0xff) * 1000;
}
@@ -185,8 +237,8 @@ int imx_tmu_get_temp(struct udevice *dev, int *temp)
return ret;
while (cpu_tmp >= pdata->alert) {
- printf("CPU Temperature (%dC) has beyond alert (%dC), close to critical (%dC)", cpu_tmp, pdata->alert, pdata->critical);
- puts(" waiting...\n");
+ dev_info(dev, "CPU Temperature (%dC) has beyond alert (%dC), close to critical (%dC) waiting...\n",
+ cpu_tmp, pdata->alert, pdata->critical);
mdelay(pdata->polling_delay);
ret = read_temperature(dev, &cpu_tmp);
if (ret)
@@ -205,19 +257,39 @@ static const struct dm_thermal_ops imx_tmu_ops = {
static int imx_tmu_calibration(struct udevice *dev)
{
int i, val, len, ret;
+ int index;
u32 range[4];
const fdt32_t *calibration;
struct imx_tmu_plat *pdata = dev_get_plat(dev);
ulong drv_data = dev_get_driver_data(dev);
- debug("%s\n", __func__);
+ dev_dbg(dev, "%s\n", __func__);
if (drv_data & (FLAGS_VER2 | FLAGS_VER3))
return 0;
+ if (drv_data & FLAGS_VER4) {
+ calibration = dev_read_prop(dev, "fsl,tmu-calibration", &len);
+ if (!calibration || len % 8 || len > 128) {
+ printf("TMU: invalid calibration data.\n");
+ return -ENODEV;
+ }
+
+ for (i = 0; i < len; i += 8, calibration += 2) {
+ index = i / 8;
+ writel(index, &pdata->regs->regs_v4.ttcfgr);
+ val = fdt32_to_cpu(*calibration);
+ writel(val, &pdata->regs->regs_v4.tscfgr);
+ val = fdt32_to_cpu(*(calibration + 1));
+ writel((1 << 31) | val, &pdata->regs->regs_v4.ttrcr[index]);
+ }
+
+ return 0;
+ }
+
ret = dev_read_u32_array(dev, "fsl,tmu-range", range, 4);
if (ret) {
- printf("TMU: missing calibration range, ret = %d.\n", ret);
+ dev_err(dev, "TMU: missing calibration range, ret = %d.\n", ret);
return ret;
}
@@ -229,7 +301,7 @@ static int imx_tmu_calibration(struct udevice *dev)
calibration = dev_read_prop(dev, "fsl,tmu-calibration", &len);
if (!calibration || len % 8) {
- printf("TMU: invalid calibration data.\n");
+ dev_err(dev, "TMU: invalid calibration data.\n");
return -ENODEV;
}
@@ -243,8 +315,103 @@ static int imx_tmu_calibration(struct udevice *dev)
return 0;
}
-void __weak imx_tmu_arch_init(void *reg_base)
+#if defined(CONFIG_IMX8MM) || defined(CONFIG_IMX8MN)
+static void imx_tmu_mx8mm_mx8mn_init(struct udevice *dev)
+{
+ /* Load TCALIV and TASR from fuses */
+ struct ocotp_regs *ocotp =
+ (struct ocotp_regs *)OCOTP_BASE_ADDR;
+ struct fuse_bank *bank = &ocotp->bank[3];
+ struct fuse_bank3_regs *fuse =
+ (struct fuse_bank3_regs *)bank->fuse_regs;
+ struct imx_tmu_plat *pdata = dev_get_plat(dev);
+ void *reg_base = (void *)pdata->regs;
+
+ u32 tca_rt, tca_hr, tca_en;
+ u32 buf_vref, buf_slope;
+
+ tca_rt = fuse->ana0 & 0xFF;
+ tca_hr = (fuse->ana0 & 0xFF00) >> 8;
+ tca_en = (fuse->ana0 & 0x2000000) >> 25;
+
+ buf_vref = (fuse->ana0 & 0x1F00000) >> 20;
+ buf_slope = (fuse->ana0 & 0xF0000) >> 16;
+
+ writel(buf_vref | (buf_slope << 16), (ulong)reg_base + 0x28);
+ writel((tca_en << 31) | (tca_hr << 16) | tca_rt,
+ (ulong)reg_base + 0x30);
+}
+#else
+static inline void imx_tmu_mx8mm_mx8mn_init(struct udevice *dev) { }
+#endif
+
+#if defined(CONFIG_IMX8MP)
+static void imx_tmu_mx8mp_init(struct udevice *dev)
{
+ /* Load TCALIV0/1/m40 and TRIM from fuses */
+ struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
+ struct fuse_bank *bank = &ocotp->bank[38];
+ struct fuse_bank38_regs *fuse =
+ (struct fuse_bank38_regs *)bank->fuse_regs;
+ struct fuse_bank *bank2 = &ocotp->bank[39];
+ struct fuse_bank39_regs *fuse2 =
+ (struct fuse_bank39_regs *)bank2->fuse_regs;
+ struct imx_tmu_plat *pdata = dev_get_plat(dev);
+ void *reg_base = (void *)pdata->regs;
+ u32 buf_vref, buf_slope, bjt_cur, vlsb, bgr;
+ u32 reg;
+ u32 tca40[2], tca25[2], tca105[2];
+
+ /* For blank sample */
+ if (!fuse->ana_trim2 && !fuse->ana_trim3 &&
+ !fuse->ana_trim4 && !fuse2->ana_trim5) {
+ /* Use a default 25C binary codes */
+ tca25[0] = 1596;
+ tca25[1] = 1596;
+ writel(tca25[0], (ulong)reg_base + 0x30);
+ writel(tca25[1], (ulong)reg_base + 0x34);
+ return;
+ }
+
+ buf_vref = (fuse->ana_trim2 & 0xc0) >> 6;
+ buf_slope = (fuse->ana_trim2 & 0xF00) >> 8;
+ bjt_cur = (fuse->ana_trim2 & 0xF000) >> 12;
+ bgr = (fuse->ana_trim2 & 0xF0000) >> 16;
+ vlsb = (fuse->ana_trim2 & 0xF00000) >> 20;
+ writel(buf_vref | (buf_slope << 16), (ulong)reg_base + 0x28);
+
+ reg = (bgr << 28) | (bjt_cur << 20) | (vlsb << 12) | (1 << 7);
+ writel(reg, (ulong)reg_base + 0x3c);
+
+ tca40[0] = (fuse->ana_trim3 & 0xFFF0000) >> 16;
+ tca25[0] = (fuse->ana_trim3 & 0xF0000000) >> 28;
+ tca25[0] |= ((fuse->ana_trim4 & 0xFF) << 4);
+ tca105[0] = (fuse->ana_trim4 & 0xFFF00) >> 8;
+ tca40[1] = (fuse->ana_trim4 & 0xFFF00000) >> 20;
+ tca25[1] = fuse2->ana_trim5 & 0xFFF;
+ tca105[1] = (fuse2->ana_trim5 & 0xFFF000) >> 12;
+
+ /* use 25c for 1p calibration */
+ writel(tca25[0] | (tca105[0] << 16), (ulong)reg_base + 0x30);
+ writel(tca25[1] | (tca105[1] << 16), (ulong)reg_base + 0x34);
+ writel(tca40[0] | (tca40[1] << 16), (ulong)reg_base + 0x38);
+}
+#else
+static inline void imx_tmu_mx8mp_init(struct udevice *dev) { }
+#endif
+
+static inline void imx_tmu_mx93_init(struct udevice *dev) { }
+
+static void imx_tmu_arch_init(struct udevice *dev)
+{
+ if (is_imx8mm() || is_imx8mn())
+ imx_tmu_mx8mm_mx8mn_init(dev);
+ else if (is_imx8mp())
+ imx_tmu_mx8mp_init(dev);
+ else if (is_imx93())
+ imx_tmu_mx93_init(dev);
+ else
+ dev_err(dev, "Unsupported SoC, TMU calibration not loaded!\n");
}
static void imx_tmu_init(struct udevice *dev)
@@ -252,7 +419,7 @@ static void imx_tmu_init(struct udevice *dev)
struct imx_tmu_plat *pdata = dev_get_plat(dev);
ulong drv_data = dev_get_driver_data(dev);
- debug("%s\n", __func__);
+ dev_dbg(dev, "%s\n", __func__);
if (drv_data & FLAGS_VER3) {
/* Disable monitoring */
@@ -267,6 +434,15 @@ static void imx_tmu_init(struct udevice *dev)
/* Disable interrupt, using polling instead */
writel(0x0, &pdata->regs->regs_v2.tier);
+ } else if (drv_data & FLAGS_VER4) {
+ /* Disable monitoring */
+ writel(TMR_DISABLE, &pdata->regs->regs_v4.tmr);
+
+ /* Disable interrupt, using polling instead */
+ writel(TIER_DISABLE, &pdata->regs->regs_v4.tier);
+
+ /* Set update_interval */
+ writel(TMTMIR_DEFAULT, &pdata->regs->regs_v4.tmtmir);
} else {
/* Disable monitoring */
writel(TMR_DISABLE, &pdata->regs->regs_v1.tmr);
@@ -278,7 +454,7 @@ static void imx_tmu_init(struct udevice *dev)
writel(TMTMIR_DEFAULT, &pdata->regs->regs_v1.tmtmir);
}
- imx_tmu_arch_init((void *)pdata->regs);
+ imx_tmu_arch_init(dev);
}
static int imx_tmu_enable_msite(struct udevice *dev)
@@ -287,7 +463,7 @@ static int imx_tmu_enable_msite(struct udevice *dev)
ulong drv_data = dev_get_driver_data(dev);
u32 reg;
- debug("%s\n", __func__);
+ dev_dbg(dev, "%s\n", __func__);
if (!pdata->regs)
return -EIO;
@@ -319,6 +495,22 @@ static int imx_tmu_enable_msite(struct udevice *dev)
/* Enable monitor */
reg |= TER_EN;
writel(reg, &pdata->regs->regs_v2.ter);
+ } else if (drv_data & FLAGS_VER4) {
+ reg = readl(&pdata->regs->regs_v4.tcmcfg);
+ reg |= (1 << 30) | (1 << 28);
+ reg &= ~0xF000; /* set SAR clk = IPG clk /16 */
+ writel(reg, &pdata->regs->regs_v4.tcmcfg);
+
+ /* Set ALPF*/
+ reg = readl(&pdata->regs->regs_v4.tmr);
+ reg |= TMR_ALPF;
+ writel(reg, &pdata->regs->regs_v4.tmr);
+
+ writel(1, &pdata->regs->regs_v4.tmsr);
+
+ /* Enable ME */
+ reg |= TMR_ME;
+ writel(reg, &pdata->regs->regs_v4.tmr);
} else {
/* Clear the ME before setting MSITE and ALPF*/
reg = readl(&pdata->regs->regs_v1.tmr);
@@ -346,7 +538,7 @@ static int imx_tmu_bind(struct udevice *dev)
const void *prop;
int minc, maxc;
- debug("%s dev name %s\n", __func__, dev->name);
+ dev_dbg(dev, "%s\n", __func__);
prop = dev_read_prop(dev, "compatible", NULL);
if (!prop)
@@ -367,8 +559,7 @@ static int imx_tmu_bind(struct udevice *dev)
dev->driver_data, offset,
NULL);
if (ret)
- printf("Error binding driver '%s': %d\n",
- dev->driver->name, ret);
+ dev_err(dev, "Error binding driver: %d\n", ret);
}
return 0;
@@ -381,7 +572,7 @@ static int imx_tmu_parse_fdt(struct udevice *dev)
ofnode trips_np;
int ret;
- debug("%s dev name %s\n", __func__, dev->name);
+ dev_dbg(dev, "%s\n", __func__);
if (pdata->zone_node) {
pdata->regs = (union tmu_regs *)dev_read_addr_ptr(dev);
@@ -409,7 +600,7 @@ static int imx_tmu_parse_fdt(struct udevice *dev)
else
pdata->id = 0;
- debug("args.args_count %d, id %d\n", args.args_count, pdata->id);
+ dev_dbg(dev, "args.args_count %d, id %d\n", args.args_count, pdata->id);
pdata->polling_delay = dev_read_u32_default(dev, "polling-delay", 1000);
@@ -428,8 +619,8 @@ static int imx_tmu_parse_fdt(struct udevice *dev)
continue;
}
- debug("id %d polling_delay %d, critical %d, alert %d\n",
- pdata->id, pdata->polling_delay, pdata->critical, pdata->alert);
+ dev_dbg(dev, "id %d polling_delay %d, critical %d, alert %d\n",
+ pdata->id, pdata->polling_delay, pdata->critical, pdata->alert);
return 0;
}
@@ -441,7 +632,7 @@ static int imx_tmu_probe(struct udevice *dev)
ret = imx_tmu_parse_fdt(dev);
if (ret) {
- printf("Error in parsing TMU FDT %d\n", ret);
+ dev_err(dev, "Error in parsing TMU FDT %d\n", ret);
return ret;
}
@@ -460,6 +651,7 @@ static const struct udevice_id imx_tmu_ids[] = {
{ .compatible = "fsl,imx8mq-tmu", },
{ .compatible = "fsl,imx8mm-tmu", .data = FLAGS_VER2, },
{ .compatible = "fsl,imx8mp-tmu", .data = FLAGS_VER3, },
+ { .compatible = "fsl,imx93-tmu", .data = FLAGS_VER4, },
{ }
};
diff --git a/drivers/watchdog/ulp_wdog.c b/drivers/watchdog/ulp_wdog.c
index c21aa3af55f..0eea04ed2c6 100644
--- a/drivers/watchdog/ulp_wdog.c
+++ b/drivers/watchdog/ulp_wdog.c
@@ -122,6 +122,7 @@ void hw_watchdog_init(void)
ulp_watchdog_init(wdog, CONFIG_WATCHDOG_TIMEOUT_MSECS);
}
+#if !CONFIG_IS_ENABLED(SYSRESET)
void reset_cpu(void)
{
struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE_ADDR;
@@ -159,6 +160,7 @@ void reset_cpu(void)
while (1);
}
+#endif
static int ulp_wdt_start(struct udevice *dev, u64 timeout_ms, ulong flags)
{
generated by cgit v1.2.3 (git 2.0.4) at 2025-08-06 11:23:18 +0000