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-rw-r--r--drivers/clk/Kconfig1
-rw-r--r--drivers/clk/Makefile1
-rw-r--r--drivers/clk/thead/Kconfig19
-rw-r--r--drivers/clk/thead/Makefile5
-rw-r--r--drivers/clk/thead/clk-th1520-ap.c1031
-rw-r--r--drivers/ram/Kconfig1
-rw-r--r--drivers/ram/Makefile4
-rw-r--r--drivers/ram/thead/Kconfig5
-rw-r--r--drivers/ram/thead/Makefile1
-rw-r--r--drivers/ram/thead/th1520_ddr.c787
10 files changed, 1855 insertions, 0 deletions
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 18bd640a68b..19aa2ffa539 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -271,6 +271,7 @@ source "drivers/clk/starfive/Kconfig"
source "drivers/clk/stm32/Kconfig"
source "drivers/clk/tegra/Kconfig"
source "drivers/clk/ti/Kconfig"
+source "drivers/clk/thead/Kconfig"
source "drivers/clk/uniphier/Kconfig"
endmenu
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 8411205ee04..5f0c0d8a5c2 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -20,6 +20,7 @@ obj-y += imx/
obj-$(CONFIG_CLK_JH7110) += starfive/
obj-y += tegra/
obj-y += ti/
+obj-$(CONFIG_CLK_THEAD) += thead/
obj-$(CONFIG_$(PHASE_)CLK_INTEL) += intel/
obj-$(CONFIG_ARCH_ASPEED) += aspeed/
obj-$(CONFIG_ARCH_MEDIATEK) += mediatek/
diff --git a/drivers/clk/thead/Kconfig b/drivers/clk/thead/Kconfig
new file mode 100644
index 00000000000..e815286b085
--- /dev/null
+++ b/drivers/clk/thead/Kconfig
@@ -0,0 +1,19 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# Copyright (c) 2025, Yao Zi <ziyao@disroot.org>
+
+config CLK_THEAD
+ bool "Clock support for T-Head SoCs"
+ depends on CLK
+
+if CLK_THEAD
+
+config CLK_THEAD_TH1520_AP
+ bool "T-Head TH1520 AP clock support"
+ select CLK_CCF
+ default THEAD_TH1520
+ help
+ This enables support clock driver for T-Head TH1520 Application
+ processor.
+
+endif
diff --git a/drivers/clk/thead/Makefile b/drivers/clk/thead/Makefile
new file mode 100644
index 00000000000..8cc05ed7914
--- /dev/null
+++ b/drivers/clk/thead/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# Copyright (C) 2025 Yao Zi <ziyao@disroot.org>
+
+obj-$(CONFIG_CLK_THEAD_TH1520_AP) += clk-th1520-ap.o
diff --git a/drivers/clk/thead/clk-th1520-ap.c b/drivers/clk/thead/clk-th1520-ap.c
new file mode 100644
index 00000000000..b80ad05b8ad
--- /dev/null
+++ b/drivers/clk/thead/clk-th1520-ap.c
@@ -0,0 +1,1031 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org>
+ * Copyright (C) 2023 Vivo Communication Technology Co. Ltd.
+ * Copyright (C) 2025 Yao Zi <ziyao@disroot.org>
+ * Authors: Yangtao Li <frank.li@vivo.com>
+ */
+
+#include <asm/io.h>
+#include <dm.h>
+#include <linux/bitfield.h>
+#include <linux/clk-provider.h>
+
+#include <dt-bindings/clock/thead,th1520-clk-ap.h>
+
+#define TH1520_PLL_POSTDIV2 GENMASK(26, 24)
+#define TH1520_PLL_POSTDIV1 GENMASK(22, 20)
+#define TH1520_PLL_FBDIV GENMASK(19, 8)
+#define TH1520_PLL_REFDIV GENMASK(5, 0)
+#define TH1520_PLL_BYPASS BIT(30)
+#define TH1520_PLL_DSMPD BIT(24)
+#define TH1520_PLL_FRAC GENMASK(23, 0)
+#define TH1520_PLL_FRAC_BITS 24
+
+static const char ccu_osc_name_to_be_filled[] = "TO BE FILLED";
+
+struct ccu_internal {
+ u8 shift;
+ u8 width;
+};
+
+struct ccu_div_internal {
+ u8 shift;
+ u8 width;
+};
+
+struct ccu_common {
+ void __iomem *reg;
+ const char *name;
+ struct clk clk;
+ int clkid;
+ u16 cfg0;
+ u16 cfg1;
+};
+
+struct ccu_mux {
+ struct ccu_common common;
+ struct ccu_internal mux;
+ const char **parents;
+ size_t num_parents;
+};
+
+struct ccu_gate {
+ struct ccu_common common;
+ const char *parent;
+ u32 enable;
+};
+
+struct ccu_div {
+ struct ccu_div_internal div;
+ struct ccu_common common;
+ struct ccu_internal mux;
+ const char **parents;
+ size_t num_parents;
+ u32 enable;
+};
+
+struct ccu_pll {
+ struct ccu_common common;
+};
+
+#define TH_CCU_ARG(_shift, _width) \
+ { \
+ .shift = _shift, \
+ .width = _width, \
+ }
+
+#define TH_CCU_DIV_FLAGS(_shift, _width, _flags) \
+ { \
+ .shift = _shift, \
+ .width = _width, \
+ }
+
+#define CCU_GATE(_clkid, _struct, _name, _parent, _reg, _gate, _flags) \
+ struct ccu_gate _struct = { \
+ .parent = _parent, \
+ .enable = _gate, \
+ .common = { \
+ .clkid = _clkid, \
+ .cfg0 = _reg, \
+ .name = _name, \
+ } \
+ }
+
+static inline struct ccu_common *clk_to_ccu_common(struct clk *clk)
+{
+ return container_of(clk, struct ccu_common, clk);
+}
+
+static inline struct ccu_mux *clk_to_ccu_mux(struct clk *clk)
+{
+ struct ccu_common *common = clk_to_ccu_common(clk);
+
+ return container_of(common, struct ccu_mux, common);
+}
+
+static inline struct ccu_pll *clk_to_ccu_pll(struct clk *clk)
+{
+ struct ccu_common *common = clk_to_ccu_common(clk);
+
+ return container_of(common, struct ccu_pll, common);
+}
+
+static inline struct ccu_div *clk_to_ccu_div(struct clk *clk)
+{
+ struct ccu_common *common = clk_to_ccu_common(clk);
+
+ return container_of(common, struct ccu_div, common);
+}
+
+static inline struct ccu_gate *clk_to_ccu_gate(struct clk *clk)
+{
+ struct ccu_common *common = clk_to_ccu_common(clk);
+
+ return container_of(common, struct ccu_gate, common);
+}
+
+static int ccu_set_parent_helper(struct ccu_common *common,
+ struct ccu_internal *mux,
+ u8 index)
+{
+ clrsetbits_le32(common->reg + common->cfg0,
+ GENMASK(mux->width - 1, 0) << mux->shift,
+ index << mux->shift);
+
+ return 0;
+}
+
+static void ccu_disable_helper(struct ccu_common *common, u32 gate)
+{
+ if (!gate)
+ return;
+
+ clrsetbits_le32(common->reg + common->cfg0,
+ gate, ~gate);
+}
+
+static int ccu_enable_helper(struct ccu_common *common, u32 gate)
+{
+ u32 val;
+
+ if (!gate)
+ return 0;
+
+ clrsetbits_le32(common->reg + common->cfg0, gate, gate);
+ val = readl(common->reg + common->cfg0);
+
+ return 0;
+}
+
+static int ccu_get_parent_index_helper(const char * const *parents,
+ int num_parents, struct clk *parent)
+{
+ const char *parent_name = parent->dev->name;
+ unsigned int index;
+
+ for (index = 0; index < num_parents; index++) {
+ if (!strcmp(parents[index], parent_name))
+ return index;
+ }
+
+ return -ENOENT;
+}
+
+static unsigned long ccu_div_get_rate(struct clk *clk)
+{
+ struct ccu_div *cd = clk_to_ccu_div(clk);
+ unsigned long rate;
+ unsigned int val;
+
+ val = readl(cd->common.reg + cd->common.cfg0);
+ val = val >> cd->div.shift;
+ val &= GENMASK(cd->div.width - 1, 0);
+ rate = divider_recalc_rate(clk, clk_get_parent_rate(clk), val, NULL,
+ 0, cd->div.width);
+
+ return rate;
+}
+
+static int ccu_div_get_parent(struct ccu_div *cd)
+{
+ u32 val = readl(cd->common.reg + cd->common.cfg0);
+
+ return (val >> cd->mux.shift) & GENMASK(cd->mux.width - 1, 0);
+}
+
+static int ccu_div_set_parent(struct clk *clk, struct clk *parent)
+{
+ struct ccu_div *cd = clk_to_ccu_div(clk);
+ u8 id;
+
+ id = ccu_get_parent_index_helper(cd->parents, cd->num_parents, parent);
+ if (id < 0)
+ return id;
+
+ return ccu_set_parent_helper(&cd->common, &cd->mux, id);
+}
+
+static int ccu_div_disable(struct clk *clk)
+{
+ struct ccu_div *cd = clk_to_ccu_div(clk);
+
+ ccu_disable_helper(&cd->common, cd->enable);
+
+ return 0;
+}
+
+static int ccu_div_enable(struct clk *clk)
+{
+ struct ccu_div *cd = clk_to_ccu_div(clk);
+
+ return ccu_enable_helper(&cd->common, cd->enable);
+}
+
+static const struct clk_ops ccu_div_ops = {
+ .disable = ccu_div_disable,
+ .enable = ccu_div_enable,
+ .set_parent = ccu_div_set_parent,
+ .get_rate = ccu_div_get_rate,
+};
+
+U_BOOT_DRIVER(th1520_clk_div) = {
+ .name = "th1520_clk_div",
+ .id = UCLASS_CLK,
+ .ops = &ccu_div_ops,
+};
+
+static unsigned long th1520_pll_vco_recalc_rate(struct clk *clk,
+ unsigned long parent_rate)
+{
+ struct ccu_pll *pll = clk_to_ccu_pll(clk);
+ unsigned long div, mul, frac;
+ unsigned int cfg0, cfg1;
+ u64 rate = parent_rate;
+
+ cfg0 = readl(pll->common.reg + pll->common.cfg0);
+ cfg1 = readl(pll->common.reg + pll->common.cfg1);
+
+ mul = FIELD_GET(TH1520_PLL_FBDIV, cfg0);
+ div = FIELD_GET(TH1520_PLL_REFDIV, cfg0);
+ if (!(cfg1 & TH1520_PLL_DSMPD)) {
+ mul <<= TH1520_PLL_FRAC_BITS;
+ frac = FIELD_GET(TH1520_PLL_FRAC, cfg1);
+ mul += frac;
+ div <<= TH1520_PLL_FRAC_BITS;
+ }
+
+ rate = parent_rate * mul;
+ rate = rate / div;
+
+ return rate;
+}
+
+static unsigned long th1520_pll_postdiv_recalc_rate(struct clk *clk,
+ unsigned long parent_rate)
+{
+ struct ccu_pll *pll = clk_to_ccu_pll(clk);
+ unsigned long div, rate = parent_rate;
+ unsigned int cfg0, cfg1;
+
+ cfg0 = readl(pll->common.reg + pll->common.cfg0);
+ cfg1 = readl(pll->common.reg + pll->common.cfg1);
+
+ if (cfg1 & TH1520_PLL_BYPASS)
+ return rate;
+
+ div = FIELD_GET(TH1520_PLL_POSTDIV1, cfg0) *
+ FIELD_GET(TH1520_PLL_POSTDIV2, cfg0);
+
+ rate = rate / div;
+
+ return rate;
+}
+
+static unsigned long ccu_pll_get_rate(struct clk *clk)
+{
+ unsigned long rate = clk_get_parent_rate(clk);
+
+ rate = th1520_pll_vco_recalc_rate(clk, rate);
+ rate = th1520_pll_postdiv_recalc_rate(clk, rate);
+
+ return rate;
+}
+
+static const struct clk_ops clk_pll_ops = {
+ .get_rate = ccu_pll_get_rate,
+};
+
+U_BOOT_DRIVER(th1520_clk_pll) = {
+ .name = "th1520_clk_pll",
+ .id = UCLASS_CLK,
+ .ops = &clk_pll_ops,
+};
+
+static struct ccu_pll cpu_pll0_clk = {
+ .common = {
+ .clkid = CLK_CPU_PLL0,
+ .cfg0 = 0x000,
+ .cfg1 = 0x004,
+ .name = "cpu-pll0",
+ },
+};
+
+static struct ccu_pll cpu_pll1_clk = {
+ .common = {
+ .clkid = CLK_CPU_PLL1,
+ .cfg0 = 0x010,
+ .cfg1 = 0x014,
+ .name = "cpu-pll1",
+ },
+};
+
+static struct ccu_pll gmac_pll_clk = {
+ .common = {
+ .clkid = CLK_GMAC_PLL,
+ .cfg0 = 0x020,
+ .cfg1 = 0x024,
+ .name = "gmac-pll",
+ },
+};
+
+static const char *gmac_pll_clk_parent[] = {
+ "gmac-pll",
+};
+
+static struct ccu_pll video_pll_clk = {
+ .common = {
+ .clkid = CLK_VIDEO_PLL,
+ .cfg0 = 0x030,
+ .cfg1 = 0x034,
+ .name = "video-pll",
+ },
+};
+
+static const char *video_pll_clk_parent[] = {
+ "video-pll",
+};
+
+static struct ccu_pll dpu0_pll_clk = {
+ .common = {
+ .clkid = CLK_DPU0_PLL,
+ .cfg0 = 0x040,
+ .cfg1 = 0x044,
+ .name = "dpu0-pll",
+ },
+};
+
+static const char *dpu0_pll_clk_parent[] = {
+ "dpu0-pll",
+};
+
+static struct ccu_pll dpu1_pll_clk = {
+ .common = {
+ .clkid = CLK_DPU1_PLL,
+ .cfg0 = 0x050,
+ .cfg1 = 0x054,
+ .name = "dpu1-pll",
+ },
+};
+
+static const char *dpu1_pll_clk_parent[] = {
+ "dpu1-pll",
+};
+
+static struct ccu_pll tee_pll_clk = {
+ .common = {
+ .clkid = CLK_TEE_PLL,
+ .cfg0 = 0x060,
+ .cfg1 = 0x064,
+ .name = "tee-pll",
+ },
+};
+
+static const char *c910_i0_parents[] = {
+ "cpu-pll0", ccu_osc_name_to_be_filled,
+};
+
+static struct ccu_mux c910_i0_clk = {
+ .parents = c910_i0_parents,
+ .num_parents = ARRAY_SIZE(c910_i0_parents),
+ .mux = TH_CCU_ARG(1, 1),
+ .common = {
+ .clkid = CLK_C910_I0,
+ .cfg0 = 0x100,
+ .name = "c910-i0",
+ }
+};
+
+static const char *c910_parents[] = {
+ "c910-i0", "cpu-pll1",
+};
+
+static struct ccu_mux c910_clk = {
+ .parents = c910_parents,
+ .num_parents = ARRAY_SIZE(c910_parents),
+ .mux = TH_CCU_ARG(0, 1),
+ .common = {
+ .clkid = CLK_C910,
+ .cfg0 = 0x100,
+ .name = "c910",
+ }
+};
+
+static const char *ahb2_cpusys_parents[] = {
+ "gmac-pll", ccu_osc_name_to_be_filled,
+};
+
+static struct ccu_div ahb2_cpusys_hclk = {
+ .parents = ahb2_cpusys_parents,
+ .num_parents = ARRAY_SIZE(ahb2_cpusys_parents),
+ .div = TH_CCU_DIV_FLAGS(0, 3, CLK_DIVIDER_ONE_BASED),
+ .mux = TH_CCU_ARG(5, 1),
+ .common = {
+ .clkid = CLK_AHB2_CPUSYS_HCLK,
+ .cfg0 = 0x120,
+ .name = "ahb2-cpusys-hclk",
+ },
+};
+
+static const char *ahb2_cpusys_hclk_parents[] = {
+ "ahb2-cpusys-hclk",
+};
+
+static struct ccu_div apb3_cpusys_pclk = {
+ .parents = ahb2_cpusys_hclk_parents,
+ .num_parents = ARRAY_SIZE(ahb2_cpusys_hclk_parents),
+ .div = TH_CCU_ARG(0, 3),
+ .common = {
+ .clkid = CLK_APB3_CPUSYS_PCLK,
+ .cfg0 = 0x130,
+ .name = "apb3-cpusys-pclk",
+ },
+};
+
+static struct ccu_div axi4_cpusys2_aclk = {
+ .parents = gmac_pll_clk_parent,
+ .num_parents = ARRAY_SIZE(gmac_pll_clk_parent),
+ .div = TH_CCU_DIV_FLAGS(0, 3, CLK_DIVIDER_ONE_BASED),
+ .common = {
+ .clkid = CLK_AXI4_CPUSYS2_ACLK,
+ .cfg0 = 0x134,
+ .name = "axi4-cpusys2-aclk",
+ },
+};
+
+static const char *axi_parents[] = {
+ "video-pll", ccu_osc_name_to_be_filled,
+};
+
+static struct ccu_div axi_aclk = {
+ .parents = axi_parents,
+ .num_parents = ARRAY_SIZE(axi_parents),
+ .div = TH_CCU_DIV_FLAGS(0, 4, CLK_DIVIDER_ONE_BASED),
+ .mux = TH_CCU_ARG(5, 1),
+ .common = {
+ .clkid = CLK_AXI_ACLK,
+ .cfg0 = 0x138,
+ .name = "axi-aclk",
+ },
+};
+
+static const char *perisys_ahb_hclk_parents[] = {
+ "gmac-pll", ccu_osc_name_to_be_filled,
+};
+
+static struct ccu_div perisys_ahb_hclk = {
+ .parents = perisys_ahb_hclk_parents,
+ .num_parents = ARRAY_SIZE(perisys_ahb_hclk_parents),
+ .enable = BIT(6),
+ .div = TH_CCU_DIV_FLAGS(0, 4, CLK_DIVIDER_ONE_BASED),
+ .mux = TH_CCU_ARG(5, 1),
+ .common = {
+ .clkid = CLK_PERI_AHB_HCLK,
+ .cfg0 = 0x140,
+ .name = "perisys-ahb-hclk",
+ },
+};
+
+static const char *perisys_ahb_hclk_parent[] = {
+ "perisys-ahb-hclk",
+};
+
+static struct ccu_div perisys_apb_pclk = {
+ .parents = perisys_ahb_hclk_parent,
+ .num_parents = ARRAY_SIZE(perisys_ahb_hclk_parent),
+ .div = TH_CCU_ARG(0, 3),
+ .common = {
+ .clkid = CLK_PERI_APB_PCLK,
+ .cfg0 = 0x150,
+ .name = "perisys-apb-pclk",
+ },
+};
+
+static struct ccu_div peri2sys_apb_pclk = {
+ .parents = gmac_pll_clk_parent,
+ .num_parents = ARRAY_SIZE(gmac_pll_clk_parent),
+ .div = TH_CCU_DIV_FLAGS(4, 3, CLK_DIVIDER_ONE_BASED),
+ .common = {
+ .clkid = CLK_PERI2APB_PCLK,
+ .cfg0 = 0x150,
+ .name = "peri2sys-apb-pclk",
+ },
+};
+
+static const char *apb_parents[] = {
+ "gmac-pll", ccu_osc_name_to_be_filled,
+};
+
+static struct ccu_div apb_pclk = {
+ .parents = apb_parents,
+ .num_parents = ARRAY_SIZE(apb_parents),
+ .enable = BIT(5),
+ .div = TH_CCU_DIV_FLAGS(0, 4, CLK_DIVIDER_ONE_BASED),
+ .mux = TH_CCU_ARG(7, 1),
+ .common = {
+ .clkid = CLK_APB_PCLK,
+ .cfg0 = 0x1c4,
+ .name = "apb-pclk",
+ },
+};
+
+static const char *npu_parents[] = {
+ "gmac-pll", "video-pll",
+};
+
+static struct ccu_div npu_clk = {
+ .parents = npu_parents,
+ .num_parents = ARRAY_SIZE(npu_parents),
+ .enable = BIT(4),
+ .div = TH_CCU_DIV_FLAGS(0, 3, CLK_DIVIDER_ONE_BASED),
+ .mux = TH_CCU_ARG(6, 1),
+ .common = {
+ .clkid = CLK_NPU,
+ .cfg0 = 0x1c8,
+ .name = "npu",
+ },
+};
+
+static struct ccu_div vi_clk = {
+ .parents = video_pll_clk_parent,
+ .num_parents = ARRAY_SIZE(video_pll_clk_parent),
+ .div = TH_CCU_DIV_FLAGS(16, 4, CLK_DIVIDER_ONE_BASED),
+ .common = {
+ .clkid = CLK_VI,
+ .cfg0 = 0x1d0,
+ .name = "vi",
+ },
+};
+
+static struct ccu_div vi_ahb_clk = {
+ .parents = video_pll_clk_parent,
+ .num_parents = ARRAY_SIZE(video_pll_clk_parent),
+ .div = TH_CCU_DIV_FLAGS(0, 4, CLK_DIVIDER_ONE_BASED),
+ .common = {
+ .clkid = CLK_VI_AHB,
+ .cfg0 = 0x1d0,
+ .name = "vi-ahb",
+ },
+};
+
+static struct ccu_div vo_axi_clk = {
+ .parents = video_pll_clk_parent,
+ .num_parents = ARRAY_SIZE(video_pll_clk_parent),
+ .enable = BIT(5),
+ .div = TH_CCU_DIV_FLAGS(0, 4, CLK_DIVIDER_ONE_BASED),
+ .common = {
+ .clkid = CLK_VO_AXI,
+ .cfg0 = 0x1dc,
+ .name = "vo-axi",
+ },
+};
+
+static struct ccu_div vp_apb_clk = {
+ .parents = gmac_pll_clk_parent,
+ .num_parents = ARRAY_SIZE(gmac_pll_clk_parent),
+ .div = TH_CCU_DIV_FLAGS(0, 3, CLK_DIVIDER_ONE_BASED),
+ .common = {
+ .clkid = CLK_VP_APB,
+ .cfg0 = 0x1e0,
+ .name = "vp-apb",
+ },
+};
+
+static struct ccu_div vp_axi_clk = {
+ .parents = video_pll_clk_parent,
+ .num_parents = ARRAY_SIZE(video_pll_clk_parent),
+ .enable = BIT(15),
+ .div = TH_CCU_DIV_FLAGS(8, 4, CLK_DIVIDER_ONE_BASED),
+ .common = {
+ .clkid = CLK_VP_AXI,
+ .cfg0 = 0x1e0,
+ .name = "vp-axi",
+ },
+};
+
+static struct ccu_div venc_clk = {
+ .parents = gmac_pll_clk_parent,
+ .num_parents = ARRAY_SIZE(gmac_pll_clk_parent),
+ .enable = BIT(5),
+ .div = TH_CCU_DIV_FLAGS(0, 3, CLK_DIVIDER_ONE_BASED),
+ .common = {
+ .clkid = CLK_VENC,
+ .cfg0 = 0x1e4,
+ .name = "venc",
+ },
+};
+
+static struct ccu_div dpu0_clk = {
+ .parents = dpu0_pll_clk_parent,
+ .num_parents = ARRAY_SIZE(dpu0_pll_clk_parent),
+ .div = TH_CCU_DIV_FLAGS(0, 8, CLK_DIVIDER_ONE_BASED),
+ .common = {
+ .clkid = CLK_DPU0,
+ .cfg0 = 0x1e8,
+ .name = "dpu0",
+ },
+};
+
+static struct ccu_div dpu1_clk = {
+ .parents = dpu1_pll_clk_parent,
+ .num_parents = ARRAY_SIZE(dpu1_pll_clk_parent),
+ .div = TH_CCU_DIV_FLAGS(0, 8, CLK_DIVIDER_ONE_BASED),
+ .common = {
+ .clkid = CLK_DPU1,
+ .cfg0 = 0x1ec,
+ .name = "dpu1",
+ },
+};
+
+static CCU_GATE(CLK_BROM, brom_clk, "brom", "ahb2-cpusys-hclk", 0x100, BIT(4), 0);
+static CCU_GATE(CLK_BMU, bmu_clk, "bmu", "axi4-cpusys2-aclk", 0x100, BIT(5), 0);
+static CCU_GATE(CLK_AON2CPU_A2X, aon2cpu_a2x_clk, "aon2cpu-a2x", "axi4-cpusys2-aclk",
+ 0x134, BIT(8), 0);
+static CCU_GATE(CLK_X2X_CPUSYS, x2x_cpusys_clk, "x2x-cpusys", "axi4-cpusys2-aclk",
+ 0x134, BIT(7), 0);
+static CCU_GATE(CLK_CPU2AON_X2H, cpu2aon_x2h_clk, "cpu2aon-x2h", "axi-aclk", 0x138, BIT(8), 0);
+static CCU_GATE(CLK_CPU2PERI_X2H, cpu2peri_x2h_clk, "cpu2peri-x2h", "axi4-cpusys2-aclk",
+ 0x140, BIT(9), CLK_IGNORE_UNUSED);
+static CCU_GATE(CLK_PERISYS_APB1_HCLK, perisys_apb1_hclk, "perisys-apb1-hclk", "perisys-ahb-hclk",
+ 0x150, BIT(9), 0);
+static CCU_GATE(CLK_PERISYS_APB2_HCLK, perisys_apb2_hclk, "perisys-apb2-hclk", "perisys-ahb-hclk",
+ 0x150, BIT(10), CLK_IGNORE_UNUSED);
+static CCU_GATE(CLK_PERISYS_APB3_HCLK, perisys_apb3_hclk, "perisys-apb3-hclk", "perisys-ahb-hclk",
+ 0x150, BIT(11), CLK_IGNORE_UNUSED);
+static CCU_GATE(CLK_PERISYS_APB4_HCLK, perisys_apb4_hclk, "perisys-apb4-hclk", "perisys-ahb-hclk",
+ 0x150, BIT(12), 0);
+static CCU_GATE(CLK_NPU_AXI, npu_axi_clk, "npu-axi", "axi-aclk", 0x1c8, BIT(5), 0);
+static CCU_GATE(CLK_CPU2VP, cpu2vp_clk, "cpu2vp", "axi-aclk", 0x1e0, BIT(13), 0);
+static CCU_GATE(CLK_EMMC_SDIO, emmc_sdio_clk, "emmc-sdio", "emmc-sdio-ref", 0x204, BIT(30), 0);
+static CCU_GATE(CLK_GMAC1, gmac1_clk, "gmac1", "gmac-pll", 0x204, BIT(26), 0);
+static CCU_GATE(CLK_PADCTRL1, padctrl1_clk, "padctrl1", "perisys-apb-pclk", 0x204, BIT(24), 0);
+static CCU_GATE(CLK_DSMART, dsmart_clk, "dsmart", "perisys-apb-pclk", 0x204, BIT(23), 0);
+static CCU_GATE(CLK_PADCTRL0, padctrl0_clk, "padctrl0", "perisys-apb-pclk", 0x204, BIT(22), 0);
+static CCU_GATE(CLK_GMAC_AXI, gmac_axi_clk, "gmac-axi", "axi4-cpusys2-aclk", 0x204, BIT(21), 0);
+static CCU_GATE(CLK_GPIO3, gpio3_clk, "gpio3-clk", "peri2sys-apb-pclk", 0x204, BIT(20), 0);
+static CCU_GATE(CLK_GMAC0, gmac0_clk, "gmac0", "gmac-pll", 0x204, BIT(19), 0);
+static CCU_GATE(CLK_PWM, pwm_clk, "pwm", "perisys-apb-pclk", 0x204, BIT(18), 0);
+static CCU_GATE(CLK_QSPI0, qspi0_clk, "qspi0", "video-pll", 0x204, BIT(17), 0);
+static CCU_GATE(CLK_QSPI1, qspi1_clk, "qspi1", "video-pll", 0x204, BIT(16), 0);
+static CCU_GATE(CLK_SPI, spi_clk, "spi", "video-pll", 0x204, BIT(15), 0);
+static CCU_GATE(CLK_UART0_PCLK, uart0_pclk, "uart0-pclk", "perisys-apb-pclk", 0x204, BIT(14), 0);
+static CCU_GATE(CLK_UART1_PCLK, uart1_pclk, "uart1-pclk", "perisys-apb-pclk", 0x204, BIT(13), 0);
+static CCU_GATE(CLK_UART2_PCLK, uart2_pclk, "uart2-pclk", "perisys-apb-pclk", 0x204, BIT(12), 0);
+static CCU_GATE(CLK_UART3_PCLK, uart3_pclk, "uart3-pclk", "perisys-apb-pclk", 0x204, BIT(11), 0);
+static CCU_GATE(CLK_UART4_PCLK, uart4_pclk, "uart4-pclk", "perisys-apb-pclk", 0x204, BIT(10), 0);
+static CCU_GATE(CLK_UART5_PCLK, uart5_pclk, "uart5-pclk", "perisys-apb-pclk", 0x204, BIT(9), 0);
+static CCU_GATE(CLK_GPIO0, gpio0_clk, "gpio0-clk", "perisys-apb-pclk", 0x204, BIT(8), 0);
+static CCU_GATE(CLK_GPIO1, gpio1_clk, "gpio1-clk", "perisys-apb-pclk", 0x204, BIT(7), 0);
+static CCU_GATE(CLK_GPIO2, gpio2_clk, "gpio2-clk", "peri2sys-apb-pclk", 0x204, BIT(6), 0);
+static CCU_GATE(CLK_I2C0, i2c0_clk, "i2c0", "perisys-apb-pclk", 0x204, BIT(5), 0);
+static CCU_GATE(CLK_I2C1, i2c1_clk, "i2c1", "perisys-apb-pclk", 0x204, BIT(4), 0);
+static CCU_GATE(CLK_I2C2, i2c2_clk, "i2c2", "perisys-apb-pclk", 0x204, BIT(3), 0);
+static CCU_GATE(CLK_I2C3, i2c3_clk, "i2c3", "perisys-apb-pclk", 0x204, BIT(2), 0);
+static CCU_GATE(CLK_I2C4, i2c4_clk, "i2c4", "perisys-apb-pclk", 0x204, BIT(1), 0);
+static CCU_GATE(CLK_I2C5, i2c5_clk, "i2c5", "perisys-apb-pclk", 0x204, BIT(0), 0);
+static CCU_GATE(CLK_SPINLOCK, spinlock_clk, "spinlock", "ahb2-cpusys-hclk", 0x208, BIT(10), 0);
+static CCU_GATE(CLK_DMA, dma_clk, "dma", "axi4-cpusys2-aclk", 0x208, BIT(8), 0);
+static CCU_GATE(CLK_MBOX0, mbox0_clk, "mbox0", "apb3-cpusys-pclk", 0x208, BIT(7), 0);
+static CCU_GATE(CLK_MBOX1, mbox1_clk, "mbox1", "apb3-cpusys-pclk", 0x208, BIT(6), 0);
+static CCU_GATE(CLK_MBOX2, mbox2_clk, "mbox2", "apb3-cpusys-pclk", 0x208, BIT(5), 0);
+static CCU_GATE(CLK_MBOX3, mbox3_clk, "mbox3", "apb3-cpusys-pclk", 0x208, BIT(4), 0);
+static CCU_GATE(CLK_WDT0, wdt0_clk, "wdt0", "apb3-cpusys-pclk", 0x208, BIT(3), 0);
+static CCU_GATE(CLK_WDT1, wdt1_clk, "wdt1", "apb3-cpusys-pclk", 0x208, BIT(2), 0);
+static CCU_GATE(CLK_TIMER0, timer0_clk, "timer0", "apb3-cpusys-pclk", 0x208, BIT(1), 0);
+static CCU_GATE(CLK_TIMER1, timer1_clk, "timer1", "apb3-cpusys-pclk", 0x208, BIT(0), 0);
+static CCU_GATE(CLK_SRAM0, sram0_clk, "sram0", "axi-aclk", 0x20c, BIT(4), 0);
+static CCU_GATE(CLK_SRAM1, sram1_clk, "sram1", "axi-aclk", 0x20c, BIT(3), 0);
+static CCU_GATE(CLK_SRAM2, sram2_clk, "sram2", "axi-aclk", 0x20c, BIT(2), 0);
+static CCU_GATE(CLK_SRAM3, sram3_clk, "sram3", "axi-aclk", 0x20c, BIT(1), 0);
+
+static const char *uart_sclk_parents[] = {
+ "gmac-pll-clk-100m", ccu_osc_name_to_be_filled,
+};
+
+static struct ccu_mux uart_sclk = {
+ .parents = uart_sclk_parents,
+ .num_parents = ARRAY_SIZE(uart_sclk_parents),
+ .mux = TH_CCU_ARG(0, 1),
+ .common = {
+ .clkid = CLK_UART_SCLK,
+ .cfg0 = 0x210,
+ .name = "uart-sclk",
+ }
+};
+
+static struct ccu_common *th1520_pll_clks[] = {
+ &cpu_pll0_clk.common,
+ &cpu_pll1_clk.common,
+ &gmac_pll_clk.common,
+ &video_pll_clk.common,
+ &dpu0_pll_clk.common,
+ &dpu1_pll_clk.common,
+ &tee_pll_clk.common,
+};
+
+static struct ccu_common *th1520_div_clks[] = {
+ &ahb2_cpusys_hclk.common,
+ &apb3_cpusys_pclk.common,
+ &axi4_cpusys2_aclk.common,
+ &perisys_ahb_hclk.common,
+ &perisys_apb_pclk.common,
+ &axi_aclk.common,
+ &peri2sys_apb_pclk.common,
+ &apb_pclk.common,
+ &npu_clk.common,
+ &vi_clk.common,
+ &vi_ahb_clk.common,
+ &vo_axi_clk.common,
+ &vp_apb_clk.common,
+ &vp_axi_clk.common,
+ &venc_clk.common,
+ &dpu0_clk.common,
+ &dpu1_clk.common,
+};
+
+static struct ccu_common *th1520_mux_clks[] = {
+ &c910_i0_clk.common,
+ &c910_clk.common,
+ &uart_sclk.common,
+};
+
+static struct ccu_common *th1520_gate_clks[] = {
+ &emmc_sdio_clk.common,
+ &aon2cpu_a2x_clk.common,
+ &x2x_cpusys_clk.common,
+ &brom_clk.common,
+ &bmu_clk.common,
+ &cpu2aon_x2h_clk.common,
+ &cpu2peri_x2h_clk.common,
+ &cpu2vp_clk.common,
+ &perisys_apb1_hclk.common,
+ &perisys_apb2_hclk.common,
+ &perisys_apb3_hclk.common,
+ &perisys_apb4_hclk.common,
+ &npu_axi_clk.common,
+ &gmac1_clk.common,
+ &padctrl1_clk.common,
+ &dsmart_clk.common,
+ &padctrl0_clk.common,
+ &gmac_axi_clk.common,
+ &gpio3_clk.common,
+ &gmac0_clk.common,
+ &pwm_clk.common,
+ &qspi0_clk.common,
+ &qspi1_clk.common,
+ &spi_clk.common,
+ &uart0_pclk.common,
+ &uart1_pclk.common,
+ &uart2_pclk.common,
+ &uart3_pclk.common,
+ &uart4_pclk.common,
+ &uart5_pclk.common,
+ &gpio0_clk.common,
+ &gpio1_clk.common,
+ &gpio2_clk.common,
+ &i2c0_clk.common,
+ &i2c1_clk.common,
+ &i2c2_clk.common,
+ &i2c3_clk.common,
+ &i2c4_clk.common,
+ &i2c5_clk.common,
+ &spinlock_clk.common,
+ &dma_clk.common,
+ &mbox0_clk.common,
+ &mbox1_clk.common,
+ &mbox2_clk.common,
+ &mbox3_clk.common,
+ &wdt0_clk.common,
+ &wdt1_clk.common,
+ &timer0_clk.common,
+ &timer1_clk.common,
+ &sram0_clk.common,
+ &sram1_clk.common,
+ &sram2_clk.common,
+ &sram3_clk.common,
+};
+
+static void th1520_clk_fill_osc_name(const char **names, size_t name_num,
+ const char *osc_name)
+{
+ size_t i;
+
+ for (i = 0; i < name_num; i++) {
+ if (names[i] == ccu_osc_name_to_be_filled)
+ names[i] = osc_name;
+ }
+}
+
+static int th1520_clk_probe(struct udevice *dev)
+{
+ struct clk *clk, osc_clk;
+ const char *osc_name;
+ void __iomem *base;
+ fdt_addr_t addr;
+ int ret, i;
+
+ addr = dev_read_addr(dev);
+ if (addr == FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ base = (void __iomem *)addr;
+
+ ret = clk_get_by_index(dev, 0, &osc_clk);
+ if (ret) {
+ pr_err("failed to get osc clock: %d\n", ret);
+ return ret;
+ }
+
+ osc_name = clk_hw_get_name(&osc_clk);
+
+ for (i = 0; i < ARRAY_SIZE(th1520_pll_clks); i++) {
+ struct ccu_common *common = th1520_pll_clks[i];
+
+ common->reg = base;
+
+ ret = clk_register(&common->clk, "th1520_clk_pll",
+ common->name, osc_name);
+ if (ret) {
+ pr_err("failed to register PLL %s: %d\n",
+ common->name, ret);
+ return ret;
+ }
+
+ common->clk.id = common->clkid;
+ }
+
+ for (i = 0; i < ARRAY_SIZE(th1520_div_clks); i++) {
+ struct ccu_div *cd = container_of(th1520_div_clks[i],
+ struct ccu_div, common);
+ const char *current_parent;
+
+ cd->common.reg = base;
+ th1520_clk_fill_osc_name(cd->parents, cd->num_parents,
+ osc_name);
+
+ if (cd->num_parents > 1)
+ current_parent = cd->parents[ccu_div_get_parent(cd)];
+ else
+ current_parent = cd->parents[0];
+
+ ret = clk_register(&cd->common.clk, "th1520_clk_div",
+ cd->common.name,
+ current_parent);
+
+ if (ret) {
+ pr_err("failed to register div clock %s: %d\n",
+ cd->common.name, ret);
+ return ret;
+ }
+
+ cd->common.clk.id = cd->common.clkid;
+ }
+
+ clk = clk_register_fixed_factor(dev, "gmac-pll-clk-100m", "gmac-pll",
+ 0, 1, 10);
+ if (IS_ERR(clk)) {
+ pr_err("failed to register gmac-pll-clk-100m: %d\n",
+ (int)PTR_ERR(clk));
+ return PTR_ERR(clk);
+ }
+ clk->id = CLK_PLL_GMAC_100M;
+
+ clk = clk_register_fixed_factor(dev, "emmc-sdio-ref", "video-pll",
+ 0, 1, 4);
+ if (IS_ERR(clk)) {
+ pr_err("failed to register emmc-sdio-ref: %d\n",
+ (int)PTR_ERR(clk));
+ return PTR_ERR(clk);
+ }
+
+ for (i = 0; i < ARRAY_SIZE(th1520_mux_clks); i++) {
+ struct ccu_mux *cm = container_of(th1520_mux_clks[i],
+ struct ccu_mux, common);
+
+ th1520_clk_fill_osc_name(cm->parents, cm->num_parents,
+ osc_name);
+
+ clk = clk_register_mux(dev, cm->common.name,
+ cm->parents, cm->num_parents,
+ 0,
+ base + cm->common.cfg0,
+ cm->mux.shift, cm->mux.width,
+ 0);
+ if (IS_ERR(clk)) {
+ pr_err("failed to register mux clock %s: %d\n",
+ cm->common.name, (int)PTR_ERR(clk));
+ return PTR_ERR(clk);
+ }
+
+ clk->id = cm->common.clkid;
+ }
+
+ for (i = 0; i < ARRAY_SIZE(th1520_gate_clks); i++) {
+ struct ccu_gate *cg = container_of(th1520_gate_clks[i],
+ struct ccu_gate, common);
+
+ th1520_clk_fill_osc_name(&cg->parent, 1, osc_name);
+
+ clk = clk_register_gate(dev, cg->common.name,
+ cg->parent,
+ 0,
+ base + cg->common.cfg0,
+ ffs(cg->enable) - 1, 0, NULL);
+ if (IS_ERR(clk)) {
+ pr_err("failed to register gate clock %s: %d\n",
+ cg->common.name, (int)PTR_ERR(clk));
+ return PTR_ERR(clk);
+ }
+
+ clk->id = cg->common.clkid;
+ }
+
+ return 0;
+}
+
+static const struct udevice_id th1520_clk_match[] = {
+ {
+ .compatible = "thead,th1520-clk-ap",
+ },
+ { /* sentinel */ },
+};
+
+static int th1520_clk_enable(struct clk *clk)
+{
+ struct clk *c;
+ int ret;
+
+ ret = clk_get_by_id(clk->id, &c);
+ if (ret)
+ return ret;
+
+ return clk_enable(c);
+}
+
+static int th1520_clk_disable(struct clk *clk)
+{
+ struct clk *c;
+ int ret;
+
+ ret = clk_get_by_id(clk->id, &c);
+ if (ret)
+ return ret;
+
+ return clk_disable(c);
+}
+
+static ulong th1520_clk_get_rate(struct clk *clk)
+{
+ struct clk *c;
+ int ret;
+
+ ret = clk_get_by_id(clk->id, &c);
+ if (ret)
+ return ret;
+
+ return clk_get_rate(c);
+}
+
+static ulong th1520_clk_set_rate(struct clk *clk, ulong rate)
+{
+ struct clk *c;
+ int ret;
+
+ ret = clk_get_by_id(clk->id, &c);
+ if (ret)
+ return ret;
+
+ return clk_set_rate(c, rate);
+}
+
+static int th1520_clk_set_parent(struct clk *clk, struct clk *parent)
+{
+ struct clk *c, *p;
+ int ret;
+
+ ret = clk_get_by_id(clk->id, &c);
+ if (ret)
+ return ret;
+
+ ret = clk_get_by_id(parent->id, &p);
+ if (ret)
+ return ret;
+
+ return clk_set_parent(c, p);
+}
+
+static const struct clk_ops th1520_clk_ops = {
+ .enable = th1520_clk_enable,
+ .disable = th1520_clk_disable,
+ .get_rate = th1520_clk_get_rate,
+ .set_rate = th1520_clk_set_rate,
+ .set_parent = th1520_clk_set_parent,
+};
+
+U_BOOT_DRIVER(th1520_clk) = {
+ .name = "th1520-clk",
+ .id = UCLASS_CLK,
+ .of_match = th1520_clk_match,
+ .probe = th1520_clk_probe,
+ .ops = &th1520_clk_ops,
+};
diff --git a/drivers/ram/Kconfig b/drivers/ram/Kconfig
index 2a40b0c9f81..39d03e8d3d3 100644
--- a/drivers/ram/Kconfig
+++ b/drivers/ram/Kconfig
@@ -135,3 +135,4 @@ source "drivers/ram/sifive/Kconfig"
source "drivers/ram/stm32mp1/Kconfig"
source "drivers/ram/starfive/Kconfig"
source "drivers/ram/sunxi/Kconfig"
+source "drivers/ram/thead/Kconfig"
diff --git a/drivers/ram/Makefile b/drivers/ram/Makefile
index f92e86eaa3f..82afd5fcbcc 100644
--- a/drivers/ram/Makefile
+++ b/drivers/ram/Makefile
@@ -30,3 +30,7 @@ obj-$(CONFIG_ARCH_OCTEON) += octeon/
obj-$(CONFIG_ARCH_RENESAS) += renesas/
obj-$(CONFIG_CADENCE_DDR_CTRL) += cadence/
+
+ifdef CONFIG_XPL_BUILD
+obj-$(CONFIG_SPL_THEAD_TH1520_DDR) += thead/
+endif
diff --git a/drivers/ram/thead/Kconfig b/drivers/ram/thead/Kconfig
new file mode 100644
index 00000000000..7b05abb6986
--- /dev/null
+++ b/drivers/ram/thead/Kconfig
@@ -0,0 +1,5 @@
+config SPL_THEAD_TH1520_DDR
+ bool "T-Head TH1520 DDR driver in SPL"
+ depends on SPL_RAM && THEAD_TH1520
+ help
+ This enables DDR support for T-Head TH1520 platforms.
diff --git a/drivers/ram/thead/Makefile b/drivers/ram/thead/Makefile
new file mode 100644
index 00000000000..ad4d053cfc2
--- /dev/null
+++ b/drivers/ram/thead/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_SPL_THEAD_TH1520_DDR) += th1520_ddr.o
diff --git a/drivers/ram/thead/th1520_ddr.c b/drivers/ram/thead/th1520_ddr.c
new file mode 100644
index 00000000000..bb4736b0236
--- /dev/null
+++ b/drivers/ram/thead/th1520_ddr.c
@@ -0,0 +1,787 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2017-2024 Alibaba Group Holding Limited
+ * Copyright (C) 2025 Yao Zi <ziyao@disroot.org>
+ */
+
+#include <binman.h>
+#include <binman_sym.h>
+#include <dm.h>
+#include <init.h>
+#include <linux/bitfield.h>
+#include <linux/iopoll.h>
+#include <ram.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#pragma pack(push, 1)
+
+struct th1520_ddr_fw {
+ u64 magic;
+ u8 type, ranknum, bitwidth, freq;
+ u8 reserved[8];
+
+ u32 cfgnum;
+ union th1520_ddr_cfg {
+ u32 opaddr;
+
+ struct th1520_ddr_phy {
+ u32 opaddr;
+ u16 data;
+ } phy;
+
+ struct th1520_ddr_range {
+ u32 opaddr;
+ u32 num;
+ u16 data[];
+ } range;
+ } cfgs[];
+};
+
+#pragma pack(pop)
+
+/* Firmware constants */
+#define TH1520_DDR_MAGIC 0x4452444445415448
+
+#define TH1520_DDR_TYPE_LPDDR4 0
+#define TH1520_DDR_TYPE_LPDDR4X 1
+
+#define TH1520_DDR_FREQ_2133 0
+#define TH1520_DDR_FREQ_3200 1
+#define TH1520_DDR_FREQ_3733 2
+#define TH1520_DDR_FREQ_4266 3
+
+#define TH1520_DDR_CFG_OP GENMASK(31, 24)
+#define TH1520_DDR_CFG_ADDR GENMASK(23, 0)
+
+#define TH1520_DDR_CFG_PHY0 0
+#define TH1520_DDR_CFG_PHY1 1
+#define TH1520_DDR_CFG_PHY 2
+#define TH1520_DDR_CFG_RANGE 3
+#define TH1520_DDR_CFG_WAITFW0 4
+#define TH1520_DDR_CFG_WAITFW1 5
+
+/* Driver constants */
+#define TH1520_SYS_PLL_TIMEOUT_US 30
+#define TH1520_CTRL_INIT_TIMEOUT_US 1000000
+#define TH1520_PHY_MSG_TIMEOUT_US 1000000
+
+/* System configuration registers */
+#define TH1520_SYS_DDR_CFG0 0x00
+#define TH1520_SYS_DDR_CFG0_APB_RSTN BIT(4)
+#define TH1520_SYS_DDR_CFG0_CTRL_RSTN BIT(5)
+#define TH1520_SYS_DDR_CFG0_PHY_PWROK_RSTN BIT(6)
+#define TH1520_SYS_DDR_CFG0_PHY_CORE_RSTN BIT(7)
+#define TH1520_SYS_DDR_CFG0_APB_PORT_RSTN(n) BIT(n + 4 + 4)
+#define TH1520_SYS_DDR_CFG1 0x04
+#define TH1520_SYS_PLL_CFG0 0x08
+#define TH1520_SYS_PLL_CFG0_POSTDIV2 GENMASK(26, 24)
+#define TH1520_SYS_PLL_CFG0_POSTDIV1 GENMASK(22, 20)
+#define TH1520_SYS_PLL_CFG0_FBDIV GENMASK(19, 8)
+#define TH1520_SYS_PLL_CFG0_REFDIV GENMASK(5, 0)
+#define TH1520_SYS_PLL_CFG1 0x0c
+#define TH1520_SYS_PLL_CFG1_RST BIT(30)
+#define TH1520_SYS_PLL_CFG1_FOUTPOSTDIVPD BIT(27)
+#define TH1520_SYS_PLL_CFG1_FOUT4PHASEPD BIT(25)
+#define Th1520_SYS_PLL_CFG1_DACPD BIT(24)
+#define TH1520_SYS_PLL_CFG2 0x10
+#define TH1520_SYS_PLL_CFG3 0x14
+#define TH1520_SYS_PLL_STS 0x18
+#define TH1520_SYS_PLL_STS_EN BIT(16)
+#define TH1520_SYS_PLL_STS_LOCKED BIT(0)
+
+/* DDR Controller Registers */
+#define TH1520_CTRL_MSTR 0x0000
+#define TH1520_CTRL_STAT 0x0004
+#define TH1520_CTRL_MRCTRL0 0x0010
+#define TH1520_CTRL_MRCTRL1 0x0014
+#define TH1520_CTRL_MRSTAT 0x0018
+#define TH1520_CTRL_DERATEEN 0x0020
+#define TH1520_CTRL_DERATEINT 0x0024
+#define TH1520_CTRL_DERATECTL 0x002c
+#define TH1520_CTRL_PWRCTL 0x0030
+#define TH1520_CTRL_PWRTMG 0x0034
+#define TH1520_CTRL_HWLPCTL 0x0038
+#define TH1520_CTRL_RFSHCTL0 0x0050
+#define TH1520_CTRL_RFSHCTL1 0x0054
+#define TH1520_CTRL_RFSHCTL3 0x0060
+#define TH1520_CTRL_RFSHTMG 0x0064
+#define TH1520_CTRL_RFSHTMG1 0x0068
+#define TH1520_CTRL_CRCPARCTL0 0x00c0
+#define TH1520_CTRL_CRCPARSTAT 0x00cc
+#define TH1520_CTRL_INIT0 0x00d0
+#define TH1520_CTRL_INIT1 0x00d4
+#define TH1520_CTRL_INIT2 0x00d8
+#define TH1520_CTRL_INIT3 0x00dc
+#define TH1520_CTRL_INIT4 0x00e0
+#define TH1520_CTRL_INIT5 0x00e4
+#define TH1520_CTRL_INIT6 0x00e8
+#define TH1520_CTRL_INIT7 0x00ec
+#define TH1520_CTRL_DIMMCTL 0x00f0
+#define TH1520_CTRL_RANKCTL 0x00f4
+#define TH1520_CTRL_RANKCTL1 0x00f8
+#define TH1520_CTRL_DRAMTMG0 0x0100
+#define TH1520_CTRL_DRAMTMG1 0x0104
+#define TH1520_CTRL_DRAMTMG2 0x0108
+#define TH1520_CTRL_DRAMTMG3 0x010c
+#define TH1520_CTRL_DRAMTMG4 0x0110
+#define TH1520_CTRL_DRAMTMG5 0x0114
+#define TH1520_CTRL_DRAMTMG6 0x0118
+#define TH1520_CTRL_DRAMTMG7 0x011c
+#define TH1520_CTRL_DRAMTMG8 0x0120
+#define TH1520_CTRL_DRAMTMG12 0x0130
+#define TH1520_CTRL_DRAMTMG13 0x0134
+#define TH1520_CTRL_DRAMTMG14 0x0138
+#define TH1520_CTRL_DRAMTMG17 0x0144
+#define TH1520_CTRL_ZQCTL0 0x0180
+#define TH1520_CTRL_ZQCTL1 0x0184
+#define TH1520_CTRL_ZQCTL2 0x0188
+#define TH1520_CTRL_ZQSTAT 0x018c
+#define TH1520_CTRL_DFITMG0 0x0190
+#define TH1520_CTRL_DFITMG1 0x0194
+#define TH1520_CTRL_DFILPCFG0 0x0198
+#define TH1520_CTRL_DFIUPD0 0x01a0
+#define TH1520_CTRL_DFIUPD1 0x01a4
+#define TH1520_CTRL_DFIUPD2 0x01a8
+#define TH1520_CTRL_DFIMISC 0x01b0
+#define TH1520_CTRL_DFITMG2 0x01b4
+#define TH1520_CTRL_DFISTAT 0x01bc
+#define TH1520_CTRL_DBICTL 0x01c0
+#define TH1520_CTRL_DFIPHYMSTR 0x01c4
+#define TH1520_CTRL_ADDRMAP0 0x0200
+#define TH1520_CTRL_ADDRMAP1 0x0204
+#define TH1520_CTRL_ADDRMAP2 0x0208
+#define TH1520_CTRL_ADDRMAP3 0x020c
+#define TH1520_CTRL_ADDRMAP4 0x0210
+#define TH1520_CTRL_ADDRMAP5 0x0214
+#define TH1520_CTRL_ADDRMAP6 0x0218
+#define TH1520_CTRL_ADDRMAP7 0x021c
+#define TH1520_CTRL_ADDRMAP8 0x0220
+#define TH1520_CTRL_ADDRMAP9 0x0224
+#define TH1520_CTRL_ADDRMAP10 0x0228
+#define TH1520_CTRL_ADDRMAP11 0x022c
+#define TH1520_CTRL_ODTCFG 0x0240
+#define TH1520_CTRL_ODTMAP 0x0244
+#define TH1520_CTRL_SCHED 0x0250
+#define TH1520_CTRL_SCHED1 0x0254
+#define TH1520_CTRL_PERFHPR1 0x025c
+#define TH1520_CTRL_PERFLPR1 0x0264
+#define TH1520_CTRL_PERFWR1 0x026c
+#define TH1520_CTRL_SCHED3 0x0270
+#define TH1520_CTRL_SCHED4 0x0274
+#define TH1520_CTRL_DBG0 0x0300
+#define TH1520_CTRL_DBG1 0x0304
+#define TH1520_CTRL_DBGCAM 0x0308
+#define TH1520_CTRL_DBGCMD 0x030c
+#define TH1520_CTRL_DBGSTAT 0x0310
+#define TH1520_CTRL_SWCTL 0x0320
+#define TH1520_CTRL_SWSTAT 0x0324
+#define TH1520_CTRL_SWCTLSTATIC 0x0328
+#define TH1520_CTRL_POISONCFG 0x036c
+#define TH1520_CTRL_POISONSTAT 0x0370
+#define TH1520_CTRL_DERATESTAT 0x03f0
+#define TH1520_CTRL_PSTAT 0x03fc
+#define TH1520_CTRL_PCCFG 0x0400
+#define TH1520_CTRL_PCFGR_0 0x0404
+#define TH1520_CTRL_PCFGW_0 0x0408
+#define TH1520_CTRL_PCTRL_0 0x0490
+#define TH1520_CTRL_PCFGQOS0_0 0x0494
+#define TH1520_CTRL_PCFGQOS1_0 0x0498
+#define TH1520_CTRL_PCFGWQOS0_0 0x049c
+#define TH1520_CTRL_PCFGWQOS1_0 0x04a0
+#define TH1520_CTRL_PCFGR_1 0x04b4
+#define TH1520_CTRL_PCFGW_1 0x04b8
+#define TH1520_CTRL_PCTRL_1 0x0540
+#define TH1520_CTRL_PCFGQOS0_1 0x0544
+#define TH1520_CTRL_PCFGQOS1_1 0x0548
+#define TH1520_CTRL_PCFGWQOS0_1 0x054c
+#define TH1520_CTRL_PCFGWQOS1_1 0x0550
+#define TH1520_CTRL_PCFGR_2 0x0564
+#define TH1520_CTRL_PCFGW_2 0x0568
+#define TH1520_CTRL_PCTRL_2 0x05f0
+#define TH1520_CTRL_PCFGQOS0_2 0x05f4
+#define TH1520_CTRL_PCFGQOS1_2 0x05f8
+#define TH1520_CTRL_PCFGWQOS0_2 0x05fc
+#define TH1520_CTRL_PCFGWQOS1_2 0x0600
+#define TH1520_CTRL_PCFGR_3 0x0614
+#define TH1520_CTRL_PCFGW_3 0x0618
+#define TH1520_CTRL_PCTRL_3 0x06a0
+#define TH1520_CTRL_PCFGQOS0_3 0x06a4
+#define TH1520_CTRL_PCFGQOS1_3 0x06a8
+#define TH1520_CTRL_PCFGWQOS0_3 0x06ac
+#define TH1520_CTRL_PCFGWQOS1_3 0x06b0
+#define TH1520_CTRL_PCFGR_4 0x06c4
+#define TH1520_CTRL_PCFGW_4 0x06c8
+#define TH1520_CTRL_PCTRL_4 0x0750
+#define TH1520_CTRL_PCFGQOS0_4 0x0754
+#define TH1520_CTRL_PCFGQOS1_4 0x0758
+#define TH1520_CTRL_PCFGWQOS0_4 0x075c
+#define TH1520_CTRL_PCFGWQOS1_4 0x0760
+#define TH1520_CTRL_UMCTL2_VER_NUMBER 0x0ff0
+#define TH1520_CTRL_UMCTL2_VER_TYPE 0x0ff4
+#define TH1520_CTRL_DCH1_STAT 0x1b04
+#define TH1520_CTRL_DCH1_MRCTRL0 0x1b10
+#define TH1520_CTRL_DCH1_MRCTRL1 0x1b14
+#define TH1520_CTRL_DCH1_MRSTAT 0x1b18
+#define TH1520_CTRL_DCH1_DERATECTL 0x1b2c
+#define TH1520_CTRL_DCH1_PWRCTL 0x1b30
+#define TH1520_CTRL_DCH1_HWLPCTL 0x1b38
+#define TH1520_CTRL_DCH1_CRCPARCTL0 0x1bc0
+#define TH1520_CTRL_DCH1_ZQCTL2 0x1c88
+#define TH1520_CTRL_DCH1_DFISTAT 0x1cbc
+#define TH1520_CTRL_DCH1_ODTMAP 0x1d44
+#define TH1520_CTRL_DCH1_DBG1 0x1e04
+#define TH1520_CTRL_DCH1_DBGCMD 0x1e0c
+#define TH1520_CTRL_DCH1_DBGCAM 0x1e08
+
+/* PHY configuration registers */
+#define TH1520_DDR_PHY_REG(regid) ((regid) * 2)
+
+/* UctShadowRegs */
+#define TH1520_PHY_MSG_STATUS TH1520_DDR_PHY_REG(0xd0004)
+#define TH1520_PHY_MSG_STATUS_EMPTY BIT(0)
+/* DctWriteProt */
+#define TH1520_PHY_MSG_ACK TH1520_DDR_PHY_REG(0xd0031)
+#define TH1520_PHY_MSG_ACK_EN BIT(0)
+/* UctWriteOnlyShadow */
+#define TH1520_PHY_MSG_ID TH1520_DDR_PHY_REG(0xd0032)
+#define TH1520_PHY_MSG_ID_COMPLETION 0x7
+#define TH1520_PHY_MSG_ID_ERROR 0xff
+/* UctDatWriteOnlyShadow */
+#define TH1520_PHY_MSG_DATA TH1520_DDR_PHY_REG(0xd0034)
+
+struct th1520_ddr_priv {
+ void __iomem *phy0;
+ void __iomem *phy1;
+ void __iomem *ctrl;
+ void __iomem *sys;
+};
+
+binman_sym_declare(ulong, ddr_fw, image_pos);
+
+static int th1520_ddr_pll_config(void __iomem *sysreg, unsigned int frequency)
+{
+ u32 tmp;
+ int ret;
+
+ tmp = TH1520_SYS_PLL_CFG1_RST |
+ TH1520_SYS_PLL_CFG1_FOUTPOSTDIVPD |
+ TH1520_SYS_PLL_CFG1_FOUT4PHASEPD |
+ Th1520_SYS_PLL_CFG1_DACPD;
+ writel(tmp, sysreg + TH1520_SYS_PLL_CFG1);
+
+ switch (frequency) {
+ case TH1520_DDR_FREQ_3733:
+ writel(FIELD_PREP(TH1520_SYS_PLL_CFG0_REFDIV, 1) |
+ FIELD_PREP(TH1520_SYS_PLL_CFG0_FBDIV, 77) |
+ FIELD_PREP(TH1520_SYS_PLL_CFG0_POSTDIV1, 2) |
+ FIELD_PREP(TH1520_SYS_PLL_CFG0_POSTDIV2, 1),
+ sysreg + TH1520_SYS_PLL_CFG0);
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ udelay(2);
+ tmp &= ~TH1520_SYS_PLL_CFG1_RST;
+ writel(tmp, sysreg + TH1520_SYS_PLL_CFG1);
+
+ ret = readl_poll_timeout(sysreg + TH1520_SYS_PLL_STS, tmp,
+ tmp & TH1520_SYS_PLL_STS_LOCKED,
+ TH1520_SYS_PLL_TIMEOUT_US);
+
+ writel(TH1520_SYS_PLL_STS_EN, sysreg + TH1520_SYS_PLL_STS);
+
+ return ret;
+}
+
+static int th1520_ddr_ctrl_init(void __iomem *ctrlreg, struct th1520_ddr_fw *fw)
+{
+ int ret;
+ u32 tmp;
+
+ writel(0x00000001, ctrlreg + TH1520_CTRL_DBG1);
+ writel(0x00000001, ctrlreg + TH1520_CTRL_PWRCTL);
+
+ ret = readl_poll_timeout(ctrlreg + TH1520_CTRL_STAT, tmp,
+ tmp == 0x00000000,
+ TH1520_CTRL_INIT_TIMEOUT_US);
+ if (ret)
+ return ret;
+
+ if (fw->ranknum == 2)
+ writel(0x03080020, ctrlreg + TH1520_CTRL_MSTR);
+ else
+ return -EINVAL;
+
+ writel(0x00003030, ctrlreg + TH1520_CTRL_MRCTRL0);
+ writel(0x0002d90f, ctrlreg + TH1520_CTRL_MRCTRL1);
+
+ switch (fw->freq) {
+ case TH1520_DDR_FREQ_3733:
+ writel(0x000013f3, ctrlreg + TH1520_CTRL_DERATEEN);
+ writel(0x40000000, ctrlreg + TH1520_CTRL_DERATEINT);
+ writel(0x00000001, ctrlreg + TH1520_CTRL_DERATECTL);
+ writel(0x00000020, ctrlreg + TH1520_CTRL_PWRCTL);
+ writel(0x0040ae04, ctrlreg + TH1520_CTRL_PWRTMG);
+ writel(0x00430000, ctrlreg + TH1520_CTRL_HWLPCTL);
+ writel(0x00210004, ctrlreg + TH1520_CTRL_RFSHCTL0);
+ writel(0x000d0021, ctrlreg + TH1520_CTRL_RFSHCTL1);
+ writel(0x00000001, ctrlreg + TH1520_CTRL_RFSHCTL3);
+ writel(0x81c00084, ctrlreg + TH1520_CTRL_RFSHTMG);
+ writel(0x00540000, ctrlreg + TH1520_CTRL_RFSHTMG1);
+ writel(0x00000000, ctrlreg + TH1520_CTRL_CRCPARCTL0);
+ writel(0xc0020002, ctrlreg + TH1520_CTRL_INIT0);
+ writel(0x00010002, ctrlreg + TH1520_CTRL_INIT1);
+ writel(0x00001f00, ctrlreg + TH1520_CTRL_INIT2);
+ writel(0x00640036, ctrlreg + TH1520_CTRL_INIT3);
+ writel(0x00f20008, ctrlreg + TH1520_CTRL_INIT4);
+ writel(0x0004000b, ctrlreg + TH1520_CTRL_INIT5);
+ writel(0x00440012, ctrlreg + TH1520_CTRL_INIT6);
+ writel(0x0004001a, ctrlreg + TH1520_CTRL_INIT7);
+ writel(0x00000000, ctrlreg + TH1520_CTRL_DIMMCTL);
+ writel(0x0000ab9f, ctrlreg + TH1520_CTRL_RANKCTL);
+ writel(0x00000017, ctrlreg + TH1520_CTRL_RANKCTL1);
+ writel(0x1f263f28, ctrlreg + TH1520_CTRL_DRAMTMG0);
+ writel(0x00080839, ctrlreg + TH1520_CTRL_DRAMTMG1);
+ writel(0x08121d17, ctrlreg + TH1520_CTRL_DRAMTMG2);
+ writel(0x00d0e000, ctrlreg + TH1520_CTRL_DRAMTMG3);
+ writel(0x11040a12, ctrlreg + TH1520_CTRL_DRAMTMG4);
+ writel(0x02050e0e, ctrlreg + TH1520_CTRL_DRAMTMG5);
+ writel(0x01010008, ctrlreg + TH1520_CTRL_DRAMTMG6);
+ writel(0x00000502, ctrlreg + TH1520_CTRL_DRAMTMG7);
+ writel(0x00000101, ctrlreg + TH1520_CTRL_DRAMTMG8);
+ writel(0x00020000, ctrlreg + TH1520_CTRL_DRAMTMG12);
+ writel(0x0d100002, ctrlreg + TH1520_CTRL_DRAMTMG13);
+ writel(0x0000010c, ctrlreg + TH1520_CTRL_DRAMTMG14);
+ writel(0x03a50021, ctrlreg + TH1520_CTRL_ZQCTL0);
+ writel(0x02f00800, ctrlreg + TH1520_CTRL_ZQCTL1);
+ writel(0x00000000, ctrlreg + TH1520_CTRL_ZQCTL2);
+ writel(0x059f820c, ctrlreg + TH1520_CTRL_DFITMG0);
+ writel(0x000c0303, ctrlreg + TH1520_CTRL_DFITMG1);
+ writel(0x0351a101, ctrlreg + TH1520_CTRL_DFILPCFG0);
+ writel(0x00000011, ctrlreg + TH1520_CTRL_DFIMISC);
+ writel(0x00001f0c, ctrlreg + TH1520_CTRL_DFITMG2);
+ writel(0x00000007, ctrlreg + TH1520_CTRL_DBICTL);
+ writel(0x14000001, ctrlreg + TH1520_CTRL_DFIPHYMSTR);
+ writel(0x06090b40, ctrlreg + TH1520_CTRL_ODTCFG);
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ writel(0x00400018, ctrlreg + TH1520_CTRL_DFIUPD0);
+ writel(0x00280032, ctrlreg + TH1520_CTRL_DFIUPD1);
+ writel(0x00000000, ctrlreg + TH1520_CTRL_DFIUPD2);
+ writel(0x00000000, ctrlreg + TH1520_CTRL_ODTMAP);
+ writel(0x1f829b1c, ctrlreg + TH1520_CTRL_SCHED);
+ writel(0x4400b00f, ctrlreg + TH1520_CTRL_SCHED1);
+ writel(0x0f000001, ctrlreg + TH1520_CTRL_PERFHPR1);
+ writel(0x0f00007f, ctrlreg + TH1520_CTRL_PERFLPR1);
+ writel(0x0f00007f, ctrlreg + TH1520_CTRL_PERFWR1);
+ writel(0x00000208, ctrlreg + TH1520_CTRL_SCHED3);
+ writel(0x08400810, ctrlreg + TH1520_CTRL_SCHED4);
+ writel(0x00000000, ctrlreg + TH1520_CTRL_DBG0);
+ writel(0x00000000, ctrlreg + TH1520_CTRL_DBG1);
+ writel(0x00000000, ctrlreg + TH1520_CTRL_DBGCMD);
+ writel(0x00000001, ctrlreg + TH1520_CTRL_SWCTL);
+ writel(0x00000000, ctrlreg + TH1520_CTRL_SWCTLSTATIC);
+ writel(0x00000001, ctrlreg + TH1520_CTRL_POISONCFG);
+ writel(0x00000001, ctrlreg + TH1520_CTRL_PCTRL_0);
+ writel(0x00000001, ctrlreg + TH1520_CTRL_PCTRL_1);
+ writel(0x00000001, ctrlreg + TH1520_CTRL_PCTRL_2);
+ writel(0x00000001, ctrlreg + TH1520_CTRL_PCTRL_3);
+ writel(0x00000001, ctrlreg + TH1520_CTRL_PCTRL_4);
+ writel(0x00003030, ctrlreg + TH1520_CTRL_DCH1_MRCTRL0);
+ writel(0x0002d90f, ctrlreg + TH1520_CTRL_DCH1_MRCTRL1);
+ writel(0x00000001, ctrlreg + TH1520_CTRL_DCH1_DERATECTL);
+ writel(0x00000020, ctrlreg + TH1520_CTRL_DCH1_PWRCTL);
+ writel(0x00430002, ctrlreg + TH1520_CTRL_DCH1_HWLPCTL);
+ writel(0x00000000, ctrlreg + TH1520_CTRL_DCH1_CRCPARCTL0);
+ writel(0x00000000, ctrlreg + TH1520_CTRL_DCH1_ZQCTL2);
+ writel(0x00000000, ctrlreg + TH1520_CTRL_DCH1_ODTMAP);
+ writel(0x00000000, ctrlreg + TH1520_CTRL_DCH1_DBG1);
+ writel(0x00000000, ctrlreg + TH1520_CTRL_DCH1_DBGCMD);
+
+ ret = readl_poll_timeout(ctrlreg + TH1520_CTRL_RFSHCTL3, tmp,
+ tmp == 0x00000001,
+ TH1520_CTRL_INIT_TIMEOUT_US);
+ if (ret)
+ return ret;
+
+ writel(0x00000010, ctrlreg + TH1520_CTRL_PCCFG);
+ writel(0x0000500f, ctrlreg + TH1520_CTRL_PCFGR_0);
+ writel(0x0000500f, ctrlreg + TH1520_CTRL_PCFGW_0);
+ writel(0x00005020, ctrlreg + TH1520_CTRL_PCFGR_1);
+ writel(0x0000501f, ctrlreg + TH1520_CTRL_PCFGW_1);
+ writel(0x0000501f, ctrlreg + TH1520_CTRL_PCFGR_2);
+ writel(0x0000503f, ctrlreg + TH1520_CTRL_PCFGW_2);
+ writel(0x000051ff, ctrlreg + TH1520_CTRL_PCFGR_3);
+ writel(0x000051ff, ctrlreg + TH1520_CTRL_PCFGW_3);
+ writel(0x0000503f, ctrlreg + TH1520_CTRL_PCFGR_4);
+ writel(0x0000503f, ctrlreg + TH1520_CTRL_PCFGW_4);
+
+ ret = readl_poll_timeout(ctrlreg + TH1520_CTRL_PWRCTL, tmp,
+ tmp == 0x00000020,
+ TH1520_CTRL_INIT_TIMEOUT_US);
+ if (ret)
+ return ret;
+
+ writel(0x00000020, ctrlreg + TH1520_CTRL_PWRCTL);
+
+ ret = readl_poll_timeout(ctrlreg + TH1520_CTRL_DCH1_PWRCTL, tmp,
+ tmp == 0x00000020,
+ TH1520_CTRL_INIT_TIMEOUT_US);
+ if (ret)
+ return ret;
+
+ writel(0x00000020, ctrlreg + TH1520_CTRL_DCH1_PWRCTL);
+ writel(0x00000000, ctrlreg + TH1520_CTRL_DBG1);
+
+ ret = readl_poll_timeout(ctrlreg + TH1520_CTRL_PWRCTL, tmp,
+ tmp == 0x00000020,
+ TH1520_CTRL_INIT_TIMEOUT_US);
+ if (ret)
+ return ret;
+
+ writel(0x00000020, ctrlreg + TH1520_CTRL_PWRCTL);
+
+ ret = readl_poll_timeout(ctrlreg + TH1520_CTRL_PWRCTL, tmp,
+ tmp == 0x00000020,
+ TH1520_CTRL_INIT_TIMEOUT_US);
+ if (ret)
+ return ret;
+
+ writel(0x00000020, ctrlreg + TH1520_CTRL_PWRCTL);
+ writel(0x00000000, ctrlreg + TH1520_CTRL_DCH1_DBG1);
+
+ ret = readl_poll_timeout(ctrlreg + TH1520_CTRL_DCH1_PWRCTL, tmp,
+ tmp == 0x00000020,
+ TH1520_CTRL_INIT_TIMEOUT_US);
+ if (ret)
+ return ret;
+
+ writel(0x00000020, ctrlreg + TH1520_CTRL_DCH1_PWRCTL);
+
+ ret = readl_poll_timeout(ctrlreg + TH1520_CTRL_DCH1_PWRCTL, tmp,
+ tmp == 0x00000020,
+ TH1520_CTRL_INIT_TIMEOUT_US);
+ if (ret)
+ return ret;
+
+ writel(0x00000020, ctrlreg + TH1520_CTRL_DCH1_PWRCTL);
+ writel(0x14000001, ctrlreg + TH1520_CTRL_DFIPHYMSTR);
+ writel(0x00000000, ctrlreg + TH1520_CTRL_SWCTL);
+ writel(0x00000010, ctrlreg + TH1520_CTRL_DFIMISC);
+ writel(0x00000010, ctrlreg + TH1520_CTRL_DFIMISC);
+ writel(0x00000002, ctrlreg + TH1520_CTRL_DBG1);
+ writel(0x00000002, ctrlreg + TH1520_CTRL_DCH1_DBG1);
+
+ switch (fw->bitwidth) {
+ case 64:
+ writel(0x00040018, ctrlreg + TH1520_CTRL_ADDRMAP0);
+ writel(0x00090909, ctrlreg + TH1520_CTRL_ADDRMAP1);
+ writel(0x00000000, ctrlreg + TH1520_CTRL_ADDRMAP2);
+ writel(0x01010101, ctrlreg + TH1520_CTRL_ADDRMAP3);
+ writel(0x00001f1f, ctrlreg + TH1520_CTRL_ADDRMAP4);
+ writel(0x080f0808, ctrlreg + TH1520_CTRL_ADDRMAP5);
+ writel(0x08080808, ctrlreg + TH1520_CTRL_ADDRMAP6);
+ writel(0x00000f0f, ctrlreg + TH1520_CTRL_ADDRMAP7);
+ writel(0x08080808, ctrlreg + TH1520_CTRL_ADDRMAP9);
+ writel(0x08080808, ctrlreg + TH1520_CTRL_ADDRMAP10);
+ writel(0x00000008, ctrlreg + TH1520_CTRL_ADDRMAP11);
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int th1520_ddr_read_msg(void __iomem *phyreg, u16 *id, u16 *data)
+{
+ u32 tmp;
+ int ret;
+
+ ret = readw_poll_timeout(phyreg + TH1520_PHY_MSG_STATUS, tmp,
+ !(tmp & TH1520_PHY_MSG_STATUS_EMPTY),
+ TH1520_PHY_MSG_TIMEOUT_US);
+ if (ret)
+ return ret;
+
+ *id = readw(phyreg + TH1520_PHY_MSG_ID);
+ *data = readw(phyreg + TH1520_PHY_MSG_DATA);
+
+ writew(0, phyreg + TH1520_PHY_MSG_ACK);
+
+ ret = readw_poll_timeout(phyreg + TH1520_PHY_MSG_STATUS, tmp,
+ tmp & TH1520_PHY_MSG_STATUS_EMPTY,
+ TH1520_PHY_MSG_TIMEOUT_US);
+ if (ret)
+ return ret;
+
+ writew(TH1520_PHY_MSG_ACK_EN, phyreg + TH1520_PHY_MSG_ACK);
+
+ return 0;
+}
+
+static int th1520_phy_wait_pmu_completion(void __iomem *phyreg)
+{
+ u16 id, data;
+ int ret;
+
+ do {
+ ret = th1520_ddr_read_msg(phyreg, &id, &data);
+
+ if (ret)
+ return ret;
+ } while (id != TH1520_PHY_MSG_ID_COMPLETION &&
+ id != TH1520_PHY_MSG_ID_ERROR &&
+ !ret);
+
+ return id == TH1520_PHY_MSG_ID_COMPLETION ? ret : -EIO;
+}
+
+static int lpddr4_load_firmware(struct th1520_ddr_priv *priv,
+ struct th1520_ddr_fw *fw)
+{
+ union th1520_ddr_cfg *cfg;
+ size_t i, j;
+ int ret;
+
+ for (cfg = fw->cfgs, i = 0; i < fw->cfgnum; i++) {
+ u32 addr = FIELD_GET(TH1520_DDR_CFG_ADDR, cfg->opaddr) * 2;
+ u32 op = FIELD_GET(TH1520_DDR_CFG_OP, cfg->opaddr);
+
+ switch (op) {
+ case TH1520_DDR_CFG_PHY0:
+ writew(cfg->phy.data, priv->phy0 + addr);
+ break;
+ case TH1520_DDR_CFG_PHY1:
+ writew(cfg->phy.data, priv->phy1 + addr);
+ break;
+ case TH1520_DDR_CFG_PHY:
+ writew(cfg->phy.data, priv->phy0 + addr);
+ writew(cfg->phy.data, priv->phy1 + addr);
+ break;
+ case TH1520_DDR_CFG_RANGE:
+ for (j = 0; j < cfg->range.num; j++) {
+ writew(cfg->range.data[j],
+ priv->phy0 + addr + j * 2);
+ writew(cfg->range.data[j],
+ priv->phy1 + addr + j * 2);
+ }
+ break;
+ case TH1520_DDR_CFG_WAITFW0:
+ ret = th1520_phy_wait_pmu_completion(priv->phy0);
+
+ if (ret) {
+ pr_err("phy 0 training failed: %d\n", ret);
+ return ret;
+ }
+
+ break;
+ case TH1520_DDR_CFG_WAITFW1:
+ ret = th1520_phy_wait_pmu_completion(priv->phy1);
+
+ if (ret) {
+ pr_err("phy 1 training failed: %d\n", ret);
+ return ret;
+ }
+
+ break;
+ default:
+ pr_err("Unknown DRAM configuration %d\n", op);
+
+ return -EOPNOTSUPP;
+ }
+
+ if (op == TH1520_DDR_CFG_RANGE)
+ cfg = (void *)cfg + sizeof(cfg->range) +
+ cfg->range.num * sizeof(u16);
+ else
+ cfg = (union th1520_ddr_cfg *)(&cfg->phy + 1);
+ }
+
+ return 0;
+}
+
+static int th1520_ddr_ctrl_enable(void __iomem *ctrlreg,
+ struct th1520_ddr_fw *fw)
+{
+ u32 tmp;
+ int ret;
+
+ writel(0x00000030, ctrlreg + TH1520_CTRL_DFIMISC);
+
+ ret = readl_poll_timeout(ctrlreg + TH1520_CTRL_DFISTAT, tmp,
+ tmp == 0x00000001,
+ TH1520_CTRL_INIT_TIMEOUT_US);
+ if (ret)
+ return ret;
+
+ ret = readl_poll_timeout(ctrlreg + TH1520_CTRL_DCH1_DFISTAT, tmp,
+ tmp == 0x00000001,
+ TH1520_CTRL_INIT_TIMEOUT_US);
+ if (ret)
+ return ret;
+
+ writel(0x00000010, ctrlreg + TH1520_CTRL_DFIMISC);
+ writel(0x00000011, ctrlreg + TH1520_CTRL_DFIMISC);
+ writel(0x0000000a, ctrlreg + TH1520_CTRL_PWRCTL);
+ writel(0x0000000a, ctrlreg + TH1520_CTRL_DCH1_PWRCTL);
+ writel(0x00000001, ctrlreg + TH1520_CTRL_SWCTL);
+
+ ret = readl_poll_timeout(ctrlreg + TH1520_CTRL_SWSTAT, tmp,
+ tmp == 0x00000001,
+ TH1520_CTRL_INIT_TIMEOUT_US);
+ if (ret)
+ return ret;
+
+ ret = readl_poll_timeout(ctrlreg + TH1520_CTRL_STAT, tmp,
+ tmp == 0x00000001,
+ TH1520_CTRL_INIT_TIMEOUT_US);
+ if (ret)
+ return ret;
+
+ ret = readl_poll_timeout(ctrlreg + TH1520_CTRL_DCH1_STAT, tmp,
+ tmp == 0x00000001,
+ TH1520_CTRL_INIT_TIMEOUT_US);
+ if (ret)
+ return ret;
+
+ writel(0x14000001, ctrlreg + TH1520_CTRL_DFIPHYMSTR);
+ writel(0x00000000, ctrlreg + TH1520_CTRL_SWCTL);
+ writel(0x00020002, ctrlreg + TH1520_CTRL_INIT0);
+ writel(0x00000001, ctrlreg + TH1520_CTRL_SWCTL);
+
+ ret = readl_poll_timeout(ctrlreg + TH1520_CTRL_SWSTAT, tmp,
+ tmp == 0x00000001,
+ TH1520_CTRL_INIT_TIMEOUT_US);
+
+ if (ret)
+ return ret;
+
+ writel(0x00000000, ctrlreg + TH1520_CTRL_DBG1);
+ writel(0x00000000, ctrlreg + TH1520_CTRL_DCH1_DBG1);
+
+ return 0;
+}
+
+static void th1520_ddr_enable_self_refresh(void __iomem *ctrlreg,
+ void __iomem *sysreg)
+{
+ writel(0x00000000, ctrlreg + TH1520_CTRL_RFSHCTL3);
+
+ writel(0x000a0000, sysreg + TH1520_SYS_DDR_CFG1);
+
+ writel(0x00000000, ctrlreg + TH1520_CTRL_SWCTL);
+ writel(0x00000001, ctrlreg + TH1520_CTRL_SWCTLSTATIC);
+ writel(0x0040ae04, ctrlreg + TH1520_CTRL_PWRTMG);
+ writel(0x00430003, ctrlreg + TH1520_CTRL_HWLPCTL);
+ writel(0x00430003, ctrlreg + TH1520_CTRL_DCH1_HWLPCTL);
+ writel(0x00000001, ctrlreg + TH1520_CTRL_SWCTL);
+ writel(0x00000000, ctrlreg + TH1520_CTRL_SWCTLSTATIC);
+ writel(0x0000000b, ctrlreg + TH1520_CTRL_PWRCTL);
+ writel(0x0000000b, ctrlreg + TH1520_CTRL_DCH1_PWRCTL);
+}
+
+static int th1520_ddr_init(struct th1520_ddr_priv *priv)
+{
+ struct th1520_ddr_fw *fw = (void *)binman_sym(ulong, ddr_fw, image_pos);
+ u32 reset;
+ int ret;
+
+ ret = th1520_ddr_pll_config(priv->sys, fw->freq);
+ if (ret) {
+ pr_err("failed to configure PLL: %d\n", ret);
+ return ret;
+ }
+
+ reset = TH1520_SYS_DDR_CFG0_PHY_PWROK_RSTN;
+ writel(reset, priv->sys + TH1520_SYS_DDR_CFG0);
+ reset |= TH1520_SYS_DDR_CFG0_PHY_CORE_RSTN;
+ writel(reset, priv->sys + TH1520_SYS_DDR_CFG0);
+ reset |= TH1520_SYS_DDR_CFG0_APB_RSTN;
+ writel(reset, priv->sys + TH1520_SYS_DDR_CFG0);
+
+ ret = th1520_ddr_ctrl_init(priv->ctrl, fw);
+ if (ret) {
+ pr_err("failed to initialize DDR controller: %d\n", ret);
+ return ret;
+ }
+
+ reset |= TH1520_SYS_DDR_CFG0_APB_PORT_RSTN(0) |
+ TH1520_SYS_DDR_CFG0_APB_PORT_RSTN(1) |
+ TH1520_SYS_DDR_CFG0_APB_PORT_RSTN(2) |
+ TH1520_SYS_DDR_CFG0_APB_PORT_RSTN(3) |
+ TH1520_SYS_DDR_CFG0_APB_PORT_RSTN(4) |
+ TH1520_SYS_DDR_CFG0_CTRL_RSTN;
+ writel(reset, priv->sys + TH1520_SYS_DDR_CFG0);
+
+ lpddr4_load_firmware(priv, fw);
+
+ ret = th1520_ddr_ctrl_enable(priv->ctrl, fw);
+ if (ret) {
+ pr_err("failed to enable DDR controller: %d\n", ret);
+ return ret;
+ }
+
+ th1520_ddr_enable_self_refresh(priv->ctrl, priv->sys);
+
+ return 0;
+}
+
+static int th1520_ddr_probe(struct udevice *dev)
+{
+ struct th1520_ddr_priv *priv = dev_get_priv(dev);
+ fdt_addr_t addr;
+
+ addr = dev_read_addr_name(dev, "phy-0");
+ priv->phy0 = (void __iomem *)addr;
+ if (addr == FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ addr = dev_read_addr_name(dev, "phy-1");
+ priv->phy1 = (void __iomem *)addr;
+ if (addr == FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ addr = dev_read_addr_name(dev, "ctrl");
+ priv->ctrl = (void __iomem *)addr;
+ if (addr == FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ addr = dev_read_addr_name(dev, "sys");
+ priv->sys = (void __iomem *)addr;
+ if (addr == FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ return th1520_ddr_init(priv);
+}
+
+static int th1520_ddr_get_info(struct udevice *dev, struct ram_info *info)
+{
+ info->base = gd->ram_base;
+ info->size = gd->ram_size;
+
+ return 0;
+}
+
+static struct ram_ops th1520_ddr_ops = {
+ .get_info = th1520_ddr_get_info,
+};
+
+static const struct udevice_id th1520_ddr_ids[] = {
+ { .compatible = "thead,th1520-ddrc" },
+ { }
+};
+
+U_BOOT_DRIVER(th1520_ddr) = {
+ .name = "th1520_ddr",
+ .id = UCLASS_RAM,
+ .ops = &th1520_ddr_ops,
+ .of_match = th1520_ddr_ids,
+ .probe = th1520_ddr_probe,
+ .priv_auto = sizeof(struct th1520_ddr_priv),
+};
generated by cgit v1.2.3 (git 2.0.4) at 2025-08-05 13:30:08 +0000