diff options
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/i2c/Kconfig | 6 | ||||
| -rw-r--r-- | drivers/i2c/Makefile | 2 | ||||
| -rw-r--r-- | drivers/pci/pci-aardvark.c | 6 |
3 files changed, 12 insertions, 2 deletions
diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig index 66bd6fe2f34..7c447a8aa0a 100644 --- a/drivers/i2c/Kconfig +++ b/drivers/i2c/Kconfig @@ -627,6 +627,12 @@ config SYS_I2C_VERSATILE Add support for the Arm Ltd Versatile Express I2C driver. The I2C host controller is present in the development boards manufactured by Arm Ltd. +config SYS_I2C_MV + bool "Marvell PXA (Armada 3720) I2C driver" + help + Support for PXA based I2C controller used on Armada 3720 SoC. + In Linux, this driver is called i2c-pxa. + config SYS_I2C_MVTWSI bool "Marvell I2C driver" help diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile index 916427452a5..fca6b157f8a 100644 --- a/drivers/i2c/Makefile +++ b/drivers/i2c/Makefile @@ -10,7 +10,6 @@ obj-$(CONFIG_$(SPL_)DM_I2C_GPIO) += i2c-gpio.o obj-$(CONFIG_$(SPL_)I2C_CROS_EC_TUNNEL) += cros_ec_tunnel.o obj-$(CONFIG_$(SPL_)I2C_CROS_EC_LDO) += cros_ec_ldo.o -obj-$(CONFIG_I2C_MV) += mv_i2c.o obj-$(CONFIG_$(SPL_)SYS_I2C_LEGACY) += i2c_core.o obj-$(CONFIG_SYS_I2C_ASPEED) += ast_i2c.o obj-$(CONFIG_SYS_I2C_AT91) += at91_i2c.o @@ -29,6 +28,7 @@ obj-$(CONFIG_SYS_I2C_IPROC) += iproc_i2c.o obj-$(CONFIG_SYS_I2C_KONA) += kona_i2c.o obj-$(CONFIG_SYS_I2C_LPC32XX) += lpc32xx_i2c.o obj-$(CONFIG_SYS_I2C_MESON) += meson_i2c.o +obj-$(CONFIG_SYS_I2C_MV) += mv_i2c.o obj-$(CONFIG_SYS_I2C_MVTWSI) += mvtwsi.o obj-$(CONFIG_SYS_I2C_MXC) += mxc_i2c.o obj-$(CONFIG_SYS_I2C_NEXELL) += nx_i2c.o diff --git a/drivers/pci/pci-aardvark.c b/drivers/pci/pci-aardvark.c index 38eff495ab1..9e623b6e617 100644 --- a/drivers/pci/pci-aardvark.c +++ b/drivers/pci/pci-aardvark.c @@ -445,7 +445,7 @@ static int pcie_advk_read_config(const struct udevice *bus, pci_dev_t bdf, * for returning CRS, so that if U-Boot does support CRS in the future, * it will work for Aardvark. */ - allow_crs = pcie->cfgcrssve; + allow_crs = (offset == PCI_VENDOR_ID) && (size == PCI_SIZE_32) && pcie->cfgcrssve; if (advk_readl(pcie, PIO_START)) { dev_err(pcie->dev, @@ -581,6 +581,10 @@ static int pcie_advk_write_config(struct udevice *bus, pci_dev_t bdf, if (offset >= 0x10 && offset < 0x34) { data = pcie->cfgcache[(offset - 0x10) / 4]; data = pci_conv_size_to_32(data, value, offset, size); + /* This PCI bridge does not have configurable bars */ + if ((offset & ~3) == PCI_BASE_ADDRESS_0 || + (offset & ~3) == PCI_BASE_ADDRESS_1) + data = 0x0; pcie->cfgcache[(offset - 0x10) / 4] = data; } else if ((offset & ~3) == PCI_ROM_ADDRESS1) { data = advk_readl(pcie, PCIE_CORE_EXP_ROM_BAR_REG); |