1 files changed, 50 insertions, 0 deletions
diff --git a/include/configs/maxbcm.h b/include/configs/maxbcm.h
new file mode 100644
index 00000000000..4c2b538f888
--- /dev/null
+++ b/include/configs/maxbcm.h
@@ -0,0 +1,50 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2014 Stefan Roese <sr@denx.de>
+ */
+
+#ifndef _CONFIG_DB_MV7846MP_GP_H
+#define _CONFIG_DB_MV7846MP_GP_H
+
+#include <linux/sizes.h>
+
+/*
+ * High Level Configuration Options (easy to change)
+ */
+
+/*
+ * TEXT_BASE needs to be below 16MiB, since this area is scrubbed
+ * for DDR ECC byte filling in the SPL before loading the main
+ * U-Boot into it.
+ */
+
+/* I2C */
+#define CFG_I2C_MVTWSI_BASE0		MVEBU_TWSI_BASE
+
+/* SPI NOR flash default params, used by sf commands */
+
+/* Environment in SPI NOR flash */
+
+/*
+ * mv-common.h should be defined after CMD configs since it used them
+ * to enable certain macros
+ */
+#include "mv-common.h"
+
+/*
+ * Memory layout while starting into the bin_hdr via the
+ * BootROM:
+ *
+ * 0x4000.4000 - 0x4003.4000	headers space (192KiB)
+ * 0x4000.4030			bin_hdr start address
+ * 0x4003.4000 - 0x4004.7c00	BootROM memory allocations (15KiB)
+ * 0x4007.fffc			BootROM stack top
+ *
+ * The address space between 0x4007.fffc and 0x400f.fff is not locked in
+ * L2 cache thus cannot be used.
+ */
+
+/* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
+#define CFG_SYS_SDRAM_SIZE		SZ_1G
+
+#endif /* _CONFIG_DB_MV7846MP_GP_H */