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-rw-r--r--include/configs/alt.h10
-rw-r--r--include/configs/blanche.h4
-rw-r--r--include/configs/condor.h13
-rw-r--r--include/configs/ebisu.h2
-rw-r--r--include/configs/falcon.h3
-rw-r--r--include/configs/genmai.h15
-rw-r--r--include/configs/gose.h10
-rw-r--r--include/configs/grpeach.h12
-rw-r--r--include/configs/koelsch.h12
-rw-r--r--include/configs/lager.h12
-rw-r--r--include/configs/porter.h12
-rw-r--r--include/configs/silk.h12
-rw-r--r--include/configs/stout.h12
-rw-r--r--include/configs/v3hsk.h13
14 files changed, 15 insertions, 127 deletions
diff --git a/include/configs/alt.h b/include/configs/alt.h
index 8f03762583e..4c5d2de2bdf 100644
--- a/include/configs/alt.h
+++ b/include/configs/alt.h
@@ -20,16 +20,6 @@
#define RCAR_GEN2_SDRAM_SIZE (1024u * 1024 * 1024)
#define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024)
-/* SH Ether */
-#define CFG_SH_ETHER_USE_PORT 0
-#define CFG_SH_ETHER_PHY_ADDR 0x1
-#define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
-#define CFG_SH_ETHER_CACHE_WRITEBACK
-#define CFG_SH_ETHER_CACHE_INVALIDATE
-#define CFG_SH_ETHER_ALIGNE_SIZE 64
-
-/* Board Clock */
-
#define CFG_EXTRA_ENV_SETTINGS \
"bootm_size=0x10000000\0" \
"usb_pgood_delay=2000\0"
diff --git a/include/configs/blanche.h b/include/configs/blanche.h
index d4e0f677e67..46521aa16bf 100644
--- a/include/configs/blanche.h
+++ b/include/configs/blanche.h
@@ -29,8 +29,4 @@
#define CFG_SYS_FLASH_BANKS_SIZES { (CFG_SYS_FLASH_SIZE) }
#endif
-/* Board Clock */
-
-/* ENV setting */
-
#endif /* __BLANCHE_H */
diff --git a/include/configs/condor.h b/include/configs/condor.h
index 50c8d173383..b340800cc11 100644
--- a/include/configs/condor.h
+++ b/include/configs/condor.h
@@ -11,17 +11,4 @@
#include "rcar-gen3-common.h"
-/* Environment compatibility */
-
-/* SH Ether */
-#define CFG_SH_ETHER_USE_PORT 0
-#define CFG_SH_ETHER_PHY_ADDR 0x1
-#define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
-#define CFG_SH_ETHER_CACHE_WRITEBACK
-#define CFG_SH_ETHER_CACHE_INVALIDATE
-#define CFG_SH_ETHER_ALIGNE_SIZE 64
-
-/* Board Clock */
-/* XTAL_CLK : 33.33MHz */
-
#endif /* __CONDOR_H */
diff --git a/include/configs/ebisu.h b/include/configs/ebisu.h
index ad5944230a6..707e7c28d55 100644
--- a/include/configs/ebisu.h
+++ b/include/configs/ebisu.h
@@ -9,8 +9,6 @@
#ifndef __EBISU_H
#define __EBISU_H
-#undef DEBUG
-
#include "rcar-gen3-common.h"
/* Environment in eMMC, at the end of 2nd "boot sector" */
diff --git a/include/configs/falcon.h b/include/configs/falcon.h
index 0b62ff9fbe1..e1cace73550 100644
--- a/include/configs/falcon.h
+++ b/include/configs/falcon.h
@@ -11,7 +11,4 @@
#include "rcar-gen4-common.h"
-/* Board Clock */
-/* XTAL_CLK : 16.66MHz */
-
#endif /* __FALCON_H */
diff --git a/include/configs/genmai.h b/include/configs/genmai.h
new file mode 100644
index 00000000000..1d43f8e06af
--- /dev/null
+++ b/include/configs/genmai.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Configuration settings for the Renesas GENMAI board
+ *
+ * Copyright (C) 2017-2019 Renesas Electronics
+ */
+
+#ifndef __GENMAI_H
+#define __GENMAI_H
+
+/* Internal RAM Size (RZ/A1=3M, RZ/A1M=5M, RZ/A1H=10M) */
+#define CFG_SYS_SDRAM_BASE 0x20000000
+#define CFG_SYS_SDRAM_SIZE (10 * 1024 * 1024)
+
+#endif /* __GENAMI_H */
diff --git a/include/configs/gose.h b/include/configs/gose.h
index 7ae0726518d..4a5954af76f 100644
--- a/include/configs/gose.h
+++ b/include/configs/gose.h
@@ -19,16 +19,6 @@
#define RCAR_GEN2_SDRAM_SIZE (1048u * 1024 * 1024)
#define RCAR_GEN2_UBOOT_SDRAM_SIZE (512u * 1024 * 1024)
-/* SH Ether */
-#define CFG_SH_ETHER_USE_PORT 0
-#define CFG_SH_ETHER_PHY_ADDR 0x1
-#define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
-#define CFG_SH_ETHER_CACHE_WRITEBACK
-#define CFG_SH_ETHER_CACHE_INVALIDATE
-#define CFG_SH_ETHER_ALIGNE_SIZE 64
-
-/* Board Clock */
-
#define CFG_EXTRA_ENV_SETTINGS \
"bootm_size=0x10000000\0"
diff --git a/include/configs/grpeach.h b/include/configs/grpeach.h
index 8de4a36e931..e4564b67a79 100644
--- a/include/configs/grpeach.h
+++ b/include/configs/grpeach.h
@@ -8,20 +8,8 @@
#ifndef __GRPEACH_H
#define __GRPEACH_H
-/* Board Clock , P1 clock frequency (XTAL=13.33MHz) */
-
-/* Miscellaneous */
-
/* Internal RAM Size (RZ/A1=3M, RZ/A1M=5M, RZ/A1H=10M) */
#define CFG_SYS_SDRAM_BASE 0x20000000
#define CFG_SYS_SDRAM_SIZE (10 * 1024 * 1024)
-/* Network interface */
-#define CFG_SH_ETHER_USE_PORT 0
-#define CFG_SH_ETHER_PHY_ADDR 0
-#define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII
-#define CFG_SH_ETHER_CACHE_WRITEBACK
-#define CFG_SH_ETHER_CACHE_INVALIDATE
-#define CFG_SH_ETHER_ALIGNE_SIZE 64
-
#endif /* __GRPEACH_H */
diff --git a/include/configs/koelsch.h b/include/configs/koelsch.h
index d47d70178cc..c2713b77e0a 100644
--- a/include/configs/koelsch.h
+++ b/include/configs/koelsch.h
@@ -19,19 +19,7 @@
#define RCAR_GEN2_SDRAM_SIZE (2048u * 1024 * 1024)
#define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024)
-/* SH Ether */
-#define CFG_SH_ETHER_USE_PORT 0
-#define CFG_SH_ETHER_PHY_ADDR 0x1
-#define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
-#define CFG_SH_ETHER_CACHE_WRITEBACK
-#define CFG_SH_ETHER_CACHE_INVALIDATE
-#define CFG_SH_ETHER_ALIGNE_SIZE 64
-
-/* Board Clock */
-
#define CFG_EXTRA_ENV_SETTINGS \
"bootm_size=0x10000000\0"
-/* SPL support */
-
#endif /* __KOELSCH_H */
diff --git a/include/configs/lager.h b/include/configs/lager.h
index 2577c7a7da6..13f327fabf2 100644
--- a/include/configs/lager.h
+++ b/include/configs/lager.h
@@ -20,19 +20,7 @@
#define RCAR_GEN2_SDRAM_SIZE (2048u * 1024 * 1024)
#define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024)
-/* SH Ether */
-#define CFG_SH_ETHER_USE_PORT 0
-#define CFG_SH_ETHER_PHY_ADDR 0x1
-#define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
-#define CFG_SH_ETHER_CACHE_WRITEBACK
-#define CFG_SH_ETHER_CACHE_INVALIDATE
-#define CFG_SH_ETHER_ALIGNE_SIZE 64
-
-/* Board Clock */
-
#define CFG_EXTRA_ENV_SETTINGS \
"bootm_size=0x10000000\0"
-/* SPL support */
-
#endif /* __LAGER_H */
diff --git a/include/configs/porter.h b/include/configs/porter.h
index 2cb430be8b0..4612845db19 100644
--- a/include/configs/porter.h
+++ b/include/configs/porter.h
@@ -21,19 +21,7 @@
#define RCAR_GEN2_SDRAM_SIZE (2048u * 1024 * 1024)
#define RCAR_GEN2_UBOOT_SDRAM_SIZE (1024u * 1024 * 1024)
-/* SH Ether */
-#define CFG_SH_ETHER_USE_PORT 0
-#define CFG_SH_ETHER_PHY_ADDR 0x1
-#define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
-#define CFG_SH_ETHER_CACHE_WRITEBACK
-#define CFG_SH_ETHER_CACHE_INVALIDATE
-#define CFG_SH_ETHER_ALIGNE_SIZE 64
-
-/* Board Clock */
-
#define CFG_EXTRA_ENV_SETTINGS \
"bootm_size=0x10000000\0"
-/* SPL support */
-
#endif /* __PORTER_H */
diff --git a/include/configs/silk.h b/include/configs/silk.h
index 7bed32d8553..09ef2a848bd 100644
--- a/include/configs/silk.h
+++ b/include/configs/silk.h
@@ -21,19 +21,7 @@
#define RCAR_GEN2_SDRAM_SIZE (1024u * 1024 * 1024)
#define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024)
-/* SH Ether */
-#define CFG_SH_ETHER_USE_PORT 0
-#define CFG_SH_ETHER_PHY_ADDR 0x1
-#define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
-#define CFG_SH_ETHER_CACHE_WRITEBACK
-#define CFG_SH_ETHER_CACHE_INVALIDATE
-#define CFG_SH_ETHER_ALIGNE_SIZE 64
-
-/* Board Clock */
-
#define CFG_EXTRA_ENV_SETTINGS \
"bootm_size=0x10000000\0"
-/* SPL support */
-
#endif /* __SILK_H */
diff --git a/include/configs/stout.h b/include/configs/stout.h
index 1278ba63f4f..f98ebb324f3 100644
--- a/include/configs/stout.h
+++ b/include/configs/stout.h
@@ -25,19 +25,7 @@
/* SCIF */
#define CFG_SCIF_A
-/* SH Ether */
-#define CFG_SH_ETHER_USE_PORT 0
-#define CFG_SH_ETHER_PHY_ADDR 0x1
-#define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
-#define CFG_SH_ETHER_CACHE_WRITEBACK
-#define CFG_SH_ETHER_CACHE_INVALIDATE
-#define CFG_SH_ETHER_ALIGNE_SIZE 64
-
-/* Board Clock */
-
#define CFG_EXTRA_ENV_SETTINGS \
"bootm_size=0x10000000\0"
-/* SPL support */
-
#endif /* __STOUT_H */
diff --git a/include/configs/v3hsk.h b/include/configs/v3hsk.h
index 58c2e88c0b7..3298e627e53 100644
--- a/include/configs/v3hsk.h
+++ b/include/configs/v3hsk.h
@@ -12,17 +12,4 @@
#include "rcar-gen3-common.h"
-/* Environment compatibility */
-
-/* SH Ether */
-#define CFG_SH_ETHER_USE_PORT 0
-#define CFG_SH_ETHER_PHY_ADDR 0x0
-#define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RGMII_ID
-#define CFG_SH_ETHER_CACHE_WRITEBACK
-#define CFG_SH_ETHER_CACHE_INVALIDATE
-#define CFG_SH_ETHER_ALIGNE_SIZE 64
-
-/* Board Clock */
-/* XTAL_CLK : 33.33MHz */
-
#endif /* __V3HSK_H */
generated by cgit v1.2.3 (git 2.0.4) at 2025-07-15 05:35:58 +0000