diff options
Diffstat (limited to 'include/dt-bindings/clock/mt7986-clk.h')
| -rw-r--r-- | include/dt-bindings/clock/mt7986-clk.h | 71 |
1 files changed, 40 insertions, 31 deletions
diff --git a/include/dt-bindings/clock/mt7986-clk.h b/include/dt-bindings/clock/mt7986-clk.h index 5a9b169324b..5da260386fd 100644 --- a/include/dt-bindings/clock/mt7986-clk.h +++ b/include/dt-bindings/clock/mt7986-clk.h @@ -1,41 +1,32 @@ -/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* SPDX-License-Identifier: GPL-2.0 */ /* - * Copyright (c) 2021 MediaTek Inc. + * Copyright (C) 2022 MediaTek Inc. All rights reserved. + * * Author: Sam Shih <sam.shih@mediatek.com> */ #ifndef _DT_BINDINGS_CLK_MT7986_H #define _DT_BINDINGS_CLK_MT7986_H -/* APMIXEDSYS */ - -#define CLK_APMIXED_ARMPLL 0 -#define CLK_APMIXED_NET2PLL 1 -#define CLK_APMIXED_MMPLL 2 -#define CLK_APMIXED_SGMPLL 3 -#define CLK_APMIXED_WEDMCUPLL 4 -#define CLK_APMIXED_NET1PLL 5 -#define CLK_APMIXED_MPLL 6 -#define CLK_APMIXED_APLL2 7 - /* TOPCKGEN */ #define CLK_TOP_XTAL 0 #define CLK_TOP_XTAL_D2 1 #define CLK_TOP_RTC_32K 2 #define CLK_TOP_RTC_32P7K 3 +/* #define CLK_TOP_A_TUNER 4 */ #define CLK_TOP_MPLL_D2 4 #define CLK_TOP_MPLL_D4 5 #define CLK_TOP_MPLL_D8 6 #define CLK_TOP_MPLL_D8_D2 7 #define CLK_TOP_MPLL_D3_D2 8 -#define CLK_TOP_MMPLL_D2 9 -#define CLK_TOP_MMPLL_D4 10 -#define CLK_TOP_MMPLL_D8 11 +#define CLK_TOP_MMPLL_D2 9 +#define CLK_TOP_MMPLL_D4 10 +#define CLK_TOP_MMPLL_D8 11 #define CLK_TOP_MMPLL_D8_D2 12 #define CLK_TOP_MMPLL_D3_D8 13 -#define CLK_TOP_MMPLL_U2PHY 14 -#define CLK_TOP_APLL2_D4 15 +#define CLK_TOP_MMPLL_U2PHYD 14 +#define CLK_TOP_APLL2_D4 15 #define CLK_TOP_NET1PLL_D4 16 #define CLK_TOP_NET1PLL_D5 17 #define CLK_TOP_NET1PLL_D5_D2 18 @@ -50,7 +41,7 @@ #define CLK_TOP_SPINFI_SEL 27 #define CLK_TOP_SPI_SEL 28 #define CLK_TOP_SPIM_MST_SEL 29 -#define CLK_TOP_UART_SEL 30 +#define CLK_TOP_UART_SEL 30 #define CLK_TOP_PWM_SEL 31 #define CLK_TOP_I2C_SEL 32 #define CLK_TOP_PEXTP_TL_SEL 33 @@ -74,16 +65,16 @@ #define CLK_TOP_EIP_B_SEL 51 #define CLK_TOP_PCIE_PHY_SEL 52 #define CLK_TOP_USB3_PHY_SEL 53 -#define CLK_TOP_F26M_SEL 54 +#define CLK_TOP_F26M_SEL 54 #define CLK_TOP_AUD_L_SEL 55 #define CLK_TOP_A_TUNER_SEL 56 -#define CLK_TOP_U2U3_SEL 57 +#define CLK_TOP_U2U3_SEL 57 #define CLK_TOP_U2U3_SYS_SEL 58 #define CLK_TOP_U2U3_XHCI_SEL 59 #define CLK_TOP_DA_U2_REFSEL 60 #define CLK_TOP_DA_U2_CK_1P_SEL 61 #define CLK_TOP_AP2CNN_HOST_SEL 62 -#define CLK_TOP_JTAG 63 +#define CLK_TOP_NR_CLK 63 /* INFRACFG */ @@ -143,20 +134,35 @@ #define CLK_INFRA_IPCIER_CK 53 #define CLK_INFRA_IPCIEB_CK 54 #define CLK_INFRA_TRNG_CK 55 +#define CLK_INFRA_AO_NR_CLK 46 + +/* APMIXEDSYS */ + +#define CLK_APMIXED_ARMPLL 0 +#define CLK_APMIXED_NET2PLL 1 +#define CLK_APMIXED_MMPLL 2 +#define CLK_APMIXED_SGMPLL 3 +#define CLK_APMIXED_WEDMCUPLL 4 +#define CLK_APMIXED_NET1PLL 5 +#define CLK_APMIXED_MPLL 6 +#define CLK_APMIXED_APLL2 7 +#define CLK_APMIXED_NR_CLK 8 /* SGMIISYS_0 */ -#define CLK_SGMII0_TX250M_EN 0 -#define CLK_SGMII0_RX250M_EN 1 -#define CLK_SGMII0_CDR_REF 2 -#define CLK_SGMII0_CDR_FB 3 +#define CLK_SGM0_TX_EN 0 +#define CLK_SGM0_RX_EN 1 +#define CLK_SGM0_CK0_EN 2 +#define CLK_SGM0_CDR_CK0_EN 3 +#define CLK_SGMII0_NR_CLK 4 /* SGMIISYS_1 */ -#define CLK_SGMII1_TX250M_EN 0 -#define CLK_SGMII1_RX250M_EN 1 -#define CLK_SGMII1_CDR_REF 2 -#define CLK_SGMII1_CDR_FB 3 +#define CLK_SGM1_TX_EN 0 +#define CLK_SGM1_RX_EN 1 +#define CLK_SGM1_CK1_EN 2 +#define CLK_SGM1_CDR_CK1_EN 3 +#define CLK_SGMII1_NR_CLK 4 /* ETHSYS */ @@ -165,5 +171,8 @@ #define CLK_ETH_GP1_EN 2 #define CLK_ETH_WOCPU1_EN 3 #define CLK_ETH_WOCPU0_EN 4 +#define CLK_ETH_NR_CLK 5 + +#endif -#endif /* _DT_BINDINGS_CLK_MT7986_H */ +/* _DT_BINDINGS_CLK_MT7986_H */ |