diff options
Diffstat (limited to 'include/dt-bindings/clock/qcom,qdu1000-gcc.h')
| -rw-r--r-- | include/dt-bindings/clock/qcom,qdu1000-gcc.h | 177 |
1 files changed, 0 insertions, 177 deletions
diff --git a/include/dt-bindings/clock/qcom,qdu1000-gcc.h b/include/dt-bindings/clock/qcom,qdu1000-gcc.h deleted file mode 100644 index 2fd36cbfddb..00000000000 --- a/include/dt-bindings/clock/qcom,qdu1000-gcc.h +++ /dev/null @@ -1,177 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ -/* - * Copyright (c) 2021-2023, Qualcomm Innovation Center, Inc. All rights reserved. - */ - -#ifndef _DT_BINDINGS_CLK_QCOM_GCC_QDU1000_H -#define _DT_BINDINGS_CLK_QCOM_GCC_QDU1000_H - -/* GCC clocks */ -#define GCC_GPLL0 0 -#define GCC_GPLL0_OUT_EVEN 1 -#define GCC_GPLL1 2 -#define GCC_GPLL2 3 -#define GCC_GPLL2_OUT_EVEN 4 -#define GCC_GPLL3 5 -#define GCC_GPLL4 6 -#define GCC_GPLL5 7 -#define GCC_GPLL5_OUT_EVEN 8 -#define GCC_GPLL6 9 -#define GCC_GPLL7 10 -#define GCC_GPLL8 11 -#define GCC_AGGRE_NOC_ECPRI_DMA_CLK 12 -#define GCC_AGGRE_NOC_ECPRI_DMA_CLK_SRC 13 -#define GCC_AGGRE_NOC_ECPRI_GSI_CLK_SRC 14 -#define GCC_BOOT_ROM_AHB_CLK 15 -#define GCC_CFG_NOC_ECPRI_CC_AHB_CLK 16 -#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 17 -#define GCC_DDRSS_ECPRI_DMA_CLK 18 -#define GCC_ECPRI_AHB_CLK 19 -#define GCC_ECPRI_CC_GPLL0_CLK_SRC 20 -#define GCC_ECPRI_CC_GPLL1_EVEN_CLK_SRC 21 -#define GCC_ECPRI_CC_GPLL2_EVEN_CLK_SRC 22 -#define GCC_ECPRI_CC_GPLL3_CLK_SRC 23 -#define GCC_ECPRI_CC_GPLL4_CLK_SRC 24 -#define GCC_ECPRI_CC_GPLL5_EVEN_CLK_SRC 25 -#define GCC_ECPRI_XO_CLK 26 -#define GCC_ETH_DBG_SNOC_AXI_CLK 27 -#define GCC_GEMNOC_PCIE_QX_CLK 28 -#define GCC_GP1_CLK 29 -#define GCC_GP1_CLK_SRC 30 -#define GCC_GP2_CLK 31 -#define GCC_GP2_CLK_SRC 32 -#define GCC_GP3_CLK 33 -#define GCC_GP3_CLK_SRC 34 -#define GCC_PCIE_0_AUX_CLK 35 -#define GCC_PCIE_0_AUX_CLK_SRC 36 -#define GCC_PCIE_0_CFG_AHB_CLK 37 -#define GCC_PCIE_0_CLKREF_EN 38 -#define GCC_PCIE_0_MSTR_AXI_CLK 39 -#define GCC_PCIE_0_PHY_AUX_CLK 40 -#define GCC_PCIE_0_PHY_RCHNG_CLK 41 -#define GCC_PCIE_0_PHY_RCHNG_CLK_SRC 42 -#define GCC_PCIE_0_PIPE_CLK 43 -#define GCC_PCIE_0_SLV_AXI_CLK 44 -#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 45 -#define GCC_PDM2_CLK 46 -#define GCC_PDM2_CLK_SRC 47 -#define GCC_PDM_AHB_CLK 48 -#define GCC_PDM_XO4_CLK 49 -#define GCC_QMIP_ANOC_PCIE_CLK 50 -#define GCC_QMIP_ECPRI_DMA0_CLK 51 -#define GCC_QMIP_ECPRI_DMA1_CLK 52 -#define GCC_QMIP_ECPRI_GSI_CLK 53 -#define GCC_QUPV3_WRAP0_CORE_2X_CLK 54 -#define GCC_QUPV3_WRAP0_CORE_CLK 55 -#define GCC_QUPV3_WRAP0_S0_CLK 56 -#define GCC_QUPV3_WRAP0_S0_CLK_SRC 57 -#define GCC_QUPV3_WRAP0_S1_CLK 58 -#define GCC_QUPV3_WRAP0_S1_CLK_SRC 59 -#define GCC_QUPV3_WRAP0_S2_CLK 60 -#define GCC_QUPV3_WRAP0_S2_CLK_SRC 61 -#define GCC_QUPV3_WRAP0_S3_CLK 62 -#define GCC_QUPV3_WRAP0_S3_CLK_SRC 63 -#define GCC_QUPV3_WRAP0_S4_CLK 64 -#define GCC_QUPV3_WRAP0_S4_CLK_SRC 65 -#define GCC_QUPV3_WRAP0_S5_CLK 66 -#define GCC_QUPV3_WRAP0_S5_CLK_SRC 67 -#define GCC_QUPV3_WRAP0_S6_CLK 68 -#define GCC_QUPV3_WRAP0_S6_CLK_SRC 69 -#define GCC_QUPV3_WRAP0_S7_CLK 70 -#define GCC_QUPV3_WRAP0_S7_CLK_SRC 71 -#define GCC_QUPV3_WRAP1_CORE_2X_CLK 72 -#define GCC_QUPV3_WRAP1_CORE_CLK 73 -#define GCC_QUPV3_WRAP1_S0_CLK 74 -#define GCC_QUPV3_WRAP1_S0_CLK_SRC 75 -#define GCC_QUPV3_WRAP1_S1_CLK 76 -#define GCC_QUPV3_WRAP1_S1_CLK_SRC 77 -#define GCC_QUPV3_WRAP1_S2_CLK 78 -#define GCC_QUPV3_WRAP1_S2_CLK_SRC 79 -#define GCC_QUPV3_WRAP1_S3_CLK 80 -#define GCC_QUPV3_WRAP1_S3_CLK_SRC 81 -#define GCC_QUPV3_WRAP1_S4_CLK 82 -#define GCC_QUPV3_WRAP1_S4_CLK_SRC 83 -#define GCC_QUPV3_WRAP1_S5_CLK 84 -#define GCC_QUPV3_WRAP1_S5_CLK_SRC 85 -#define GCC_QUPV3_WRAP1_S6_CLK 86 -#define GCC_QUPV3_WRAP1_S6_CLK_SRC 87 -#define GCC_QUPV3_WRAP1_S7_CLK 88 -#define GCC_QUPV3_WRAP1_S7_CLK_SRC 89 -#define GCC_QUPV3_WRAP_0_M_AHB_CLK 90 -#define GCC_QUPV3_WRAP_0_S_AHB_CLK 91 -#define GCC_QUPV3_WRAP_1_M_AHB_CLK 92 -#define GCC_QUPV3_WRAP_1_S_AHB_CLK 93 -#define GCC_SDCC5_AHB_CLK 94 -#define GCC_SDCC5_APPS_CLK 95 -#define GCC_SDCC5_APPS_CLK_SRC 96 -#define GCC_SDCC5_ICE_CORE_CLK 97 -#define GCC_SDCC5_ICE_CORE_CLK_SRC 98 -#define GCC_SNOC_CNOC_GEMNOC_PCIE_QX_CLK 99 -#define GCC_SNOC_CNOC_GEMNOC_PCIE_SOUTH_QX_CLK 100 -#define GCC_SNOC_CNOC_PCIE_QX_CLK 101 -#define GCC_SNOC_PCIE_SF_CENTER_QX_CLK 102 -#define GCC_SNOC_PCIE_SF_SOUTH_QX_CLK 103 -#define GCC_TSC_CFG_AHB_CLK 104 -#define GCC_TSC_CLK_SRC 105 -#define GCC_TSC_CNTR_CLK 106 -#define GCC_TSC_ETU_CLK 107 -#define GCC_USB2_CLKREF_EN 108 -#define GCC_USB30_PRIM_MASTER_CLK 109 -#define GCC_USB30_PRIM_MASTER_CLK_SRC 110 -#define GCC_USB30_PRIM_MOCK_UTMI_CLK 111 -#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 112 -#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC 113 -#define GCC_USB30_PRIM_SLEEP_CLK 114 -#define GCC_USB3_PRIM_PHY_AUX_CLK 115 -#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 116 -#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 117 -#define GCC_USB3_PRIM_PHY_PIPE_CLK 118 -#define GCC_SM_BUS_AHB_CLK 119 -#define GCC_SM_BUS_XO_CLK 120 -#define GCC_SM_BUS_XO_CLK_SRC 121 -#define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC 122 -#define GCC_ETH_100G_C2C_HM_APB_CLK 123 -#define GCC_ETH_100G_FH_HM_APB_0_CLK 124 -#define GCC_ETH_100G_FH_HM_APB_1_CLK 125 -#define GCC_ETH_100G_FH_HM_APB_2_CLK 126 -#define GCC_ETH_DBG_C2C_HM_APB_CLK 127 -#define GCC_AGGRE_NOC_ECPRI_GSI_CLK 128 -#define GCC_PCIE_0_PIPE_CLK_SRC 129 -#define GCC_PCIE_0_PHY_AUX_CLK_SRC 130 -#define GCC_GPLL1_OUT_EVEN 131 -#define GCC_DDRSS_ECPRI_GSI_CLK 132 - -/* GCC resets */ -#define GCC_ECPRI_CC_BCR 0 -#define GCC_ECPRI_SS_BCR 1 -#define GCC_ETH_WRAPPER_BCR 2 -#define GCC_PCIE_0_BCR 3 -#define GCC_PCIE_0_LINK_DOWN_BCR 4 -#define GCC_PCIE_0_NOCSR_COM_PHY_BCR 5 -#define GCC_PCIE_0_PHY_BCR 6 -#define GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR 7 -#define GCC_PCIE_PHY_CFG_AHB_BCR 8 -#define GCC_PCIE_PHY_COM_BCR 9 -#define GCC_PDM_BCR 10 -#define GCC_QUPV3_WRAPPER_0_BCR 11 -#define GCC_QUPV3_WRAPPER_1_BCR 12 -#define GCC_QUSB2PHY_PRIM_BCR 13 -#define GCC_QUSB2PHY_SEC_BCR 14 -#define GCC_SDCC5_BCR 15 -#define GCC_TCSR_PCIE_BCR 16 -#define GCC_TSC_BCR 17 -#define GCC_USB30_PRIM_BCR 18 -#define GCC_USB3_DP_PHY_PRIM_BCR 19 -#define GCC_USB3_DP_PHY_SEC_BCR 20 -#define GCC_USB3_PHY_PRIM_BCR 21 -#define GCC_USB3_PHY_SEC_BCR 22 -#define GCC_USB3PHY_PHY_PRIM_BCR 23 -#define GCC_USB3PHY_PHY_SEC_BCR 24 -#define GCC_USB_PHY_CFG_AHB2PHY_BCR 25 - -/* GCC power domains */ -#define PCIE_0_GDSC 0 -#define PCIE_0_PHY_GDSC 1 -#define USB30_PRIM_GDSC 2 - -#endif |