diff options
Diffstat (limited to 'include/dt-bindings/clock/qcom,sm7150-gcc.h')
| -rw-r--r-- | include/dt-bindings/clock/qcom,sm7150-gcc.h | 186 |
1 files changed, 0 insertions, 186 deletions
diff --git a/include/dt-bindings/clock/qcom,sm7150-gcc.h b/include/dt-bindings/clock/qcom,sm7150-gcc.h deleted file mode 100644 index 7719ffc8613..00000000000 --- a/include/dt-bindings/clock/qcom,sm7150-gcc.h +++ /dev/null @@ -1,186 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ -/* - * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. - * Copyright (c) 2023, Danila Tikhonov <danila@jiaxyga.com> - * Copyright (c) 2023, David Wronek <davidwronek@gmail.com> - */ - -#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SM7150_H -#define _DT_BINDINGS_CLK_QCOM_GCC_SM7150_H - -/* GCC clock registers */ -#define GCC_GPLL0_MAIN_DIV_CDIV 0 -#define GPLL0 1 -#define GPLL0_OUT_EVEN 2 -#define GPLL6 3 -#define GPLL7 4 -#define GCC_AGGRE_NOC_PCIE_TBU_CLK 5 -#define GCC_AGGRE_UFS_PHY_AXI_CLK 6 -#define GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK 7 -#define GCC_AGGRE_USB3_PRIM_AXI_CLK 8 -#define GCC_APC_VS_CLK 9 -#define GCC_BOOT_ROM_AHB_CLK 10 -#define GCC_CAMERA_HF_AXI_CLK 11 -#define GCC_CAMERA_SF_AXI_CLK 12 -#define GCC_CE1_AHB_CLK 13 -#define GCC_CE1_AXI_CLK 14 -#define GCC_CE1_CLK 15 -#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 16 -#define GCC_CPUSS_AHB_CLK 17 -#define GCC_CPUSS_AHB_CLK_SRC 18 -#define GCC_CPUSS_RBCPR_CLK 19 -#define GCC_CPUSS_RBCPR_CLK_SRC 20 -#define GCC_DDRSS_GPU_AXI_CLK 21 -#define GCC_DISP_GPLL0_CLK_SRC 22 -#define GCC_DISP_GPLL0_DIV_CLK_SRC 23 -#define GCC_DISP_HF_AXI_CLK 24 -#define GCC_DISP_SF_AXI_CLK 25 -#define GCC_GP1_CLK 26 -#define GCC_GP1_CLK_SRC 27 -#define GCC_GP2_CLK 28 -#define GCC_GP2_CLK_SRC 29 -#define GCC_GP3_CLK 30 -#define GCC_GP3_CLK_SRC 31 -#define GCC_GPU_GPLL0_CLK_SRC 32 -#define GCC_GPU_GPLL0_DIV_CLK_SRC 33 -#define GCC_GPU_MEMNOC_GFX_CLK 34 -#define GCC_GPU_SNOC_DVM_GFX_CLK 35 -#define GCC_GPU_VS_CLK 36 -#define GCC_NPU_AXI_CLK 37 -#define GCC_NPU_CFG_AHB_CLK 38 -#define GCC_NPU_GPLL0_CLK_SRC 39 -#define GCC_NPU_GPLL0_DIV_CLK_SRC 40 -#define GCC_PCIE_0_AUX_CLK 41 -#define GCC_PCIE_0_AUX_CLK_SRC 42 -#define GCC_PCIE_0_CFG_AHB_CLK 43 -#define GCC_PCIE_0_CLKREF_CLK 44 -#define GCC_PCIE_0_MSTR_AXI_CLK 45 -#define GCC_PCIE_0_PIPE_CLK 46 -#define GCC_PCIE_0_SLV_AXI_CLK 47 -#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 48 -#define GCC_PCIE_PHY_AUX_CLK 49 -#define GCC_PCIE_PHY_REFGEN_CLK 50 -#define GCC_PCIE_PHY_REFGEN_CLK_SRC 51 -#define GCC_PDM2_CLK 52 -#define GCC_PDM2_CLK_SRC 53 -#define GCC_PDM_AHB_CLK 54 -#define GCC_PDM_XO4_CLK 55 -#define GCC_PRNG_AHB_CLK 56 -#define GCC_QUPV3_WRAP0_CORE_2X_CLK 57 -#define GCC_QUPV3_WRAP0_CORE_CLK 58 -#define GCC_QUPV3_WRAP0_S0_CLK 59 -#define GCC_QUPV3_WRAP0_S0_CLK_SRC 60 -#define GCC_QUPV3_WRAP0_S1_CLK 61 -#define GCC_QUPV3_WRAP0_S1_CLK_SRC 62 -#define GCC_QUPV3_WRAP0_S2_CLK 63 -#define GCC_QUPV3_WRAP0_S2_CLK_SRC 64 -#define GCC_QUPV3_WRAP0_S3_CLK 65 -#define GCC_QUPV3_WRAP0_S3_CLK_SRC 66 -#define GCC_QUPV3_WRAP0_S4_CLK 67 -#define GCC_QUPV3_WRAP0_S4_CLK_SRC 68 -#define GCC_QUPV3_WRAP0_S5_CLK 69 -#define GCC_QUPV3_WRAP0_S5_CLK_SRC 70 -#define GCC_QUPV3_WRAP0_S6_CLK 71 -#define GCC_QUPV3_WRAP0_S6_CLK_SRC 72 -#define GCC_QUPV3_WRAP0_S7_CLK 73 -#define GCC_QUPV3_WRAP0_S7_CLK_SRC 74 -#define GCC_QUPV3_WRAP1_CORE_2X_CLK 75 -#define GCC_QUPV3_WRAP1_CORE_CLK 76 -#define GCC_QUPV3_WRAP1_S0_CLK 77 -#define GCC_QUPV3_WRAP1_S0_CLK_SRC 78 -#define GCC_QUPV3_WRAP1_S1_CLK 79 -#define GCC_QUPV3_WRAP1_S1_CLK_SRC 80 -#define GCC_QUPV3_WRAP1_S2_CLK 81 -#define GCC_QUPV3_WRAP1_S2_CLK_SRC 82 -#define GCC_QUPV3_WRAP1_S3_CLK 83 -#define GCC_QUPV3_WRAP1_S3_CLK_SRC 84 -#define GCC_QUPV3_WRAP1_S4_CLK 85 -#define GCC_QUPV3_WRAP1_S4_CLK_SRC 86 -#define GCC_QUPV3_WRAP1_S5_CLK 87 -#define GCC_QUPV3_WRAP1_S5_CLK_SRC 88 -#define GCC_QUPV3_WRAP1_S6_CLK 89 -#define GCC_QUPV3_WRAP1_S6_CLK_SRC 90 -#define GCC_QUPV3_WRAP1_S7_CLK 91 -#define GCC_QUPV3_WRAP1_S7_CLK_SRC 92 -#define GCC_QUPV3_WRAP_0_M_AHB_CLK 93 -#define GCC_QUPV3_WRAP_0_S_AHB_CLK 94 -#define GCC_QUPV3_WRAP_1_M_AHB_CLK 95 -#define GCC_QUPV3_WRAP_1_S_AHB_CLK 96 -#define GCC_SDCC1_AHB_CLK 97 -#define GCC_SDCC1_APPS_CLK 98 -#define GCC_SDCC1_APPS_CLK_SRC 99 -#define GCC_SDCC1_ICE_CORE_CLK 100 -#define GCC_SDCC1_ICE_CORE_CLK_SRC 101 -#define GCC_SDCC2_AHB_CLK 102 -#define GCC_SDCC2_APPS_CLK 103 -#define GCC_SDCC2_APPS_CLK_SRC 104 -#define GCC_SDCC4_AHB_CLK 105 -#define GCC_SDCC4_APPS_CLK 106 -#define GCC_SDCC4_APPS_CLK_SRC 107 -#define GCC_SYS_NOC_CPUSS_AHB_CLK 108 -#define GCC_TSIF_AHB_CLK 109 -#define GCC_TSIF_INACTIVITY_TIMERS_CLK 110 -#define GCC_TSIF_REF_CLK 111 -#define GCC_TSIF_REF_CLK_SRC 112 -#define GCC_UFS_MEM_CLKREF_CLK 113 -#define GCC_UFS_PHY_AHB_CLK 114 -#define GCC_UFS_PHY_AXI_CLK 115 -#define GCC_UFS_PHY_AXI_CLK_SRC 116 -#define GCC_UFS_PHY_AXI_HW_CTL_CLK 117 -#define GCC_UFS_PHY_ICE_CORE_CLK 118 -#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 119 -#define GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK 120 -#define GCC_UFS_PHY_PHY_AUX_CLK 121 -#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 122 -#define GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK 123 -#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 124 -#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 125 -#define GCC_UFS_PHY_UNIPRO_CORE_CLK 126 -#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 127 -#define GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK 128 -#define GCC_USB30_PRIM_MASTER_CLK 129 -#define GCC_USB30_PRIM_MASTER_CLK_SRC 130 -#define GCC_USB30_PRIM_MOCK_UTMI_CLK 131 -#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 132 -#define GCC_USB30_PRIM_SLEEP_CLK 133 -#define GCC_USB3_PRIM_CLKREF_CLK 134 -#define GCC_USB3_PRIM_PHY_AUX_CLK 135 -#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 136 -#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 137 -#define GCC_USB3_PRIM_PHY_PIPE_CLK 138 -#define GCC_USB_PHY_CFG_AHB2PHY_CLK 139 -#define GCC_VDDA_VS_CLK 140 -#define GCC_VDDCX_VS_CLK 141 -#define GCC_VDDMX_VS_CLK 142 -#define GCC_VIDEO_AXI_CLK 143 -#define GCC_VS_CTRL_AHB_CLK 144 -#define GCC_VS_CTRL_CLK 145 -#define GCC_VS_CTRL_CLK_SRC 146 -#define GCC_VSENSOR_CLK_SRC 147 - -/* GCC Resets */ -#define GCC_PCIE_0_BCR 0 -#define GCC_PCIE_PHY_BCR 1 -#define GCC_PCIE_PHY_COM_BCR 2 -#define GCC_UFS_PHY_BCR 3 -#define GCC_USB30_PRIM_BCR 4 -#define GCC_USB3_DP_PHY_PRIM_BCR 5 -#define GCC_USB3_DP_PHY_SEC_BCR 6 -#define GCC_USB3_PHY_PRIM_BCR 7 -#define GCC_USB3_PHY_SEC_BCR 8 -#define GCC_QUSB2PHY_PRIM_BCR 9 -#define GCC_VIDEO_AXI_CLK_BCR 10 - -/* GCC GDSCRs */ -#define PCIE_0_GDSC 0 -#define UFS_PHY_GDSC 1 -#define USB30_PRIM_GDSC 2 -#define HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDSC 3 -#define HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDSC 4 -#define HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_GDSC 5 -#define HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_GDSC 6 -#define HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC 7 -#define HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC 8 -#define HLOS1_VOTE_MMNOC_MMU_TBU_SF_GDSC 9 - -#endif |