diff options
Diffstat (limited to 'include/dt-bindings/memory')
27 files changed, 403 insertions, 4140 deletions
diff --git a/include/dt-bindings/memory/bcm-ns3-mc.h b/include/dt-bindings/memory/bcm-ns3-mc.h new file mode 100644 index 00000000000..d2478d9ae31 --- /dev/null +++ b/include/dt-bindings/memory/bcm-ns3-mc.h @@ -0,0 +1,63 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2020 Broadcom + */ + +#ifndef DT_BINDINGS_BCM_NS3_MC_H +#define DT_BINDINGS_BCM_NS3_MC_H + +/* + * +--------+----------+ 0x8b000000 + * | NITRO CRASH DUMP | 32MB + * +--------+----------+ 0x8d000000 + * | SHMEM (NS) | 16 MB + * +-------------------+ 0x8e000000 + * | | TEE_RAM(S)| 4MB + * + TZDRAM +----------+ 0x8e400000 + * | | TA_RAM(S) | 12MB + * +--------+----------+ 0x8f000000 + * | BL31 + TMON + LPM | + * | memory | 1MB + * +-------------------+ 0x8f100000 + */ + +#define BCM_NS3_MEM_NITRO_CRASH_START 0x8ae00000 +#define BCM_NS3_MEM_NITRO_CRASH_LEN 0x21fffff +#define BCM_NS3_MEM_NITRO_CRASH_SIZE 0x2200000 + +#define BCM_NS3_MEM_SHARE_START 0x8d000000 +#define BCM_NS3_MEM_SHARE_LEN 0x020fffff + +/* ATF/U-Boot/Linux error logs */ +#define BCM_NS3_MEM_ELOG_START 0x8f113000 +#define BCM_NS3_MEM_ELOG_LEN 0x00100000 + +/* CRMU Page table memroy */ +#define BCM_NS3_MEM_CRMU_PT_START 0x880000000 +#define BCM_NS3_MEM_CRMU_PT_LEN 0x200000 + +/* default memory starting address and length */ +#define BCM_NS3_MEM_START 0x80000000UL +#define BCM_NS3_MEM_LEN 0x80000000UL +#define BCM_NS3_MEM_END (BCM_NS3_MEM_START + BCM_NS3_MEM_LEN) + +/* memory starting address and length for BANK_1 */ +#define BCM_NS3_BANK_1_MEM_START 0x880000000UL +#define BCM_NS3_BANK_1_MEM_LEN 0x180000000UL + +/* memory layout information */ +#define BCM_NS3_DDR_INFO_BASE 0x8f220000 +#define BCM_NS3_DDR_INFO_RSVD_LEN 0x1000 +#define BCM_NS3_DDR_INFO_LEN 73 +#define BCM_NS3_DDR_INFO_SIG 0x42434d44 +#define BCM_NS3_MAX_NR_BANKS 4 + +#define BCM_NS3_GIC_LPI_BASE 0x8ad70000 +#define BCM_NS3_MEM_RSVE_START BCM_NS3_GIC_LPI_BASE +#define BCM_NS3_MEM_RSVE_END ((BCM_NS3_MEM_ELOG_START + \ + BCM_NS3_MEM_ELOG_LEN) - \ + BCM_NS3_MEM_RSVE_START) + +#define BCM_NS3_CRMU_PGT_START 0x880000000UL +#define BCM_NS3_CRMU_PGT_SIZE 0x100000 +#endif diff --git a/include/dt-bindings/memory/imxrt-sdram.h b/include/dt-bindings/memory/imxrt-sdram.h new file mode 100644 index 00000000000..4b3b0c2f504 --- /dev/null +++ b/include/dt-bindings/memory/imxrt-sdram.h @@ -0,0 +1,101 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2019 + * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com> + */ + +#ifndef DT_BINDINGS_IMXRT_SDRAM_H +#define DT_BINDINGS_IMXRT_SDRAM_H + +#define MEM_SIZE_4K 0x00 +#define MEM_SIZE_8K 0x01 +#define MEM_SIZE_16K 0x02 +#define MEM_SIZE_32K 0x03 +#define MEM_SIZE_64K 0x04 +#define MEM_SIZE_128K 0x05 +#define MEM_SIZE_256K 0x06 +#define MEM_SIZE_512K 0x07 +#define MEM_SIZE_1M 0x08 +#define MEM_SIZE_2M 0x09 +#define MEM_SIZE_4M 0x0A +#define MEM_SIZE_8M 0x0B +#define MEM_SIZE_16M 0x0C +#define MEM_SIZE_32M 0x0D +#define MEM_SIZE_64M 0x0E +#define MEM_SIZE_128M 0x0F +#define MEM_SIZE_256M 0x10 +#define MEM_SIZE_512M 0x11 +#define MEM_SIZE_1G 0x12 +#define MEM_SIZE_2G 0x13 +#define MEM_SIZE_4G 0x14 + +#define MUX_A8_SDRAM_A8 0x0 +#define MUX_A8_NAND_CE 0x1 +#define MUX_A8_NOR_CE 0x2 +#define MUX_A8_PSRAM_CE 0x3 +#define MUX_A8_DBI_CSX 0x4 + +#define MUX_CSX0_NOR_PSRAM_A24 0x0 +#define MUX_CSX0_SDRAM_CS1 0x1 +#define MUX_CSX0_SDRAM_CS2 0x2 +#define MUX_CSX0_SDRAM_CS3 0x3 +#define MUX_CSX0_NAND_CE 0x4 +#define MUX_CSX0_NOR_CE 0x5 +#define MUX_CSX0_PSRAM_CE 0x6 +#define MUX_CSX0_DBI_CSX 0x7 + +#define MUX_CSX1_NOR_PSRAM_A25 0x0 +#define MUX_CSX1_SDRAM_CS1 0x1 +#define MUX_CSX1_SDRAM_CS2 0x2 +#define MUX_CSX1_SDRAM_CS3 0x3 +#define MUX_CSX1_NAND_CE 0x4 +#define MUX_CSX1_NOR_CE 0x5 +#define MUX_CSX1_PSRAM_CE 0x6 +#define MUX_CSX1_DBI_CSX 0x7 + +#define MUX_CSX2_NOR_PSRAM_A26 0x0 +#define MUX_CSX2_SDRAM_CS1 0x1 +#define MUX_CSX2_SDRAM_CS2 0x2 +#define MUX_CSX2_SDRAM_CS3 0x3 +#define MUX_CSX2_NAND_CE 0x4 +#define MUX_CSX2_NOR_CE 0x5 +#define MUX_CSX2_PSRAM_CE 0x6 +#define MUX_CSX2_DBI_CSX 0x7 + +#define MUX_CSX3_NOR_PSRAM_A27 0x0 +#define MUX_CSX3_SDRAM_CS1 0x1 +#define MUX_CSX3_SDRAM_CS2 0x2 +#define MUX_CSX3_SDRAM_CS3 0x3 +#define MUX_CSX3_NAND_CE 0x4 +#define MUX_CSX3_NOR_CE 0x5 +#define MUX_CSX3_PSRAM_CE 0x6 +#define MUX_CSX3_DBI_CSX 0x7 + +#define MUX_RDY_NAND_RDY_WAIT 0x0 +#define MUX_RDY_SDRAM_CS1 0x1 +#define MUX_RDY_SDRAM_CS2 0x2 +#define MUX_RDY_SDRAM_CS3 0x3 +#define MUX_RDY_NOR_CE 0x4 +#define MUX_RDY_PSRAM_CE 0x5 +#define MUX_RDY_DBI_CSX 0x6 +#define MUX_RDY_NOR_PSRAM_A27 0x7 + +#define MEM_WIDTH_8BITS 0x0 +#define MEM_WIDTH_16BITS 0x1 +#define MEM_WIDTH_32BITS 0x2 + +#define BL_1 0x0 +#define BL_2 0x1 +#define BL_4 0x2 +#define BL_8 0x3 + +#define COL_12BITS 0x0 +#define COL_11BITS 0x1 +#define COL_10BITS 0x2 +#define COL_9BITS 0x3 + +#define CL_1 0x0 +#define CL_2 0x2 +#define CL_3 0x3 + +#endif diff --git a/include/dt-bindings/memory/mediatek,mt6893-memory-port.h b/include/dt-bindings/memory/mediatek,mt6893-memory-port.h deleted file mode 100644 index 26e8b400db0..00000000000 --- a/include/dt-bindings/memory/mediatek,mt6893-memory-port.h +++ /dev/null @@ -1,288 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ -/* - * Copyright (c) 2020 MediaTek Inc. - * Copyright (c) 2025 Collabora Ltd - * AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> - */ -#ifndef _DT_BINDINGS_MEMORY_MT6893_LARB_PORT_H_ -#define _DT_BINDINGS_MEMORY_MT6893_LARB_PORT_H_ - -#include <dt-bindings/memory/mtk-memory-port.h> - -/* - * MM IOMMU supports 16GB dma address. - * - * The address will preassign like this: - * - * modules dma-address-region larbs-ports - * disp 0 ~ 4G larb0/2 - * vcodec 4G ~ 8G larb4/5/7 - * cam/mdp 8G ~ 12G larb9/11/13/14/16/17/18/19/20 - * CCU0 0x4000_0000 ~ 0x43ff_ffff larb13: port 9/10 - * CCU1 0x4400_0000 ~ 0x47ff_ffff larb14: port 4/5 - * - * larb3/6/8/10/12/15 are null. - */ - -/* larb0 */ -#define M4U_PORT_L0_DISP_POSTMASK0 MTK_M4U_DOM_ID(0, 0) -#define M4U_PORT_L0_MDP_RDMA4 MTK_M4U_DOM_ID(0, 1) -#define M4U_PORT_L0_OVL_RDMA0_HDR MTK_M4U_DOM_ID(0, 2) -#define M4U_PORT_L0_OVL_2L_RDMA1_HDR MTK_M4U_DOM_ID(0, 3) -#define M4U_PORT_L0_OVL_2L_RDMA3_HDR MTK_M4U_DOM_ID(0, 4) -#define M4U_PORT_L0_OVL_RDMA0 MTK_M4U_DOM_ID(0, 5) -#define M4U_PORT_L0_OVL_2L_RDMA1 MTK_M4U_DOM_ID(0, 6) -#define M4U_PORT_L0_OVL_2L_RDMA3 MTK_M4U_DOM_ID(0, 7) -#define M4U_PORT_L0_OVL_RDMA1_SYSRAM MTK_M4U_DOM_ID(0, 8) -#define M4U_PORT_L0_OVL_2L_RDMA0_SYSRAM MTK_M4U_DOM_ID(0, 9) -#define M4U_PORT_L0_OVL_2L_RDMA2_SYSRAM MTK_M4U_DOM_ID(0, 10) -#define M4U_PORT_L0_DISP_WDMA0 MTK_M4U_DOM_ID(0, 11) -#define M4U_PORT_L0_DISP_RDMA0 MTK_M4U_DOM_ID(0, 12) -#define M4U_PORT_L0_DISP_UFBC_WDMA0 MTK_M4U_DOM_ID(0, 13) -#define M4U_PORT_L0_DISP_FAKE0 MTK_M4U_DOM_ID(0, 14) - -/* larb1 */ -#define M4U_PORT_L1_DISP_POSTMASK1 MTK_M4U_DOM_ID(1, 0) -#define M4U_PORT_L1_MDP_RDMA5 MTK_M4U_DOM_ID(1, 1) -#define M4U_PORT_L1_OVL_RDMA1_HDR MTK_M4U_DOM_ID(1, 2) -#define M4U_PORT_L1_OVL_2L_RDMA0_HDR MTK_M4U_DOM_ID(1, 3) -#define M4U_PORT_L1_OVL_2L_RDMA2_HDR MTK_M4U_DOM_ID(1, 4) -#define M4U_PORT_L1_OVL_RDMA1 MTK_M4U_DOM_ID(1, 5) -#define M4U_PORT_L1_OVL_2L_RDMA0 MTK_M4U_DOM_ID(1, 6) -#define M4U_PORT_L1_OVL_2L_RDMA2 MTK_M4U_DOM_ID(1, 7) -#define M4U_PORT_L1_OVL_RDMA0_SYSRAM MTK_M4U_DOM_ID(1, 8) -#define M4U_PORT_L1_OVL_2L_RDMA1_SYSRAM MTK_M4U_DOM_ID(1, 9) -#define M4U_PORT_L1_OVL_2L_RDMA3_SYSRAM MTK_M4U_DOM_ID(1, 10) -#define M4U_PORT_L1_DISP_WDMA1 MTK_M4U_DOM_ID(1, 11) -#define M4U_PORT_L1_DISP_RDMA1 MTK_M4U_DOM_ID(1, 12) -#define M4U_PORT_L1_DISP_UFBC_WDMA1 MTK_M4U_DOM_ID(1, 13) -#define M4U_PORT_L1_DISP_FAKE1 MTK_M4U_DOM_ID(1, 14) - -/* larb2 */ -#define M4U_PORT_L2_MDP_RDMA0 MTK_M4U_DOM_ID(2, 0) -#define M4U_PORT_L2_MDP_RDMA2 MTK_M4U_DOM_ID(2, 1) -#define M4U_PORT_L2_MDP_WROT0 MTK_M4U_DOM_ID(2, 2) -#define M4U_PORT_L2_MDP_WROT2 MTK_M4U_DOM_ID(2, 3) -#define M4U_PORT_L2_MDP_FILMGRAIN0 MTK_M4U_DOM_ID(2, 4) -#define M4U_PORT_L2_MDP_FAKE0 MTK_M4U_DOM_ID(2, 5) - -/* larb3: null */ - -/* larb4 */ -#define M4U_PORT_L4_VDEC_MC_EXT_MDP MTK_M4U_DOM_ID(4, 0) -#define M4U_PORT_L4_VDEC_UFO_EXT_MDP MTK_M4U_DOM_ID(4, 1) -#define M4U_PORT_L4_VDEC_PP_EXT_MDP MTK_M4U_DOM_ID(4, 2) -#define M4U_PORT_L4_VDEC_PRED_RD_EXT_MDP MTK_M4U_DOM_ID(4, 3) -#define M4U_PORT_L4_VDEC_PRED_WR_EXT_MDP MTK_M4U_DOM_ID(4, 4) -#define M4U_PORT_L4_VDEC_PPWRAP_EXT_MDP MTK_M4U_DOM_ID(4, 5) -#define M4U_PORT_L4_VDEC_TILE_EXT_MDP MTK_M4U_DOM_ID(4, 6) -#define M4U_PORT_L4_VDEC_VLD_EXT_MDP MTK_M4U_DOM_ID(4, 7) -#define M4U_PORT_L4_VDEC_VLD2_EXT_MDP MTK_M4U_DOM_ID(4, 8) -#define M4U_PORT_L4_VDEC_AVC_MV_EXT_MDP MTK_M4U_DOM_ID(4, 9) -#define M4U_PORT_L4_VDEC_RG_CTRL_DMA_EXT_MDP MTK_M4U_DOM_ID(4, 10) - -/* larb5 */ -#define M4U_PORT_L5_VDEC_LAT0_VLD_EXT_DISP MTK_M4U_DOM_ID(5, 0) -#define M4U_PORT_L5_VDEC_LAT0_VLD2_EXT_DISP MTK_M4U_DOM_ID(5, 1) -#define M4U_PORT_L5_VDEC_LAT0_AVC_MV_EXT_DISP MTK_M4U_DOM_ID(5, 2) -#define M4U_PORT_L5_VDEC_LAT0_PRED_RD_EXT_DISP MTK_M4U_DOM_ID(5, 3) -#define M4U_PORT_L5_VDEC_LAT0_TILE_EXT_DISP MTK_M4U_DOM_ID(5, 4) -#define M4U_PORT_L5_VDEC_LAT0_WDMA_EXT_DISP MTK_M4U_DOM_ID(5, 5) -#define M4U_PORT_L5_VDEC_LAT0_RG_CTRL_DMA_EXT_DISP MTK_M4U_DOM_ID(5, 6) -#define M4U_PORT_L5_VDEC_UFO_ENC_EXT_DISP MTK_M4U_DOM_ID(5, 7) - -/* larb6: null */ - -/* larb7 */ -#define M4U_PORT_L7_VENC_RCPU_DISP MTK_M4U_DOM_ID(7, 0) -#define M4U_PORT_L7_VENC_REC_DISP MTK_M4U_DOM_ID(7, 1) -#define M4U_PORT_L7_VENC_BSDMA_DISP MTK_M4U_DOM_ID(7, 2) -#define M4U_PORT_L7_VENC_SV_COMV_DISP MTK_M4U_DOM_ID(7, 3) -#define M4U_PORT_L7_VENC_RD_COMV_DISP MTK_M4U_DOM_ID(7, 4) -#define M4U_PORT_L7_VENC_NBM_RDMA_DISP MTK_M4U_DOM_ID(7, 5) -#define M4U_PORT_L7_VENC_NBM_RDMA_LITE_DISP MTK_M4U_DOM_ID(7, 6) -#define M4U_PORT_L7_JPGENC_Y_RDMA_DISP MTK_M4U_DOM_ID(7, 7) -#define M4U_PORT_L7_JPGENC_C_RDMA_DISP MTK_M4U_DOM_ID(7, 8) -#define M4U_PORT_L7_JPGENC_Q_TABLE_DISP MTK_M4U_DOM_ID(7, 9) -#define M4U_PORT_L7_JPGENC_BSDMA_DISP MTK_M4U_DOM_ID(7, 10) -#define M4U_PORT_L7_JPGENC_WDMA0_DISP MTK_M4U_DOM_ID(7, 11) -#define M4U_PORT_L7_JPGENC_BSDMA0_DISP MTK_M4U_DOM_ID(7, 12) -#define M4U_PORT_L7_VENC_NBM_WDMA_DISP MTK_M4U_DOM_ID(7, 13) -#define M4U_PORT_L7_VENC_NBM_WDMA_LITE_DISP MTK_M4U_DOM_ID(7, 14) -#define M4U_PORT_L7_VENC_CUR_LUMA_DISP MTK_M4U_DOM_ID(7, 15) -#define M4U_PORT_L7_VENC_CUR_CHROMA_DISP MTK_M4U_DOM_ID(7, 16) -#define M4U_PORT_L7_VENC_REF_LUMA_DISP MTK_M4U_DOM_ID(7, 17) -#define M4U_PORT_L7_VENC_REF_CHROMA_DISP MTK_M4U_DOM_ID(7, 18) -#define M4U_PORT_L7_VENC_SUB_R_LUMA_DISP MTK_M4U_DOM_ID(7, 19) -#define M4U_PORT_L7_VENC_SUB_W_LUMA_DISP MTK_M4U_DOM_ID(7, 20) -#define M4U_PORT_L7_VENC_FCS_NBM_RDMA_DISP MTK_M4U_DOM_ID(7, 21) -#define M4U_PORT_L7_VENC_FCS_NBM_WDMA_DISP MTK_M4U_DOM_ID(7, 22) -#define M4U_PORT_L7_JPGENC_WDMA1_DISP MTK_M4U_DOM_ID(7, 23) -#define M4U_PORT_L7_JPGENC_BSDMA1_DISP MTK_M4U_DOM_ID(7, 24) -#define M4U_PORT_L7_JPGENC_HUFF_OFFSET1_DISP MTK_M4U_DOM_ID(7, 25) -#define M4U_PORT_L7_JPGENC_HUFF_OFFSET0_DISP MTK_M4U_DOM_ID(7, 26) - -/* larb8: null */ - -/* larb9 */ -#define M4U_PORT_L9_IMG_IMGI_D1_MDP MTK_M4U_DOM_ID(9, 0) -#define M4U_PORT_L9_IMG_IMGBI_D1_MDP MTK_M4U_DOM_ID(9, 1) -#define M4U_PORT_L9_IMG_DMGI_D1_MDP MTK_M4U_DOM_ID(9, 2) -#define M4U_PORT_L9_IMG_DEPI_D1_MDP MTK_M4U_DOM_ID(9, 3) -#define M4U_PORT_L9_IMG_ICE_D1_MDP MTK_M4U_DOM_ID(9, 4) -#define M4U_PORT_L9_IMG_SMTI_D1_MDP MTK_M4U_DOM_ID(9, 5) -#define M4U_PORT_L9_IMG_SMTO_D2_MDP MTK_M4U_DOM_ID(9, 6) -#define M4U_PORT_L9_IMG_SMTO_D1_MDP MTK_M4U_DOM_ID(9, 7) -#define M4U_PORT_L9_IMG_CRZO_D1_MDP MTK_M4U_DOM_ID(9, 8) -#define M4U_PORT_L9_IMG_IMG3O_D1_MDP MTK_M4U_DOM_ID(9, 9) -#define M4U_PORT_L9_IMG_VIPI_D1_MDP MTK_M4U_DOM_ID(9, 10) -#define M4U_PORT_L9_IMG_SMTI_D5_MDP MTK_M4U_DOM_ID(9, 11) -#define M4U_PORT_L9_IMG_TIMGO_D1_MDP MTK_M4U_DOM_ID(9, 12) -#define M4U_PORT_L9_IMG_UFBC_W0_MDP MTK_M4U_DOM_ID(9, 13) -#define M4U_PORT_L9_IMG_UFBC_R0_MDP MTK_M4U_DOM_ID(9, 14) -#define M4U_PORT_L9_IMG_WPE_RDMA1_MDP MTK_M4U_DOM_ID(9, 15) -#define M4U_PORT_L9_IMG_WPE_RDMA0_MDP MTK_M4U_DOM_ID(9, 16) -#define M4U_PORT_L9_IMG_WPE_WDMA_MDP MTK_M4U_DOM_ID(9, 17) -#define M4U_PORT_L9_IMG_MFB_RDMA0_MDP MTK_M4U_DOM_ID(9, 18) -#define M4U_PORT_L9_IMG_MFB_RDMA1_MDP MTK_M4U_DOM_ID(9, 19) -#define M4U_PORT_L9_IMG_MFB_RDMA2_MDP MTK_M4U_DOM_ID(9, 20) -#define M4U_PORT_L9_IMG_MFB_RDMA3_MDP MTK_M4U_DOM_ID(9, 21) -#define M4U_PORT_L9_IMG_MFB_RDMA4_MDP MTK_M4U_DOM_ID(9, 22) -#define M4U_PORT_L9_IMG_MFB_RDMA5_MDP MTK_M4U_DOM_ID(9, 23) -#define M4U_PORT_L9_IMG_MFB_WDMA0_MDP MTK_M4U_DOM_ID(9, 24) -#define M4U_PORT_L9_IMG_MFB_WDMA1_MDP MTK_M4U_DOM_ID(9, 25) -#define M4U_PORT_L9_IMG_RESERVE6_MDP MTK_M4U_DOM_ID(9, 26) -#define M4U_PORT_L9_IMG_RESERVE7_MDP MTK_M4U_DOM_ID(9, 27) -#define M4U_PORT_L9_IMG_RESERVE8_MDP MTK_M4U_DOM_ID(9, 28) - -/* larb10: null */ - -/* larb11 */ -#define M4U_PORT_L11_IMG_IMGI_D1_DISP MTK_M4U_DOM_ID(11, 0) -#define M4U_PORT_L11_IMG_IMGBI_D1_DISP MTK_M4U_DOM_ID(11, 1) -#define M4U_PORT_L11_IMG_DMGI_D1_DISP MTK_M4U_DOM_ID(11, 2) -#define M4U_PORT_L11_IMG_DEPI_D1_DISP MTK_M4U_DOM_ID(11, 3) -#define M4U_PORT_L11_IMG_ICE_D1_DISP MTK_M4U_DOM_ID(11, 4) -#define M4U_PORT_L11_IMG_SMTI_D1_DISP MTK_M4U_DOM_ID(11, 5) -#define M4U_PORT_L11_IMG_SMTO_D2_DISP MTK_M4U_DOM_ID(11, 6) -#define M4U_PORT_L11_IMG_SMTO_D1_DISP MTK_M4U_DOM_ID(11, 7) -#define M4U_PORT_L11_IMG_CRZO_D1_DISP MTK_M4U_DOM_ID(11, 8) -#define M4U_PORT_L11_IMG_IMG3O_D1_DISP MTK_M4U_DOM_ID(11, 9) -#define M4U_PORT_L11_IMG_VIPI_D1_DISP MTK_M4U_DOM_ID(11, 10) -#define M4U_PORT_L11_IMG_SMTI_D5_DISP MTK_M4U_DOM_ID(11, 11) -#define M4U_PORT_L11_IMG_TIMGO_D1_DISP MTK_M4U_DOM_ID(11, 12) -#define M4U_PORT_L11_IMG_UFBC_W0_DISP MTK_M4U_DOM_ID(11, 13) -#define M4U_PORT_L11_IMG_UFBC_R0_DISP MTK_M4U_DOM_ID(11, 14) -#define M4U_PORT_L11_IMG_WPE_RDMA1_DISP MTK_M4U_DOM_ID(11, 15) -#define M4U_PORT_L11_IMG_WPE_RDMA0_DISP MTK_M4U_DOM_ID(11, 16) -#define M4U_PORT_L11_IMG_WPE_WDMA_DISP MTK_M4U_DOM_ID(11, 17) -#define M4U_PORT_L11_IMG_MFB_RDMA0_DISP MTK_M4U_DOM_ID(11, 18) -#define M4U_PORT_L11_IMG_MFB_RDMA1_DISP MTK_M4U_DOM_ID(11, 19) -#define M4U_PORT_L11_IMG_MFB_RDMA2_DISP MTK_M4U_DOM_ID(11, 20) -#define M4U_PORT_L11_IMG_MFB_RDMA3_DISP MTK_M4U_DOM_ID(11, 21) -#define M4U_PORT_L11_IMG_MFB_RDMA4_DISP MTK_M4U_DOM_ID(11, 22) -#define M4U_PORT_L11_IMG_MFB_RDMA5_DISP MTK_M4U_DOM_ID(11, 23) -#define M4U_PORT_L11_IMG_MFB_WDMA0_DISP MTK_M4U_DOM_ID(11, 24) -#define M4U_PORT_L11_IMG_MFB_WDMA1_DISP MTK_M4U_DOM_ID(11, 25) -#define M4U_PORT_L11_IMG_RESERVE6_DISP MTK_M4U_DOM_ID(11, 26) -#define M4U_PORT_L11_IMG_RESERVE7_DISP MTK_M4U_DOM_ID(11, 27) -#define M4U_PORT_L11_IMG_RESERVE8_DISP MTK_M4U_DOM_ID(11, 28) - -/* larb12: null */ - -/* larb13 */ -#define M4U_PORT_L13_CAM_MRAWI_MDP MTK_M4U_DOM_ID(13, 0) -#define M4U_PORT_L13_CAM_MRAWO0_MDP MTK_M4U_DOM_ID(13, 1) -#define M4U_PORT_L13_CAM_MRAWO1_MDP MTK_M4U_DOM_ID(13, 2) -#define M4U_PORT_L13_CAM_CAMSV1_MDP MTK_M4U_DOM_ID(13, 3) -#define M4U_PORT_L13_CAM_CAMSV2_MDP MTK_M4U_DOM_ID(13, 4) -#define M4U_PORT_L13_CAM_CAMSV3_MDP MTK_M4U_DOM_ID(13, 5) -#define M4U_PORT_L13_CAM_CAMSV4_MDP MTK_M4U_DOM_ID(13, 6) -#define M4U_PORT_L13_CAM_CAMSV5_MDP MTK_M4U_DOM_ID(13, 7) -#define M4U_PORT_L13_CAM_CAMSV6_MDP MTK_M4U_DOM_ID(13, 8) -#define M4U_PORT_L13_CAM_CCUI_MDP MTK_M4U_DOM_ID(13, 9) -#define M4U_PORT_L13_CAM_CCUO_MDP MTK_M4U_DOM_ID(13, 10) -#define M4U_PORT_L13_CAM_FAKE_MDP MTK_M4U_DOM_ID(13, 11) - -/* larb14 */ -#define M4U_PORT_L14_CAM_MRAWI_DISP MTK_M4U_DOM_ID(14, 0) -#define M4U_PORT_L14_CAM_MRAWO0_DISP MTK_M4U_DOM_ID(14, 1) -#define M4U_PORT_L14_CAM_MRAWO1_DISP MTK_M4U_DOM_ID(14, 2) -#define M4U_PORT_L14_CAM_CAMSV0_DISP MTK_M4U_DOM_ID(14, 3) -#define M4U_PORT_L14_CAM_CCUI_DISP MTK_M4U_DOM_ID(14, 4) -#define M4U_PORT_L14_CAM_CCUO_DISP MTK_M4U_DOM_ID(14, 5) - -/* larb15: null */ - -/* larb16 */ -#define M4U_PORT_L16_CAM_IMGO_R1_A_MDP MTK_M4U_DOM_ID(16, 0) -#define M4U_PORT_L16_CAM_RRZO_R1_A_MDP MTK_M4U_DOM_ID(16, 1) -#define M4U_PORT_L16_CAM_CQI_R1_A_MDP MTK_M4U_DOM_ID(16, 2) -#define M4U_PORT_L16_CAM_BPCI_R1_A_MDP MTK_M4U_DOM_ID(16, 3) -#define M4U_PORT_L16_CAM_YUVO_R1_A_MDP MTK_M4U_DOM_ID(16, 4) -#define M4U_PORT_L16_CAM_UFDI_R2_A_MDP MTK_M4U_DOM_ID(16, 5) -#define M4U_PORT_L16_CAM_RAWI_R2_A_MDP MTK_M4U_DOM_ID(16, 6) -#define M4U_PORT_L16_CAM_RAWI_R3_A_MDP MTK_M4U_DOM_ID(16, 7) -#define M4U_PORT_L16_CAM_AAO_R1_A_MDP MTK_M4U_DOM_ID(16, 8) -#define M4U_PORT_L16_CAM_AFO_R1_A_MDP MTK_M4U_DOM_ID(16, 9) -#define M4U_PORT_L16_CAM_FLKO_R1_A_MDP MTK_M4U_DOM_ID(16, 10) -#define M4U_PORT_L16_CAM_LCESO_R1_A_MDP MTK_M4U_DOM_ID(16, 11) -#define M4U_PORT_L16_CAM_CRZO_R1_A_MDP MTK_M4U_DOM_ID(16, 12) -#define M4U_PORT_L16_CAM_LTMSO_R1_A_MDP MTK_M4U_DOM_ID(16, 13) -#define M4U_PORT_L16_CAM_RSSO_R1_A_MDP MTK_M4U_DOM_ID(16, 14) -#define M4U_PORT_L16_CAM_AAHO_R1_A_MDP MTK_M4U_DOM_ID(16, 15) -#define M4U_PORT_L16_CAM_LSCI_R1_A_MDP MTK_M4U_DOM_ID(16, 16) - -/* larb17 */ -#define M4U_PORT_L17_CAM_IMGO_R1_B_DISP MTK_M4U_DOM_ID(17, 0) -#define M4U_PORT_L17_CAM_RRZO_R1_B_DISP MTK_M4U_DOM_ID(17, 1) -#define M4U_PORT_L17_CAM_CQI_R1_B_DISP MTK_M4U_DOM_ID(17, 2) -#define M4U_PORT_L17_CAM_BPCI_R1_B_DISP MTK_M4U_DOM_ID(17, 3) -#define M4U_PORT_L17_CAM_YUVO_R1_B_DISP MTK_M4U_DOM_ID(17, 4) -#define M4U_PORT_L17_CAM_UFDI_R2_B_DISP MTK_M4U_DOM_ID(17, 5) -#define M4U_PORT_L17_CAM_RAWI_R2_B_DISP MTK_M4U_DOM_ID(17, 6) -#define M4U_PORT_L17_CAM_RAWI_R3_B_DISP MTK_M4U_DOM_ID(17, 7) -#define M4U_PORT_L17_CAM_AAO_R1_B_DISP MTK_M4U_DOM_ID(17, 8) -#define M4U_PORT_L17_CAM_AFO_R1_B_DISP MTK_M4U_DOM_ID(17, 9) -#define M4U_PORT_L17_CAM_FLKO_R1_B_DISP MTK_M4U_DOM_ID(17, 10) -#define M4U_PORT_L17_CAM_LCESO_R1_B_DISP MTK_M4U_DOM_ID(17, 11) -#define M4U_PORT_L17_CAM_CRZO_R1_B_DISP MTK_M4U_DOM_ID(17, 12) -#define M4U_PORT_L17_CAM_LTMSO_R1_B_DISP MTK_M4U_DOM_ID(17, 13) -#define M4U_PORT_L17_CAM_RSSO_R1_B_DISP MTK_M4U_DOM_ID(17, 14) -#define M4U_PORT_L17_CAM_AAHO_R1_B_DISP MTK_M4U_DOM_ID(17, 15) -#define M4U_PORT_L17_CAM_LSCI_R1_B_DISP MTK_M4U_DOM_ID(17, 16) - -/* larb18 */ -#define M4U_PORT_L18_CAM_IMGO_R1_C_MDP MTK_M4U_DOM_ID(18, 0) -#define M4U_PORT_L18_CAM_RRZO_R1_C_MDP MTK_M4U_DOM_ID(18, 1) -#define M4U_PORT_L18_CAM_CQI_R1_C_MDP MTK_M4U_DOM_ID(18, 2) -#define M4U_PORT_L18_CAM_BPCI_R1_C_MDP MTK_M4U_DOM_ID(18, 3) -#define M4U_PORT_L18_CAM_YUVO_R1_C_MDP MTK_M4U_DOM_ID(18, 4) -#define M4U_PORT_L18_CAM_UFDI_R2_C_MDP MTK_M4U_DOM_ID(18, 5) -#define M4U_PORT_L18_CAM_RAWI_R2_C_MDP MTK_M4U_DOM_ID(18, 6) -#define M4U_PORT_L18_CAM_RAWI_R3_C_MDP MTK_M4U_DOM_ID(18, 7) -#define M4U_PORT_L18_CAM_AAO_R1_C_MDP MTK_M4U_DOM_ID(18, 8) -#define M4U_PORT_L18_CAM_AFO_R1_C_MDP MTK_M4U_DOM_ID(18, 9) -#define M4U_PORT_L18_CAM_FLKO_R1_C_MDP MTK_M4U_DOM_ID(18, 10) -#define M4U_PORT_L18_CAM_LCESO_R1_C_MDP MTK_M4U_DOM_ID(18, 11) -#define M4U_PORT_L18_CAM_CRZO_R1_C_MDP MTK_M4U_DOM_ID(18, 12) -#define M4U_PORT_L18_CAM_LTMSO_R1_C_MDP MTK_M4U_DOM_ID(18, 13) -#define M4U_PORT_L18_CAM_RSSO_R1_C_MDP MTK_M4U_DOM_ID(18, 14) -#define M4U_PORT_L18_CAM_AAHO_R1_C_MDP MTK_M4U_DOM_ID(18, 15) -#define M4U_PORT_L18_CAM_LSCI_R1_C_MDP MTK_M4U_DOM_ID(18, 16) - -/* larb19 */ -#define M4U_PORT_L19_IPE_DVS_RDMA_DISP MTK_M4U_DOM_ID(19, 0) -#define M4U_PORT_L19_IPE_DVS_WDMA_DISP MTK_M4U_DOM_ID(19, 1) -#define M4U_PORT_L19_IPE_DVP_RDMA_DISP MTK_M4U_DOM_ID(19, 2) -#define M4U_PORT_L19_IPE_DVP_WDMA_DISP MTK_M4U_DOM_ID(19, 3) - -/* larb20 */ -#define M4U_PORT_L20_IPE_FDVT_RDA_DISP MTK_M4U_DOM_ID(20, 0) -#define M4U_PORT_L20_IPE_FDVT_RDB_DISP MTK_M4U_DOM_ID(20, 1) -#define M4U_PORT_L20_IPE_FDVT_WRA_DISP MTK_M4U_DOM_ID(20, 2) -#define M4U_PORT_L20_IPE_FDVT_WRB_DISP MTK_M4U_DOM_ID(20, 3) -#define M4U_PORT_L20_IPE_RSC_RDMA0_DISP MTK_M4U_DOM_ID(20, 4) -#define M4U_PORT_L20_IPE_RSC_WDMA_DISP MTK_M4U_DOM_ID(20, 5) - -#endif diff --git a/include/dt-bindings/memory/mediatek,mt8188-memory-port.h b/include/dt-bindings/memory/mediatek,mt8188-memory-port.h deleted file mode 100644 index 337ab11262a..00000000000 --- a/include/dt-bindings/memory/mediatek,mt8188-memory-port.h +++ /dev/null @@ -1,489 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ -/* - * Copyright (c) 2022 MediaTek Inc. - * Author: Chengci Xu <chengci.xu@mediatek.com> - */ -#ifndef _DT_BINDINGS_MEMORY_MEDIATEK_MT8188_LARB_PORT_H_ -#define _DT_BINDINGS_MEMORY_MEDIATEK_MT8188_LARB_PORT_H_ - -#include <dt-bindings/memory/mtk-memory-port.h> - -/* - * MM IOMMU larbs: - * From below, for example larb11 has larb11a/larb11b/larb11c, - * the index of larb is not in order. So we reindexed these larbs from a - * software view. - */ -#define SMI_L0_ID 0 -#define SMI_L1_ID 1 -#define SMI_L2_ID 2 -#define SMI_L3_ID 3 -#define SMI_L4_ID 4 -#define SMI_L5_ID 5 -#define SMI_L6_ID 6 -#define SMI_L7_ID 7 -#define SMI_L9_ID 8 -#define SMI_L10_ID 9 -#define SMI_L11A_ID 10 -#define SMI_L11B_ID 11 -#define SMI_L11C_ID 12 -#define SMI_L12_ID 13 -#define SMI_L13_ID 14 -#define SMI_L14_ID 15 -#define SMI_L15_ID 16 -#define SMI_L16A_ID 17 -#define SMI_L16B_ID 18 -#define SMI_L17A_ID 19 -#define SMI_L17B_ID 20 -#define SMI_L19_ID 21 -#define SMI_L21_ID 22 -#define SMI_L23_ID 23 -#define SMI_L27_ID 24 -#define SMI_L28_ID 25 - -/* - * MM IOMMU supports 16GB dma address. We separate it to four ranges: - * 0 ~ 4G; 4G ~ 8G; 8G ~ 12G; 12G ~ 16G, we could adjust these masters - * locate in anyone region. BUT: - * a) Make sure all the ports inside a larb are in one range. - * b) The iova of any master can NOT cross the 4G/8G/12G boundary. - * - * This is the suggested mapping in this SoC: - * - * modules dma-address-region larbs-ports - * disp 0 ~ 4G larb0/1/2/3 - * vcodec 4G ~ 8G larb19(21)[1]/21(22)/23 - * cam/mdp 8G ~ 12G the other larbs. - * N/A 12G ~ 16G - * CCU0 0x24000_0000 ~ 0x243ff_ffff larb27(24): port 0/1 - * CCU1 0x24400_0000 ~ 0x247ff_ffff larb27(24): port 2/3 - * - * This SoC have two MM IOMMU HWs, this is the connected information: - * iommu-vdo: larb0/2/5/9/10/11A/11C/13/16B/17B/19/21 - * iommu-vpp: larb1/3/4/6/7/11B/12/14/15/16A/17A/23/27 - * - * [1]: This is larb19, but the index is 21 from the SW view. - */ - -/* MM IOMMU ports */ -/* LARB 0 -- VDO-0 */ -#define M4U_PORT_L0_DISP_RDMA1 MTK_M4U_ID(SMI_L0_ID, 0) -#define M4U_PORT_L0_DISP_WDMA0 MTK_M4U_ID(SMI_L0_ID, 1) -#define M4U_PORT_L0_DISP_OVL0_RDMA0 MTK_M4U_ID(SMI_L0_ID, 2) -#define M4U_PORT_L0_DISP_OVL0_RDMA1 MTK_M4U_ID(SMI_L0_ID, 3) -#define M4U_PORT_L0_DISP_OVL0_HDR MTK_M4U_ID(SMI_L0_ID, 4) -#define M4U_PORT_L0_DISP_POSTMASK0 MTK_M4U_ID(SMI_L0_ID, 5) -#define M4U_PORT_L0_DISP_FAKE_ENG0 MTK_M4U_ID(SMI_L0_ID, 6) - -/* LARB 1 -- VD0-0 */ -#define M4U_PORT_L1_DISP_RDMA0 MTK_M4U_ID(SMI_L1_ID, 0) -#define M4U_PORT_L1_DISP_WDMA1 MTK_M4U_ID(SMI_L1_ID, 1) -#define M4U_PORT_L1_DISP_OVL1_RDMA0 MTK_M4U_ID(SMI_L1_ID, 2) -#define M4U_PORT_L1_DISP_OVL1_RDMA1 MTK_M4U_ID(SMI_L1_ID, 3) -#define M4U_PORT_L1_DISP_OVL1_HDR MTK_M4U_ID(SMI_L1_ID, 4) -#define M4U_PORT_L1_DISP_WROT0 MTK_M4U_ID(SMI_L1_ID, 5) -#define M4U_PORT_L1_DISP_FAKE_ENG1 MTK_M4U_ID(SMI_L1_ID, 6) - -/* LARB 2 -- VDO-1 */ -#define M4U_PORT_L2_MDP_RDMA0 MTK_M4U_ID(SMI_L2_ID, 0) -#define M4U_PORT_L2_MDP_RDMA2 MTK_M4U_ID(SMI_L2_ID, 1) -#define M4U_PORT_L2_MDP_RDMA4 MTK_M4U_ID(SMI_L2_ID, 2) -#define M4U_PORT_L2_MDP_RDMA6 MTK_M4U_ID(SMI_L2_ID, 3) -#define M4U_PORT_L2_DISP_FAKE1 MTK_M4U_ID(SMI_L2_ID, 4) - -/* LARB 3 -- VDO-1 */ -#define M4U_PORT_L3_MDP_RDMA1 MTK_M4U_ID(SMI_L3_ID, 0) -#define M4U_PORT_L3_MDP_RDMA3 MTK_M4U_ID(SMI_L3_ID, 1) -#define M4U_PORT_L3_MDP_RDMA5 MTK_M4U_ID(SMI_L3_ID, 2) -#define M4U_PORT_L3_MDP_RDMA7 MTK_M4U_ID(SMI_L3_ID, 3) -#define M4U_PORT_L3_HDR_DS_SMI MTK_M4U_ID(SMI_L3_ID, 4) -#define M4U_PORT_L3_HDR_ADL_SMI MTK_M4U_ID(SMI_L3_ID, 5) -#define M4U_PORT_L3_DISP_FAKE1 MTK_M4U_ID(SMI_L3_ID, 6) - -/* LARB 4 -- VPP-0 */ -#define M4U_PORT_L4_MDP_RDMA MTK_M4U_ID(SMI_L4_ID, 0) -#define M4U_PORT_L4_MDP_FG MTK_M4U_ID(SMI_L4_ID, 1) -#define M4U_PORT_L4_MDP_OVL MTK_M4U_ID(SMI_L4_ID, 2) -#define M4U_PORT_L4_MDP_WROT MTK_M4U_ID(SMI_L4_ID, 3) -#define M4U_PORT_L4_FAKE_ENG MTK_M4U_ID(SMI_L4_ID, 4) -#define M4U_PORT_L4_DISP_RDMA MTK_M4U_ID(SMI_L4_ID, 5) -#define M4U_PORT_L4_DISP_WDMA MTK_M4U_ID(SMI_L4_ID, 6) - -/* LARB 5 -- VPP-1 */ -#define M4U_PORT_L5_SVPP1_MDP_RDMA MTK_M4U_ID(SMI_L5_ID, 0) -#define M4U_PORT_L5_SVPP1_MDP_FG MTK_M4U_ID(SMI_L5_ID, 1) -#define M4U_PORT_L5_SVPP1_MDP_OVL MTK_M4U_ID(SMI_L5_ID, 2) -#define M4U_PORT_L5_SVPP1_MDP_WROT MTK_M4U_ID(SMI_L5_ID, 3) -#define M4U_PORT_L5_SVPP2_MDP_RDMA MTK_M4U_ID(SMI_L5_ID, 4) -#define M4U_PORT_L5_SVPP2_MDP_FG MTK_M4U_ID(SMI_L5_ID, 5) -#define M4U_PORT_L5_SVPP2_MDP_WROT MTK_M4U_ID(SMI_L5_ID, 6) -#define M4U_PORT_L5_LARB5_FAKE_ENG MTK_M4U_ID(SMI_L5_ID, 7) - -/* LARB 6 -- VPP-1 */ -#define M4U_PORT_L6_SVPP3_MDP_RDMA MTK_M4U_ID(SMI_L6_ID, 0) -#define M4U_PORT_L6_SVPP3_MDP_FG MTK_M4U_ID(SMI_L6_ID, 1) -#define M4U_PORT_L6_SVPP3_MDP_WROT MTK_M4U_ID(SMI_L6_ID, 2) -#define M4U_PORT_L6_LARB6_FAKE_ENG MTK_M4U_ID(SMI_L6_ID, 3) - -/* LARB 7 -- WPE */ -#define M4U_PORT_L7_WPE_RDMA_0 MTK_M4U_ID(SMI_L7_ID, 0) -#define M4U_PORT_L7_WPE_RDMA_1 MTK_M4U_ID(SMI_L7_ID, 1) -#define M4U_PORT_L7_WPE_WDMA_0 MTK_M4U_ID(SMI_L7_ID, 2) - -/* LARB 9 -- IMG-M */ -#define M4U_PORT_L9_IMGI_T1_A MTK_M4U_ID(SMI_L9_ID, 0) -#define M4U_PORT_L9_UFDI_T1_A MTK_M4U_ID(SMI_L9_ID, 1) -#define M4U_PORT_L9_IMGBI_T1_A MTK_M4U_ID(SMI_L9_ID, 2) -#define M4U_PORT_L9_IMGCI_T1_A MTK_M4U_ID(SMI_L9_ID, 3) -#define M4U_PORT_L9_SMTI_T1_A MTK_M4U_ID(SMI_L9_ID, 4) -#define M4U_PORT_L9_SMTI_T4_A MTK_M4U_ID(SMI_L9_ID, 5) -#define M4U_PORT_L9_TNCSTI_T1_A MTK_M4U_ID(SMI_L9_ID, 6) -#define M4U_PORT_L9_TNCSTI_T4_A MTK_M4U_ID(SMI_L9_ID, 7) -#define M4U_PORT_L9_YUVO_T1_A MTK_M4U_ID(SMI_L9_ID, 8) -#define M4U_PORT_L9_YUVBO_T1_A MTK_M4U_ID(SMI_L9_ID, 9) -#define M4U_PORT_L9_YUVCO_T1_A MTK_M4U_ID(SMI_L9_ID, 10) -#define M4U_PORT_L9_TIMGO_T1_A MTK_M4U_ID(SMI_L9_ID, 11) -#define M4U_PORT_L9_YUVO_T2_A MTK_M4U_ID(SMI_L9_ID, 12) -#define M4U_PORT_L9_YUVO_T5_A MTK_M4U_ID(SMI_L9_ID, 13) -#define M4U_PORT_L9_IMGI_T1_B MTK_M4U_ID(SMI_L9_ID, 14) -#define M4U_PORT_L9_IMGBI_T1_B MTK_M4U_ID(SMI_L9_ID, 15) -#define M4U_PORT_L9_IMGCI_T1_B MTK_M4U_ID(SMI_L9_ID, 16) -#define M4U_PORT_L9_SMTI_T4_B MTK_M4U_ID(SMI_L9_ID, 17) -#define M4U_PORT_L9_TNCSO_T1_A MTK_M4U_ID(SMI_L9_ID, 18) -#define M4U_PORT_L9_SMTO_T1_A MTK_M4U_ID(SMI_L9_ID, 19) -#define M4U_PORT_L9_SMTO_T4_A MTK_M4U_ID(SMI_L9_ID, 20) -#define M4U_PORT_L9_TNCSTO_T1_A MTK_M4U_ID(SMI_L9_ID, 21) -#define M4U_PORT_L9_YUVO_T2_B MTK_M4U_ID(SMI_L9_ID, 22) -#define M4U_PORT_L9_YUVO_T5_B MTK_M4U_ID(SMI_L9_ID, 23) -#define M4U_PORT_L9_SMTO_T4_B MTK_M4U_ID(SMI_L9_ID, 24) - -/* LARB 10 -- IMG-D */ -#define M4U_PORT_L10_IMGI_D1 MTK_M4U_ID(SMI_L10_ID, 0) -#define M4U_PORT_L10_IMGBI_D1 MTK_M4U_ID(SMI_L10_ID, 1) -#define M4U_PORT_L10_IMGCI_D1 MTK_M4U_ID(SMI_L10_ID, 2) -#define M4U_PORT_L10_IMGDI_D1 MTK_M4U_ID(SMI_L10_ID, 3) -#define M4U_PORT_L10_DEPI_D1 MTK_M4U_ID(SMI_L10_ID, 4) -#define M4U_PORT_L10_DMGI_D1 MTK_M4U_ID(SMI_L10_ID, 5) -#define M4U_PORT_L10_SMTI_D1 MTK_M4U_ID(SMI_L10_ID, 6) -#define M4U_PORT_L10_RECI_D1 MTK_M4U_ID(SMI_L10_ID, 7) -#define M4U_PORT_L10_RECI_D1_N MTK_M4U_ID(SMI_L10_ID, 8) -#define M4U_PORT_L10_TNRWI_D1 MTK_M4U_ID(SMI_L10_ID, 9) -#define M4U_PORT_L10_TNRCI_D1 MTK_M4U_ID(SMI_L10_ID, 10) -#define M4U_PORT_L10_TNRCI_D1_N MTK_M4U_ID(SMI_L10_ID, 11) -#define M4U_PORT_L10_IMG4O_D1 MTK_M4U_ID(SMI_L10_ID, 12) -#define M4U_PORT_L10_IMG4BO_D1 MTK_M4U_ID(SMI_L10_ID, 13) -#define M4U_PORT_L10_SMTI_D8 MTK_M4U_ID(SMI_L10_ID, 14) -#define M4U_PORT_L10_SMTO_D1 MTK_M4U_ID(SMI_L10_ID, 15) -#define M4U_PORT_L10_TNRMO_D1 MTK_M4U_ID(SMI_L10_ID, 16) -#define M4U_PORT_L10_TNRMO_D1_N MTK_M4U_ID(SMI_L10_ID, 17) -#define M4U_PORT_L10_SMTO_D8 MTK_M4U_ID(SMI_L10_ID, 18) -#define M4U_PORT_L10_DBGO_D1 MTK_M4U_ID(SMI_L10_ID, 19) - -/* LARB 11A -- IMG-D */ -#define M4U_PORT_L11A_WPE_RDMA_0 MTK_M4U_ID(SMI_L11A_ID, 0) -#define M4U_PORT_L11A_WPE_RDMA_1 MTK_M4U_ID(SMI_L11A_ID, 1) -#define M4U_PORT_L11A_WPE_RDMA_4P_0 MTK_M4U_ID(SMI_L11A_ID, 2) -#define M4U_PORT_L11A_WPE_RDMA_4P_1 MTK_M4U_ID(SMI_L11A_ID, 3) -#define M4U_PORT_L11A_WPE_CQ0 MTK_M4U_ID(SMI_L11A_ID, 4) -#define M4U_PORT_L11A_WPE_CQ1 MTK_M4U_ID(SMI_L11A_ID, 5) -#define M4U_PORT_L11A_PIMGI_P1 MTK_M4U_ID(SMI_L11A_ID, 6) -#define M4U_PORT_L11A_PIMGBI_P1 MTK_M4U_ID(SMI_L11A_ID, 7) -#define M4U_PORT_L11A_PIMGCI_P1 MTK_M4U_ID(SMI_L11A_ID, 8) -#define M4U_PORT_L11A_IMGI_T1_C MTK_M4U_ID(SMI_L11A_ID, 9) -#define M4U_PORT_L11A_IMGBI_T1_C MTK_M4U_ID(SMI_L11A_ID, 10) -#define M4U_PORT_L11A_IMGCI_T1_C MTK_M4U_ID(SMI_L11A_ID, 11) -#define M4U_PORT_L11A_SMTI_T1_C MTK_M4U_ID(SMI_L11A_ID, 12) -#define M4U_PORT_L11A_SMTI_T4_C MTK_M4U_ID(SMI_L11A_ID, 13) -#define M4U_PORT_L11A_SMTI_T6_C MTK_M4U_ID(SMI_L11A_ID, 14) -#define M4U_PORT_L11A_YUVO_T1_C MTK_M4U_ID(SMI_L11A_ID, 15) -#define M4U_PORT_L11A_YUVBO_T1_C MTK_M4U_ID(SMI_L11A_ID, 16) -#define M4U_PORT_L11A_YUVCO_T1_C MTK_M4U_ID(SMI_L11A_ID, 17) -#define M4U_PORT_L11A_WPE_WDMA_0 MTK_M4U_ID(SMI_L11A_ID, 18) -#define M4U_PORT_L11A_WPE_WDMA_4P_0 MTK_M4U_ID(SMI_L11A_ID, 19) -#define M4U_PORT_L11A_WROT_P1 MTK_M4U_ID(SMI_L11A_ID, 20) -#define M4U_PORT_L11A_TCCSO_P1 MTK_M4U_ID(SMI_L11A_ID, 21) -#define M4U_PORT_L11A_TCCSI_P1 MTK_M4U_ID(SMI_L11A_ID, 22) -#define M4U_PORT_L11A_TIMGO_T1_C MTK_M4U_ID(SMI_L11A_ID, 23) -#define M4U_PORT_L11A_YUVO_T2_C MTK_M4U_ID(SMI_L11A_ID, 24) -#define M4U_PORT_L11A_YUVO_T5_C MTK_M4U_ID(SMI_L11A_ID, 25) -#define M4U_PORT_L11A_SMTO_T1_C MTK_M4U_ID(SMI_L11A_ID, 26) -#define M4U_PORT_L11A_SMTO_T4_C MTK_M4U_ID(SMI_L11A_ID, 27) -#define M4U_PORT_L11A_SMTO_T6_C MTK_M4U_ID(SMI_L11A_ID, 28) -#define M4U_PORT_L11A_DBGO_T1_C MTK_M4U_ID(SMI_L11A_ID, 29) - -/* LARB 11B -- IMG-D */ -#define M4U_PORT_L11B_WPE_RDMA_0 MTK_M4U_ID(SMI_L11B_ID, 0) -#define M4U_PORT_L11B_WPE_RDMA_1 MTK_M4U_ID(SMI_L11B_ID, 1) -#define M4U_PORT_L11B_WPE_RDMA_4P_0 MTK_M4U_ID(SMI_L11B_ID, 2) -#define M4U_PORT_L11B_WPE_RDMA_4P_1 MTK_M4U_ID(SMI_L11B_ID, 3) -#define M4U_PORT_L11B_WPE_CQ0 MTK_M4U_ID(SMI_L11B_ID, 4) -#define M4U_PORT_L11B_WPE_CQ1 MTK_M4U_ID(SMI_L11B_ID, 5) -#define M4U_PORT_L11B_PIMGI_P1 MTK_M4U_ID(SMI_L11B_ID, 6) -#define M4U_PORT_L11B_PIMGBI_P1 MTK_M4U_ID(SMI_L11B_ID, 7) -#define M4U_PORT_L11B_PIMGCI_P1 MTK_M4U_ID(SMI_L11B_ID, 8) -#define M4U_PORT_L11B_IMGI_T1_C MTK_M4U_ID(SMI_L11B_ID, 9) -#define M4U_PORT_L11B_IMGBI_T1_C MTK_M4U_ID(SMI_L11B_ID, 10) -#define M4U_PORT_L11B_IMGCI_T1_C MTK_M4U_ID(SMI_L11B_ID, 11) -#define M4U_PORT_L11B_SMTI_T1_C MTK_M4U_ID(SMI_L11B_ID, 12) -#define M4U_PORT_L11B_SMTI_T4_C MTK_M4U_ID(SMI_L11B_ID, 13) -#define M4U_PORT_L11B_SMTI_T6_C MTK_M4U_ID(SMI_L11B_ID, 14) -#define M4U_PORT_L11B_YUVO_T1_C MTK_M4U_ID(SMI_L11B_ID, 15) -#define M4U_PORT_L11B_YUVBO_T1_C MTK_M4U_ID(SMI_L11B_ID, 16) -#define M4U_PORT_L11B_YUVCO_T1_C MTK_M4U_ID(SMI_L11B_ID, 17) -#define M4U_PORT_L11B_WPE_WDMA_0 MTK_M4U_ID(SMI_L11B_ID, 18) -#define M4U_PORT_L11B_WPE_WDMA_4P_0 MTK_M4U_ID(SMI_L11B_ID, 19) -#define M4U_PORT_L11B_WROT_P1 MTK_M4U_ID(SMI_L11B_ID, 20) -#define M4U_PORT_L11B_TCCSO_P1 MTK_M4U_ID(SMI_L11B_ID, 21) -#define M4U_PORT_L11B_TCCSI_P1 MTK_M4U_ID(SMI_L11B_ID, 22) -#define M4U_PORT_L11B_TIMGO_T1_C MTK_M4U_ID(SMI_L11B_ID, 23) -#define M4U_PORT_L11B_YUVO_T2_C MTK_M4U_ID(SMI_L11B_ID, 24) -#define M4U_PORT_L11B_YUVO_T5_C MTK_M4U_ID(SMI_L11B_ID, 25) -#define M4U_PORT_L11B_SMTO_T1_C MTK_M4U_ID(SMI_L11B_ID, 26) -#define M4U_PORT_L11B_SMTO_T4_C MTK_M4U_ID(SMI_L11B_ID, 27) -#define M4U_PORT_L11B_SMTO_T6_C MTK_M4U_ID(SMI_L11B_ID, 28) -#define M4U_PORT_L11B_DBGO_T1_C MTK_M4U_ID(SMI_L11B_ID, 29) - -/* LARB 11C -- IMG-D */ -#define M4U_PORT_L11C_WPE_RDMA_0 MTK_M4U_ID(SMI_L11C_ID, 0) -#define M4U_PORT_L11C_WPE_RDMA_1 MTK_M4U_ID(SMI_L11C_ID, 1) -#define M4U_PORT_L11C_WPE_RDMA_4P_0 MTK_M4U_ID(SMI_L11C_ID, 2) -#define M4U_PORT_L11C_WPE_RDMA_4P_1 MTK_M4U_ID(SMI_L11C_ID, 3) -#define M4U_PORT_L11C_WPE_CQ0 MTK_M4U_ID(SMI_L11C_ID, 4) -#define M4U_PORT_L11C_WPE_CQ1 MTK_M4U_ID(SMI_L11C_ID, 5) -#define M4U_PORT_L11C_PIMGI_P1 MTK_M4U_ID(SMI_L11C_ID, 6) -#define M4U_PORT_L11C_PIMGBI_P1 MTK_M4U_ID(SMI_L11C_ID, 7) -#define M4U_PORT_L11C_PIMGCI_P1 MTK_M4U_ID(SMI_L11C_ID, 8) -#define M4U_PORT_L11C_IMGI_T1_C MTK_M4U_ID(SMI_L11C_ID, 9) -#define M4U_PORT_L11C_IMGBI_T1_C MTK_M4U_ID(SMI_L11C_ID, 10) -#define M4U_PORT_L11C_IMGCI_T1_C MTK_M4U_ID(SMI_L11C_ID, 11) -#define M4U_PORT_L11C_SMTI_T1_C MTK_M4U_ID(SMI_L11C_ID, 12) -#define M4U_PORT_L11C_SMTI_T4_C MTK_M4U_ID(SMI_L11C_ID, 13) -#define M4U_PORT_L11C_SMTI_T6_C MTK_M4U_ID(SMI_L11C_ID, 14) -#define M4U_PORT_L11C_YUVO_T1_C MTK_M4U_ID(SMI_L11C_ID, 15) -#define M4U_PORT_L11C_YUVBO_T1_C MTK_M4U_ID(SMI_L11C_ID, 16) -#define M4U_PORT_L11C_YUVCO_T1_C MTK_M4U_ID(SMI_L11C_ID, 17) -#define M4U_PORT_L11C_WPE_WDMA_0 MTK_M4U_ID(SMI_L11C_ID, 18) -#define M4U_PORT_L11C_WPE_WDMA_4P_0 MTK_M4U_ID(SMI_L11C_ID, 19) -#define M4U_PORT_L11C_WROT_P1 MTK_M4U_ID(SMI_L11C_ID, 20) -#define M4U_PORT_L11C_TCCSO_P1 MTK_M4U_ID(SMI_L11C_ID, 21) -#define M4U_PORT_L11C_TCCSI_P1 MTK_M4U_ID(SMI_L11C_ID, 22) -#define M4U_PORT_L11C_TIMGO_T1_C MTK_M4U_ID(SMI_L11C_ID, 23) -#define M4U_PORT_L11C_YUVO_T2_C MTK_M4U_ID(SMI_L11C_ID, 24) -#define M4U_PORT_L11C_YUVO_T5_C MTK_M4U_ID(SMI_L11C_ID, 25) -#define M4U_PORT_L11C_SMTO_T1_C MTK_M4U_ID(SMI_L11C_ID, 26) -#define M4U_PORT_L11C_SMTO_T4_C MTK_M4U_ID(SMI_L11C_ID, 27) -#define M4U_PORT_L11C_SMTO_T6_C MTK_M4U_ID(SMI_L11C_ID, 28) -#define M4U_PORT_L11C_DBGO_T1_C MTK_M4U_ID(SMI_L11C_ID, 29) - -/* LARB 12 -- IPE */ -#define M4U_PORT_L12_FDVT_RDA_0 MTK_M4U_ID(SMI_L12_ID, 0) -#define M4U_PORT_L12_FDVT_RDB_0 MTK_M4U_ID(SMI_L12_ID, 1) -#define M4U_PORT_L12_FDVT_WRA_0 MTK_M4U_ID(SMI_L12_ID, 2) -#define M4U_PORT_L12_FDVT_WRB_0 MTK_M4U_ID(SMI_L12_ID, 3) -#define M4U_PORT_L12_ME_RDMA MTK_M4U_ID(SMI_L12_ID, 4) -#define M4U_PORT_L12_ME_WDMA MTK_M4U_ID(SMI_L12_ID, 5) -#define M4U_PORT_L12_DVS_RDMA MTK_M4U_ID(SMI_L12_ID, 6) -#define M4U_PORT_L12_DVS_WDMA MTK_M4U_ID(SMI_L12_ID, 7) -#define M4U_PORT_L12_DVP_RDMA MTK_M4U_ID(SMI_L12_ID, 8) -#define M4U_PORT_L12_DVP_WDMA MTK_M4U_ID(SMI_L12_ID, 9) -#define M4U_PORT_L12_FDVT_2ND_RDA_0 MTK_M4U_ID(SMI_L12_ID, 10) -#define M4U_PORT_L12_FDVT_2ND_RDB_0 MTK_M4U_ID(SMI_L12_ID, 11) -#define M4U_PORT_L12_FDVT_2ND_WRA_0 MTK_M4U_ID(SMI_L12_ID, 12) -#define M4U_PORT_L12_FDVT_2ND_WRB_0 MTK_M4U_ID(SMI_L12_ID, 13) -#define M4U_PORT_L12_DHZEI_E1 MTK_M4U_ID(SMI_L12_ID, 14) -#define M4U_PORT_L12_DHZEO_E1 MTK_M4U_ID(SMI_L12_ID, 15) - -/* LARB 13 -- CAM-1 */ -#define M4U_PORT_L13_CAMSV_CQI_E1 MTK_M4U_ID(SMI_L13_ID, 0) -#define M4U_PORT_L13_CAMSV_CQI_E2 MTK_M4U_ID(SMI_L13_ID, 1) -#define M4U_PORT_L13_GCAMSV_A_IMGO_1 MTK_M4U_ID(SMI_L13_ID, 2) -#define M4U_PORT_L13_GCAMSV_C_IMGO_1 MTK_M4U_ID(SMI_L13_ID, 3) -#define M4U_PORT_L13_GCAMSV_A_IMGO_2 MTK_M4U_ID(SMI_L13_ID, 4) -#define M4U_PORT_L13_GCAMSV_C_IMGO_2 MTK_M4U_ID(SMI_L13_ID, 5) -#define M4U_PORT_L13_PDAI_A_0 MTK_M4U_ID(SMI_L13_ID, 6) -#define M4U_PORT_L13_PDAI_A_1 MTK_M4U_ID(SMI_L13_ID, 7) -#define M4U_PORT_L13_CAMSV_CQI_B_E1 MTK_M4U_ID(SMI_L13_ID, 8) -#define M4U_PORT_L13_CAMSV_CQI_B_E2 MTK_M4U_ID(SMI_L13_ID, 9) -#define M4U_PORT_L13_CAMSV_CQI_C_E1 MTK_M4U_ID(SMI_L13_ID, 10) -#define M4U_PORT_L13_CAMSV_CQI_C_E2 MTK_M4U_ID(SMI_L13_ID, 11) -#define M4U_PORT_L13_GCAMSV_E_IMGO_1 MTK_M4U_ID(SMI_L13_ID, 12) -#define M4U_PORT_L13_GCAMSV_E_IMGO_2 MTK_M4U_ID(SMI_L13_ID, 13) -#define M4U_PORT_L13_GCAMSV_A_UFEO_1 MTK_M4U_ID(SMI_L13_ID, 14) -#define M4U_PORT_L13_GCAMSV_C_UFEO_1 MTK_M4U_ID(SMI_L13_ID, 15) -#define M4U_PORT_L13_GCAMSV_A_UFEO_2 MTK_M4U_ID(SMI_L13_ID, 16) -#define M4U_PORT_L13_GCAMSV_C_UFEO_2 MTK_M4U_ID(SMI_L13_ID, 17) -#define M4U_PORT_L13_GCAMSV_E_UFEO_1 MTK_M4U_ID(SMI_L13_ID, 18) -#define M4U_PORT_L13_GCAMSV_E_UFEO_2 MTK_M4U_ID(SMI_L13_ID, 19) -#define M4U_PORT_L13_GCAMSV_G_IMGO_1 MTK_M4U_ID(SMI_L13_ID, 20) -#define M4U_PORT_L13_GCAMSV_G_IMGO_2 MTK_M4U_ID(SMI_L13_ID, 21) -#define M4U_PORT_L13_PDAO_A MTK_M4U_ID(SMI_L13_ID, 22) -#define M4U_PORT_L13_PDAO_C MTK_M4U_ID(SMI_L13_ID, 23) - -/* LARB 14 -- CAM-1 */ -#define M4U_PORT_L14_GCAMSV_B_IMGO_1 MTK_M4U_ID(SMI_L14_ID, 0) -#define M4U_PORT_L14_GCAMSV_B_IMGO_2 MTK_M4U_ID(SMI_L14_ID, 1) -#define M4U_PORT_L14_SCAMSV_A_IMGO_1 MTK_M4U_ID(SMI_L14_ID, 2) -#define M4U_PORT_L14_SCAMSV_A_IMGO_2 MTK_M4U_ID(SMI_L14_ID, 3) -#define M4U_PORT_L14_SCAMSV_B_IMGO_1 MTK_M4U_ID(SMI_L14_ID, 4) -#define M4U_PORT_L14_SCAMSV_B_IMGO_2 MTK_M4U_ID(SMI_L14_ID, 5) -#define M4U_PORT_L14_PDAI_B_0 MTK_M4U_ID(SMI_L14_ID, 6) -#define M4U_PORT_L14_PDAI_B_1 MTK_M4U_ID(SMI_L14_ID, 7) -#define M4U_PORT_L14_GCAMSV_D_IMGO_1 MTK_M4U_ID(SMI_L14_ID, 8) -#define M4U_PORT_L14_GCAMSV_D_IMGO_2 MTK_M4U_ID(SMI_L14_ID, 9) -#define M4U_PORT_L14_GCAMSV_F_IMGO_1 MTK_M4U_ID(SMI_L14_ID, 10) -#define M4U_PORT_L14_GCAMSV_F_IMGO_2 MTK_M4U_ID(SMI_L14_ID, 11) -#define M4U_PORT_L14_GCAMSV_H_IMGO_1 MTK_M4U_ID(SMI_L14_ID, 12) -#define M4U_PORT_L14_GCAMSV_H_IMGO_2 MTK_M4U_ID(SMI_L14_ID, 13) -#define M4U_PORT_L14_GCAMSV_B_UFEO_1 MTK_M4U_ID(SMI_L14_ID, 14) -#define M4U_PORT_L14_GCAMSV_B_UFEO_2 MTK_M4U_ID(SMI_L14_ID, 15) -#define M4U_PORT_L14_GCAMSV_D_UFEO_1 MTK_M4U_ID(SMI_L14_ID, 16) -#define M4U_PORT_L14_GCAMSV_D_UFEO_2 MTK_M4U_ID(SMI_L14_ID, 17) -#define M4U_PORT_L14_PDAO_B MTK_M4U_ID(SMI_L14_ID, 18) -#define M4U_PORT_L14_IPUI MTK_M4U_ID(SMI_L14_ID, 19) -#define M4U_PORT_L14_IPUO MTK_M4U_ID(SMI_L14_ID, 20) -#define M4U_PORT_L14_IPU3O MTK_M4U_ID(SMI_L14_ID, 21) -#define M4U_PORT_L14_FAKE MTK_M4U_ID(SMI_L14_ID, 22) - -/* LARB 15 -- IMG-D */ -#define M4U_PORT_L15_VIPI_D1 MTK_M4U_ID(SMI_L15_ID, 0) -#define M4U_PORT_L15_VIPBI_D1 MTK_M4U_ID(SMI_L15_ID, 1) -#define M4U_PORT_L15_SMTI_D6 MTK_M4U_ID(SMI_L15_ID, 2) -#define M4U_PORT_L15_TNCSTI_D1 MTK_M4U_ID(SMI_L15_ID, 3) -#define M4U_PORT_L15_TNCSTI_D4 MTK_M4U_ID(SMI_L15_ID, 4) -#define M4U_PORT_L15_SMTI_D4 MTK_M4U_ID(SMI_L15_ID, 5) -#define M4U_PORT_L15_IMG3O_D1 MTK_M4U_ID(SMI_L15_ID, 6) -#define M4U_PORT_L15_IMG3BO_D1 MTK_M4U_ID(SMI_L15_ID, 7) -#define M4U_PORT_L15_IMG3CO_D1 MTK_M4U_ID(SMI_L15_ID, 8) -#define M4U_PORT_L15_IMG2O_D1 MTK_M4U_ID(SMI_L15_ID, 9) -#define M4U_PORT_L15_SMTI_D9 MTK_M4U_ID(SMI_L15_ID, 10) -#define M4U_PORT_L15_SMTO_D4 MTK_M4U_ID(SMI_L15_ID, 11) -#define M4U_PORT_L15_FEO_D1 MTK_M4U_ID(SMI_L15_ID, 12) -#define M4U_PORT_L15_TNCSO_D1 MTK_M4U_ID(SMI_L15_ID, 13) -#define M4U_PORT_L15_TNCSTO_D1 MTK_M4U_ID(SMI_L15_ID, 14) -#define M4U_PORT_L15_SMTO_D6 MTK_M4U_ID(SMI_L15_ID, 15) -#define M4U_PORT_L15_SMTO_D9 MTK_M4U_ID(SMI_L15_ID, 16) -#define M4U_PORT_L15_TNCO_D1 MTK_M4U_ID(SMI_L15_ID, 17) -#define M4U_PORT_L15_TNCO_D1_N MTK_M4U_ID(SMI_L15_ID, 18) - -/* LARB 16A -- CAM */ -#define M4U_PORT_L16A_IMGO_R1 MTK_M4U_ID(SMI_L16A_ID, 0) -#define M4U_PORT_L16A_CQI_R1 MTK_M4U_ID(SMI_L16A_ID, 1) -#define M4U_PORT_L16A_CQI_R2 MTK_M4U_ID(SMI_L16A_ID, 2) -#define M4U_PORT_L16A_BPCI_R1 MTK_M4U_ID(SMI_L16A_ID, 3) -#define M4U_PORT_L16A_LSCI_R1 MTK_M4U_ID(SMI_L16A_ID, 4) -#define M4U_PORT_L16A_RAWI_R2 MTK_M4U_ID(SMI_L16A_ID, 5) -#define M4U_PORT_L16A_RAWI_R3 MTK_M4U_ID(SMI_L16A_ID, 6) -#define M4U_PORT_L16A_UFDI_R2 MTK_M4U_ID(SMI_L16A_ID, 7) -#define M4U_PORT_L16A_UFDI_R3 MTK_M4U_ID(SMI_L16A_ID, 8) -#define M4U_PORT_L16A_RAWI_R4 MTK_M4U_ID(SMI_L16A_ID, 9) -#define M4U_PORT_L16A_RAWI_R5 MTK_M4U_ID(SMI_L16A_ID, 10) -#define M4U_PORT_L16A_AAI_R1 MTK_M4U_ID(SMI_L16A_ID, 11) -#define M4U_PORT_L16A_UFDI_R5 MTK_M4U_ID(SMI_L16A_ID, 12) -#define M4U_PORT_L16A_FHO_R1 MTK_M4U_ID(SMI_L16A_ID, 13) -#define M4U_PORT_L16A_AAO_R1 MTK_M4U_ID(SMI_L16A_ID, 14) -#define M4U_PORT_L16A_TSFSO_R1 MTK_M4U_ID(SMI_L16A_ID, 15) -#define M4U_PORT_L16A_FLKO_R1 MTK_M4U_ID(SMI_L16A_ID, 16) - -/* LARB 16B -- CAM */ -#define M4U_PORT_L16B_IMGO_R1 MTK_M4U_ID(SMI_L16B_ID, 0) -#define M4U_PORT_L16B_CQI_R1 MTK_M4U_ID(SMI_L16B_ID, 1) -#define M4U_PORT_L16B_CQI_R2 MTK_M4U_ID(SMI_L16B_ID, 2) -#define M4U_PORT_L16B_BPCI_R1 MTK_M4U_ID(SMI_L16B_ID, 3) -#define M4U_PORT_L16B_LSCI_R1 MTK_M4U_ID(SMI_L16B_ID, 4) -#define M4U_PORT_L16B_RAWI_R2 MTK_M4U_ID(SMI_L16B_ID, 5) -#define M4U_PORT_L16B_RAWI_R3 MTK_M4U_ID(SMI_L16B_ID, 6) -#define M4U_PORT_L16B_UFDI_R2 MTK_M4U_ID(SMI_L16B_ID, 7) -#define M4U_PORT_L16B_UFDI_R3 MTK_M4U_ID(SMI_L16B_ID, 8) -#define M4U_PORT_L16B_RAWI_R4 MTK_M4U_ID(SMI_L16B_ID, 9) -#define M4U_PORT_L16B_RAWI_R5 MTK_M4U_ID(SMI_L16B_ID, 10) -#define M4U_PORT_L16B_AAI_R1 MTK_M4U_ID(SMI_L16B_ID, 11) -#define M4U_PORT_L16B_UFDI_R5 MTK_M4U_ID(SMI_L16B_ID, 12) -#define M4U_PORT_L16B_FHO_R1 MTK_M4U_ID(SMI_L16B_ID, 13) -#define M4U_PORT_L16B_AAO_R1 MTK_M4U_ID(SMI_L16B_ID, 14) -#define M4U_PORT_L16B_TSFSO_R1 MTK_M4U_ID(SMI_L16B_ID, 15) -#define M4U_PORT_L16B_FLKO_R1 MTK_M4U_ID(SMI_L16B_ID, 16) - -/* LARB 17A -- CAM */ -#define M4U_PORT_L17A_YUVO_R1 MTK_M4U_ID(SMI_L17A_ID, 0) -#define M4U_PORT_L17A_YUVO_R3 MTK_M4U_ID(SMI_L17A_ID, 1) -#define M4U_PORT_L17A_YUVCO_R1 MTK_M4U_ID(SMI_L17A_ID, 2) -#define M4U_PORT_L17A_YUVO_R2 MTK_M4U_ID(SMI_L17A_ID, 3) -#define M4U_PORT_L17A_RZH1N2TO_R1 MTK_M4U_ID(SMI_L17A_ID, 4) -#define M4U_PORT_L17A_DRZS4NO_R1 MTK_M4U_ID(SMI_L17A_ID, 5) -#define M4U_PORT_L17A_TNCSO_R1 MTK_M4U_ID(SMI_L17A_ID, 6) - -/* LARB 17B -- CAM */ -#define M4U_PORT_L17B_YUVO_R1 MTK_M4U_ID(SMI_L17B_ID, 0) -#define M4U_PORT_L17B_YUVO_R3 MTK_M4U_ID(SMI_L17B_ID, 1) -#define M4U_PORT_L17B_YUVCO_R1 MTK_M4U_ID(SMI_L17B_ID, 2) -#define M4U_PORT_L17B_YUVO_R2 MTK_M4U_ID(SMI_L17B_ID, 3) -#define M4U_PORT_L17B_RZH1N2TO_R1 MTK_M4U_ID(SMI_L17B_ID, 4) -#define M4U_PORT_L17B_DRZS4NO_R1 MTK_M4U_ID(SMI_L17B_ID, 5) -#define M4U_PORT_L17B_TNCSO_R1 MTK_M4U_ID(SMI_L17B_ID, 6) - -/* LARB 19 -- VENC */ -#define M4U_PORT_L19_VENC_RCPU MTK_M4U_ID(SMI_L19_ID, 0) -#define M4U_PORT_L19_VENC_REC MTK_M4U_ID(SMI_L19_ID, 1) -#define M4U_PORT_L19_VENC_BSDMA MTK_M4U_ID(SMI_L19_ID, 2) -#define M4U_PORT_L19_VENC_SV_COMV MTK_M4U_ID(SMI_L19_ID, 3) -#define M4U_PORT_L19_VENC_RD_COMV MTK_M4U_ID(SMI_L19_ID, 4) -#define M4U_PORT_L19_VENC_NBM_RDMA MTK_M4U_ID(SMI_L19_ID, 5) -#define M4U_PORT_L19_VENC_NBM_RDMA_LITE MTK_M4U_ID(SMI_L19_ID, 6) -#define M4U_PORT_L19_JPGENC_Y_RDMA MTK_M4U_ID(SMI_L19_ID, 7) -#define M4U_PORT_L19_JPGENC_C_RDMA MTK_M4U_ID(SMI_L19_ID, 8) -#define M4U_PORT_L19_JPGENC_Q_TABLE MTK_M4U_ID(SMI_L19_ID, 9) -#define M4U_PORT_L19_VENC_SUB_W_LUMA MTK_M4U_ID(SMI_L19_ID, 10) -#define M4U_PORT_L19_VENC_FCS_NBM_RDMA MTK_M4U_ID(SMI_L19_ID, 11) -#define M4U_PORT_L19_JPGENC_BSDMA MTK_M4U_ID(SMI_L19_ID, 12) -#define M4U_PORT_L19_JPGDEC_WDMA_0 MTK_M4U_ID(SMI_L19_ID, 13) -#define M4U_PORT_L19_JPGDEC_BSDMA_0 MTK_M4U_ID(SMI_L19_ID, 14) -#define M4U_PORT_L19_VENC_NBM_WDMA MTK_M4U_ID(SMI_L19_ID, 15) -#define M4U_PORT_L19_VENC_NBM_WDMA_LITE MTK_M4U_ID(SMI_L19_ID, 16) -#define M4U_PORT_L19_VENC_FCS_NBM_WDMA MTK_M4U_ID(SMI_L19_ID, 17) -#define M4U_PORT_L19_JPGDEC_WDMA_1 MTK_M4U_ID(SMI_L19_ID, 18) -#define M4U_PORT_L19_JPGDEC_BSDMA_1 MTK_M4U_ID(SMI_L19_ID, 19) -#define M4U_PORT_L19_JPGDEC_HUFF_OFFSET_1 MTK_M4U_ID(SMI_L19_ID, 20) -#define M4U_PORT_L19_JPGDEC_HUFF_OFFSET_0 MTK_M4U_ID(SMI_L19_ID, 21) -#define M4U_PORT_L19_VENC_CUR_LUMA MTK_M4U_ID(SMI_L19_ID, 22) -#define M4U_PORT_L19_VENC_CUR_CHROMA MTK_M4U_ID(SMI_L19_ID, 23) -#define M4U_PORT_L19_VENC_REF_LUMA MTK_M4U_ID(SMI_L19_ID, 24) -#define M4U_PORT_L19_VENC_REF_CHROMA MTK_M4U_ID(SMI_L19_ID, 25) -#define M4U_PORT_L19_VENC_SUB_R_LUMA MTK_M4U_ID(SMI_L19_ID, 26) - -/* LARB 21 -- VDEC-CORE0 */ -#define M4U_PORT_L21_HW_VDEC_MC_EXT MTK_M4U_ID(SMI_L21_ID, 0) -#define M4U_PORT_L21_HW_VDEC_UFO_EXT MTK_M4U_ID(SMI_L21_ID, 1) -#define M4U_PORT_L21_HW_VDEC_PP_EXT MTK_M4U_ID(SMI_L21_ID, 2) -#define M4U_PORT_L21_HW_VDEC_PRED_RD_EXT MTK_M4U_ID(SMI_L21_ID, 3) -#define M4U_PORT_L21_HW_VDEC_PRED_WR_EXT MTK_M4U_ID(SMI_L21_ID, 4) -#define M4U_PORT_L21_HW_VDEC_PPWRAP_EXT MTK_M4U_ID(SMI_L21_ID, 5) -#define M4U_PORT_L21_HW_VDEC_TILE_EXT MTK_M4U_ID(SMI_L21_ID, 6) -#define M4U_PORT_L21_HW_VDEC_VLD_EXT MTK_M4U_ID(SMI_L21_ID, 7) -#define M4U_PORT_L21_HW_VDEC_VLD2_EXT MTK_M4U_ID(SMI_L21_ID, 8) -#define M4U_PORT_L21_HW_VDEC_AVC_MV_EXT MTK_M4U_ID(SMI_L21_ID, 9) -#define M4U_PORT_L21_HW_VDEC_UFO_EXT_C MTK_M4U_ID(SMI_L21_ID, 10) - -/* LARB 23 -- VDEC-SOC */ -#define M4U_PORT_L23_HW_VDEC_LAT0_VLD_EXT MTK_M4U_ID(SMI_L23_ID, 0) -#define M4U_PORT_L23_HW_VDEC_LAT0_VLD2_EXT MTK_M4U_ID(SMI_L23_ID, 1) -#define M4U_PORT_L23_HW_VDEC_LAT0_AVC_MV_EXT MTK_M4U_ID(SMI_L23_ID, 2) -#define M4U_PORT_L23_HW_VDEC_LAT0_PRED_RD_EXT MTK_M4U_ID(SMI_L23_ID, 3) -#define M4U_PORT_L23_HW_VDEC_LAT0_TILE_EXT MTK_M4U_ID(SMI_L23_ID, 4) -#define M4U_PORT_L23_HW_VDEC_LAT0_WDMA_EXT MTK_M4U_ID(SMI_L23_ID, 5) -#define M4U_PORT_L23_HW_VDEC_UFO_ENC_EXT MTK_M4U_ID(SMI_L23_ID, 6) -#define M4U_PORT_L23_HW_VDEC_UFO_ENC_EXT_C MTK_M4U_ID(SMI_L23_ID, 7) -#define M4U_PORT_L23_HW_VDEC_MC_EXT_C MTK_M4U_ID(SMI_L23_ID, 8) - -/* LARB 27 -- CCU */ -#define M4U_PORT_L27_CCUI MTK_M4U_ID(SMI_L27_ID, 0) -#define M4U_PORT_L27_CCUO MTK_M4U_ID(SMI_L27_ID, 1) -#define M4U_PORT_L27_CCUI2 MTK_M4U_ID(SMI_L27_ID, 2) -#define M4U_PORT_L27_CCUO2 MTK_M4U_ID(SMI_L27_ID, 3) - -/* LARB 28 -- AXI-CCU */ -#define M4U_PORT_L28_CCU_AXI_0 MTK_M4U_ID(SMI_L28_ID, 0) - -/* infra/peri */ -#define IFR_IOMMU_PORT_PCIE_0 MTK_IFAIOMMU_PERI_ID(0) - -#endif diff --git a/include/dt-bindings/memory/mediatek,mt8365-larb-port.h b/include/dt-bindings/memory/mediatek,mt8365-larb-port.h deleted file mode 100644 index 56d5a5dd519..00000000000 --- a/include/dt-bindings/memory/mediatek,mt8365-larb-port.h +++ /dev/null @@ -1,90 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ -/* - * Copyright (c) 2022 MediaTek Inc. - * Author: Yong Wu <yong.wu@mediatek.com> - */ -#ifndef _DT_BINDINGS_MEMORY_MT8365_LARB_PORT_H_ -#define _DT_BINDINGS_MEMORY_MT8365_LARB_PORT_H_ - -#include <dt-bindings/memory/mtk-memory-port.h> - -#define M4U_LARB0_ID 0 -#define M4U_LARB1_ID 1 -#define M4U_LARB2_ID 2 -#define M4U_LARB3_ID 3 - -/* larb0 */ -#define M4U_PORT_DISP_OVL0 MTK_M4U_ID(M4U_LARB0_ID, 0) -#define M4U_PORT_DISP_OVL0_2L MTK_M4U_ID(M4U_LARB0_ID, 1) -#define M4U_PORT_DISP_RDMA0 MTK_M4U_ID(M4U_LARB0_ID, 2) -#define M4U_PORT_DISP_WDMA0 MTK_M4U_ID(M4U_LARB0_ID, 3) -#define M4U_PORT_DISP_RDMA1 MTK_M4U_ID(M4U_LARB0_ID, 4) -#define M4U_PORT_MDP_RDMA0 MTK_M4U_ID(M4U_LARB0_ID, 5) -#define M4U_PORT_MDP_WROT1 MTK_M4U_ID(M4U_LARB0_ID, 6) -#define M4U_PORT_MDP_WROT0 MTK_M4U_ID(M4U_LARB0_ID, 7) -#define M4U_PORT_MDP_RDMA1 MTK_M4U_ID(M4U_LARB0_ID, 8) -#define M4U_PORT_DISP_FAKE0 MTK_M4U_ID(M4U_LARB0_ID, 9) -#define M4U_PORT_APU_READ MTK_M4U_ID(M4U_LARB0_ID, 10) -#define M4U_PORT_APU_WRITE MTK_M4U_ID(M4U_LARB0_ID, 11) - -/* larb1 */ -#define M4U_PORT_VENC_RCPU MTK_M4U_ID(M4U_LARB1_ID, 0) -#define M4U_PORT_VENC_REC MTK_M4U_ID(M4U_LARB1_ID, 1) -#define M4U_PORT_VENC_BSDMA MTK_M4U_ID(M4U_LARB1_ID, 2) -#define M4U_PORT_VENC_SV_COMV MTK_M4U_ID(M4U_LARB1_ID, 3) -#define M4U_PORT_VENC_RD_COMV MTK_M4U_ID(M4U_LARB1_ID, 4) -#define M4U_PORT_VENC_NBM_RDMA MTK_M4U_ID(M4U_LARB1_ID, 5) -#define M4U_PORT_VENC_NBM_RDMA_LITE MTK_M4U_ID(M4U_LARB1_ID, 6) -#define M4U_PORT_JPGENC_Y_RDMA MTK_M4U_ID(M4U_LARB1_ID, 7) -#define M4U_PORT_JPGENC_C_RDMA MTK_M4U_ID(M4U_LARB1_ID, 8) -#define M4U_PORT_JPGENC_Q_TABLE MTK_M4U_ID(M4U_LARB1_ID, 9) -#define M4U_PORT_JPGENC_BSDMA MTK_M4U_ID(M4U_LARB1_ID, 10) -#define M4U_PORT_JPGDEC_WDMA MTK_M4U_ID(M4U_LARB1_ID, 11) -#define M4U_PORT_JPGDEC_BSDMA MTK_M4U_ID(M4U_LARB1_ID, 12) -#define M4U_PORT_VENC_NBM_WDMA MTK_M4U_ID(M4U_LARB1_ID, 13) -#define M4U_PORT_VENC_NBM_WDMA_LITE MTK_M4U_ID(M4U_LARB1_ID, 14) -#define M4U_PORT_VENC_CUR_LUMA MTK_M4U_ID(M4U_LARB1_ID, 15) -#define M4U_PORT_VENC_CUR_CHROMA MTK_M4U_ID(M4U_LARB1_ID, 16) -#define M4U_PORT_VENC_REF_LUMA MTK_M4U_ID(M4U_LARB1_ID, 17) -#define M4U_PORT_VENC_REF_CHROMA MTK_M4U_ID(M4U_LARB1_ID, 18) - -/* larb2 */ -#define M4U_PORT_CAM_IMGO MTK_M4U_ID(M4U_LARB2_ID, 0) -#define M4U_PORT_CAM_RRZO MTK_M4U_ID(M4U_LARB2_ID, 1) -#define M4U_PORT_CAM_AAO MTK_M4U_ID(M4U_LARB2_ID, 2) -#define M4U_PORT_CAM_LCS MTK_M4U_ID(M4U_LARB2_ID, 3) -#define M4U_PORT_CAM_ESFKO MTK_M4U_ID(M4U_LARB2_ID, 4) -#define M4U_PORT_CAM_CAM_SV0 MTK_M4U_ID(M4U_LARB2_ID, 5) -#define M4U_PORT_CAM_CAM_SV1 MTK_M4U_ID(M4U_LARB2_ID, 6) -#define M4U_PORT_CAM_LSCI MTK_M4U_ID(M4U_LARB2_ID, 7) -#define M4U_PORT_CAM_LSCI_D MTK_M4U_ID(M4U_LARB2_ID, 8) -#define M4U_PORT_CAM_AFO MTK_M4U_ID(M4U_LARB2_ID, 9) -#define M4U_PORT_CAM_SPARE MTK_M4U_ID(M4U_LARB2_ID, 10) -#define M4U_PORT_CAM_BPCI MTK_M4U_ID(M4U_LARB2_ID, 11) -#define M4U_PORT_CAM_BPCI_D MTK_M4U_ID(M4U_LARB2_ID, 12) -#define M4U_PORT_CAM_UFDI MTK_M4U_ID(M4U_LARB2_ID, 13) -#define M4U_PORT_CAM_IMGI MTK_M4U_ID(M4U_LARB2_ID, 14) -#define M4U_PORT_CAM_IMG2O MTK_M4U_ID(M4U_LARB2_ID, 15) -#define M4U_PORT_CAM_IMG3O MTK_M4U_ID(M4U_LARB2_ID, 16) -#define M4U_PORT_CAM_WPE0_I MTK_M4U_ID(M4U_LARB2_ID, 17) -#define M4U_PORT_CAM_WPE1_I MTK_M4U_ID(M4U_LARB2_ID, 18) -#define M4U_PORT_CAM_WPE_O MTK_M4U_ID(M4U_LARB2_ID, 19) -#define M4U_PORT_CAM_FD0_I MTK_M4U_ID(M4U_LARB2_ID, 20) -#define M4U_PORT_CAM_FD1_I MTK_M4U_ID(M4U_LARB2_ID, 21) -#define M4U_PORT_CAM_FD0_O MTK_M4U_ID(M4U_LARB2_ID, 22) -#define M4U_PORT_CAM_FD1_O MTK_M4U_ID(M4U_LARB2_ID, 23) - -/* larb3 */ -#define M4U_PORT_HW_VDEC_MC_EXT MTK_M4U_ID(M4U_LARB3_ID, 0) -#define M4U_PORT_HW_VDEC_UFO_EXT MTK_M4U_ID(M4U_LARB3_ID, 1) -#define M4U_PORT_HW_VDEC_PP_EXT MTK_M4U_ID(M4U_LARB3_ID, 2) -#define M4U_PORT_HW_VDEC_PRED_RD_EXT MTK_M4U_ID(M4U_LARB3_ID, 3) -#define M4U_PORT_HW_VDEC_PRED_WR_EXT MTK_M4U_ID(M4U_LARB3_ID, 4) -#define M4U_PORT_HW_VDEC_PPWRAP_EXT MTK_M4U_ID(M4U_LARB3_ID, 5) -#define M4U_PORT_HW_VDEC_TILE_EXT MTK_M4U_ID(M4U_LARB3_ID, 6) -#define M4U_PORT_HW_VDEC_VLD_EXT MTK_M4U_ID(M4U_LARB3_ID, 7) -#define M4U_PORT_HW_VDEC_VLD2_EXT MTK_M4U_ID(M4U_LARB3_ID, 8) -#define M4U_PORT_HW_VDEC_AVC_MV_EXT MTK_M4U_ID(M4U_LARB3_ID, 9) -#define M4U_PORT_HW_VDEC_RG_CTRL_DMA_EXT MTK_M4U_ID(M4U_LARB3_ID, 10) - -#endif diff --git a/include/dt-bindings/memory/mpc83xx-sdram.h b/include/dt-bindings/memory/mpc83xx-sdram.h new file mode 100644 index 00000000000..7d4ce01cc48 --- /dev/null +++ b/include/dt-bindings/memory/mpc83xx-sdram.h @@ -0,0 +1,161 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2018 + * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc + */ + +#ifndef DT_BINDINGS_MPC83XX_SDRAM_H +#define DT_BINDINGS_MPC83XX_SDRAM_H + +/* DDR Control Driver register */ + +#define DSO_DISABLE 0 +#define DSO_ENABLE 1 + +#define DSO_P_IMPEDANCE_HIGHEST_Z 0x0 +#define DSO_P_IMPEDANCE_MUCH_HIGHER_Z 0x8 +#define DSO_P_IMPEDANCE_HIGHER_Z 0xC +#define DSO_P_IMPEDANCE_NOMINAL 0xE +#define DSO_P_IMPEDANCE_LOWER_Z 0xF + +#define DSO_N_IMPEDANCE_HIGHEST_Z 0x0 +#define DSO_N_IMPEDANCE_MUCH_HIGHER_Z 0x8 +#define DSO_N_IMPEDANCE_HIGHER_Z 0xC +#define DSO_N_IMPEDANCE_NOMINAL 0xE +#define DSO_N_IMPEDANCE_LOWER_Z 0xF + +#define ODT_TERMINATION_75_OHM 0 +#define ODT_TERMINATION_150_OHM 1 + +#define DDR_TYPE_DDR2_1_8_VOLT 0 +#define DDR_TYPE_DDR1_2_5_VOLT 1 + +#define MVREF_SEL_EXTERNAL 0 +#define MVREF_SEL_INTERNAL_GVDD 1 + +#define M_ODR_ENABLE 0 +#define M_ODR_DISABLE 1 + +/* CS config register */ + +#define AUTO_PRECHARGE_ENABLE 0x00800000 +#define AUTO_PRECHARGE_DISABLE 0x00000000 + +#define ODT_RD_NEVER 0x00000000 +#define ODT_RD_ONLY_CURRENT 0x00100000 +#define ODT_RD_ONLY_OTHER_CS 0x00200000 +#define ODT_RD_ONLY_OTHER_DIMM 0x00300000 +#define ODT_RD_ALL 0x00400000 + +#define ODT_WR_NEVER 0x00000000 +#define ODT_WR_ONLY_CURRENT 0x00010000 +#define ODT_WR_ONLY_OTHER_CS 0x00020000 +#define ODT_WR_ONLY_OTHER_DIMM 0x00030000 +#define ODT_WR_ALL 0x00040000 + +/* DDR SDRAM Clock Control register */ + +#define CLOCK_ADJUST_025 0x01000000 +#define CLOCK_ADJUST_05 0x02000000 +#define CLOCK_ADJUST_075 0x03000000 +#define CLOCK_ADJUST_1 0x04000000 + +#define CASLAT_20 0x3 /* CAS latency = 2.0 */ +#define CASLAT_25 0x4 /* CAS latency = 2.5 */ +#define CASLAT_30 0x5 /* CAS latency = 3.0 */ +#define CASLAT_35 0x6 /* CAS latency = 3.5 */ +#define CASLAT_40 0x7 /* CAS latency = 4.0 */ +#define CASLAT_45 0x8 /* CAS latency = 4.5 */ +#define CASLAT_50 0x9 /* CAS latency = 5.0 */ +#define CASLAT_55 0xa /* CAS latency = 5.5 */ +#define CASLAT_60 0xb /* CAS latency = 6.0 */ +#define CASLAT_65 0xc /* CAS latency = 6.5 */ +#define CASLAT_70 0xd /* CAS latency = 7.0 */ +#define CASLAT_75 0xe /* CAS latency = 7.5 */ +#define CASLAT_80 0xf /* CAS latency = 8.0 */ + +/* DDR SDRAM Timing Configuration 2 register */ + +#define READ_LAT_PLUS_1 0x0 +#define READ_LAT 0x2 +#define READ_LAT_PLUS_1_4 0x3 +#define READ_LAT_PLUS_1_2 0x4 +#define READ_LAT_PLUS_3_4 0x5 +#define READ_LAT_PLUS_5_4 0x7 +#define READ_LAT_PLUS_3_2 0x8 +#define READ_LAT_PLUS_7_4 0x9 +#define READ_LAT_PLUS_2 0xA +#define READ_LAT_PLUS_9_4 0xB +#define READ_LAT_PLUS_5_2 0xC +#define READ_LAT_PLUS_11_4 0xD +#define READ_LAT_PLUS_3 0xE +#define READ_LAT_PLUS_13_4 0xF +#define READ_LAT_PLUS_7_2 0x10 +#define READ_LAT_PLUS_15_4 0x11 +#define READ_LAT_PLUS_4 0x12 +#define READ_LAT_PLUS_17_4 0x13 +#define READ_LAT_PLUS_9_2 0x14 +#define READ_LAT_PLUS_19_4 0x15 + +#define CLOCK_DELAY_0 0x0 +#define CLOCK_DELAY_1_4 0x1 +#define CLOCK_DELAY_1_2 0x2 +#define CLOCK_DELAY_3_4 0x3 +#define CLOCK_DELAY_1 0x4 +#define CLOCK_DELAY_5_4 0x5 +#define CLOCK_DELAY_3_2 0x6 + +/* DDR SDRAM Control Configuration */ + +#define SREN_DISABLE 0x0 +#define SREN_ENABLE 0x1 + +#define ECC_DISABLE 0x0 +#define ECC_ENABLE 0x1 + +#define RD_DISABLE 0x0 +#define RD_ENABLE 0x1 + +#define TYPE_DDR1 0x2 +#define TYPE_DDR2 0x3 + +#define DYN_PWR_DISABLE 0x0 +#define DYN_PWR_ENABLE 0x1 + +#define DATA_BUS_WIDTH_16 0x1 +#define DATA_BUS_WIDTH_32 0x2 + +#define NCAP_DISABLE 0x0 +#define NCAP_ENABLE 0x1 + +#define TIMING_1T 0x0 +#define TIMING_2T 0x1 + +#define INTERLEAVE_NONE 0x0 +#define INTERLEAVE_1_AND_2 0x1 + +#define PRECHARGE_MA_10 0x0 +#define PRECHARGE_MA_8 0x1 + +#define STRENGTH_FULL 0x0 +#define STRENGTH_HALF 0x1 + +#define INITIALIZATION_DONT_BYPASS 0x0 +#define INITIALIZATION_BYPASS 0x1 + +/* DDR SDRAM Control Configuration 2 register */ + +#define MODE_NORMAL 0x0 +#define MODE_REFRESH 0x1 + +#define DLL_RESET_ENABLE 0x0 +#define DLL_RESET_DISABLE 0x1 + +#define DQS_TRUE 0x0 + +#define ODT_ASSERT_NEVER 0x0 +#define ODT_ASSERT_WRITES 0x1 +#define ODT_ASSERT_READS 0x2 +#define ODT_ASSERT_ALWAYS 0x3 + +#endif diff --git a/include/dt-bindings/memory/mt2701-larb-port.h b/include/dt-bindings/memory/mt2701-larb-port.h deleted file mode 100644 index 25d03526f14..00000000000 --- a/include/dt-bindings/memory/mt2701-larb-port.h +++ /dev/null @@ -1,77 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2015 MediaTek Inc. - * Author: Honghui Zhang <honghui.zhang@mediatek.com> - */ - -#ifndef _DT_BINDINGS_MEMORY_MT2701_LARB_PORT_H_ -#define _DT_BINDINGS_MEMORY_MT2701_LARB_PORT_H_ - -/* - * Mediatek m4u generation 1 such as mt2701 has flat m4u port numbers, - * the first port's id for larb[N] would be the last port's id of larb[N - 1] - * plus one while larb[0]'s first port number is 0. The definition of - * MT2701_M4U_ID_LARBx is following HW register spec. - * But m4u generation 2 like mt8173 have different port number, it use fixed - * offset for each larb, the first port's id for larb[N] would be (N * 32). - */ -#define LARB0_PORT_OFFSET 0 -#define LARB1_PORT_OFFSET 11 -#define LARB2_PORT_OFFSET 21 -#define LARB3_PORT_OFFSET 44 - -#define MT2701_M4U_ID_LARB0(port) ((port) + LARB0_PORT_OFFSET) -#define MT2701_M4U_ID_LARB1(port) ((port) + LARB1_PORT_OFFSET) -#define MT2701_M4U_ID_LARB2(port) ((port) + LARB2_PORT_OFFSET) - -/* Port define for larb0 */ -#define MT2701_M4U_PORT_DISP_OVL_0 MT2701_M4U_ID_LARB0(0) -#define MT2701_M4U_PORT_DISP_RDMA1 MT2701_M4U_ID_LARB0(1) -#define MT2701_M4U_PORT_DISP_RDMA MT2701_M4U_ID_LARB0(2) -#define MT2701_M4U_PORT_DISP_WDMA MT2701_M4U_ID_LARB0(3) -#define MT2701_M4U_PORT_MM_CMDQ MT2701_M4U_ID_LARB0(4) -#define MT2701_M4U_PORT_MDP_RDMA MT2701_M4U_ID_LARB0(5) -#define MT2701_M4U_PORT_MDP_WDMA MT2701_M4U_ID_LARB0(6) -#define MT2701_M4U_PORT_MDP_ROTO MT2701_M4U_ID_LARB0(7) -#define MT2701_M4U_PORT_MDP_ROTCO MT2701_M4U_ID_LARB0(8) -#define MT2701_M4U_PORT_MDP_ROTVO MT2701_M4U_ID_LARB0(9) -#define MT2701_M4U_PORT_MDP_RDMA1 MT2701_M4U_ID_LARB0(10) - -/* Port define for larb1 */ -#define MT2701_M4U_PORT_VDEC_MC_EXT MT2701_M4U_ID_LARB1(0) -#define MT2701_M4U_PORT_VDEC_PP_EXT MT2701_M4U_ID_LARB1(1) -#define MT2701_M4U_PORT_VDEC_PPWRAP_EXT MT2701_M4U_ID_LARB1(2) -#define MT2701_M4U_PORT_VDEC_AVC_MV_EXT MT2701_M4U_ID_LARB1(3) -#define MT2701_M4U_PORT_VDEC_PRED_RD_EXT MT2701_M4U_ID_LARB1(4) -#define MT2701_M4U_PORT_VDEC_PRED_WR_EXT MT2701_M4U_ID_LARB1(5) -#define MT2701_M4U_PORT_VDEC_VLD_EXT MT2701_M4U_ID_LARB1(6) -#define MT2701_M4U_PORT_VDEC_VLD2_EXT MT2701_M4U_ID_LARB1(7) -#define MT2701_M4U_PORT_VDEC_TILE_EXT MT2701_M4U_ID_LARB1(8) -#define MT2701_M4U_PORT_VDEC_IMG_RESZ_EXT MT2701_M4U_ID_LARB1(9) - -/* Port define for larb2 */ -#define MT2701_M4U_PORT_VENC_RCPU MT2701_M4U_ID_LARB2(0) -#define MT2701_M4U_PORT_VENC_REC_FRM MT2701_M4U_ID_LARB2(1) -#define MT2701_M4U_PORT_VENC_BSDMA MT2701_M4U_ID_LARB2(2) -#define MT2701_M4U_PORT_JPGENC_RDMA MT2701_M4U_ID_LARB2(3) -#define MT2701_M4U_PORT_VENC_LT_RCPU MT2701_M4U_ID_LARB2(4) -#define MT2701_M4U_PORT_VENC_LT_REC_FRM MT2701_M4U_ID_LARB2(5) -#define MT2701_M4U_PORT_VENC_LT_BSDMA MT2701_M4U_ID_LARB2(6) -#define MT2701_M4U_PORT_JPGDEC_BSDMA MT2701_M4U_ID_LARB2(7) -#define MT2701_M4U_PORT_VENC_SV_COMV MT2701_M4U_ID_LARB2(8) -#define MT2701_M4U_PORT_VENC_RD_COMV MT2701_M4U_ID_LARB2(9) -#define MT2701_M4U_PORT_JPGENC_BSDMA MT2701_M4U_ID_LARB2(10) -#define MT2701_M4U_PORT_VENC_CUR_LUMA MT2701_M4U_ID_LARB2(11) -#define MT2701_M4U_PORT_VENC_CUR_CHROMA MT2701_M4U_ID_LARB2(12) -#define MT2701_M4U_PORT_VENC_REF_LUMA MT2701_M4U_ID_LARB2(13) -#define MT2701_M4U_PORT_VENC_REF_CHROMA MT2701_M4U_ID_LARB2(14) -#define MT2701_M4U_PORT_IMG_RESZ MT2701_M4U_ID_LARB2(15) -#define MT2701_M4U_PORT_VENC_LT_SV_COMV MT2701_M4U_ID_LARB2(16) -#define MT2701_M4U_PORT_VENC_LT_RD_COMV MT2701_M4U_ID_LARB2(17) -#define MT2701_M4U_PORT_VENC_LT_CUR_LUMA MT2701_M4U_ID_LARB2(18) -#define MT2701_M4U_PORT_VENC_LT_CUR_CHROMA MT2701_M4U_ID_LARB2(19) -#define MT2701_M4U_PORT_VENC_LT_REF_LUMA MT2701_M4U_ID_LARB2(20) -#define MT2701_M4U_PORT_VENC_LT_REF_CHROMA MT2701_M4U_ID_LARB2(21) -#define MT2701_M4U_PORT_JPGDEC_WDMA MT2701_M4U_ID_LARB2(22) - -#endif diff --git a/include/dt-bindings/memory/mt2712-larb-port.h b/include/dt-bindings/memory/mt2712-larb-port.h deleted file mode 100644 index e41a2841bcf..00000000000 --- a/include/dt-bindings/memory/mt2712-larb-port.h +++ /dev/null @@ -1,95 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2017 MediaTek Inc. - * Author: Yong Wu <yong.wu@mediatek.com> - */ -#ifndef _DT_BINDINGS_MEMORY_MT2712_LARB_PORT_H_ -#define _DT_BINDINGS_MEMORY_MT2712_LARB_PORT_H_ - -#include <dt-bindings/memory/mtk-memory-port.h> - -#define M4U_LARB0_ID 0 -#define M4U_LARB1_ID 1 -#define M4U_LARB2_ID 2 -#define M4U_LARB3_ID 3 -#define M4U_LARB4_ID 4 -#define M4U_LARB5_ID 5 -#define M4U_LARB6_ID 6 -#define M4U_LARB7_ID 7 -#define M4U_LARB8_ID 8 -#define M4U_LARB9_ID 9 - -/* larb0 */ -#define M4U_PORT_DISP_OVL0 MTK_M4U_ID(M4U_LARB0_ID, 0) -#define M4U_PORT_DISP_RDMA0 MTK_M4U_ID(M4U_LARB0_ID, 1) -#define M4U_PORT_DISP_WDMA0 MTK_M4U_ID(M4U_LARB0_ID, 2) -#define M4U_PORT_DISP_OD_R MTK_M4U_ID(M4U_LARB0_ID, 3) -#define M4U_PORT_DISP_OD_W MTK_M4U_ID(M4U_LARB0_ID, 4) -#define M4U_PORT_MDP_RDMA0 MTK_M4U_ID(M4U_LARB0_ID, 5) -#define M4U_PORT_MDP_WDMA MTK_M4U_ID(M4U_LARB0_ID, 6) -#define M4U_PORT_DISP_RDMA2 MTK_M4U_ID(M4U_LARB0_ID, 7) - -/* larb1 */ -#define M4U_PORT_HW_VDEC_MC_EXT MTK_M4U_ID(M4U_LARB1_ID, 0) -#define M4U_PORT_HW_VDEC_PP_EXT MTK_M4U_ID(M4U_LARB1_ID, 1) -#define M4U_PORT_HW_VDEC_UFO_EXT MTK_M4U_ID(M4U_LARB1_ID, 2) -#define M4U_PORT_HW_VDEC_VLD_EXT MTK_M4U_ID(M4U_LARB1_ID, 3) -#define M4U_PORT_HW_VDEC_VLD2_EXT MTK_M4U_ID(M4U_LARB1_ID, 4) -#define M4U_PORT_HW_VDEC_AVC_MV_EXT MTK_M4U_ID(M4U_LARB1_ID, 5) -#define M4U_PORT_HW_VDEC_PRED_RD_EXT MTK_M4U_ID(M4U_LARB1_ID, 6) -#define M4U_PORT_HW_VDEC_PRED_WR_EXT MTK_M4U_ID(M4U_LARB1_ID, 7) -#define M4U_PORT_HW_VDEC_PPWRAP_EXT MTK_M4U_ID(M4U_LARB1_ID, 8) -#define M4U_PORT_HW_VDEC_TILE MTK_M4U_ID(M4U_LARB1_ID, 9) -#define M4U_PORT_HW_IMG_RESZ_EXT MTK_M4U_ID(M4U_LARB1_ID, 10) - -/* larb2 */ -#define M4U_PORT_CAM_DMA0 MTK_M4U_ID(M4U_LARB2_ID, 0) -#define M4U_PORT_CAM_DMA1 MTK_M4U_ID(M4U_LARB2_ID, 1) -#define M4U_PORT_CAM_DMA2 MTK_M4U_ID(M4U_LARB2_ID, 2) - -/* larb3 */ -#define M4U_PORT_VENC_RCPU MTK_M4U_ID(M4U_LARB3_ID, 0) -#define M4U_PORT_VENC_REC MTK_M4U_ID(M4U_LARB3_ID, 1) -#define M4U_PORT_VENC_BSDMA MTK_M4U_ID(M4U_LARB3_ID, 2) -#define M4U_PORT_VENC_SV_COMV MTK_M4U_ID(M4U_LARB3_ID, 3) -#define M4U_PORT_VENC_RD_COMV MTK_M4U_ID(M4U_LARB3_ID, 4) -#define M4U_PORT_VENC_CUR_CHROMA MTK_M4U_ID(M4U_LARB3_ID, 5) -#define M4U_PORT_VENC_REF_CHROMA MTK_M4U_ID(M4U_LARB3_ID, 6) -#define M4U_PORT_VENC_CUR_LUMA MTK_M4U_ID(M4U_LARB3_ID, 7) -#define M4U_PORT_VENC_REF_LUMA MTK_M4U_ID(M4U_LARB3_ID, 8) - -/* larb4 */ -#define M4U_PORT_DISP_OVL1 MTK_M4U_ID(M4U_LARB4_ID, 0) -#define M4U_PORT_DISP_RDMA1 MTK_M4U_ID(M4U_LARB4_ID, 1) -#define M4U_PORT_DISP_WDMA1 MTK_M4U_ID(M4U_LARB4_ID, 2) -#define M4U_PORT_DISP_OD1_R MTK_M4U_ID(M4U_LARB4_ID, 3) -#define M4U_PORT_DISP_OD1_W MTK_M4U_ID(M4U_LARB4_ID, 4) -#define M4U_PORT_MDP_RDMA1 MTK_M4U_ID(M4U_LARB4_ID, 5) -#define M4U_PORT_MDP_WROT1 MTK_M4U_ID(M4U_LARB4_ID, 6) - -/* larb5 */ -#define M4U_PORT_DISP_OVL2 MTK_M4U_ID(M4U_LARB5_ID, 0) -#define M4U_PORT_DISP_WDMA2 MTK_M4U_ID(M4U_LARB5_ID, 1) -#define M4U_PORT_MDP_RDMA2 MTK_M4U_ID(M4U_LARB5_ID, 2) -#define M4U_PORT_MDP_WROT0 MTK_M4U_ID(M4U_LARB5_ID, 3) - -/* larb6 */ -#define M4U_PORT_JPGDEC_WDMA_0 MTK_M4U_ID(M4U_LARB6_ID, 0) -#define M4U_PORT_JPGDEC_WDMA_1 MTK_M4U_ID(M4U_LARB6_ID, 1) -#define M4U_PORT_JPGDEC_BSDMA_0 MTK_M4U_ID(M4U_LARB6_ID, 2) -#define M4U_PORT_JPGDEC_BSDMA_1 MTK_M4U_ID(M4U_LARB6_ID, 3) - -/* larb7 */ -#define M4U_PORT_MDP_RDMA3 MTK_M4U_ID(M4U_LARB7_ID, 0) -#define M4U_PORT_MDP_WROT2 MTK_M4U_ID(M4U_LARB7_ID, 1) - -/* larb8 */ -#define M4U_PORT_VDO MTK_M4U_ID(M4U_LARB8_ID, 0) -#define M4U_PORT_NR MTK_M4U_ID(M4U_LARB8_ID, 1) -#define M4U_PORT_WR_CHANNEL0 MTK_M4U_ID(M4U_LARB8_ID, 2) - -/* larb9 */ -#define M4U_PORT_TVD MTK_M4U_ID(M4U_LARB9_ID, 0) -#define M4U_PORT_WR_CHANNEL1 MTK_M4U_ID(M4U_LARB9_ID, 1) - -#endif diff --git a/include/dt-bindings/memory/mt6779-larb-port.h b/include/dt-bindings/memory/mt6779-larb-port.h deleted file mode 100644 index 3fb438a96e3..00000000000 --- a/include/dt-bindings/memory/mt6779-larb-port.h +++ /dev/null @@ -1,206 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2019 MediaTek Inc. - * Author: Chao Hao <chao.hao@mediatek.com> - */ - -#ifndef _DT_BINDINGS_MEMORY_MT6779_LARB_PORT_H_ -#define _DT_BINDINGS_MEMORY_MT6779_LARB_PORT_H_ - -#include <dt-bindings/memory/mtk-memory-port.h> - -#define M4U_LARB0_ID 0 -#define M4U_LARB1_ID 1 -#define M4U_LARB2_ID 2 -#define M4U_LARB3_ID 3 -#define M4U_LARB4_ID 4 -#define M4U_LARB5_ID 5 -#define M4U_LARB6_ID 6 -#define M4U_LARB7_ID 7 -#define M4U_LARB8_ID 8 -#define M4U_LARB9_ID 9 -#define M4U_LARB10_ID 10 -#define M4U_LARB11_ID 11 - -/* larb0 */ -#define M4U_PORT_DISP_POSTMASK0 MTK_M4U_ID(M4U_LARB0_ID, 0) -#define M4U_PORT_DISP_OVL0_HDR MTK_M4U_ID(M4U_LARB0_ID, 1) -#define M4U_PORT_DISP_OVL1_HDR MTK_M4U_ID(M4U_LARB0_ID, 2) -#define M4U_PORT_DISP_OVL0 MTK_M4U_ID(M4U_LARB0_ID, 3) -#define M4U_PORT_DISP_OVL1 MTK_M4U_ID(M4U_LARB0_ID, 4) -#define M4U_PORT_DISP_PVRIC0 MTK_M4U_ID(M4U_LARB0_ID, 5) -#define M4U_PORT_DISP_RDMA0 MTK_M4U_ID(M4U_LARB0_ID, 6) -#define M4U_PORT_DISP_WDMA0 MTK_M4U_ID(M4U_LARB0_ID, 7) -#define M4U_PORT_DISP_FAKE0 MTK_M4U_ID(M4U_LARB0_ID, 8) - -/* larb1 */ -#define M4U_PORT_DISP_OVL0_2L_HDR MTK_M4U_ID(M4U_LARB1_ID, 0) -#define M4U_PORT_DISP_OVL1_2L_HDR MTK_M4U_ID(M4U_LARB1_ID, 1) -#define M4U_PORT_DISP_OVL0_2L MTK_M4U_ID(M4U_LARB1_ID, 2) -#define M4U_PORT_DISP_OVL1_2L MTK_M4U_ID(M4U_LARB1_ID, 3) -#define M4U_PORT_DISP_RDMA1 MTK_M4U_ID(M4U_LARB1_ID, 4) -#define M4U_PORT_MDP_PVRIC0 MTK_M4U_ID(M4U_LARB1_ID, 5) -#define M4U_PORT_MDP_PVRIC1 MTK_M4U_ID(M4U_LARB1_ID, 6) -#define M4U_PORT_MDP_RDMA0 MTK_M4U_ID(M4U_LARB1_ID, 7) -#define M4U_PORT_MDP_RDMA1 MTK_M4U_ID(M4U_LARB1_ID, 8) -#define M4U_PORT_MDP_WROT0_R MTK_M4U_ID(M4U_LARB1_ID, 9) -#define M4U_PORT_MDP_WROT0_W MTK_M4U_ID(M4U_LARB1_ID, 10) -#define M4U_PORT_MDP_WROT1_R MTK_M4U_ID(M4U_LARB1_ID, 11) -#define M4U_PORT_MDP_WROT1_W MTK_M4U_ID(M4U_LARB1_ID, 12) -#define M4U_PORT_DISP_FAKE1 MTK_M4U_ID(M4U_LARB1_ID, 13) - -/* larb2-VDEC */ -#define M4U_PORT_HW_VDEC_MC_EXT MTK_M4U_ID(M4U_LARB2_ID, 0) -#define M4U_PORT_HW_VDEC_UFO_EXT MTK_M4U_ID(M4U_LARB2_ID, 1) -#define M4U_PORT_HW_VDEC_PP_EXT MTK_M4U_ID(M4U_LARB2_ID, 2) -#define M4U_PORT_HW_VDEC_PRED_RD_EXT MTK_M4U_ID(M4U_LARB2_ID, 3) -#define M4U_PORT_HW_VDEC_PRED_WR_EXT MTK_M4U_ID(M4U_LARB2_ID, 4) -#define M4U_PORT_HW_VDEC_PPWRAP_EXT MTK_M4U_ID(M4U_LARB2_ID, 5) -#define M4U_PORT_HW_VDEC_TILE_EXT MTK_M4U_ID(M4U_LARB2_ID, 6) -#define M4U_PORT_HW_VDEC_VLD_EXT MTK_M4U_ID(M4U_LARB2_ID, 7) -#define M4U_PORT_HW_VDEC_VLD2_EXT MTK_M4U_ID(M4U_LARB2_ID, 8) -#define M4U_PORT_HW_VDEC_AVC_MV_EXT MTK_M4U_ID(M4U_LARB2_ID, 9) -#define M4U_PORT_HW_VDEC_UFO_ENC_EXT MTK_M4U_ID(M4U_LARB2_ID, 10) -#define M4U_PORT_HW_VDEC_RG_CTRL_DMA_EXT MTK_M4U_ID(M4U_LARB2_ID, 11) - -/* larb3-VENC */ -#define M4U_PORT_VENC_RCPU MTK_M4U_ID(M4U_LARB3_ID, 0) -#define M4U_PORT_VENC_REC MTK_M4U_ID(M4U_LARB3_ID, 1) -#define M4U_PORT_VENC_BSDMA MTK_M4U_ID(M4U_LARB3_ID, 2) -#define M4U_PORT_VENC_SV_COMV MTK_M4U_ID(M4U_LARB3_ID, 3) -#define M4U_PORT_VENC_RD_COMV MTK_M4U_ID(M4U_LARB3_ID, 4) -#define M4U_PORT_VENC_NBM_RDMA MTK_M4U_ID(M4U_LARB3_ID, 5) -#define M4U_PORT_VENC_NBM_RDMA_LITE MTK_M4U_ID(M4U_LARB3_ID, 6) -#define M4U_PORT_JPGENC_Y_RDMA MTK_M4U_ID(M4U_LARB3_ID, 7) -#define M4U_PORT_JPGENC_C_RDMA MTK_M4U_ID(M4U_LARB3_ID, 8) -#define M4U_PORT_JPGENC_Q_TABLE MTK_M4U_ID(M4U_LARB3_ID, 9) -#define M4U_PORT_JPGENC_BSDMA MTK_M4U_ID(M4U_LARB3_ID, 10) -#define M4U_PORT_JPGDEC_WDMA MTK_M4U_ID(M4U_LARB3_ID, 11) -#define M4U_PORT_JPGDEC_BSDMA MTK_M4U_ID(M4U_LARB3_ID, 12) -#define M4U_PORT_VENC_NBM_WDMA MTK_M4U_ID(M4U_LARB3_ID, 13) -#define M4U_PORT_VENC_NBM_WDMA_LITE MTK_M4U_ID(M4U_LARB3_ID, 14) -#define M4U_PORT_VENC_CUR_LUMA MTK_M4U_ID(M4U_LARB3_ID, 15) -#define M4U_PORT_VENC_CUR_CHROMA MTK_M4U_ID(M4U_LARB3_ID, 16) -#define M4U_PORT_VENC_REF_LUMA MTK_M4U_ID(M4U_LARB3_ID, 17) -#define M4U_PORT_VENC_REF_CHROMA MTK_M4U_ID(M4U_LARB3_ID, 18) - -/* larb4-dummy */ - -/* larb5-IMG */ -#define M4U_PORT_IMGI_D1 MTK_M4U_ID(M4U_LARB5_ID, 0) -#define M4U_PORT_IMGBI_D1 MTK_M4U_ID(M4U_LARB5_ID, 1) -#define M4U_PORT_DMGI_D1 MTK_M4U_ID(M4U_LARB5_ID, 2) -#define M4U_PORT_DEPI_D1 MTK_M4U_ID(M4U_LARB5_ID, 3) -#define M4U_PORT_LCEI_D1 MTK_M4U_ID(M4U_LARB5_ID, 4) -#define M4U_PORT_SMTI_D1 MTK_M4U_ID(M4U_LARB5_ID, 5) -#define M4U_PORT_SMTO_D2 MTK_M4U_ID(M4U_LARB5_ID, 6) -#define M4U_PORT_SMTO_D1 MTK_M4U_ID(M4U_LARB5_ID, 7) -#define M4U_PORT_CRZO_D1 MTK_M4U_ID(M4U_LARB5_ID, 8) -#define M4U_PORT_IMG3O_D1 MTK_M4U_ID(M4U_LARB5_ID, 9) -#define M4U_PORT_VIPI_D1 MTK_M4U_ID(M4U_LARB5_ID, 10) -#define M4U_PORT_WPE_RDMA1 MTK_M4U_ID(M4U_LARB5_ID, 11) -#define M4U_PORT_WPE_RDMA0 MTK_M4U_ID(M4U_LARB5_ID, 12) -#define M4U_PORT_WPE_WDMA MTK_M4U_ID(M4U_LARB5_ID, 13) -#define M4U_PORT_TIMGO_D1 MTK_M4U_ID(M4U_LARB5_ID, 14) -#define M4U_PORT_MFB_RDMA0 MTK_M4U_ID(M4U_LARB5_ID, 15) -#define M4U_PORT_MFB_RDMA1 MTK_M4U_ID(M4U_LARB5_ID, 16) -#define M4U_PORT_MFB_RDMA2 MTK_M4U_ID(M4U_LARB5_ID, 17) -#define M4U_PORT_MFB_RDMA3 MTK_M4U_ID(M4U_LARB5_ID, 18) -#define M4U_PORT_MFB_WDMA MTK_M4U_ID(M4U_LARB5_ID, 19) -#define M4U_PORT_RESERVE1 MTK_M4U_ID(M4U_LARB5_ID, 20) -#define M4U_PORT_RESERVE2 MTK_M4U_ID(M4U_LARB5_ID, 21) -#define M4U_PORT_RESERVE3 MTK_M4U_ID(M4U_LARB5_ID, 22) -#define M4U_PORT_RESERVE4 MTK_M4U_ID(M4U_LARB5_ID, 23) -#define M4U_PORT_RESERVE5 MTK_M4U_ID(M4U_LARB5_ID, 24) -#define M4U_PORT_RESERVE6 MTK_M4U_ID(M4U_LARB5_ID, 25) - -/* larb6-IMG-VPU */ -#define M4U_PORT_IMG_IPUO MTK_M4U_ID(M4U_LARB6_ID, 0) -#define M4U_PORT_IMG_IPU3O MTK_M4U_ID(M4U_LARB6_ID, 1) -#define M4U_PORT_IMG_IPUI MTK_M4U_ID(M4U_LARB6_ID, 2) - -/* larb7-DVS */ -#define M4U_PORT_DVS_RDMA MTK_M4U_ID(M4U_LARB7_ID, 0) -#define M4U_PORT_DVS_WDMA MTK_M4U_ID(M4U_LARB7_ID, 1) -#define M4U_PORT_DVP_RDMA MTK_M4U_ID(M4U_LARB7_ID, 2) -#define M4U_PORT_DVP_WDMA MTK_M4U_ID(M4U_LARB7_ID, 3) - -/* larb8-IPESYS */ -#define M4U_PORT_FDVT_RDA MTK_M4U_ID(M4U_LARB8_ID, 0) -#define M4U_PORT_FDVT_RDB MTK_M4U_ID(M4U_LARB8_ID, 1) -#define M4U_PORT_FDVT_WRA MTK_M4U_ID(M4U_LARB8_ID, 2) -#define M4U_PORT_FDVT_WRB MTK_M4U_ID(M4U_LARB8_ID, 3) -#define M4U_PORT_FE_RD0 MTK_M4U_ID(M4U_LARB8_ID, 4) -#define M4U_PORT_FE_RD1 MTK_M4U_ID(M4U_LARB8_ID, 5) -#define M4U_PORT_FE_WR0 MTK_M4U_ID(M4U_LARB8_ID, 6) -#define M4U_PORT_FE_WR1 MTK_M4U_ID(M4U_LARB8_ID, 7) -#define M4U_PORT_RSC_RDMA0 MTK_M4U_ID(M4U_LARB8_ID, 8) -#define M4U_PORT_RSC_WDMA MTK_M4U_ID(M4U_LARB8_ID, 9) - -/* larb9-CAM */ -#define M4U_PORT_CAM_IMGO_R1_C MTK_M4U_ID(M4U_LARB9_ID, 0) -#define M4U_PORT_CAM_RRZO_R1_C MTK_M4U_ID(M4U_LARB9_ID, 1) -#define M4U_PORT_CAM_LSCI_R1_C MTK_M4U_ID(M4U_LARB9_ID, 2) -#define M4U_PORT_CAM_BPCI_R1_C MTK_M4U_ID(M4U_LARB9_ID, 3) -#define M4U_PORT_CAM_YUVO_R1_C MTK_M4U_ID(M4U_LARB9_ID, 4) -#define M4U_PORT_CAM_UFDI_R2_C MTK_M4U_ID(M4U_LARB9_ID, 5) -#define M4U_PORT_CAM_RAWI_R2_C MTK_M4U_ID(M4U_LARB9_ID, 6) -#define M4U_PORT_CAM_RAWI_R5_C MTK_M4U_ID(M4U_LARB9_ID, 7) -#define M4U_PORT_CAM_CAMSV_1 MTK_M4U_ID(M4U_LARB9_ID, 8) -#define M4U_PORT_CAM_CAMSV_2 MTK_M4U_ID(M4U_LARB9_ID, 9) -#define M4U_PORT_CAM_CAMSV_3 MTK_M4U_ID(M4U_LARB9_ID, 10) -#define M4U_PORT_CAM_CAMSV_4 MTK_M4U_ID(M4U_LARB9_ID, 11) -#define M4U_PORT_CAM_CAMSV_5 MTK_M4U_ID(M4U_LARB9_ID, 12) -#define M4U_PORT_CAM_CAMSV_6 MTK_M4U_ID(M4U_LARB9_ID, 13) -#define M4U_PORT_CAM_AAO_R1_C MTK_M4U_ID(M4U_LARB9_ID, 14) -#define M4U_PORT_CAM_AFO_R1_C MTK_M4U_ID(M4U_LARB9_ID, 15) -#define M4U_PORT_CAM_FLKO_R1_C MTK_M4U_ID(M4U_LARB9_ID, 16) -#define M4U_PORT_CAM_LCESO_R1_C MTK_M4U_ID(M4U_LARB9_ID, 17) -#define M4U_PORT_CAM_CRZO_R1_C MTK_M4U_ID(M4U_LARB9_ID, 18) -#define M4U_PORT_CAM_LTMSO_R1_C MTK_M4U_ID(M4U_LARB9_ID, 19) -#define M4U_PORT_CAM_RSSO_R1_C MTK_M4U_ID(M4U_LARB9_ID, 20) -#define M4U_PORT_CAM_CCUI MTK_M4U_ID(M4U_LARB9_ID, 21) -#define M4U_PORT_CAM_CCUO MTK_M4U_ID(M4U_LARB9_ID, 22) -#define M4U_PORT_CAM_FAKE MTK_M4U_ID(M4U_LARB9_ID, 23) - -/* larb10-CAM_A */ -#define M4U_PORT_CAM_IMGO_R1_A MTK_M4U_ID(M4U_LARB10_ID, 0) -#define M4U_PORT_CAM_RRZO_R1_A MTK_M4U_ID(M4U_LARB10_ID, 1) -#define M4U_PORT_CAM_LSCI_R1_A MTK_M4U_ID(M4U_LARB10_ID, 2) -#define M4U_PORT_CAM_BPCI_R1_A MTK_M4U_ID(M4U_LARB10_ID, 3) -#define M4U_PORT_CAM_YUVO_R1_A MTK_M4U_ID(M4U_LARB10_ID, 4) -#define M4U_PORT_CAM_UFDI_R2_A MTK_M4U_ID(M4U_LARB10_ID, 5) -#define M4U_PORT_CAM_RAWI_R2_A MTK_M4U_ID(M4U_LARB10_ID, 6) -#define M4U_PORT_CAM_RAWI_R5_A MTK_M4U_ID(M4U_LARB10_ID, 7) -#define M4U_PORT_CAM_IMGO_R1_B MTK_M4U_ID(M4U_LARB10_ID, 8) -#define M4U_PORT_CAM_RRZO_R1_B MTK_M4U_ID(M4U_LARB10_ID, 9) -#define M4U_PORT_CAM_LSCI_R1_B MTK_M4U_ID(M4U_LARB10_ID, 10) -#define M4U_PORT_CAM_BPCI_R1_B MTK_M4U_ID(M4U_LARB10_ID, 11) -#define M4U_PORT_CAM_YUVO_R1_B MTK_M4U_ID(M4U_LARB10_ID, 12) -#define M4U_PORT_CAM_UFDI_R2_B MTK_M4U_ID(M4U_LARB10_ID, 13) -#define M4U_PORT_CAM_RAWI_R2_B MTK_M4U_ID(M4U_LARB10_ID, 14) -#define M4U_PORT_CAM_RAWI_R5_B MTK_M4U_ID(M4U_LARB10_ID, 15) -#define M4U_PORT_CAM_CAMSV_0 MTK_M4U_ID(M4U_LARB10_ID, 16) -#define M4U_PORT_CAM_AAO_R1_A MTK_M4U_ID(M4U_LARB10_ID, 17) -#define M4U_PORT_CAM_AFO_R1_A MTK_M4U_ID(M4U_LARB10_ID, 18) -#define M4U_PORT_CAM_FLKO_R1_A MTK_M4U_ID(M4U_LARB10_ID, 19) -#define M4U_PORT_CAM_LCESO_R1_A MTK_M4U_ID(M4U_LARB10_ID, 20) -#define M4U_PORT_CAM_CRZO_R1_A MTK_M4U_ID(M4U_LARB10_ID, 21) -#define M4U_PORT_CAM_AAO_R1_B MTK_M4U_ID(M4U_LARB10_ID, 22) -#define M4U_PORT_CAM_AFO_R1_B MTK_M4U_ID(M4U_LARB10_ID, 23) -#define M4U_PORT_CAM_FLKO_R1_B MTK_M4U_ID(M4U_LARB10_ID, 24) -#define M4U_PORT_CAM_LCESO_R1_B MTK_M4U_ID(M4U_LARB10_ID, 25) -#define M4U_PORT_CAM_CRZO_R1_B MTK_M4U_ID(M4U_LARB10_ID, 26) -#define M4U_PORT_CAM_LTMSO_R1_A MTK_M4U_ID(M4U_LARB10_ID, 27) -#define M4U_PORT_CAM_RSSO_R1_A MTK_M4U_ID(M4U_LARB10_ID, 28) -#define M4U_PORT_CAM_LTMSO_R1_B MTK_M4U_ID(M4U_LARB10_ID, 29) -#define M4U_PORT_CAM_RSSO_R1_B MTK_M4U_ID(M4U_LARB10_ID, 30) - -/* larb11-CAM-VPU */ -#define M4U_PORT_CAM_IPUO MTK_M4U_ID(M4U_LARB11_ID, 0) -#define M4U_PORT_CAM_IPU2O MTK_M4U_ID(M4U_LARB11_ID, 1) -#define M4U_PORT_CAM_IPU3O MTK_M4U_ID(M4U_LARB11_ID, 2) -#define M4U_PORT_CAM_IPUI MTK_M4U_ID(M4U_LARB11_ID, 3) -#define M4U_PORT_CAM_IPU2I MTK_M4U_ID(M4U_LARB11_ID, 4) - -#endif diff --git a/include/dt-bindings/memory/mt6795-larb-port.h b/include/dt-bindings/memory/mt6795-larb-port.h deleted file mode 100644 index 58cf6a6b637..00000000000 --- a/include/dt-bindings/memory/mt6795-larb-port.h +++ /dev/null @@ -1,95 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ -/* - * Copyright (c) 2022 Collabora Ltd. - * Author: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> - */ - -#ifndef _DT_BINDINGS_MEMORY_MT6795_LARB_PORT_H_ -#define _DT_BINDINGS_MEMORY_MT6795_LARB_PORT_H_ - -#include <dt-bindings/memory/mtk-memory-port.h> - -#define M4U_LARB0_ID 0 -#define M4U_LARB1_ID 1 -#define M4U_LARB2_ID 2 -#define M4U_LARB3_ID 3 -#define M4U_LARB4_ID 4 - -/* larb0 */ -#define M4U_PORT_DISP_OVL0 MTK_M4U_ID(M4U_LARB0_ID, 0) -#define M4U_PORT_DISP_RDMA0 MTK_M4U_ID(M4U_LARB0_ID, 1) -#define M4U_PORT_DISP_RDMA1 MTK_M4U_ID(M4U_LARB0_ID, 2) -#define M4U_PORT_DISP_WDMA0 MTK_M4U_ID(M4U_LARB0_ID, 3) -#define M4U_PORT_DISP_OVL1 MTK_M4U_ID(M4U_LARB0_ID, 4) -#define M4U_PORT_DISP_RDMA2 MTK_M4U_ID(M4U_LARB0_ID, 5) -#define M4U_PORT_DISP_WDMA1 MTK_M4U_ID(M4U_LARB0_ID, 6) -#define M4U_PORT_DISP_OD_R MTK_M4U_ID(M4U_LARB0_ID, 7) -#define M4U_PORT_DISP_OD_W MTK_M4U_ID(M4U_LARB0_ID, 8) -#define M4U_PORT_MDP_RDMA0 MTK_M4U_ID(M4U_LARB0_ID, 9) -#define M4U_PORT_MDP_RDMA1 MTK_M4U_ID(M4U_LARB0_ID, 10) -#define M4U_PORT_MDP_WDMA MTK_M4U_ID(M4U_LARB0_ID, 11) -#define M4U_PORT_MDP_WROT0 MTK_M4U_ID(M4U_LARB0_ID, 12) -#define M4U_PORT_MDP_WROT1 MTK_M4U_ID(M4U_LARB0_ID, 13) - -/* larb1 */ -#define M4U_PORT_VDEC_MC MTK_M4U_ID(M4U_LARB1_ID, 0) -#define M4U_PORT_VDEC_PP MTK_M4U_ID(M4U_LARB1_ID, 1) -#define M4U_PORT_VDEC_UFO MTK_M4U_ID(M4U_LARB1_ID, 2) -#define M4U_PORT_VDEC_VLD MTK_M4U_ID(M4U_LARB1_ID, 3) -#define M4U_PORT_VDEC_VLD2 MTK_M4U_ID(M4U_LARB1_ID, 4) -#define M4U_PORT_VDEC_AVC_MV MTK_M4U_ID(M4U_LARB1_ID, 5) -#define M4U_PORT_VDEC_PRED_RD MTK_M4U_ID(M4U_LARB1_ID, 6) -#define M4U_PORT_VDEC_PRED_WR MTK_M4U_ID(M4U_LARB1_ID, 7) -#define M4U_PORT_VDEC_PPWRAP MTK_M4U_ID(M4U_LARB1_ID, 8) - -/* larb2 */ -#define M4U_PORT_CAM_IMGO MTK_M4U_ID(M4U_LARB2_ID, 0) -#define M4U_PORT_CAM_RRZO MTK_M4U_ID(M4U_LARB2_ID, 1) -#define M4U_PORT_CAM_AAO MTK_M4U_ID(M4U_LARB2_ID, 2) -#define M4U_PORT_CAM_LCSO MTK_M4U_ID(M4U_LARB2_ID, 3) -#define M4U_PORT_CAM_ESFKO MTK_M4U_ID(M4U_LARB2_ID, 4) -#define M4U_PORT_CAM_IMGO_S MTK_M4U_ID(M4U_LARB2_ID, 5) -#define M4U_PORT_CAM_LSCI MTK_M4U_ID(M4U_LARB2_ID, 6) -#define M4U_PORT_CAM_LSCI_D MTK_M4U_ID(M4U_LARB2_ID, 7) -#define M4U_PORT_CAM_BPCI MTK_M4U_ID(M4U_LARB2_ID, 8) -#define M4U_PORT_CAM_BPCI_D MTK_M4U_ID(M4U_LARB2_ID, 9) -#define M4U_PORT_CAM_UFDI MTK_M4U_ID(M4U_LARB2_ID, 10) -#define M4U_PORT_CAM_IMGI MTK_M4U_ID(M4U_LARB2_ID, 11) -#define M4U_PORT_CAM_IMG2O MTK_M4U_ID(M4U_LARB2_ID, 12) -#define M4U_PORT_CAM_IMG3O MTK_M4U_ID(M4U_LARB2_ID, 13) -#define M4U_PORT_CAM_VIPI MTK_M4U_ID(M4U_LARB2_ID, 14) -#define M4U_PORT_CAM_VIP2I MTK_M4U_ID(M4U_LARB2_ID, 15) -#define M4U_PORT_CAM_VIP3I MTK_M4U_ID(M4U_LARB2_ID, 16) -#define M4U_PORT_CAM_LCEI MTK_M4U_ID(M4U_LARB2_ID, 17) -#define M4U_PORT_CAM_RB MTK_M4U_ID(M4U_LARB2_ID, 18) -#define M4U_PORT_CAM_RP MTK_M4U_ID(M4U_LARB2_ID, 19) -#define M4U_PORT_CAM_WR MTK_M4U_ID(M4U_LARB2_ID, 20) - -/* larb3 */ -#define M4U_PORT_VENC_RCPU MTK_M4U_ID(M4U_LARB3_ID, 0) -#define M4U_PORT_VENC_REC MTK_M4U_ID(M4U_LARB3_ID, 1) -#define M4U_PORT_VENC_BSDMA MTK_M4U_ID(M4U_LARB3_ID, 2) -#define M4U_PORT_VENC_SV_COMV MTK_M4U_ID(M4U_LARB3_ID, 3) -#define M4U_PORT_VENC_RD_COMV MTK_M4U_ID(M4U_LARB3_ID, 4) -#define M4U_PORT_JPGENC_BSDMA MTK_M4U_ID(M4U_LARB3_ID, 5) -#define M4U_PORT_REMDC_SDMA MTK_M4U_ID(M4U_LARB3_ID, 6) -#define M4U_PORT_REMDC_BSDMA MTK_M4U_ID(M4U_LARB3_ID, 7) -#define M4U_PORT_JPGENC_RDMA MTK_M4U_ID(M4U_LARB3_ID, 8) -#define M4U_PORT_JPGENC_SDMA MTK_M4U_ID(M4U_LARB3_ID, 9) -#define M4U_PORT_JPGDEC_WDMA MTK_M4U_ID(M4U_LARB3_ID, 10) -#define M4U_PORT_JPGDEC_BSDMA MTK_M4U_ID(M4U_LARB3_ID, 11) -#define M4U_PORT_VENC_CUR_LUMA MTK_M4U_ID(M4U_LARB3_ID, 12) -#define M4U_PORT_VENC_CUR_CHROMA MTK_M4U_ID(M4U_LARB3_ID, 13) -#define M4U_PORT_VENC_REF_LUMA MTK_M4U_ID(M4U_LARB3_ID, 14) -#define M4U_PORT_VENC_REF_CHROMA MTK_M4U_ID(M4U_LARB3_ID, 15) -#define M4U_PORT_REMDC_WDMA MTK_M4U_ID(M4U_LARB3_ID, 16) -#define M4U_PORT_VENC_NBM_RDMA MTK_M4U_ID(M4U_LARB3_ID, 17) -#define M4U_PORT_VENC_NBM_WDMA MTK_M4U_ID(M4U_LARB3_ID, 18) - -/* larb4 */ -#define M4U_PORT_MJC_MV_RD MTK_M4U_ID(M4U_LARB4_ID, 0) -#define M4U_PORT_MJC_MV_WR MTK_M4U_ID(M4U_LARB4_ID, 1) -#define M4U_PORT_MJC_DMA_RD MTK_M4U_ID(M4U_LARB4_ID, 2) -#define M4U_PORT_MJC_DMA_WR MTK_M4U_ID(M4U_LARB4_ID, 3) - -#endif diff --git a/include/dt-bindings/memory/mt8167-larb-port.h b/include/dt-bindings/memory/mt8167-larb-port.h deleted file mode 100644 index aae57d4824c..00000000000 --- a/include/dt-bindings/memory/mt8167-larb-port.h +++ /dev/null @@ -1,51 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2020 MediaTek Inc. - * Copyright (c) 2020 BayLibre, SAS - * Author: Honghui Zhang <honghui.zhang@mediatek.com> - * Author: Fabien Parent <fparent@baylibre.com> - */ -#ifndef _DT_BINDINGS_MEMORY_MT8167_LARB_PORT_H_ -#define _DT_BINDINGS_MEMORY_MT8167_LARB_PORT_H_ - -#include <dt-bindings/memory/mtk-memory-port.h> - -#define M4U_LARB0_ID 0 -#define M4U_LARB1_ID 1 -#define M4U_LARB2_ID 2 - -/* larb0 */ -#define M4U_PORT_DISP_OVL0 MTK_M4U_ID(M4U_LARB0_ID, 0) -#define M4U_PORT_DISP_RDMA0 MTK_M4U_ID(M4U_LARB0_ID, 1) -#define M4U_PORT_DISP_WDMA0 MTK_M4U_ID(M4U_LARB0_ID, 2) -#define M4U_PORT_DISP_RDMA1 MTK_M4U_ID(M4U_LARB0_ID, 3) -#define M4U_PORT_MDP_RDMA MTK_M4U_ID(M4U_LARB0_ID, 4) -#define M4U_PORT_MDP_WDMA MTK_M4U_ID(M4U_LARB0_ID, 5) -#define M4U_PORT_MDP_WROT MTK_M4U_ID(M4U_LARB0_ID, 6) -#define M4U_PORT_DISP_FAKE MTK_M4U_ID(M4U_LARB0_ID, 7) - -/* larb1*/ -#define M4U_PORT_CAM_IMGO MTK_M4U_ID(M4U_LARB1_ID, 0) -#define M4U_PORT_CAM_IMG2O MTK_M4U_ID(M4U_LARB1_ID, 1) -#define M4U_PORT_CAM_LSCI MTK_M4U_ID(M4U_LARB1_ID, 2) -#define M4U_PORT_CAM_ESFKO MTK_M4U_ID(M4U_LARB1_ID, 3) -#define M4U_PORT_CAM_AAO MTK_M4U_ID(M4U_LARB1_ID, 4) -#define M4U_PORT_VENC_REC MTK_M4U_ID(M4U_LARB1_ID, 5) -#define M4U_PORT_VENC_BSDMA MTK_M4U_ID(M4U_LARB1_ID, 6) -#define M4U_PORT_VENC_RD_COMV MTK_M4U_ID(M4U_LARB1_ID, 7) -#define M4U_PORT_CAM_IMGI MTK_M4U_ID(M4U_LARB1_ID, 8) -#define M4U_PORT_VENC_CUR_LUMA MTK_M4U_ID(M4U_LARB1_ID, 9) -#define M4U_PORT_VENC_CUR_CHROMA MTK_M4U_ID(M4U_LARB1_ID, 10) -#define M4U_PORT_VENC_REF_LUMA MTK_M4U_ID(M4U_LARB1_ID, 11) -#define M4U_PORT_VENC_REF_CHROMA MTK_M4U_ID(M4U_LARB1_ID, 12) - -/* larb2*/ -#define M4U_PORT_HW_VDEC_MC_EXT MTK_M4U_ID(M4U_LARB2_ID, 0) -#define M4U_PORT_HW_VDEC_PP_EXT MTK_M4U_ID(M4U_LARB2_ID, 1) -#define M4U_PORT_HW_VDEC_VLD_EXT MTK_M4U_ID(M4U_LARB2_ID, 2) -#define M4U_PORT_HW_VDEC_AVC_MV_EXT MTK_M4U_ID(M4U_LARB2_ID, 3) -#define M4U_PORT_HW_VDEC_PRED_RD_EXT MTK_M4U_ID(M4U_LARB2_ID, 4) -#define M4U_PORT_HW_VDEC_PRED_WR_EXT MTK_M4U_ID(M4U_LARB2_ID, 5) -#define M4U_PORT_HW_VDEC_PPWRAP_EXT MTK_M4U_ID(M4U_LARB2_ID, 6) - -#endif diff --git a/include/dt-bindings/memory/mt8173-larb-port.h b/include/dt-bindings/memory/mt8173-larb-port.h deleted file mode 100644 index 167a7fc5186..00000000000 --- a/include/dt-bindings/memory/mt8173-larb-port.h +++ /dev/null @@ -1,99 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2015-2016 MediaTek Inc. - * Author: Yong Wu <yong.wu@mediatek.com> - */ -#ifndef _DT_BINDINGS_MEMORY_MT8173_LARB_PORT_H_ -#define _DT_BINDINGS_MEMORY_MT8173_LARB_PORT_H_ - -#include <dt-bindings/memory/mtk-memory-port.h> - -#define M4U_LARB0_ID 0 -#define M4U_LARB1_ID 1 -#define M4U_LARB2_ID 2 -#define M4U_LARB3_ID 3 -#define M4U_LARB4_ID 4 -#define M4U_LARB5_ID 5 - -/* larb0 */ -#define M4U_PORT_DISP_OVL0 MTK_M4U_ID(M4U_LARB0_ID, 0) -#define M4U_PORT_DISP_RDMA0 MTK_M4U_ID(M4U_LARB0_ID, 1) -#define M4U_PORT_DISP_WDMA0 MTK_M4U_ID(M4U_LARB0_ID, 2) -#define M4U_PORT_DISP_OD_R MTK_M4U_ID(M4U_LARB0_ID, 3) -#define M4U_PORT_DISP_OD_W MTK_M4U_ID(M4U_LARB0_ID, 4) -#define M4U_PORT_MDP_RDMA0 MTK_M4U_ID(M4U_LARB0_ID, 5) -#define M4U_PORT_MDP_WDMA MTK_M4U_ID(M4U_LARB0_ID, 6) -#define M4U_PORT_MDP_WROT0 MTK_M4U_ID(M4U_LARB0_ID, 7) - -/* larb1 */ -#define M4U_PORT_HW_VDEC_MC_EXT MTK_M4U_ID(M4U_LARB1_ID, 0) -#define M4U_PORT_HW_VDEC_PP_EXT MTK_M4U_ID(M4U_LARB1_ID, 1) -#define M4U_PORT_HW_VDEC_UFO_EXT MTK_M4U_ID(M4U_LARB1_ID, 2) -#define M4U_PORT_HW_VDEC_VLD_EXT MTK_M4U_ID(M4U_LARB1_ID, 3) -#define M4U_PORT_HW_VDEC_VLD2_EXT MTK_M4U_ID(M4U_LARB1_ID, 4) -#define M4U_PORT_HW_VDEC_AVC_MV_EXT MTK_M4U_ID(M4U_LARB1_ID, 5) -#define M4U_PORT_HW_VDEC_PRED_RD_EXT MTK_M4U_ID(M4U_LARB1_ID, 6) -#define M4U_PORT_HW_VDEC_PRED_WR_EXT MTK_M4U_ID(M4U_LARB1_ID, 7) -#define M4U_PORT_HW_VDEC_PPWRAP_EXT MTK_M4U_ID(M4U_LARB1_ID, 8) -#define M4U_PORT_HW_VDEC_TILE MTK_M4U_ID(M4U_LARB1_ID, 9) - -/* larb2 */ -#define M4U_PORT_IMGO MTK_M4U_ID(M4U_LARB2_ID, 0) -#define M4U_PORT_RRZO MTK_M4U_ID(M4U_LARB2_ID, 1) -#define M4U_PORT_AAO MTK_M4U_ID(M4U_LARB2_ID, 2) -#define M4U_PORT_LCSO MTK_M4U_ID(M4U_LARB2_ID, 3) -#define M4U_PORT_ESFKO MTK_M4U_ID(M4U_LARB2_ID, 4) -#define M4U_PORT_IMGO_D MTK_M4U_ID(M4U_LARB2_ID, 5) -#define M4U_PORT_LSCI MTK_M4U_ID(M4U_LARB2_ID, 6) -#define M4U_PORT_LSCI_D MTK_M4U_ID(M4U_LARB2_ID, 7) -#define M4U_PORT_BPCI MTK_M4U_ID(M4U_LARB2_ID, 8) -#define M4U_PORT_BPCI_D MTK_M4U_ID(M4U_LARB2_ID, 9) -#define M4U_PORT_UFDI MTK_M4U_ID(M4U_LARB2_ID, 10) -#define M4U_PORT_IMGI MTK_M4U_ID(M4U_LARB2_ID, 11) -#define M4U_PORT_IMG2O MTK_M4U_ID(M4U_LARB2_ID, 12) -#define M4U_PORT_IMG3O MTK_M4U_ID(M4U_LARB2_ID, 13) -#define M4U_PORT_VIPI MTK_M4U_ID(M4U_LARB2_ID, 14) -#define M4U_PORT_VIP2I MTK_M4U_ID(M4U_LARB2_ID, 15) -#define M4U_PORT_VIP3I MTK_M4U_ID(M4U_LARB2_ID, 16) -#define M4U_PORT_LCEI MTK_M4U_ID(M4U_LARB2_ID, 17) -#define M4U_PORT_RB MTK_M4U_ID(M4U_LARB2_ID, 18) -#define M4U_PORT_RP MTK_M4U_ID(M4U_LARB2_ID, 19) -#define M4U_PORT_WR MTK_M4U_ID(M4U_LARB2_ID, 20) - -/* larb3 */ -#define M4U_PORT_VENC_RCPU MTK_M4U_ID(M4U_LARB3_ID, 0) -#define M4U_PORT_VENC_REC MTK_M4U_ID(M4U_LARB3_ID, 1) -#define M4U_PORT_VENC_BSDMA MTK_M4U_ID(M4U_LARB3_ID, 2) -#define M4U_PORT_VENC_SV_COMV MTK_M4U_ID(M4U_LARB3_ID, 3) -#define M4U_PORT_VENC_RD_COMV MTK_M4U_ID(M4U_LARB3_ID, 4) -#define M4U_PORT_JPGENC_RDMA MTK_M4U_ID(M4U_LARB3_ID, 5) -#define M4U_PORT_JPGENC_BSDMA MTK_M4U_ID(M4U_LARB3_ID, 6) -#define M4U_PORT_JPGDEC_WDMA MTK_M4U_ID(M4U_LARB3_ID, 7) -#define M4U_PORT_JPGDEC_BSDMA MTK_M4U_ID(M4U_LARB3_ID, 8) -#define M4U_PORT_VENC_CUR_LUMA MTK_M4U_ID(M4U_LARB3_ID, 9) -#define M4U_PORT_VENC_CUR_CHROMA MTK_M4U_ID(M4U_LARB3_ID, 10) -#define M4U_PORT_VENC_REF_LUMA MTK_M4U_ID(M4U_LARB3_ID, 11) -#define M4U_PORT_VENC_REF_CHROMA MTK_M4U_ID(M4U_LARB3_ID, 12) -#define M4U_PORT_VENC_NBM_RDMA MTK_M4U_ID(M4U_LARB3_ID, 13) -#define M4U_PORT_VENC_NBM_WDMA MTK_M4U_ID(M4U_LARB3_ID, 14) - -/* larb4 */ -#define M4U_PORT_DISP_OVL1 MTK_M4U_ID(M4U_LARB4_ID, 0) -#define M4U_PORT_DISP_RDMA1 MTK_M4U_ID(M4U_LARB4_ID, 1) -#define M4U_PORT_DISP_RDMA2 MTK_M4U_ID(M4U_LARB4_ID, 2) -#define M4U_PORT_DISP_WDMA1 MTK_M4U_ID(M4U_LARB4_ID, 3) -#define M4U_PORT_MDP_RDMA1 MTK_M4U_ID(M4U_LARB4_ID, 4) -#define M4U_PORT_MDP_WROT1 MTK_M4U_ID(M4U_LARB4_ID, 5) - -/* larb5 */ -#define M4U_PORT_VENC_RCPU_SET2 MTK_M4U_ID(M4U_LARB5_ID, 0) -#define M4U_PORT_VENC_REC_FRM_SET2 MTK_M4U_ID(M4U_LARB5_ID, 1) -#define M4U_PORT_VENC_REF_LUMA_SET2 MTK_M4U_ID(M4U_LARB5_ID, 2) -#define M4U_PORT_VENC_REC_CHROMA_SET2 MTK_M4U_ID(M4U_LARB5_ID, 3) -#define M4U_PORT_VENC_BSDMA_SET2 MTK_M4U_ID(M4U_LARB5_ID, 4) -#define M4U_PORT_VENC_CUR_LUMA_SET2 MTK_M4U_ID(M4U_LARB5_ID, 5) -#define M4U_PORT_VENC_CUR_CHROMA_SET2 MTK_M4U_ID(M4U_LARB5_ID, 6) -#define M4U_PORT_VENC_RD_COMA_SET2 MTK_M4U_ID(M4U_LARB5_ID, 7) -#define M4U_PORT_VENC_SV_COMA_SET2 MTK_M4U_ID(M4U_LARB5_ID, 8) - -#endif diff --git a/include/dt-bindings/memory/mt8183-larb-port.h b/include/dt-bindings/memory/mt8183-larb-port.h deleted file mode 100644 index 36abdf0ce5a..00000000000 --- a/include/dt-bindings/memory/mt8183-larb-port.h +++ /dev/null @@ -1,130 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2018 MediaTek Inc. - * Author: Yong Wu <yong.wu@mediatek.com> - */ -#ifndef _DT_BINDINGS_MEMORY_MT8183_LARB_PORT_H_ -#define _DT_BINDINGS_MEMORY_MT8183_LARB_PORT_H_ - -#include <dt-bindings/memory/mtk-memory-port.h> - -#define M4U_LARB0_ID 0 -#define M4U_LARB1_ID 1 -#define M4U_LARB2_ID 2 -#define M4U_LARB3_ID 3 -#define M4U_LARB4_ID 4 -#define M4U_LARB5_ID 5 -#define M4U_LARB6_ID 6 -#define M4U_LARB7_ID 7 - -/* larb0 */ -#define M4U_PORT_DISP_OVL0 MTK_M4U_ID(M4U_LARB0_ID, 0) -#define M4U_PORT_DISP_2L_OVL0_LARB0 MTK_M4U_ID(M4U_LARB0_ID, 1) -#define M4U_PORT_DISP_2L_OVL1_LARB0 MTK_M4U_ID(M4U_LARB0_ID, 2) -#define M4U_PORT_DISP_RDMA0 MTK_M4U_ID(M4U_LARB0_ID, 3) -#define M4U_PORT_DISP_RDMA1 MTK_M4U_ID(M4U_LARB0_ID, 4) -#define M4U_PORT_DISP_WDMA0 MTK_M4U_ID(M4U_LARB0_ID, 5) -#define M4U_PORT_MDP_RDMA0 MTK_M4U_ID(M4U_LARB0_ID, 6) -#define M4U_PORT_MDP_WROT0 MTK_M4U_ID(M4U_LARB0_ID, 7) -#define M4U_PORT_MDP_WDMA0 MTK_M4U_ID(M4U_LARB0_ID, 8) -#define M4U_PORT_DISP_FAKE0 MTK_M4U_ID(M4U_LARB0_ID, 9) - -/* larb1 */ -#define M4U_PORT_HW_VDEC_MC_EXT MTK_M4U_ID(M4U_LARB1_ID, 0) -#define M4U_PORT_HW_VDEC_PP_EXT MTK_M4U_ID(M4U_LARB1_ID, 1) -#define M4U_PORT_HW_VDEC_VLD_EXT MTK_M4U_ID(M4U_LARB1_ID, 2) -#define M4U_PORT_HW_VDEC_AVC_MV_EXT MTK_M4U_ID(M4U_LARB1_ID, 3) -#define M4U_PORT_HW_VDEC_PRED_RD_EXT MTK_M4U_ID(M4U_LARB1_ID, 4) -#define M4U_PORT_HW_VDEC_PRED_WR_EXT MTK_M4U_ID(M4U_LARB1_ID, 5) -#define M4U_PORT_HW_VDEC_PPWRAP_EXT MTK_M4U_ID(M4U_LARB1_ID, 6) - -/* larb2 VPU0 */ -#define M4U_PORT_IMG_IPUO MTK_M4U_ID(M4U_LARB2_ID, 0) -#define M4U_PORT_IMG_IPU3O MTK_M4U_ID(M4U_LARB2_ID, 1) -#define M4U_PORT_IMG_IPUI MTK_M4U_ID(M4U_LARB2_ID, 2) - -/* larb3 VPU1 */ -#define M4U_PORT_CAM_IPUO MTK_M4U_ID(M4U_LARB3_ID, 0) -#define M4U_PORT_CAM_IPU2O MTK_M4U_ID(M4U_LARB3_ID, 1) -#define M4U_PORT_CAM_IPU3O MTK_M4U_ID(M4U_LARB3_ID, 2) -#define M4U_PORT_CAM_IPUI MTK_M4U_ID(M4U_LARB3_ID, 3) -#define M4U_PORT_CAM_IPU2I MTK_M4U_ID(M4U_LARB3_ID, 4) - -/* larb4 */ -#define M4U_PORT_VENC_RCPU MTK_M4U_ID(M4U_LARB4_ID, 0) -#define M4U_PORT_VENC_REC MTK_M4U_ID(M4U_LARB4_ID, 1) -#define M4U_PORT_VENC_BSDMA MTK_M4U_ID(M4U_LARB4_ID, 2) -#define M4U_PORT_VENC_SV_COMV MTK_M4U_ID(M4U_LARB4_ID, 3) -#define M4U_PORT_VENC_RD_COMV MTK_M4U_ID(M4U_LARB4_ID, 4) -#define M4U_PORT_JPGENC_RDMA MTK_M4U_ID(M4U_LARB4_ID, 5) -#define M4U_PORT_JPGENC_BSDMA MTK_M4U_ID(M4U_LARB4_ID, 6) -#define M4U_PORT_VENC_CUR_LUMA MTK_M4U_ID(M4U_LARB4_ID, 7) -#define M4U_PORT_VENC_CUR_CHROMA MTK_M4U_ID(M4U_LARB4_ID, 8) -#define M4U_PORT_VENC_REF_LUMA MTK_M4U_ID(M4U_LARB4_ID, 9) -#define M4U_PORT_VENC_REF_CHROMA MTK_M4U_ID(M4U_LARB4_ID, 10) - -/* larb5 */ -#define M4U_PORT_CAM_IMGI MTK_M4U_ID(M4U_LARB5_ID, 0) -#define M4U_PORT_CAM_IMG2O MTK_M4U_ID(M4U_LARB5_ID, 1) -#define M4U_PORT_CAM_IMG3O MTK_M4U_ID(M4U_LARB5_ID, 2) -#define M4U_PORT_CAM_VIPI MTK_M4U_ID(M4U_LARB5_ID, 3) -#define M4U_PORT_CAM_LCEI MTK_M4U_ID(M4U_LARB5_ID, 4) -#define M4U_PORT_CAM_SMXI MTK_M4U_ID(M4U_LARB5_ID, 5) -#define M4U_PORT_CAM_SMXO MTK_M4U_ID(M4U_LARB5_ID, 6) -#define M4U_PORT_CAM_WPE0_RDMA1 MTK_M4U_ID(M4U_LARB5_ID, 7) -#define M4U_PORT_CAM_WPE0_RDMA0 MTK_M4U_ID(M4U_LARB5_ID, 8) -#define M4U_PORT_CAM_WPE0_WDMA MTK_M4U_ID(M4U_LARB5_ID, 9) -#define M4U_PORT_CAM_FDVT_RP MTK_M4U_ID(M4U_LARB5_ID, 10) -#define M4U_PORT_CAM_FDVT_WR MTK_M4U_ID(M4U_LARB5_ID, 11) -#define M4U_PORT_CAM_FDVT_RB MTK_M4U_ID(M4U_LARB5_ID, 12) -#define M4U_PORT_CAM_WPE1_RDMA0 MTK_M4U_ID(M4U_LARB5_ID, 13) -#define M4U_PORT_CAM_WPE1_RDMA1 MTK_M4U_ID(M4U_LARB5_ID, 14) -#define M4U_PORT_CAM_WPE1_WDMA MTK_M4U_ID(M4U_LARB5_ID, 15) -#define M4U_PORT_CAM_DPE_RDMA MTK_M4U_ID(M4U_LARB5_ID, 16) -#define M4U_PORT_CAM_DPE_WDMA MTK_M4U_ID(M4U_LARB5_ID, 17) -#define M4U_PORT_CAM_MFB_RDMA0 MTK_M4U_ID(M4U_LARB5_ID, 18) -#define M4U_PORT_CAM_MFB_RDMA1 MTK_M4U_ID(M4U_LARB5_ID, 19) -#define M4U_PORT_CAM_MFB_WDMA MTK_M4U_ID(M4U_LARB5_ID, 20) -#define M4U_PORT_CAM_RSC_RDMA0 MTK_M4U_ID(M4U_LARB5_ID, 21) -#define M4U_PORT_CAM_RSC_WDMA MTK_M4U_ID(M4U_LARB5_ID, 22) -#define M4U_PORT_CAM_OWE_RDMA MTK_M4U_ID(M4U_LARB5_ID, 23) -#define M4U_PORT_CAM_OWE_WDMA MTK_M4U_ID(M4U_LARB5_ID, 24) - -/* larb6 */ -#define M4U_PORT_CAM_IMGO MTK_M4U_ID(M4U_LARB6_ID, 0) -#define M4U_PORT_CAM_RRZO MTK_M4U_ID(M4U_LARB6_ID, 1) -#define M4U_PORT_CAM_AAO MTK_M4U_ID(M4U_LARB6_ID, 2) -#define M4U_PORT_CAM_AFO MTK_M4U_ID(M4U_LARB6_ID, 3) -#define M4U_PORT_CAM_LSCI0 MTK_M4U_ID(M4U_LARB6_ID, 4) -#define M4U_PORT_CAM_LSCI1 MTK_M4U_ID(M4U_LARB6_ID, 5) -#define M4U_PORT_CAM_PDO MTK_M4U_ID(M4U_LARB6_ID, 6) -#define M4U_PORT_CAM_BPCI MTK_M4U_ID(M4U_LARB6_ID, 7) -#define M4U_PORT_CAM_LCSO MTK_M4U_ID(M4U_LARB6_ID, 8) -#define M4U_PORT_CAM_CAM_RSSO_A MTK_M4U_ID(M4U_LARB6_ID, 9) -#define M4U_PORT_CAM_UFEO MTK_M4U_ID(M4U_LARB6_ID, 10) -#define M4U_PORT_CAM_SOCO MTK_M4U_ID(M4U_LARB6_ID, 11) -#define M4U_PORT_CAM_SOC1 MTK_M4U_ID(M4U_LARB6_ID, 12) -#define M4U_PORT_CAM_SOC2 MTK_M4U_ID(M4U_LARB6_ID, 13) -#define M4U_PORT_CAM_CCUI MTK_M4U_ID(M4U_LARB6_ID, 14) -#define M4U_PORT_CAM_CCUO MTK_M4U_ID(M4U_LARB6_ID, 15) -#define M4U_PORT_CAM_RAWI_A MTK_M4U_ID(M4U_LARB6_ID, 16) -#define M4U_PORT_CAM_CCUG MTK_M4U_ID(M4U_LARB6_ID, 17) -#define M4U_PORT_CAM_PSO MTK_M4U_ID(M4U_LARB6_ID, 18) -#define M4U_PORT_CAM_AFO_1 MTK_M4U_ID(M4U_LARB6_ID, 19) -#define M4U_PORT_CAM_LSCI_2 MTK_M4U_ID(M4U_LARB6_ID, 20) -#define M4U_PORT_CAM_PDI MTK_M4U_ID(M4U_LARB6_ID, 21) -#define M4U_PORT_CAM_FLKO MTK_M4U_ID(M4U_LARB6_ID, 22) -#define M4U_PORT_CAM_LMVO MTK_M4U_ID(M4U_LARB6_ID, 23) -#define M4U_PORT_CAM_UFGO MTK_M4U_ID(M4U_LARB6_ID, 24) -#define M4U_PORT_CAM_SPARE MTK_M4U_ID(M4U_LARB6_ID, 25) -#define M4U_PORT_CAM_SPARE_2 MTK_M4U_ID(M4U_LARB6_ID, 26) -#define M4U_PORT_CAM_SPARE_3 MTK_M4U_ID(M4U_LARB6_ID, 27) -#define M4U_PORT_CAM_SPARE_4 MTK_M4U_ID(M4U_LARB6_ID, 28) -#define M4U_PORT_CAM_SPARE_5 MTK_M4U_ID(M4U_LARB6_ID, 29) -#define M4U_PORT_CAM_SPARE_6 MTK_M4U_ID(M4U_LARB6_ID, 30) - -/* CCU */ -#define M4U_PORT_CCU0 MTK_M4U_ID(M4U_LARB7_ID, 0) -#define M4U_PORT_CCU1 MTK_M4U_ID(M4U_LARB7_ID, 1) - -#endif diff --git a/include/dt-bindings/memory/mt8186-memory-port.h b/include/dt-bindings/memory/mt8186-memory-port.h deleted file mode 100644 index 2bc6e443304..00000000000 --- a/include/dt-bindings/memory/mt8186-memory-port.h +++ /dev/null @@ -1,217 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2022 MediaTek Inc. - * - * Author: Anan Sun <anan.sun@mediatek.com> - * Author: Yong Wu <yong.wu@mediatek.com> - */ -#ifndef _DT_BINDINGS_MEMORY_MT8186_LARB_PORT_H_ -#define _DT_BINDINGS_MEMORY_MT8186_LARB_PORT_H_ - -#include <dt-bindings/memory/mtk-memory-port.h> - -/* - * MM IOMMU supports 16GB dma address. We separate it to four ranges: - * 0 ~ 4G; 4G ~ 8G; 8G ~ 12G; 12G ~ 16G, we could adjust these masters - * locate in anyone region. BUT: - * a) Make sure all the ports inside a larb are in one range. - * b) The iova of any master can NOT cross the 4G/8G/12G boundary. - * - * This is the suggested mapping in this SoC: - * - * modules dma-address-region larbs-ports - * disp 0 ~ 4G larb0/1/2 - * vcodec 4G ~ 8G larb4/7 - * cam/mdp 8G ~ 12G the other larbs. - * N/A 12G ~ 16G - * CCU0 0x24000_0000 ~ 0x243ff_ffff larb13: port 9/10 - * CCU1 0x24400_0000 ~ 0x247ff_ffff larb14: port 4/5 - */ - -/* MM IOMMU ports */ -/* LARB 0 -- MMSYS */ -#define IOMMU_PORT_L0_DISP_POSTMASK0 MTK_M4U_ID(0, 0) -#define IOMMU_PORT_L0_REVERSED MTK_M4U_ID(0, 1) -#define IOMMU_PORT_L0_OVL_RDMA0 MTK_M4U_ID(0, 2) -#define IOMMU_PORT_L0_DISP_FAKE0 MTK_M4U_ID(0, 3) - -/* LARB 1 -- MMSYS */ -#define IOMMU_PORT_L1_DISP_RDMA1 MTK_M4U_ID(1, 0) -#define IOMMU_PORT_L1_OVL_2L_RDMA0 MTK_M4U_ID(1, 1) -#define IOMMU_PORT_L1_DISP_RDMA0 MTK_M4U_ID(1, 2) -#define IOMMU_PORT_L1_DISP_WDMA0 MTK_M4U_ID(1, 3) -#define IOMMU_PORT_L1_DISP_FAKE1 MTK_M4U_ID(1, 4) - -/* LARB 2 -- MMSYS */ -#define IOMMU_PORT_L2_MDP_RDMA0 MTK_M4U_ID(2, 0) -#define IOMMU_PORT_L2_MDP_RDMA1 MTK_M4U_ID(2, 1) -#define IOMMU_PORT_L2_MDP_WROT0 MTK_M4U_ID(2, 2) -#define IOMMU_PORT_L2_MDP_WROT1 MTK_M4U_ID(2, 3) -#define IOMMU_PORT_L2_DISP_FAKE0 MTK_M4U_ID(2, 4) - -/* LARB 4 -- VDEC */ -#define IOMMU_PORT_L4_HW_VDEC_MC_EXT MTK_M4U_ID(4, 0) -#define IOMMU_PORT_L4_HW_VDEC_UFO_EXT MTK_M4U_ID(4, 1) -#define IOMMU_PORT_L4_HW_VDEC_PP_EXT MTK_M4U_ID(4, 2) -#define IOMMU_PORT_L4_HW_VDEC_PRED_RD_EXT MTK_M4U_ID(4, 3) -#define IOMMU_PORT_L4_HW_VDEC_PRED_WR_EXT MTK_M4U_ID(4, 4) -#define IOMMU_PORT_L4_HW_VDEC_PPWRAP_EXT MTK_M4U_ID(4, 5) -#define IOMMU_PORT_L4_HW_VDEC_TILE_EXT MTK_M4U_ID(4, 6) -#define IOMMU_PORT_L4_HW_VDEC_VLD_EXT MTK_M4U_ID(4, 7) -#define IOMMU_PORT_L4_HW_VDEC_VLD2_EXT MTK_M4U_ID(4, 8) -#define IOMMU_PORT_L4_HW_VDEC_AVC_MV_EXT MTK_M4U_ID(4, 9) -#define IOMMU_PORT_L4_HW_VDEC_UFO_ENC_EXT MTK_M4U_ID(4, 10) -#define IOMMU_PORT_L4_HW_VDEC_RG_CTRL_DMA_EXT MTK_M4U_ID(4, 11) -#define IOMMU_PORT_L4_HW_MINI_MDP_R0_EXT MTK_M4U_ID(4, 12) -#define IOMMU_PORT_L4_HW_MINI_MDP_W0_EXT MTK_M4U_ID(4, 13) - -/* LARB 7 -- VENC */ -#define IOMMU_PORT_L7_VENC_RCPU MTK_M4U_ID(7, 0) -#define IOMMU_PORT_L7_VENC_REC MTK_M4U_ID(7, 1) -#define IOMMU_PORT_L7_VENC_BSDMA MTK_M4U_ID(7, 2) -#define IOMMU_PORT_L7_VENC_SV_COMV MTK_M4U_ID(7, 3) -#define IOMMU_PORT_L7_VENC_RD_COMV MTK_M4U_ID(7, 4) -#define IOMMU_PORT_L7_VENC_CUR_LUMA MTK_M4U_ID(7, 5) -#define IOMMU_PORT_L7_VENC_CUR_CHROMA MTK_M4U_ID(7, 6) -#define IOMMU_PORT_L7_VENC_REF_LUMA MTK_M4U_ID(7, 7) -#define IOMMU_PORT_L7_VENC_REF_CHROMA MTK_M4U_ID(7, 8) -#define IOMMU_PORT_L7_JPGENC_Y_RDMA MTK_M4U_ID(7, 9) -#define IOMMU_PORT_L7_JPGENC_C_RDMA MTK_M4U_ID(7, 10) -#define IOMMU_PORT_L7_JPGENC_Q_TABLE MTK_M4U_ID(7, 11) -#define IOMMU_PORT_L7_JPGENC_BSDMA MTK_M4U_ID(7, 12) - -/* LARB 8 -- WPE */ -#define IOMMU_PORT_L8_WPE_RDMA_0 MTK_M4U_ID(8, 0) -#define IOMMU_PORT_L8_WPE_RDMA_1 MTK_M4U_ID(8, 1) -#define IOMMU_PORT_L8_WPE_WDMA_0 MTK_M4U_ID(8, 2) - -/* LARB 9 -- IMG-1 */ -#define IOMMU_PORT_L9_IMG_IMGI_D1 MTK_M4U_ID(9, 0) -#define IOMMU_PORT_L9_IMG_IMGBI_D1 MTK_M4U_ID(9, 1) -#define IOMMU_PORT_L9_IMG_DMGI_D1 MTK_M4U_ID(9, 2) -#define IOMMU_PORT_L9_IMG_DEPI_D1 MTK_M4U_ID(9, 3) -#define IOMMU_PORT_L9_IMG_LCE_D1 MTK_M4U_ID(9, 4) -#define IOMMU_PORT_L9_IMG_SMTI_D1 MTK_M4U_ID(9, 5) -#define IOMMU_PORT_L9_IMG_SMTO_D2 MTK_M4U_ID(9, 6) -#define IOMMU_PORT_L9_IMG_SMTO_D1 MTK_M4U_ID(9, 7) -#define IOMMU_PORT_L9_IMG_CRZO_D1 MTK_M4U_ID(9, 8) -#define IOMMU_PORT_L9_IMG_IMG3O_D1 MTK_M4U_ID(9, 9) -#define IOMMU_PORT_L9_IMG_VIPI_D1 MTK_M4U_ID(9, 10) -#define IOMMU_PORT_L9_IMG_SMTI_D5 MTK_M4U_ID(9, 11) -#define IOMMU_PORT_L9_IMG_TIMGO_D1 MTK_M4U_ID(9, 12) -#define IOMMU_PORT_L9_IMG_UFBC_W0 MTK_M4U_ID(9, 13) -#define IOMMU_PORT_L9_IMG_UFBC_R0 MTK_M4U_ID(9, 14) -#define IOMMU_PORT_L9_IMG_WPE_RDMA1 MTK_M4U_ID(9, 15) -#define IOMMU_PORT_L9_IMG_WPE_RDMA0 MTK_M4U_ID(9, 16) -#define IOMMU_PORT_L9_IMG_WPE_WDMA MTK_M4U_ID(9, 17) -#define IOMMU_PORT_L9_IMG_MFB_RDMA0 MTK_M4U_ID(9, 18) -#define IOMMU_PORT_L9_IMG_MFB_RDMA1 MTK_M4U_ID(9, 19) -#define IOMMU_PORT_L9_IMG_MFB_RDMA2 MTK_M4U_ID(9, 20) -#define IOMMU_PORT_L9_IMG_MFB_RDMA3 MTK_M4U_ID(9, 21) -#define IOMMU_PORT_L9_IMG_MFB_RDMA4 MTK_M4U_ID(9, 22) -#define IOMMU_PORT_L9_IMG_MFB_RDMA5 MTK_M4U_ID(9, 23) -#define IOMMU_PORT_L9_IMG_MFB_WDMA0 MTK_M4U_ID(9, 24) -#define IOMMU_PORT_L9_IMG_MFB_WDMA1 MTK_M4U_ID(9, 25) -#define IOMMU_PORT_L9_IMG_RESERVE6 MTK_M4U_ID(9, 26) -#define IOMMU_PORT_L9_IMG_RESERVE7 MTK_M4U_ID(9, 27) -#define IOMMU_PORT_L9_IMG_RESERVE8 MTK_M4U_ID(9, 28) - -/* LARB 11 -- IMG-2 */ -#define IOMMU_PORT_L11_IMG_IMGI_D1 MTK_M4U_ID(11, 0) -#define IOMMU_PORT_L11_IMG_IMGBI_D1 MTK_M4U_ID(11, 1) -#define IOMMU_PORT_L11_IMG_DMGI_D1 MTK_M4U_ID(11, 2) -#define IOMMU_PORT_L11_IMG_DEPI_D1 MTK_M4U_ID(11, 3) -#define IOMMU_PORT_L11_IMG_LCE_D1 MTK_M4U_ID(11, 4) -#define IOMMU_PORT_L11_IMG_SMTI_D1 MTK_M4U_ID(11, 5) -#define IOMMU_PORT_L11_IMG_SMTO_D2 MTK_M4U_ID(11, 6) -#define IOMMU_PORT_L11_IMG_SMTO_D1 MTK_M4U_ID(11, 7) -#define IOMMU_PORT_L11_IMG_CRZO_D1 MTK_M4U_ID(11, 8) -#define IOMMU_PORT_L11_IMG_IMG3O_D1 MTK_M4U_ID(11, 9) -#define IOMMU_PORT_L11_IMG_VIPI_D1 MTK_M4U_ID(11, 10) -#define IOMMU_PORT_L11_IMG_SMTI_D5 MTK_M4U_ID(11, 11) -#define IOMMU_PORT_L11_IMG_TIMGO_D1 MTK_M4U_ID(11, 12) -#define IOMMU_PORT_L11_IMG_UFBC_W0 MTK_M4U_ID(11, 13) -#define IOMMU_PORT_L11_IMG_UFBC_R0 MTK_M4U_ID(11, 14) -#define IOMMU_PORT_L11_IMG_WPE_RDMA1 MTK_M4U_ID(11, 15) -#define IOMMU_PORT_L11_IMG_WPE_RDMA0 MTK_M4U_ID(11, 16) -#define IOMMU_PORT_L11_IMG_WPE_WDMA MTK_M4U_ID(11, 17) -#define IOMMU_PORT_L11_IMG_MFB_RDMA0 MTK_M4U_ID(11, 18) -#define IOMMU_PORT_L11_IMG_MFB_RDMA1 MTK_M4U_ID(11, 19) -#define IOMMU_PORT_L11_IMG_MFB_RDMA2 MTK_M4U_ID(11, 20) -#define IOMMU_PORT_L11_IMG_MFB_RDMA3 MTK_M4U_ID(11, 21) -#define IOMMU_PORT_L11_IMG_MFB_RDMA4 MTK_M4U_ID(11, 22) -#define IOMMU_PORT_L11_IMG_MFB_RDMA5 MTK_M4U_ID(11, 23) -#define IOMMU_PORT_L11_IMG_MFB_WDMA0 MTK_M4U_ID(11, 24) -#define IOMMU_PORT_L11_IMG_MFB_WDMA1 MTK_M4U_ID(11, 25) -#define IOMMU_PORT_L11_IMG_RESERVE6 MTK_M4U_ID(11, 26) -#define IOMMU_PORT_L11_IMG_RESERVE7 MTK_M4U_ID(11, 27) -#define IOMMU_PORT_L11_IMG_RESERVE8 MTK_M4U_ID(11, 28) - -/* LARB 13 -- CAM */ -#define IOMMU_PORT_L13_CAM_MRAWI MTK_M4U_ID(13, 0) -#define IOMMU_PORT_L13_CAM_MRAWO_0 MTK_M4U_ID(13, 1) -#define IOMMU_PORT_L13_CAM_MRAWO_1 MTK_M4U_ID(13, 2) -#define IOMMU_PORT_L13_CAM_CAMSV_4 MTK_M4U_ID(13, 6) -#define IOMMU_PORT_L13_CAM_CAMSV_5 MTK_M4U_ID(13, 7) -#define IOMMU_PORT_L13_CAM_CAMSV_6 MTK_M4U_ID(13, 8) -#define IOMMU_PORT_L13_CAM_CCUI MTK_M4U_ID(13, 9) -#define IOMMU_PORT_L13_CAM_CCUO MTK_M4U_ID(13, 10) -#define IOMMU_PORT_L13_CAM_FAKE MTK_M4U_ID(13, 11) - -/* LARB 14 -- CAM */ -#define IOMMU_PORT_L14_CAM_CCUI MTK_M4U_ID(14, 4) -#define IOMMU_PORT_L14_CAM_CCUO MTK_M4U_ID(14, 5) - -/* LARB 16 -- RAW-A */ -#define IOMMU_PORT_L16_CAM_IMGO_R1_A MTK_M4U_ID(16, 0) -#define IOMMU_PORT_L16_CAM_RRZO_R1_A MTK_M4U_ID(16, 1) -#define IOMMU_PORT_L16_CAM_CQI_R1_A MTK_M4U_ID(16, 2) -#define IOMMU_PORT_L16_CAM_BPCI_R1_A MTK_M4U_ID(16, 3) -#define IOMMU_PORT_L16_CAM_YUVO_R1_A MTK_M4U_ID(16, 4) -#define IOMMU_PORT_L16_CAM_UFDI_R2_A MTK_M4U_ID(16, 5) -#define IOMMU_PORT_L16_CAM_RAWI_R2_A MTK_M4U_ID(16, 6) -#define IOMMU_PORT_L16_CAM_RAWI_R3_A MTK_M4U_ID(16, 7) -#define IOMMU_PORT_L16_CAM_AAO_R1_A MTK_M4U_ID(16, 8) -#define IOMMU_PORT_L16_CAM_AFO_R1_A MTK_M4U_ID(16, 9) -#define IOMMU_PORT_L16_CAM_FLKO_R1_A MTK_M4U_ID(16, 10) -#define IOMMU_PORT_L16_CAM_LCESO_R1_A MTK_M4U_ID(16, 11) -#define IOMMU_PORT_L16_CAM_CRZO_R1_A MTK_M4U_ID(16, 12) -#define IOMMU_PORT_L16_CAM_LTMSO_R1_A MTK_M4U_ID(16, 13) -#define IOMMU_PORT_L16_CAM_RSSO_R1_A MTK_M4U_ID(16, 14) -#define IOMMU_PORT_L16_CAM_AAHO_R1_A MTK_M4U_ID(16, 15) -#define IOMMU_PORT_L16_CAM_LSCI_R1_A MTK_M4U_ID(16, 16) - -/* LARB 17 -- RAW-B */ -#define IOMMU_PORT_L17_CAM_IMGO_R1_B MTK_M4U_ID(17, 0) -#define IOMMU_PORT_L17_CAM_RRZO_R1_B MTK_M4U_ID(17, 1) -#define IOMMU_PORT_L17_CAM_CQI_R1_B MTK_M4U_ID(17, 2) -#define IOMMU_PORT_L17_CAM_BPCI_R1_B MTK_M4U_ID(17, 3) -#define IOMMU_PORT_L17_CAM_YUVO_R1_B MTK_M4U_ID(17, 4) -#define IOMMU_PORT_L17_CAM_UFDI_R2_B MTK_M4U_ID(17, 5) -#define IOMMU_PORT_L17_CAM_RAWI_R2_B MTK_M4U_ID(17, 6) -#define IOMMU_PORT_L17_CAM_RAWI_R3_B MTK_M4U_ID(17, 7) -#define IOMMU_PORT_L17_CAM_AAO_R1_B MTK_M4U_ID(17, 8) -#define IOMMU_PORT_L17_CAM_AFO_R1_B MTK_M4U_ID(17, 9) -#define IOMMU_PORT_L17_CAM_FLKO_R1_B MTK_M4U_ID(17, 10) -#define IOMMU_PORT_L17_CAM_LCESO_R1_B MTK_M4U_ID(17, 11) -#define IOMMU_PORT_L17_CAM_CRZO_R1_B MTK_M4U_ID(17, 12) -#define IOMMU_PORT_L17_CAM_LTMSO_R1_B MTK_M4U_ID(17, 13) -#define IOMMU_PORT_L17_CAM_RSSO_R1_B MTK_M4U_ID(17, 14) -#define IOMMU_PORT_L17_CAM_AAHO_R1_B MTK_M4U_ID(17, 15) -#define IOMMU_PORT_L17_CAM_LSCI_R1_B MTK_M4U_ID(17, 16) - -/* LARB 19 -- IPE */ -#define IOMMU_PORT_L19_IPE_DVS_RDMA MTK_M4U_ID(19, 0) -#define IOMMU_PORT_L19_IPE_DVS_WDMA MTK_M4U_ID(19, 1) -#define IOMMU_PORT_L19_IPE_DVP_RDMA MTK_M4U_ID(19, 2) -#define IOMMU_PORT_L19_IPE_DVP_WDMA MTK_M4U_ID(19, 3) - -/* LARB 20 -- IPE */ -#define IOMMU_PORT_L20_IPE_FDVT_RDA MTK_M4U_ID(20, 0) -#define IOMMU_PORT_L20_IPE_FDVT_RDB MTK_M4U_ID(20, 1) -#define IOMMU_PORT_L20_IPE_FDVT_WRA MTK_M4U_ID(20, 2) -#define IOMMU_PORT_L20_IPE_FDVT_WRB MTK_M4U_ID(20, 3) -#define IOMMU_PORT_L20_IPE_RSC_RDMA0 MTK_M4U_ID(20, 4) -#define IOMMU_PORT_L20_IPE_RSC_WDMA MTK_M4U_ID(20, 5) - -#endif diff --git a/include/dt-bindings/memory/mt8192-larb-port.h b/include/dt-bindings/memory/mt8192-larb-port.h deleted file mode 100644 index 23035a52c67..00000000000 --- a/include/dt-bindings/memory/mt8192-larb-port.h +++ /dev/null @@ -1,243 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2020 MediaTek Inc. - * - * Author: Chao Hao <chao.hao@mediatek.com> - * Author: Yong Wu <yong.wu@mediatek.com> - */ -#ifndef _DT_BINDINGS_MEMORY_MT8192_LARB_PORT_H_ -#define _DT_BINDINGS_MEMORY_MT8192_LARB_PORT_H_ - -#include <dt-bindings/memory/mtk-memory-port.h> - -/* - * MM IOMMU supports 16GB dma address. - * - * The address will preassign like this: - * - * modules dma-address-region larbs-ports - * disp 0 ~ 4G larb0/1 - * vcodec 4G ~ 8G larb4/5/7 - * cam/mdp 8G ~ 12G larb2/9/11/13/14/16/17/18/19/20 - * CCU0 0x4000_0000 ~ 0x43ff_ffff larb13: port 9/10 - * CCU1 0x4400_0000 ~ 0x47ff_ffff larb14: port 4/5 - * - * larb3/6/8/10/12/15 is null. - */ - -/* larb0 */ -#define M4U_PORT_L0_DISP_POSTMASK0 MTK_M4U_ID(0, 0) -#define M4U_PORT_L0_OVL_RDMA0_HDR MTK_M4U_ID(0, 1) -#define M4U_PORT_L0_OVL_RDMA0 MTK_M4U_ID(0, 2) -#define M4U_PORT_L0_DISP_RDMA0 MTK_M4U_ID(0, 3) -#define M4U_PORT_L0_DISP_WDMA0 MTK_M4U_ID(0, 4) -#define M4U_PORT_L0_DISP_FAKE0 MTK_M4U_ID(0, 5) - -/* larb1 */ -#define M4U_PORT_L1_OVL_2L_RDMA0_HDR MTK_M4U_ID(1, 0) -#define M4U_PORT_L1_OVL_2L_RDMA2_HDR MTK_M4U_ID(1, 1) -#define M4U_PORT_L1_OVL_2L_RDMA0 MTK_M4U_ID(1, 2) -#define M4U_PORT_L1_OVL_2L_RDMA2 MTK_M4U_ID(1, 3) -#define M4U_PORT_L1_DISP_MDP_RDMA4 MTK_M4U_ID(1, 4) -#define M4U_PORT_L1_DISP_RDMA4 MTK_M4U_ID(1, 5) -#define M4U_PORT_L1_DISP_UFBC_WDMA0 MTK_M4U_ID(1, 6) -#define M4U_PORT_L1_DISP_FAKE1 MTK_M4U_ID(1, 7) - -/* larb2 */ -#define M4U_PORT_L2_MDP_RDMA0 MTK_M4U_ID(2, 0) -#define M4U_PORT_L2_MDP_RDMA1 MTK_M4U_ID(2, 1) -#define M4U_PORT_L2_MDP_WROT0 MTK_M4U_ID(2, 2) -#define M4U_PORT_L2_MDP_WROT1 MTK_M4U_ID(2, 3) -#define M4U_PORT_L2_MDP_DISP_FAKE0 MTK_M4U_ID(2, 4) - -/* larb3: null */ - -/* larb4 */ -#define M4U_PORT_L4_VDEC_MC_EXT MTK_M4U_ID(4, 0) -#define M4U_PORT_L4_VDEC_UFO_EXT MTK_M4U_ID(4, 1) -#define M4U_PORT_L4_VDEC_PP_EXT MTK_M4U_ID(4, 2) -#define M4U_PORT_L4_VDEC_PRED_RD_EXT MTK_M4U_ID(4, 3) -#define M4U_PORT_L4_VDEC_PRED_WR_EXT MTK_M4U_ID(4, 4) -#define M4U_PORT_L4_VDEC_PPWRAP_EXT MTK_M4U_ID(4, 5) -#define M4U_PORT_L4_VDEC_TILE_EXT MTK_M4U_ID(4, 6) -#define M4U_PORT_L4_VDEC_VLD_EXT MTK_M4U_ID(4, 7) -#define M4U_PORT_L4_VDEC_VLD2_EXT MTK_M4U_ID(4, 8) -#define M4U_PORT_L4_VDEC_AVC_MV_EXT MTK_M4U_ID(4, 9) -#define M4U_PORT_L4_VDEC_RG_CTRL_DMA_EXT MTK_M4U_ID(4, 10) - -/* larb5 */ -#define M4U_PORT_L5_VDEC_LAT0_VLD_EXT MTK_M4U_ID(5, 0) -#define M4U_PORT_L5_VDEC_LAT0_VLD2_EXT MTK_M4U_ID(5, 1) -#define M4U_PORT_L5_VDEC_LAT0_AVC_MV_EXT MTK_M4U_ID(5, 2) -#define M4U_PORT_L5_VDEC_LAT0_PRED_RD_EXT MTK_M4U_ID(5, 3) -#define M4U_PORT_L5_VDEC_LAT0_TILE_EXT MTK_M4U_ID(5, 4) -#define M4U_PORT_L5_VDEC_LAT0_WDMA_EXT MTK_M4U_ID(5, 5) -#define M4U_PORT_L5_VDEC_LAT0_RG_CTRL_DMA_EXT MTK_M4U_ID(5, 6) -#define M4U_PORT_L5_VDEC_UFO_ENC_EXT MTK_M4U_ID(5, 7) - -/* larb6: null */ - -/* larb7 */ -#define M4U_PORT_L7_VENC_RCPU MTK_M4U_ID(7, 0) -#define M4U_PORT_L7_VENC_REC MTK_M4U_ID(7, 1) -#define M4U_PORT_L7_VENC_BSDMA MTK_M4U_ID(7, 2) -#define M4U_PORT_L7_VENC_SV_COMV MTK_M4U_ID(7, 3) -#define M4U_PORT_L7_VENC_RD_COMV MTK_M4U_ID(7, 4) -#define M4U_PORT_L7_VENC_CUR_LUMA MTK_M4U_ID(7, 5) -#define M4U_PORT_L7_VENC_CUR_CHROMA MTK_M4U_ID(7, 6) -#define M4U_PORT_L7_VENC_REF_LUMA MTK_M4U_ID(7, 7) -#define M4U_PORT_L7_VENC_REF_CHROMA MTK_M4U_ID(7, 8) -#define M4U_PORT_L7_JPGENC_Y_RDMA MTK_M4U_ID(7, 9) -#define M4U_PORT_L7_JPGENC_Q_RDMA MTK_M4U_ID(7, 10) -#define M4U_PORT_L7_JPGENC_C_TABLE MTK_M4U_ID(7, 11) -#define M4U_PORT_L7_JPGENC_BSDMA MTK_M4U_ID(7, 12) -#define M4U_PORT_L7_VENC_SUB_R_LUMA MTK_M4U_ID(7, 13) -#define M4U_PORT_L7_VENC_SUB_W_LUMA MTK_M4U_ID(7, 14) - -/* larb8: null */ - -/* larb9 */ -#define M4U_PORT_L9_IMG_IMGI_D1 MTK_M4U_ID(9, 0) -#define M4U_PORT_L9_IMG_IMGBI_D1 MTK_M4U_ID(9, 1) -#define M4U_PORT_L9_IMG_DMGI_D1 MTK_M4U_ID(9, 2) -#define M4U_PORT_L9_IMG_DEPI_D1 MTK_M4U_ID(9, 3) -#define M4U_PORT_L9_IMG_ICE_D1 MTK_M4U_ID(9, 4) -#define M4U_PORT_L9_IMG_SMTI_D1 MTK_M4U_ID(9, 5) -#define M4U_PORT_L9_IMG_SMTO_D2 MTK_M4U_ID(9, 6) -#define M4U_PORT_L9_IMG_SMTO_D1 MTK_M4U_ID(9, 7) -#define M4U_PORT_L9_IMG_CRZO_D1 MTK_M4U_ID(9, 8) -#define M4U_PORT_L9_IMG_IMG3O_D1 MTK_M4U_ID(9, 9) -#define M4U_PORT_L9_IMG_VIPI_D1 MTK_M4U_ID(9, 10) -#define M4U_PORT_L9_IMG_SMTI_D5 MTK_M4U_ID(9, 11) -#define M4U_PORT_L9_IMG_TIMGO_D1 MTK_M4U_ID(9, 12) -#define M4U_PORT_L9_IMG_UFBC_W0 MTK_M4U_ID(9, 13) -#define M4U_PORT_L9_IMG_UFBC_R0 MTK_M4U_ID(9, 14) - -/* larb10: null */ - -/* larb11 */ -#define M4U_PORT_L11_IMG_IMGI_D1 MTK_M4U_ID(11, 0) -#define M4U_PORT_L11_IMG_IMGBI_D1 MTK_M4U_ID(11, 1) -#define M4U_PORT_L11_IMG_DMGI_D1 MTK_M4U_ID(11, 2) -#define M4U_PORT_L11_IMG_DEPI_D1 MTK_M4U_ID(11, 3) -#define M4U_PORT_L11_IMG_ICE_D1 MTK_M4U_ID(11, 4) -#define M4U_PORT_L11_IMG_SMTI_D1 MTK_M4U_ID(11, 5) -#define M4U_PORT_L11_IMG_SMTO_D2 MTK_M4U_ID(11, 6) -#define M4U_PORT_L11_IMG_SMTO_D1 MTK_M4U_ID(11, 7) -#define M4U_PORT_L11_IMG_CRZO_D1 MTK_M4U_ID(11, 8) -#define M4U_PORT_L11_IMG_IMG3O_D1 MTK_M4U_ID(11, 9) -#define M4U_PORT_L11_IMG_VIPI_D1 MTK_M4U_ID(11, 10) -#define M4U_PORT_L11_IMG_SMTI_D5 MTK_M4U_ID(11, 11) -#define M4U_PORT_L11_IMG_TIMGO_D1 MTK_M4U_ID(11, 12) -#define M4U_PORT_L11_IMG_UFBC_W0 MTK_M4U_ID(11, 13) -#define M4U_PORT_L11_IMG_UFBC_R0 MTK_M4U_ID(11, 14) -#define M4U_PORT_L11_IMG_WPE_RDMA1 MTK_M4U_ID(11, 15) -#define M4U_PORT_L11_IMG_WPE_RDMA0 MTK_M4U_ID(11, 16) -#define M4U_PORT_L11_IMG_WPE_WDMA MTK_M4U_ID(11, 17) -#define M4U_PORT_L11_IMG_MFB_RDMA0 MTK_M4U_ID(11, 18) -#define M4U_PORT_L11_IMG_MFB_RDMA1 MTK_M4U_ID(11, 19) -#define M4U_PORT_L11_IMG_MFB_RDMA2 MTK_M4U_ID(11, 20) -#define M4U_PORT_L11_IMG_MFB_RDMA3 MTK_M4U_ID(11, 21) -#define M4U_PORT_L11_IMG_MFB_RDMA4 MTK_M4U_ID(11, 22) -#define M4U_PORT_L11_IMG_MFB_RDMA5 MTK_M4U_ID(11, 23) -#define M4U_PORT_L11_IMG_MFB_WDMA0 MTK_M4U_ID(11, 24) -#define M4U_PORT_L11_IMG_MFB_WDMA1 MTK_M4U_ID(11, 25) - -/* larb12: null */ - -/* larb13 */ -#define M4U_PORT_L13_CAM_MRAWI MTK_M4U_ID(13, 0) -#define M4U_PORT_L13_CAM_MRAWO0 MTK_M4U_ID(13, 1) -#define M4U_PORT_L13_CAM_MRAWO1 MTK_M4U_ID(13, 2) -#define M4U_PORT_L13_CAM_CAMSV1 MTK_M4U_ID(13, 3) -#define M4U_PORT_L13_CAM_CAMSV2 MTK_M4U_ID(13, 4) -#define M4U_PORT_L13_CAM_CAMSV3 MTK_M4U_ID(13, 5) -#define M4U_PORT_L13_CAM_CAMSV4 MTK_M4U_ID(13, 6) -#define M4U_PORT_L13_CAM_CAMSV5 MTK_M4U_ID(13, 7) -#define M4U_PORT_L13_CAM_CAMSV6 MTK_M4U_ID(13, 8) -#define M4U_PORT_L13_CAM_CCUI MTK_M4U_ID(13, 9) -#define M4U_PORT_L13_CAM_CCUO MTK_M4U_ID(13, 10) -#define M4U_PORT_L13_CAM_FAKE MTK_M4U_ID(13, 11) - -/* larb14 */ -#define M4U_PORT_L14_CAM_RESERVE1 MTK_M4U_ID(14, 0) -#define M4U_PORT_L14_CAM_RESERVE2 MTK_M4U_ID(14, 1) -#define M4U_PORT_L14_CAM_RESERVE3 MTK_M4U_ID(14, 2) -#define M4U_PORT_L14_CAM_CAMSV0 MTK_M4U_ID(14, 3) -#define M4U_PORT_L14_CAM_CCUI MTK_M4U_ID(14, 4) -#define M4U_PORT_L14_CAM_CCUO MTK_M4U_ID(14, 5) - -/* larb15: null */ - -/* larb16 */ -#define M4U_PORT_L16_CAM_IMGO_R1_A MTK_M4U_ID(16, 0) -#define M4U_PORT_L16_CAM_RRZO_R1_A MTK_M4U_ID(16, 1) -#define M4U_PORT_L16_CAM_CQI_R1_A MTK_M4U_ID(16, 2) -#define M4U_PORT_L16_CAM_BPCI_R1_A MTK_M4U_ID(16, 3) -#define M4U_PORT_L16_CAM_YUVO_R1_A MTK_M4U_ID(16, 4) -#define M4U_PORT_L16_CAM_UFDI_R2_A MTK_M4U_ID(16, 5) -#define M4U_PORT_L16_CAM_RAWI_R2_A MTK_M4U_ID(16, 6) -#define M4U_PORT_L16_CAM_RAWI_R3_A MTK_M4U_ID(16, 7) -#define M4U_PORT_L16_CAM_AAO_R1_A MTK_M4U_ID(16, 8) -#define M4U_PORT_L16_CAM_AFO_R1_A MTK_M4U_ID(16, 9) -#define M4U_PORT_L16_CAM_FLKO_R1_A MTK_M4U_ID(16, 10) -#define M4U_PORT_L16_CAM_LCESO_R1_A MTK_M4U_ID(16, 11) -#define M4U_PORT_L16_CAM_CRZO_R1_A MTK_M4U_ID(16, 12) -#define M4U_PORT_L16_CAM_LTMSO_R1_A MTK_M4U_ID(16, 13) -#define M4U_PORT_L16_CAM_RSSO_R1_A MTK_M4U_ID(16, 14) -#define M4U_PORT_L16_CAM_AAHO_R1_A MTK_M4U_ID(16, 15) -#define M4U_PORT_L16_CAM_LSCI_R1_A MTK_M4U_ID(16, 16) - -/* larb17 */ -#define M4U_PORT_L17_CAM_IMGO_R1_B MTK_M4U_ID(17, 0) -#define M4U_PORT_L17_CAM_RRZO_R1_B MTK_M4U_ID(17, 1) -#define M4U_PORT_L17_CAM_CQI_R1_B MTK_M4U_ID(17, 2) -#define M4U_PORT_L17_CAM_BPCI_R1_B MTK_M4U_ID(17, 3) -#define M4U_PORT_L17_CAM_YUVO_R1_B MTK_M4U_ID(17, 4) -#define M4U_PORT_L17_CAM_UFDI_R2_B MTK_M4U_ID(17, 5) -#define M4U_PORT_L17_CAM_RAWI_R2_B MTK_M4U_ID(17, 6) -#define M4U_PORT_L17_CAM_RAWI_R3_B MTK_M4U_ID(17, 7) -#define M4U_PORT_L17_CAM_AAO_R1_B MTK_M4U_ID(17, 8) -#define M4U_PORT_L17_CAM_AFO_R1_B MTK_M4U_ID(17, 9) -#define M4U_PORT_L17_CAM_FLKO_R1_B MTK_M4U_ID(17, 10) -#define M4U_PORT_L17_CAM_LCESO_R1_B MTK_M4U_ID(17, 11) -#define M4U_PORT_L17_CAM_CRZO_R1_B MTK_M4U_ID(17, 12) -#define M4U_PORT_L17_CAM_LTMSO_R1_B MTK_M4U_ID(17, 13) -#define M4U_PORT_L17_CAM_RSSO_R1_B MTK_M4U_ID(17, 14) -#define M4U_PORT_L17_CAM_AAHO_R1_B MTK_M4U_ID(17, 15) -#define M4U_PORT_L17_CAM_LSCI_R1_B MTK_M4U_ID(17, 16) - -/* larb18 */ -#define M4U_PORT_L18_CAM_IMGO_R1_C MTK_M4U_ID(18, 0) -#define M4U_PORT_L18_CAM_RRZO_R1_C MTK_M4U_ID(18, 1) -#define M4U_PORT_L18_CAM_CQI_R1_C MTK_M4U_ID(18, 2) -#define M4U_PORT_L18_CAM_BPCI_R1_C MTK_M4U_ID(18, 3) -#define M4U_PORT_L18_CAM_YUVO_R1_C MTK_M4U_ID(18, 4) -#define M4U_PORT_L18_CAM_UFDI_R2_C MTK_M4U_ID(18, 5) -#define M4U_PORT_L18_CAM_RAWI_R2_C MTK_M4U_ID(18, 6) -#define M4U_PORT_L18_CAM_RAWI_R3_C MTK_M4U_ID(18, 7) -#define M4U_PORT_L18_CAM_AAO_R1_C MTK_M4U_ID(18, 8) -#define M4U_PORT_L18_CAM_AFO_R1_C MTK_M4U_ID(18, 9) -#define M4U_PORT_L18_CAM_FLKO_R1_C MTK_M4U_ID(18, 10) -#define M4U_PORT_L18_CAM_LCESO_R1_C MTK_M4U_ID(18, 11) -#define M4U_PORT_L18_CAM_CRZO_R1_C MTK_M4U_ID(18, 12) -#define M4U_PORT_L18_CAM_LTMSO_R1_C MTK_M4U_ID(18, 13) -#define M4U_PORT_L18_CAM_RSSO_R1_C MTK_M4U_ID(18, 14) -#define M4U_PORT_L18_CAM_AAHO_R1_C MTK_M4U_ID(18, 15) -#define M4U_PORT_L18_CAM_LSCI_R1_C MTK_M4U_ID(18, 16) - -/* larb19 */ -#define M4U_PORT_L19_IPE_DVS_RDMA MTK_M4U_ID(19, 0) -#define M4U_PORT_L19_IPE_DVS_WDMA MTK_M4U_ID(19, 1) -#define M4U_PORT_L19_IPE_DVP_RDMA MTK_M4U_ID(19, 2) -#define M4U_PORT_L19_IPE_DVP_WDMA MTK_M4U_ID(19, 3) - -/* larb20 */ -#define M4U_PORT_L20_IPE_FDVT_RDA MTK_M4U_ID(20, 0) -#define M4U_PORT_L20_IPE_FDVT_RDB MTK_M4U_ID(20, 1) -#define M4U_PORT_L20_IPE_FDVT_WRA MTK_M4U_ID(20, 2) -#define M4U_PORT_L20_IPE_FDVT_WRB MTK_M4U_ID(20, 3) -#define M4U_PORT_L20_IPE_RSC_RDMA0 MTK_M4U_ID(20, 4) -#define M4U_PORT_L20_IPE_RSC_WDMA MTK_M4U_ID(20, 5) - -#endif diff --git a/include/dt-bindings/memory/mt8195-memory-port.h b/include/dt-bindings/memory/mt8195-memory-port.h deleted file mode 100644 index 70ba9f498ee..00000000000 --- a/include/dt-bindings/memory/mt8195-memory-port.h +++ /dev/null @@ -1,408 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2022 MediaTek Inc. - * Author: Yong Wu <yong.wu@mediatek.com> - */ -#ifndef _DT_BINDINGS_MEMORY_MT8195_LARB_PORT_H_ -#define _DT_BINDINGS_MEMORY_MT8195_LARB_PORT_H_ - -#include <dt-bindings/memory/mtk-memory-port.h> - -/* - * MM IOMMU supports 16GB dma address. We separate it to four ranges: - * 0 ~ 4G; 4G ~ 8G; 8G ~ 12G; 12G ~ 16G, we could adjust these masters - * locate in anyone region. BUT: - * a) Make sure all the ports inside a larb are in one range. - * b) The iova of any master can NOT cross the 4G/8G/12G boundary. - * - * This is the suggested mapping in this SoC: - * - * modules dma-address-region larbs-ports - * disp 0 ~ 4G larb0/1/2/3 - * vcodec 4G ~ 8G larb19/20/21/22/23/24 - * cam/mdp 8G ~ 12G the other larbs. - * N/A 12G ~ 16G - * CCU0 0x24000_0000 ~ 0x243ff_ffff larb18: port 0/1 - * CCU1 0x24400_0000 ~ 0x247ff_ffff larb18: port 2/3 - * - * This SoC have two IOMMU HWs, this is the detailed connected information: - * iommu-vdo: larb0/2/5/7/9/10/11/13/17/19/21/24/25/28 - * iommu-vpp: larb1/3/4/6/8/12/14/16/18/20/22/23/26/27 - */ - -/* MM IOMMU ports */ -/* larb0 */ -#define M4U_PORT_L0_DISP_RDMA0 MTK_M4U_ID(0, 0) -#define M4U_PORT_L0_DISP_WDMA0 MTK_M4U_ID(0, 1) -#define M4U_PORT_L0_DISP_OVL0_RDMA0 MTK_M4U_ID(0, 2) -#define M4U_PORT_L0_DISP_OVL0_RDMA1 MTK_M4U_ID(0, 3) -#define M4U_PORT_L0_DISP_OVL0_HDR MTK_M4U_ID(0, 4) -#define M4U_PORT_L0_DISP_FAKE0 MTK_M4U_ID(0, 5) - -/* larb1 */ -#define M4U_PORT_L1_DISP_RDMA0 MTK_M4U_ID(1, 0) -#define M4U_PORT_L1_DISP_WDMA0 MTK_M4U_ID(1, 1) -#define M4U_PORT_L1_DISP_OVL0_RDMA0 MTK_M4U_ID(1, 2) -#define M4U_PORT_L1_DISP_OVL0_RDMA1 MTK_M4U_ID(1, 3) -#define M4U_PORT_L1_DISP_OVL0_HDR MTK_M4U_ID(1, 4) -#define M4U_PORT_L1_DISP_FAKE0 MTK_M4U_ID(1, 5) - -/* larb2 */ -#define M4U_PORT_L2_MDP_RDMA0 MTK_M4U_ID(2, 0) -#define M4U_PORT_L2_MDP_RDMA2 MTK_M4U_ID(2, 1) -#define M4U_PORT_L2_MDP_RDMA4 MTK_M4U_ID(2, 2) -#define M4U_PORT_L2_MDP_RDMA6 MTK_M4U_ID(2, 3) -#define M4U_PORT_L2_DISP_FAKE1 MTK_M4U_ID(2, 4) - -/* larb3 */ -#define M4U_PORT_L3_MDP_RDMA1 MTK_M4U_ID(3, 0) -#define M4U_PORT_L3_MDP_RDMA3 MTK_M4U_ID(3, 1) -#define M4U_PORT_L3_MDP_RDMA5 MTK_M4U_ID(3, 2) -#define M4U_PORT_L3_MDP_RDMA7 MTK_M4U_ID(3, 3) -#define M4U_PORT_L3_HDR_DS MTK_M4U_ID(3, 4) -#define M4U_PORT_L3_HDR_ADL MTK_M4U_ID(3, 5) -#define M4U_PORT_L3_DISP_FAKE1 MTK_M4U_ID(3, 6) - -/* larb4 */ -#define M4U_PORT_L4_MDP_RDMA MTK_M4U_ID(4, 0) -#define M4U_PORT_L4_MDP_FG MTK_M4U_ID(4, 1) -#define M4U_PORT_L4_MDP_OVL MTK_M4U_ID(4, 2) -#define M4U_PORT_L4_MDP_WROT MTK_M4U_ID(4, 3) -#define M4U_PORT_L4_FAKE MTK_M4U_ID(4, 4) - -/* larb5 */ -#define M4U_PORT_L5_SVPP1_MDP_RDMA MTK_M4U_ID(5, 0) -#define M4U_PORT_L5_SVPP1_MDP_FG MTK_M4U_ID(5, 1) -#define M4U_PORT_L5_SVPP1_MDP_OVL MTK_M4U_ID(5, 2) -#define M4U_PORT_L5_SVPP1_MDP_WROT MTK_M4U_ID(5, 3) -#define M4U_PORT_L5_SVPP2_MDP_RDMA MTK_M4U_ID(5, 4) -#define M4U_PORT_L5_SVPP2_MDP_FG MTK_M4U_ID(5, 5) -#define M4U_PORT_L5_SVPP2_MDP_WROT MTK_M4U_ID(5, 6) -#define M4U_PORT_L5_FAKE MTK_M4U_ID(5, 7) - -/* larb6 */ -#define M4U_PORT_L6_SVPP3_MDP_RDMA MTK_M4U_ID(6, 0) -#define M4U_PORT_L6_SVPP3_MDP_FG MTK_M4U_ID(6, 1) -#define M4U_PORT_L6_SVPP3_MDP_WROT MTK_M4U_ID(6, 2) -#define M4U_PORT_L6_FAKE MTK_M4U_ID(6, 3) - -/* larb7 */ -#define M4U_PORT_L7_IMG_WPE_RDMA0 MTK_M4U_ID(7, 0) -#define M4U_PORT_L7_IMG_WPE_RDMA1 MTK_M4U_ID(7, 1) -#define M4U_PORT_L7_IMG_WPE_WDMA0 MTK_M4U_ID(7, 2) - -/* larb8 */ -#define M4U_PORT_L8_IMG_WPE_RDMA0 MTK_M4U_ID(8, 0) -#define M4U_PORT_L8_IMG_WPE_RDMA1 MTK_M4U_ID(8, 1) -#define M4U_PORT_L8_IMG_WPE_WDMA0 MTK_M4U_ID(8, 2) - -/* larb9 */ -#define M4U_PORT_L9_IMG_IMGI_T1_A MTK_M4U_ID(9, 0) -#define M4U_PORT_L9_IMG_IMGBI_T1_A MTK_M4U_ID(9, 1) -#define M4U_PORT_L9_IMG_IMGCI_T1_A MTK_M4U_ID(9, 2) -#define M4U_PORT_L9_IMG_SMTI_T1_A MTK_M4U_ID(9, 3) -#define M4U_PORT_L9_IMG_TNCSTI_T1_A MTK_M4U_ID(9, 4) -#define M4U_PORT_L9_IMG_TNCSTI_T4_A MTK_M4U_ID(9, 5) -#define M4U_PORT_L9_IMG_YUVO_T1_A MTK_M4U_ID(9, 6) -#define M4U_PORT_L9_IMG_TIMGO_T1_A MTK_M4U_ID(9, 7) -#define M4U_PORT_L9_IMG_YUVO_T2_A MTK_M4U_ID(9, 8) -#define M4U_PORT_L9_IMG_IMGI_T1_B MTK_M4U_ID(9, 9) -#define M4U_PORT_L9_IMG_IMGBI_T1_B MTK_M4U_ID(9, 10) -#define M4U_PORT_L9_IMG_IMGCI_T1_B MTK_M4U_ID(9, 11) -#define M4U_PORT_L9_IMG_YUVO_T5_A MTK_M4U_ID(9, 12) -#define M4U_PORT_L9_IMG_SMTI_T1_B MTK_M4U_ID(9, 13) -#define M4U_PORT_L9_IMG_TNCSO_T1_A MTK_M4U_ID(9, 14) -#define M4U_PORT_L9_IMG_SMTO_T1_A MTK_M4U_ID(9, 15) -#define M4U_PORT_L9_IMG_TNCSTO_T1_A MTK_M4U_ID(9, 16) -#define M4U_PORT_L9_IMG_YUVO_T2_B MTK_M4U_ID(9, 17) -#define M4U_PORT_L9_IMG_YUVO_T5_B MTK_M4U_ID(9, 18) -#define M4U_PORT_L9_IMG_SMTO_T1_B MTK_M4U_ID(9, 19) - -/* larb10 */ -#define M4U_PORT_L10_IMG_IMGI_D1_A MTK_M4U_ID(10, 0) -#define M4U_PORT_L10_IMG_IMGCI_D1_A MTK_M4U_ID(10, 1) -#define M4U_PORT_L10_IMG_DEPI_D1_A MTK_M4U_ID(10, 2) -#define M4U_PORT_L10_IMG_DMGI_D1_A MTK_M4U_ID(10, 3) -#define M4U_PORT_L10_IMG_VIPI_D1_A MTK_M4U_ID(10, 4) -#define M4U_PORT_L10_IMG_TNRWI_D1_A MTK_M4U_ID(10, 5) -#define M4U_PORT_L10_IMG_RECI_D1_A MTK_M4U_ID(10, 6) -#define M4U_PORT_L10_IMG_SMTI_D1_A MTK_M4U_ID(10, 7) -#define M4U_PORT_L10_IMG_SMTI_D6_A MTK_M4U_ID(10, 8) -#define M4U_PORT_L10_IMG_PIMGI_P1_A MTK_M4U_ID(10, 9) -#define M4U_PORT_L10_IMG_PIMGBI_P1_A MTK_M4U_ID(10, 10) -#define M4U_PORT_L10_IMG_PIMGCI_P1_A MTK_M4U_ID(10, 11) -#define M4U_PORT_L10_IMG_PIMGI_P1_B MTK_M4U_ID(10, 12) -#define M4U_PORT_L10_IMG_PIMGBI_P1_B MTK_M4U_ID(10, 13) -#define M4U_PORT_L10_IMG_PIMGCI_P1_B MTK_M4U_ID(10, 14) -#define M4U_PORT_L10_IMG_IMG3O_D1_A MTK_M4U_ID(10, 15) -#define M4U_PORT_L10_IMG_IMG4O_D1_A MTK_M4U_ID(10, 16) -#define M4U_PORT_L10_IMG_IMG3CO_D1_A MTK_M4U_ID(10, 17) -#define M4U_PORT_L10_IMG_FEO_D1_A MTK_M4U_ID(10, 18) -#define M4U_PORT_L10_IMG_IMG2O_D1_A MTK_M4U_ID(10, 19) -#define M4U_PORT_L10_IMG_TNRWO_D1_A MTK_M4U_ID(10, 20) -#define M4U_PORT_L10_IMG_SMTO_D1_A MTK_M4U_ID(10, 21) -#define M4U_PORT_L10_IMG_WROT_P1_A MTK_M4U_ID(10, 22) -#define M4U_PORT_L10_IMG_WROT_P1_B MTK_M4U_ID(10, 23) - -/* larb11 */ -#define M4U_PORT_L11_IMG_WPE_EIS_RDMA0_A MTK_M4U_ID(11, 0) -#define M4U_PORT_L11_IMG_WPE_EIS_RDMA1_A MTK_M4U_ID(11, 1) -#define M4U_PORT_L11_IMG_WPE_EIS_WDMA0_A MTK_M4U_ID(11, 2) -#define M4U_PORT_L11_IMG_WPE_TNR_RDMA0_A MTK_M4U_ID(11, 3) -#define M4U_PORT_L11_IMG_WPE_TNR_RDMA1_A MTK_M4U_ID(11, 4) -#define M4U_PORT_L11_IMG_WPE_TNR_WDMA0_A MTK_M4U_ID(11, 5) -#define M4U_PORT_L11_IMG_WPE_EIS_CQ0_A MTK_M4U_ID(11, 6) -#define M4U_PORT_L11_IMG_WPE_EIS_CQ1_A MTK_M4U_ID(11, 7) -#define M4U_PORT_L11_IMG_WPE_TNR_CQ0_A MTK_M4U_ID(11, 8) -#define M4U_PORT_L11_IMG_WPE_TNR_CQ1_A MTK_M4U_ID(11, 9) - -/* larb12 */ -#define M4U_PORT_L12_IMG_FDVT_RDA MTK_M4U_ID(12, 0) -#define M4U_PORT_L12_IMG_FDVT_RDB MTK_M4U_ID(12, 1) -#define M4U_PORT_L12_IMG_FDVT_WRA MTK_M4U_ID(12, 2) -#define M4U_PORT_L12_IMG_FDVT_WRB MTK_M4U_ID(12, 3) -#define M4U_PORT_L12_IMG_ME_RDMA MTK_M4U_ID(12, 4) -#define M4U_PORT_L12_IMG_ME_WDMA MTK_M4U_ID(12, 5) -#define M4U_PORT_L12_IMG_DVS_RDMA MTK_M4U_ID(12, 6) -#define M4U_PORT_L12_IMG_DVS_WDMA MTK_M4U_ID(12, 7) -#define M4U_PORT_L12_IMG_DVP_RDMA MTK_M4U_ID(12, 8) -#define M4U_PORT_L12_IMG_DVP_WDMA MTK_M4U_ID(12, 9) - -/* larb13 */ -#define M4U_PORT_L13_CAM_CAMSV_CQI_E1 MTK_M4U_ID(13, 0) -#define M4U_PORT_L13_CAM_CAMSV_CQI_E2 MTK_M4U_ID(13, 1) -#define M4U_PORT_L13_CAM_GCAMSV_A_IMGO_0 MTK_M4U_ID(13, 2) -#define M4U_PORT_L13_CAM_SCAMSV_A_IMGO_0 MTK_M4U_ID(13, 3) -#define M4U_PORT_L13_CAM_GCAMSV_B_IMGO_0 MTK_M4U_ID(13, 4) -#define M4U_PORT_L13_CAM_GCAMSV_B_IMGO_1 MTK_M4U_ID(13, 5) -#define M4U_PORT_L13_CAM_GCAMSV_A_UFEO_0 MTK_M4U_ID(13, 6) -#define M4U_PORT_L13_CAM_GCAMSV_B_UFEO_0 MTK_M4U_ID(13, 7) -#define M4U_PORT_L13_CAM_PDAI_0 MTK_M4U_ID(13, 8) -#define M4U_PORT_L13_CAM_FAKE MTK_M4U_ID(13, 9) - -/* larb14 */ -#define M4U_PORT_L14_CAM_GCAMSV_A_IMGO_1 MTK_M4U_ID(14, 0) -#define M4U_PORT_L14_CAM_SCAMSV_A_IMGO_1 MTK_M4U_ID(14, 1) -#define M4U_PORT_L14_CAM_GCAMSV_B_IMGO_0 MTK_M4U_ID(14, 2) -#define M4U_PORT_L14_CAM_GCAMSV_B_IMGO_1 MTK_M4U_ID(14, 3) -#define M4U_PORT_L14_CAM_SCAMSV_B_IMGO_0 MTK_M4U_ID(14, 4) -#define M4U_PORT_L14_CAM_SCAMSV_B_IMGO_1 MTK_M4U_ID(14, 5) -#define M4U_PORT_L14_CAM_IPUI MTK_M4U_ID(14, 6) -#define M4U_PORT_L14_CAM_IPU2I MTK_M4U_ID(14, 7) -#define M4U_PORT_L14_CAM_IPUO MTK_M4U_ID(14, 8) -#define M4U_PORT_L14_CAM_IPU2O MTK_M4U_ID(14, 9) -#define M4U_PORT_L14_CAM_IPU3O MTK_M4U_ID(14, 10) -#define M4U_PORT_L14_CAM_GCAMSV_A_UFEO_1 MTK_M4U_ID(14, 11) -#define M4U_PORT_L14_CAM_GCAMSV_B_UFEO_1 MTK_M4U_ID(14, 12) -#define M4U_PORT_L14_CAM_PDAI_1 MTK_M4U_ID(14, 13) -#define M4U_PORT_L14_CAM_PDAO MTK_M4U_ID(14, 14) - -/* larb15: null */ - -/* larb16 */ -#define M4U_PORT_L16_CAM_IMGO_R1 MTK_M4U_ID(16, 0) -#define M4U_PORT_L16_CAM_CQI_R1 MTK_M4U_ID(16, 1) -#define M4U_PORT_L16_CAM_CQI_R2 MTK_M4U_ID(16, 2) -#define M4U_PORT_L16_CAM_BPCI_R1 MTK_M4U_ID(16, 3) -#define M4U_PORT_L16_CAM_LSCI_R1 MTK_M4U_ID(16, 4) -#define M4U_PORT_L16_CAM_RAWI_R2 MTK_M4U_ID(16, 5) -#define M4U_PORT_L16_CAM_RAWI_R3 MTK_M4U_ID(16, 6) -#define M4U_PORT_L16_CAM_UFDI_R2 MTK_M4U_ID(16, 7) -#define M4U_PORT_L16_CAM_UFDI_R3 MTK_M4U_ID(16, 8) -#define M4U_PORT_L16_CAM_RAWI_R4 MTK_M4U_ID(16, 9) -#define M4U_PORT_L16_CAM_RAWI_R5 MTK_M4U_ID(16, 10) -#define M4U_PORT_L16_CAM_AAI_R1 MTK_M4U_ID(16, 11) -#define M4U_PORT_L16_CAM_FHO_R1 MTK_M4U_ID(16, 12) -#define M4U_PORT_L16_CAM_AAO_R1 MTK_M4U_ID(16, 13) -#define M4U_PORT_L16_CAM_TSFSO_R1 MTK_M4U_ID(16, 14) -#define M4U_PORT_L16_CAM_FLKO_R1 MTK_M4U_ID(16, 15) - -/* larb17 */ -#define M4U_PORT_L17_CAM_YUVO_R1 MTK_M4U_ID(17, 0) -#define M4U_PORT_L17_CAM_YUVO_R3 MTK_M4U_ID(17, 1) -#define M4U_PORT_L17_CAM_YUVCO_R1 MTK_M4U_ID(17, 2) -#define M4U_PORT_L17_CAM_YUVO_R2 MTK_M4U_ID(17, 3) -#define M4U_PORT_L17_CAM_RZH1N2TO_R1 MTK_M4U_ID(17, 4) -#define M4U_PORT_L17_CAM_DRZS4NO_R1 MTK_M4U_ID(17, 5) -#define M4U_PORT_L17_CAM_TNCSO_R1 MTK_M4U_ID(17, 6) - -/* larb18 */ -#define M4U_PORT_L18_CAM_CCUI MTK_M4U_ID(18, 0) -#define M4U_PORT_L18_CAM_CCUO MTK_M4U_ID(18, 1) -#define M4U_PORT_L18_CAM_CCUI2 MTK_M4U_ID(18, 2) -#define M4U_PORT_L18_CAM_CCUO2 MTK_M4U_ID(18, 3) - -/* larb19 */ -#define M4U_PORT_L19_VENC_RCPU MTK_M4U_ID(19, 0) -#define M4U_PORT_L19_VENC_REC MTK_M4U_ID(19, 1) -#define M4U_PORT_L19_VENC_BSDMA MTK_M4U_ID(19, 2) -#define M4U_PORT_L19_VENC_SV_COMV MTK_M4U_ID(19, 3) -#define M4U_PORT_L19_VENC_RD_COMV MTK_M4U_ID(19, 4) -#define M4U_PORT_L19_VENC_NBM_RDMA MTK_M4U_ID(19, 5) -#define M4U_PORT_L19_VENC_NBM_RDMA_LITE MTK_M4U_ID(19, 6) -#define M4U_PORT_L19_JPGENC_Y_RDMA MTK_M4U_ID(19, 7) -#define M4U_PORT_L19_JPGENC_C_RDMA MTK_M4U_ID(19, 8) -#define M4U_PORT_L19_JPGENC_Q_TABLE MTK_M4U_ID(19, 9) -#define M4U_PORT_L19_VENC_SUB_W_LUMA MTK_M4U_ID(19, 10) -#define M4U_PORT_L19_VENC_FCS_NBM_RDMA MTK_M4U_ID(19, 11) -#define M4U_PORT_L19_JPGENC_BSDMA MTK_M4U_ID(19, 12) -#define M4U_PORT_L19_JPGDEC_WDMA0 MTK_M4U_ID(19, 13) -#define M4U_PORT_L19_JPGDEC_BSDMA0 MTK_M4U_ID(19, 14) -#define M4U_PORT_L19_VENC_NBM_WDMA MTK_M4U_ID(19, 15) -#define M4U_PORT_L19_VENC_NBM_WDMA_LITE MTK_M4U_ID(19, 16) -#define M4U_PORT_L19_VENC_FCS_NBM_WDMA MTK_M4U_ID(19, 17) -#define M4U_PORT_L19_JPGDEC_WDMA1 MTK_M4U_ID(19, 18) -#define M4U_PORT_L19_JPGDEC_BSDMA1 MTK_M4U_ID(19, 19) -#define M4U_PORT_L19_JPGDEC_BUFF_OFFSET1 MTK_M4U_ID(19, 20) -#define M4U_PORT_L19_JPGDEC_BUFF_OFFSET0 MTK_M4U_ID(19, 21) -#define M4U_PORT_L19_VENC_CUR_LUMA MTK_M4U_ID(19, 22) -#define M4U_PORT_L19_VENC_CUR_CHROMA MTK_M4U_ID(19, 23) -#define M4U_PORT_L19_VENC_REF_LUMA MTK_M4U_ID(19, 24) -#define M4U_PORT_L19_VENC_REF_CHROMA MTK_M4U_ID(19, 25) -#define M4U_PORT_L19_VENC_SUB_R_CHROMA MTK_M4U_ID(19, 26) - -/* larb20 */ -#define M4U_PORT_L20_VENC_RCPU MTK_M4U_ID(20, 0) -#define M4U_PORT_L20_VENC_REC MTK_M4U_ID(20, 1) -#define M4U_PORT_L20_VENC_BSDMA MTK_M4U_ID(20, 2) -#define M4U_PORT_L20_VENC_SV_COMV MTK_M4U_ID(20, 3) -#define M4U_PORT_L20_VENC_RD_COMV MTK_M4U_ID(20, 4) -#define M4U_PORT_L20_VENC_NBM_RDMA MTK_M4U_ID(20, 5) -#define M4U_PORT_L20_VENC_NBM_RDMA_LITE MTK_M4U_ID(20, 6) -#define M4U_PORT_L20_JPGENC_Y_RDMA MTK_M4U_ID(20, 7) -#define M4U_PORT_L20_JPGENC_C_RDMA MTK_M4U_ID(20, 8) -#define M4U_PORT_L20_JPGENC_Q_TABLE MTK_M4U_ID(20, 9) -#define M4U_PORT_L20_VENC_SUB_W_LUMA MTK_M4U_ID(20, 10) -#define M4U_PORT_L20_VENC_FCS_NBM_RDMA MTK_M4U_ID(20, 11) -#define M4U_PORT_L20_JPGENC_BSDMA MTK_M4U_ID(20, 12) -#define M4U_PORT_L20_JPGDEC_WDMA0 MTK_M4U_ID(20, 13) -#define M4U_PORT_L20_JPGDEC_BSDMA0 MTK_M4U_ID(20, 14) -#define M4U_PORT_L20_VENC_NBM_WDMA MTK_M4U_ID(20, 15) -#define M4U_PORT_L20_VENC_NBM_WDMA_LITE MTK_M4U_ID(20, 16) -#define M4U_PORT_L20_VENC_FCS_NBM_WDMA MTK_M4U_ID(20, 17) -#define M4U_PORT_L20_JPGDEC_WDMA1 MTK_M4U_ID(20, 18) -#define M4U_PORT_L20_JPGDEC_BSDMA1 MTK_M4U_ID(20, 19) -#define M4U_PORT_L20_JPGDEC_BUFF_OFFSET1 MTK_M4U_ID(20, 20) -#define M4U_PORT_L20_JPGDEC_BUFF_OFFSET0 MTK_M4U_ID(20, 21) -#define M4U_PORT_L20_VENC_CUR_LUMA MTK_M4U_ID(20, 22) -#define M4U_PORT_L20_VENC_CUR_CHROMA MTK_M4U_ID(20, 23) -#define M4U_PORT_L20_VENC_REF_LUMA MTK_M4U_ID(20, 24) -#define M4U_PORT_L20_VENC_REF_CHROMA MTK_M4U_ID(20, 25) -#define M4U_PORT_L20_VENC_SUB_R_CHROMA MTK_M4U_ID(20, 26) - -/* larb21 */ -#define M4U_PORT_L21_VDEC_MC_EXT MTK_M4U_ID(21, 0) -#define M4U_PORT_L21_VDEC_UFO_EXT MTK_M4U_ID(21, 1) -#define M4U_PORT_L21_VDEC_PP_EXT MTK_M4U_ID(21, 2) -#define M4U_PORT_L21_VDEC_PRED_RD_EXT MTK_M4U_ID(21, 3) -#define M4U_PORT_L21_VDEC_PRED_WR_EXT MTK_M4U_ID(21, 4) -#define M4U_PORT_L21_VDEC_PPWRAP_EXT MTK_M4U_ID(21, 5) -#define M4U_PORT_L21_VDEC_TILE_EXT MTK_M4U_ID(21, 6) -#define M4U_PORT_L21_VDEC_VLD_EXT MTK_M4U_ID(21, 7) -#define M4U_PORT_L21_VDEC_VLD2_EXT MTK_M4U_ID(21, 8) -#define M4U_PORT_L21_VDEC_AVC_MV_EXT MTK_M4U_ID(21, 9) - -/* larb22 */ -#define M4U_PORT_L22_VDEC_MC_EXT MTK_M4U_ID(22, 0) -#define M4U_PORT_L22_VDEC_UFO_EXT MTK_M4U_ID(22, 1) -#define M4U_PORT_L22_VDEC_PP_EXT MTK_M4U_ID(22, 2) -#define M4U_PORT_L22_VDEC_PRED_RD_EXT MTK_M4U_ID(22, 3) -#define M4U_PORT_L22_VDEC_PRED_WR_EXT MTK_M4U_ID(22, 4) -#define M4U_PORT_L22_VDEC_PPWRAP_EXT MTK_M4U_ID(22, 5) -#define M4U_PORT_L22_VDEC_TILE_EXT MTK_M4U_ID(22, 6) -#define M4U_PORT_L22_VDEC_VLD_EXT MTK_M4U_ID(22, 7) -#define M4U_PORT_L22_VDEC_VLD2_EXT MTK_M4U_ID(22, 8) -#define M4U_PORT_L22_VDEC_AVC_MV_EXT MTK_M4U_ID(22, 9) - -/* larb23 */ -#define M4U_PORT_L23_VDEC_UFO_ENC_EXT MTK_M4U_ID(23, 0) -#define M4U_PORT_L23_VDEC_RDMA_EXT MTK_M4U_ID(23, 1) - -/* larb24 */ -#define M4U_PORT_L24_VDEC_LAT0_VLD_EXT MTK_M4U_ID(24, 0) -#define M4U_PORT_L24_VDEC_LAT0_VLD2_EXT MTK_M4U_ID(24, 1) -#define M4U_PORT_L24_VDEC_LAT0_AVC_MC_EXT MTK_M4U_ID(24, 2) -#define M4U_PORT_L24_VDEC_LAT0_PRED_RD_EXT MTK_M4U_ID(24, 3) -#define M4U_PORT_L24_VDEC_LAT0_TILE_EXT MTK_M4U_ID(24, 4) -#define M4U_PORT_L24_VDEC_LAT0_WDMA_EXT MTK_M4U_ID(24, 5) -#define M4U_PORT_L24_VDEC_LAT1_VLD_EXT MTK_M4U_ID(24, 6) -#define M4U_PORT_L24_VDEC_LAT1_VLD2_EXT MTK_M4U_ID(24, 7) -#define M4U_PORT_L24_VDEC_LAT1_AVC_MC_EXT MTK_M4U_ID(24, 8) -#define M4U_PORT_L24_VDEC_LAT1_PRED_RD_EXT MTK_M4U_ID(24, 9) -#define M4U_PORT_L24_VDEC_LAT1_TILE_EXT MTK_M4U_ID(24, 10) -#define M4U_PORT_L24_VDEC_LAT1_WDMA_EXT MTK_M4U_ID(24, 11) - -/* larb25 */ -#define M4U_PORT_L25_CAM_MRAW0_LSCI_M1 MTK_M4U_ID(25, 0) -#define M4U_PORT_L25_CAM_MRAW0_CQI_M1 MTK_M4U_ID(25, 1) -#define M4U_PORT_L25_CAM_MRAW0_CQI_M2 MTK_M4U_ID(25, 2) -#define M4U_PORT_L25_CAM_MRAW0_IMGO_M1 MTK_M4U_ID(25, 3) -#define M4U_PORT_L25_CAM_MRAW0_IMGBO_M1 MTK_M4U_ID(25, 4) -#define M4U_PORT_L25_CAM_MRAW2_LSCI_M1 MTK_M4U_ID(25, 5) -#define M4U_PORT_L25_CAM_MRAW2_CQI_M1 MTK_M4U_ID(25, 6) -#define M4U_PORT_L25_CAM_MRAW2_CQI_M2 MTK_M4U_ID(25, 7) -#define M4U_PORT_L25_CAM_MRAW2_IMGO_M1 MTK_M4U_ID(25, 8) -#define M4U_PORT_L25_CAM_MRAW2_IMGBO_M1 MTK_M4U_ID(25, 9) -#define M4U_PORT_L25_CAM_MRAW0_AFO_M1 MTK_M4U_ID(25, 10) -#define M4U_PORT_L25_CAM_MRAW2_AFO_M1 MTK_M4U_ID(25, 11) - -/* larb26 */ -#define M4U_PORT_L26_CAM_MRAW1_LSCI_M1 MTK_M4U_ID(26, 0) -#define M4U_PORT_L26_CAM_MRAW1_CQI_M1 MTK_M4U_ID(26, 1) -#define M4U_PORT_L26_CAM_MRAW1_CQI_M2 MTK_M4U_ID(26, 2) -#define M4U_PORT_L26_CAM_MRAW1_IMGO_M1 MTK_M4U_ID(26, 3) -#define M4U_PORT_L26_CAM_MRAW1_IMGBO_M1 MTK_M4U_ID(26, 4) -#define M4U_PORT_L26_CAM_MRAW3_LSCI_M1 MTK_M4U_ID(26, 5) -#define M4U_PORT_L26_CAM_MRAW3_CQI_M1 MTK_M4U_ID(26, 6) -#define M4U_PORT_L26_CAM_MRAW3_CQI_M2 MTK_M4U_ID(26, 7) -#define M4U_PORT_L26_CAM_MRAW3_IMGO_M1 MTK_M4U_ID(26, 8) -#define M4U_PORT_L26_CAM_MRAW3_IMGBO_M1 MTK_M4U_ID(26, 9) -#define M4U_PORT_L26_CAM_MRAW1_AFO_M1 MTK_M4U_ID(26, 10) -#define M4U_PORT_L26_CAM_MRAW3_AFO_M1 MTK_M4U_ID(26, 11) - -/* larb27 */ -#define M4U_PORT_L27_CAM_IMGO_R1 MTK_M4U_ID(27, 0) -#define M4U_PORT_L27_CAM_CQI_R1 MTK_M4U_ID(27, 1) -#define M4U_PORT_L27_CAM_CQI_R2 MTK_M4U_ID(27, 2) -#define M4U_PORT_L27_CAM_BPCI_R1 MTK_M4U_ID(27, 3) -#define M4U_PORT_L27_CAM_LSCI_R1 MTK_M4U_ID(27, 4) -#define M4U_PORT_L27_CAM_RAWI_R2 MTK_M4U_ID(27, 5) -#define M4U_PORT_L27_CAM_RAWI_R3 MTK_M4U_ID(27, 6) -#define M4U_PORT_L27_CAM_UFDI_R2 MTK_M4U_ID(27, 7) -#define M4U_PORT_L27_CAM_UFDI_R3 MTK_M4U_ID(27, 8) -#define M4U_PORT_L27_CAM_RAWI_R4 MTK_M4U_ID(27, 9) -#define M4U_PORT_L27_CAM_RAWI_R5 MTK_M4U_ID(27, 10) -#define M4U_PORT_L27_CAM_AAI_R1 MTK_M4U_ID(27, 11) -#define M4U_PORT_L27_CAM_FHO_R1 MTK_M4U_ID(27, 12) -#define M4U_PORT_L27_CAM_AAO_R1 MTK_M4U_ID(27, 13) -#define M4U_PORT_L27_CAM_TSFSO_R1 MTK_M4U_ID(27, 14) -#define M4U_PORT_L27_CAM_FLKO_R1 MTK_M4U_ID(27, 15) - -/* larb28 */ -#define M4U_PORT_L28_CAM_YUVO_R1 MTK_M4U_ID(28, 0) -#define M4U_PORT_L28_CAM_YUVO_R3 MTK_M4U_ID(28, 1) -#define M4U_PORT_L28_CAM_YUVCO_R1 MTK_M4U_ID(28, 2) -#define M4U_PORT_L28_CAM_YUVO_R2 MTK_M4U_ID(28, 3) -#define M4U_PORT_L28_CAM_RZH1N2TO_R1 MTK_M4U_ID(28, 4) -#define M4U_PORT_L28_CAM_DRZS4NO_R1 MTK_M4U_ID(28, 5) -#define M4U_PORT_L28_CAM_TNCSO_R1 MTK_M4U_ID(28, 6) - -/* Infra iommu ports */ -/* PCIe1: read: BIT16; write BIT17. */ -#define IOMMU_PORT_INFRA_PCIE1 MTK_IFAIOMMU_PERI_ID(16) -/* PCIe0: read: BIT18; write BIT19. */ -#define IOMMU_PORT_INFRA_PCIE0 MTK_IFAIOMMU_PERI_ID(18) -#define IOMMU_PORT_INFRA_SSUSB_P3_R MTK_IFAIOMMU_PERI_ID(20) -#define IOMMU_PORT_INFRA_SSUSB_P3_W MTK_IFAIOMMU_PERI_ID(21) -#define IOMMU_PORT_INFRA_SSUSB_P2_R MTK_IFAIOMMU_PERI_ID(22) -#define IOMMU_PORT_INFRA_SSUSB_P2_W MTK_IFAIOMMU_PERI_ID(23) -#define IOMMU_PORT_INFRA_SSUSB_P1_1_R MTK_IFAIOMMU_PERI_ID(24) -#define IOMMU_PORT_INFRA_SSUSB_P1_1_W MTK_IFAIOMMU_PERI_ID(25) -#define IOMMU_PORT_INFRA_SSUSB_P1_0_R MTK_IFAIOMMU_PERI_ID(26) -#define IOMMU_PORT_INFRA_SSUSB_P1_0_W MTK_IFAIOMMU_PERI_ID(27) -#define IOMMU_PORT_INFRA_SSUSB2_R MTK_IFAIOMMU_PERI_ID(28) -#define IOMMU_PORT_INFRA_SSUSB2_W MTK_IFAIOMMU_PERI_ID(29) -#define IOMMU_PORT_INFRA_SSUSB_R MTK_IFAIOMMU_PERI_ID(30) -#define IOMMU_PORT_INFRA_SSUSB_W MTK_IFAIOMMU_PERI_ID(31) - -#endif diff --git a/include/dt-bindings/memory/mtk-memory-port.h b/include/dt-bindings/memory/mtk-memory-port.h deleted file mode 100644 index 2f68a0511a2..00000000000 --- a/include/dt-bindings/memory/mtk-memory-port.h +++ /dev/null @@ -1,17 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2020 MediaTek Inc. - * Author: Yong Wu <yong.wu@mediatek.com> - */ -#ifndef __DT_BINDINGS_MEMORY_MTK_MEMORY_PORT_H_ -#define __DT_BINDINGS_MEMORY_MTK_MEMORY_PORT_H_ - -#define MTK_LARB_NR_MAX 32 - -#define MTK_M4U_ID(larb, port) (((larb) << 5) | (port)) -#define MTK_M4U_TO_LARB(id) (((id) >> 5) & 0x1f) -#define MTK_M4U_TO_PORT(id) ((id) & 0x1f) - -#define MTK_IFAIOMMU_PERI_ID(port) MTK_M4U_ID(0, port) - -#endif diff --git a/include/dt-bindings/memory/rk3368-dmc.h b/include/dt-bindings/memory/rk3368-dmc.h new file mode 100644 index 00000000000..b06ffde7186 --- /dev/null +++ b/include/dt-bindings/memory/rk3368-dmc.h @@ -0,0 +1,30 @@ +#ifndef DT_BINDINGS_RK3368_DMC_H +#define DT_BINDINGS_RK3368_DMC_H + +#define DMC_MSCH_CBDR 0x0 +#define DMC_MSCH_CBRD 0x1 +#define DMC_MSCH_CRBD 0x2 + +#define DDR3_800D 0 +#define DDR3_800E 1 +#define DDR3_1066E 2 +#define DDR3_1066F 3 +#define DDR3_1066G 4 +#define DDR3_1333F 5 +#define DDR3_1333G 6 +#define DDR3_1333H 7 +#define DDR3_1333J 8 +#define DDR3_1600G 9 +#define DDR3_1600H 10 +#define DDR3_1600J 11 +#define DDR3_1600K 12 +#define DDR3_1866J 13 +#define DDR3_1866K 14 +#define DDR3_1866L 15 +#define DDR3_1866M 16 +#define DDR3_2133K 17 +#define DDR3_2133L 18 +#define DDR3_2133M 19 +#define DDR3_2133N 20 + +#endif diff --git a/include/dt-bindings/memory/stm32-sdram.h b/include/dt-bindings/memory/stm32-sdram.h new file mode 100644 index 00000000000..90ef2e15906 --- /dev/null +++ b/include/dt-bindings/memory/stm32-sdram.h @@ -0,0 +1,48 @@ +#ifndef DT_BINDINGS_STM32_SDRAM_H +#define DT_BINDINGS_STM32_SDRAM_H + +#define NO_COL_8 0x0 +#define NO_COL_9 0x1 +#define NO_COL_10 0x2 +#define NO_COL_11 0x3 + +#define NO_ROW_11 0x0 +#define NO_ROW_12 0x1 +#define NO_ROW_13 0x2 + +#define MWIDTH_8 0x0 +#define MWIDTH_16 0x1 +#define MWIDTH_32 0x2 +#define BANKS_2 0x0 +#define BANKS_4 0x1 +#define CAS_1 0x1 +#define CAS_2 0x2 +#define CAS_3 0x3 +#define SDCLK_DIS 0x0 +#define SDCLK_2 0x2 +#define SDCLK_3 0x3 +#define RD_BURST_EN 0x1 +#define RD_BURST_DIS 0x0 +#define RD_PIPE_DL_0 0x0 +#define RD_PIPE_DL_1 0x1 +#define RD_PIPE_DL_2 0x2 + +/* Timing = value +1 cycles */ +#define TMRD_1 (1 - 1) +#define TMRD_2 (2 - 1) +#define TMRD_3 (3 - 1) +#define TXSR_1 (1 - 1) +#define TXSR_6 (6 - 1) +#define TXSR_7 (7 - 1) +#define TXSR_8 (8 - 1) +#define TRAS_1 (1 - 1) +#define TRAS_4 (4 - 1) +#define TRAS_6 (6 - 1) +#define TRC_6 (6 - 1) +#define TWR_1 (1 - 1) +#define TWR_2 (2 - 1) +#define TRP_2 (2 - 1) +#define TRCD_1 (1 - 1) +#define TRCD_2 (2 - 1) + +#endif diff --git a/include/dt-bindings/memory/tegra114-mc.h b/include/dt-bindings/memory/tegra114-mc.h deleted file mode 100644 index dfe99c8a5ba..00000000000 --- a/include/dt-bindings/memory/tegra114-mc.h +++ /dev/null @@ -1,43 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef DT_BINDINGS_MEMORY_TEGRA114_MC_H -#define DT_BINDINGS_MEMORY_TEGRA114_MC_H - -#define TEGRA_SWGROUP_PTC 0 -#define TEGRA_SWGROUP_DC 1 -#define TEGRA_SWGROUP_DCB 2 -#define TEGRA_SWGROUP_EPP 3 -#define TEGRA_SWGROUP_G2 4 -#define TEGRA_SWGROUP_AVPC 5 -#define TEGRA_SWGROUP_NV 6 -#define TEGRA_SWGROUP_HDA 7 -#define TEGRA_SWGROUP_HC 8 -#define TEGRA_SWGROUP_MSENC 9 -#define TEGRA_SWGROUP_PPCS 10 -#define TEGRA_SWGROUP_VDE 11 -#define TEGRA_SWGROUP_MPCORELP 12 -#define TEGRA_SWGROUP_MPCORE 13 -#define TEGRA_SWGROUP_VI 14 -#define TEGRA_SWGROUP_ISP 15 -#define TEGRA_SWGROUP_XUSB_HOST 16 -#define TEGRA_SWGROUP_XUSB_DEV 17 -#define TEGRA_SWGROUP_EMUCIF 18 -#define TEGRA_SWGROUP_TSEC 19 - -#define TEGRA114_MC_RESET_AVPC 0 -#define TEGRA114_MC_RESET_DC 1 -#define TEGRA114_MC_RESET_DCB 2 -#define TEGRA114_MC_RESET_EPP 3 -#define TEGRA114_MC_RESET_2D 4 -#define TEGRA114_MC_RESET_HC 5 -#define TEGRA114_MC_RESET_HDA 6 -#define TEGRA114_MC_RESET_ISP 7 -#define TEGRA114_MC_RESET_MPCORE 8 -#define TEGRA114_MC_RESET_MPCORELP 9 -#define TEGRA114_MC_RESET_MPE 10 -#define TEGRA114_MC_RESET_3D 11 -#define TEGRA114_MC_RESET_3D2 12 -#define TEGRA114_MC_RESET_PPCS 13 -#define TEGRA114_MC_RESET_VDE 14 -#define TEGRA114_MC_RESET_VI 15 - -#endif diff --git a/include/dt-bindings/memory/tegra124-mc.h b/include/dt-bindings/memory/tegra124-mc.h deleted file mode 100644 index 7e73bb400ec..00000000000 --- a/include/dt-bindings/memory/tegra124-mc.h +++ /dev/null @@ -1,125 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef DT_BINDINGS_MEMORY_TEGRA124_MC_H -#define DT_BINDINGS_MEMORY_TEGRA124_MC_H - -#define TEGRA_SWGROUP_PTC 0 -#define TEGRA_SWGROUP_DC 1 -#define TEGRA_SWGROUP_DCB 2 -#define TEGRA_SWGROUP_AFI 3 -#define TEGRA_SWGROUP_AVPC 4 -#define TEGRA_SWGROUP_HDA 5 -#define TEGRA_SWGROUP_HC 6 -#define TEGRA_SWGROUP_MSENC 7 -#define TEGRA_SWGROUP_PPCS 8 -#define TEGRA_SWGROUP_SATA 9 -#define TEGRA_SWGROUP_VDE 10 -#define TEGRA_SWGROUP_MPCORELP 11 -#define TEGRA_SWGROUP_MPCORE 12 -#define TEGRA_SWGROUP_ISP2 13 -#define TEGRA_SWGROUP_XUSB_HOST 14 -#define TEGRA_SWGROUP_XUSB_DEV 15 -#define TEGRA_SWGROUP_ISP2B 16 -#define TEGRA_SWGROUP_TSEC 17 -#define TEGRA_SWGROUP_A9AVP 18 -#define TEGRA_SWGROUP_GPU 19 -#define TEGRA_SWGROUP_SDMMC1A 20 -#define TEGRA_SWGROUP_SDMMC2A 21 -#define TEGRA_SWGROUP_SDMMC3A 22 -#define TEGRA_SWGROUP_SDMMC4A 23 -#define TEGRA_SWGROUP_VIC 24 -#define TEGRA_SWGROUP_VI 25 - -#define TEGRA124_MC_RESET_AFI 0 -#define TEGRA124_MC_RESET_AVPC 1 -#define TEGRA124_MC_RESET_DC 2 -#define TEGRA124_MC_RESET_DCB 3 -#define TEGRA124_MC_RESET_HC 4 -#define TEGRA124_MC_RESET_HDA 5 -#define TEGRA124_MC_RESET_ISP2 6 -#define TEGRA124_MC_RESET_MPCORE 7 -#define TEGRA124_MC_RESET_MPCORELP 8 -#define TEGRA124_MC_RESET_MSENC 9 -#define TEGRA124_MC_RESET_PPCS 10 -#define TEGRA124_MC_RESET_SATA 11 -#define TEGRA124_MC_RESET_VDE 12 -#define TEGRA124_MC_RESET_VI 13 -#define TEGRA124_MC_RESET_VIC 14 -#define TEGRA124_MC_RESET_XUSB_HOST 15 -#define TEGRA124_MC_RESET_XUSB_DEV 16 -#define TEGRA124_MC_RESET_TSEC 17 -#define TEGRA124_MC_RESET_SDMMC1 18 -#define TEGRA124_MC_RESET_SDMMC2 19 -#define TEGRA124_MC_RESET_SDMMC3 20 -#define TEGRA124_MC_RESET_SDMMC4 21 -#define TEGRA124_MC_RESET_ISP2B 22 -#define TEGRA124_MC_RESET_GPU 23 - -#define TEGRA124_MC_PTCR 0 -#define TEGRA124_MC_DISPLAY0A 1 -#define TEGRA124_MC_DISPLAY0AB 2 -#define TEGRA124_MC_DISPLAY0B 3 -#define TEGRA124_MC_DISPLAY0BB 4 -#define TEGRA124_MC_DISPLAY0C 5 -#define TEGRA124_MC_DISPLAY0CB 6 -#define TEGRA124_MC_AFIR 14 -#define TEGRA124_MC_AVPCARM7R 15 -#define TEGRA124_MC_DISPLAYHC 16 -#define TEGRA124_MC_DISPLAYHCB 17 -#define TEGRA124_MC_HDAR 21 -#define TEGRA124_MC_HOST1XDMAR 22 -#define TEGRA124_MC_HOST1XR 23 -#define TEGRA124_MC_MSENCSRD 28 -#define TEGRA124_MC_PPCSAHBDMAR 29 -#define TEGRA124_MC_PPCSAHBSLVR 30 -#define TEGRA124_MC_SATAR 31 -#define TEGRA124_MC_VDEBSEVR 34 -#define TEGRA124_MC_VDEMBER 35 -#define TEGRA124_MC_VDEMCER 36 -#define TEGRA124_MC_VDETPER 37 -#define TEGRA124_MC_MPCORELPR 38 -#define TEGRA124_MC_MPCORER 39 -#define TEGRA124_MC_MSENCSWR 43 -#define TEGRA124_MC_AFIW 49 -#define TEGRA124_MC_AVPCARM7W 50 -#define TEGRA124_MC_HDAW 53 -#define TEGRA124_MC_HOST1XW 54 -#define TEGRA124_MC_MPCORELPW 56 -#define TEGRA124_MC_MPCOREW 57 -#define TEGRA124_MC_PPCSAHBDMAW 59 -#define TEGRA124_MC_PPCSAHBSLVW 60 -#define TEGRA124_MC_SATAW 61 -#define TEGRA124_MC_VDEBSEVW 62 -#define TEGRA124_MC_VDEDBGW 63 -#define TEGRA124_MC_VDEMBEW 64 -#define TEGRA124_MC_VDETPMW 65 -#define TEGRA124_MC_ISPRA 68 -#define TEGRA124_MC_ISPWA 70 -#define TEGRA124_MC_ISPWB 71 -#define TEGRA124_MC_XUSB_HOSTR 74 -#define TEGRA124_MC_XUSB_HOSTW 75 -#define TEGRA124_MC_XUSB_DEVR 76 -#define TEGRA124_MC_XUSB_DEVW 77 -#define TEGRA124_MC_ISPRAB 78 -#define TEGRA124_MC_ISPWAB 80 -#define TEGRA124_MC_ISPWBB 81 -#define TEGRA124_MC_TSECSRD 84 -#define TEGRA124_MC_TSECSWR 85 -#define TEGRA124_MC_A9AVPSCR 86 -#define TEGRA124_MC_A9AVPSCW 87 -#define TEGRA124_MC_GPUSRD 88 -#define TEGRA124_MC_GPUSWR 89 -#define TEGRA124_MC_DISPLAYT 90 -#define TEGRA124_MC_SDMMCRA 96 -#define TEGRA124_MC_SDMMCRAA 97 -#define TEGRA124_MC_SDMMCR 98 -#define TEGRA124_MC_SDMMCRAB 99 -#define TEGRA124_MC_SDMMCWA 100 -#define TEGRA124_MC_SDMMCWAA 101 -#define TEGRA124_MC_SDMMCW 102 -#define TEGRA124_MC_SDMMCWAB 103 -#define TEGRA124_MC_VICSRD 108 -#define TEGRA124_MC_VICSWR 109 -#define TEGRA124_MC_VIW 114 -#define TEGRA124_MC_DISPLAYD 115 - -#endif diff --git a/include/dt-bindings/memory/tegra186-mc.h b/include/dt-bindings/memory/tegra186-mc.h deleted file mode 100644 index 82a1e27f735..00000000000 --- a/include/dt-bindings/memory/tegra186-mc.h +++ /dev/null @@ -1,250 +0,0 @@ -#ifndef DT_BINDINGS_MEMORY_TEGRA186_MC_H -#define DT_BINDINGS_MEMORY_TEGRA186_MC_H - -/* special clients */ -#define TEGRA186_SID_INVALID 0x00 -#define TEGRA186_SID_PASSTHROUGH 0x7f - -/* host1x clients */ -#define TEGRA186_SID_HOST1X 0x01 -#define TEGRA186_SID_CSI 0x02 -#define TEGRA186_SID_VIC 0x03 -#define TEGRA186_SID_VI 0x04 -#define TEGRA186_SID_ISP 0x05 -#define TEGRA186_SID_NVDEC 0x06 -#define TEGRA186_SID_NVENC 0x07 -#define TEGRA186_SID_NVJPG 0x08 -#define TEGRA186_SID_NVDISPLAY 0x09 -#define TEGRA186_SID_TSEC 0x0a -#define TEGRA186_SID_TSECB 0x0b -#define TEGRA186_SID_SE 0x0c -#define TEGRA186_SID_SE1 0x0d -#define TEGRA186_SID_SE2 0x0e -#define TEGRA186_SID_SE3 0x0f - -/* GPU clients */ -#define TEGRA186_SID_GPU 0x10 - -/* other SoC clients */ -#define TEGRA186_SID_AFI 0x11 -#define TEGRA186_SID_HDA 0x12 -#define TEGRA186_SID_ETR 0x13 -#define TEGRA186_SID_EQOS 0x14 -#define TEGRA186_SID_UFSHC 0x15 -#define TEGRA186_SID_AON 0x16 -#define TEGRA186_SID_SDMMC4 0x17 -#define TEGRA186_SID_SDMMC3 0x18 -#define TEGRA186_SID_SDMMC2 0x19 -#define TEGRA186_SID_SDMMC1 0x1a -#define TEGRA186_SID_XUSB_HOST 0x1b -#define TEGRA186_SID_XUSB_DEV 0x1c -#define TEGRA186_SID_SATA 0x1d -#define TEGRA186_SID_APE 0x1e -#define TEGRA186_SID_SCE 0x1f - -/* GPC DMA clients */ -#define TEGRA186_SID_GPCDMA_0 0x20 -#define TEGRA186_SID_GPCDMA_1 0x21 -#define TEGRA186_SID_GPCDMA_2 0x22 -#define TEGRA186_SID_GPCDMA_3 0x23 -#define TEGRA186_SID_GPCDMA_4 0x24 -#define TEGRA186_SID_GPCDMA_5 0x25 -#define TEGRA186_SID_GPCDMA_6 0x26 -#define TEGRA186_SID_GPCDMA_7 0x27 - -/* APE DMA clients */ -#define TEGRA186_SID_APE_1 0x28 -#define TEGRA186_SID_APE_2 0x29 - -/* camera RTCPU */ -#define TEGRA186_SID_RCE 0x2a - -/* camera RTCPU on host1x address space */ -#define TEGRA186_SID_RCE_1X 0x2b - -/* APE DMA clients */ -#define TEGRA186_SID_APE_3 0x2c - -/* camera RTCPU running on APE */ -#define TEGRA186_SID_APE_CAM 0x2d -#define TEGRA186_SID_APE_CAM_1X 0x2e - -/* - * The BPMP has its SID value hardcoded in the firmware. Changing it requires - * considerable effort. - */ -#define TEGRA186_SID_BPMP 0x32 - -/* for SMMU tests */ -#define TEGRA186_SID_SMMU_TEST 0x33 - -/* host1x virtualization channels */ -#define TEGRA186_SID_HOST1X_CTX0 0x38 -#define TEGRA186_SID_HOST1X_CTX1 0x39 -#define TEGRA186_SID_HOST1X_CTX2 0x3a -#define TEGRA186_SID_HOST1X_CTX3 0x3b -#define TEGRA186_SID_HOST1X_CTX4 0x3c -#define TEGRA186_SID_HOST1X_CTX5 0x3d -#define TEGRA186_SID_HOST1X_CTX6 0x3e -#define TEGRA186_SID_HOST1X_CTX7 0x3f - -/* host1x command buffers */ -#define TEGRA186_SID_HOST1X_VM0 0x40 -#define TEGRA186_SID_HOST1X_VM1 0x41 -#define TEGRA186_SID_HOST1X_VM2 0x42 -#define TEGRA186_SID_HOST1X_VM3 0x43 -#define TEGRA186_SID_HOST1X_VM4 0x44 -#define TEGRA186_SID_HOST1X_VM5 0x45 -#define TEGRA186_SID_HOST1X_VM6 0x46 -#define TEGRA186_SID_HOST1X_VM7 0x47 - -/* SE data buffers */ -#define TEGRA186_SID_SE_VM0 0x48 -#define TEGRA186_SID_SE_VM1 0x49 -#define TEGRA186_SID_SE_VM2 0x4a -#define TEGRA186_SID_SE_VM3 0x4b -#define TEGRA186_SID_SE_VM4 0x4c -#define TEGRA186_SID_SE_VM5 0x4d -#define TEGRA186_SID_SE_VM6 0x4e -#define TEGRA186_SID_SE_VM7 0x4f - -/* - * memory client IDs - */ - -/* Misses from System Memory Management Unit (SMMU) Page Table Cache (PTC) */ -#define TEGRA186_MEMORY_CLIENT_PTCR 0x00 -/* PCIE reads */ -#define TEGRA186_MEMORY_CLIENT_AFIR 0x0e -/* High-definition audio (HDA) reads */ -#define TEGRA186_MEMORY_CLIENT_HDAR 0x15 -/* Host channel data reads */ -#define TEGRA186_MEMORY_CLIENT_HOST1XDMAR 0x16 -#define TEGRA186_MEMORY_CLIENT_NVENCSRD 0x1c -/* SATA reads */ -#define TEGRA186_MEMORY_CLIENT_SATAR 0x1f -/* Reads from Cortex-A9 4 CPU cores via the L2 cache */ -#define TEGRA186_MEMORY_CLIENT_MPCORER 0x27 -#define TEGRA186_MEMORY_CLIENT_NVENCSWR 0x2b -/* PCIE writes */ -#define TEGRA186_MEMORY_CLIENT_AFIW 0x31 -/* High-definition audio (HDA) writes */ -#define TEGRA186_MEMORY_CLIENT_HDAW 0x35 -/* Writes from Cortex-A9 4 CPU cores via the L2 cache */ -#define TEGRA186_MEMORY_CLIENT_MPCOREW 0x39 -/* SATA writes */ -#define TEGRA186_MEMORY_CLIENT_SATAW 0x3d -/* ISP Read client for Crossbar A */ -#define TEGRA186_MEMORY_CLIENT_ISPRA 0x44 -/* ISP Write client for Crossbar A */ -#define TEGRA186_MEMORY_CLIENT_ISPWA 0x46 -/* ISP Write client Crossbar B */ -#define TEGRA186_MEMORY_CLIENT_ISPWB 0x47 -/* XUSB reads */ -#define TEGRA186_MEMORY_CLIENT_XUSB_HOSTR 0x4a -/* XUSB_HOST writes */ -#define TEGRA186_MEMORY_CLIENT_XUSB_HOSTW 0x4b -/* XUSB reads */ -#define TEGRA186_MEMORY_CLIENT_XUSB_DEVR 0x4c -/* XUSB_DEV writes */ -#define TEGRA186_MEMORY_CLIENT_XUSB_DEVW 0x4d -/* TSEC Memory Return Data Client Description */ -#define TEGRA186_MEMORY_CLIENT_TSECSRD 0x54 -/* TSEC Memory Write Client Description */ -#define TEGRA186_MEMORY_CLIENT_TSECSWR 0x55 -/* 3D, ltcx reads instance 0 */ -#define TEGRA186_MEMORY_CLIENT_GPUSRD 0x58 -/* 3D, ltcx writes instance 0 */ -#define TEGRA186_MEMORY_CLIENT_GPUSWR 0x59 -/* sdmmca memory read client */ -#define TEGRA186_MEMORY_CLIENT_SDMMCRA 0x60 -/* sdmmcbmemory read client */ -#define TEGRA186_MEMORY_CLIENT_SDMMCRAA 0x61 -/* sdmmc memory read client */ -#define TEGRA186_MEMORY_CLIENT_SDMMCR 0x62 -/* sdmmcd memory read client */ -#define TEGRA186_MEMORY_CLIENT_SDMMCRAB 0x63 -/* sdmmca memory write client */ -#define TEGRA186_MEMORY_CLIENT_SDMMCWA 0x64 -/* sdmmcb memory write client */ -#define TEGRA186_MEMORY_CLIENT_SDMMCWAA 0x65 -/* sdmmc memory write client */ -#define TEGRA186_MEMORY_CLIENT_SDMMCW 0x66 -/* sdmmcd memory write client */ -#define TEGRA186_MEMORY_CLIENT_SDMMCWAB 0x67 -#define TEGRA186_MEMORY_CLIENT_VICSRD 0x6c -#define TEGRA186_MEMORY_CLIENT_VICSWR 0x6d -/* VI Write client */ -#define TEGRA186_MEMORY_CLIENT_VIW 0x72 -#define TEGRA186_MEMORY_CLIENT_NVDECSRD 0x78 -#define TEGRA186_MEMORY_CLIENT_NVDECSWR 0x79 -/* Audio Processing (APE) engine reads */ -#define TEGRA186_MEMORY_CLIENT_APER 0x7a -/* Audio Processing (APE) engine writes */ -#define TEGRA186_MEMORY_CLIENT_APEW 0x7b -#define TEGRA186_MEMORY_CLIENT_NVJPGSRD 0x7e -#define TEGRA186_MEMORY_CLIENT_NVJPGSWR 0x7f -/* SE Memory Return Data Client Description */ -#define TEGRA186_MEMORY_CLIENT_SESRD 0x80 -/* SE Memory Write Client Description */ -#define TEGRA186_MEMORY_CLIENT_SESWR 0x81 -/* ETR reads */ -#define TEGRA186_MEMORY_CLIENT_ETRR 0x84 -/* ETR writes */ -#define TEGRA186_MEMORY_CLIENT_ETRW 0x85 -/* TSECB Memory Return Data Client Description */ -#define TEGRA186_MEMORY_CLIENT_TSECSRDB 0x86 -/* TSECB Memory Write Client Description */ -#define TEGRA186_MEMORY_CLIENT_TSECSWRB 0x87 -/* 3D, ltcx reads instance 1 */ -#define TEGRA186_MEMORY_CLIENT_GPUSRD2 0x88 -/* 3D, ltcx writes instance 1 */ -#define TEGRA186_MEMORY_CLIENT_GPUSWR2 0x89 -/* AXI Switch read client */ -#define TEGRA186_MEMORY_CLIENT_AXISR 0x8c -/* AXI Switch write client */ -#define TEGRA186_MEMORY_CLIENT_AXISW 0x8d -/* EQOS read client */ -#define TEGRA186_MEMORY_CLIENT_EQOSR 0x8e -/* EQOS write client */ -#define TEGRA186_MEMORY_CLIENT_EQOSW 0x8f -/* UFSHC read client */ -#define TEGRA186_MEMORY_CLIENT_UFSHCR 0x90 -/* UFSHC write client */ -#define TEGRA186_MEMORY_CLIENT_UFSHCW 0x91 -/* NVDISPLAY read client */ -#define TEGRA186_MEMORY_CLIENT_NVDISPLAYR 0x92 -/* BPMP read client */ -#define TEGRA186_MEMORY_CLIENT_BPMPR 0x93 -/* BPMP write client */ -#define TEGRA186_MEMORY_CLIENT_BPMPW 0x94 -/* BPMPDMA read client */ -#define TEGRA186_MEMORY_CLIENT_BPMPDMAR 0x95 -/* BPMPDMA write client */ -#define TEGRA186_MEMORY_CLIENT_BPMPDMAW 0x96 -/* AON read client */ -#define TEGRA186_MEMORY_CLIENT_AONR 0x97 -/* AON write client */ -#define TEGRA186_MEMORY_CLIENT_AONW 0x98 -/* AONDMA read client */ -#define TEGRA186_MEMORY_CLIENT_AONDMAR 0x99 -/* AONDMA write client */ -#define TEGRA186_MEMORY_CLIENT_AONDMAW 0x9a -/* SCE read client */ -#define TEGRA186_MEMORY_CLIENT_SCER 0x9b -/* SCE write client */ -#define TEGRA186_MEMORY_CLIENT_SCEW 0x9c -/* SCEDMA read client */ -#define TEGRA186_MEMORY_CLIENT_SCEDMAR 0x9d -/* SCEDMA write client */ -#define TEGRA186_MEMORY_CLIENT_SCEDMAW 0x9e -/* APEDMA read client */ -#define TEGRA186_MEMORY_CLIENT_APEDMAR 0x9f -/* APEDMA write client */ -#define TEGRA186_MEMORY_CLIENT_APEDMAW 0xa0 -/* NVDISPLAY read client instance 2 */ -#define TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 0xa1 -#define TEGRA186_MEMORY_CLIENT_VICSRD1 0xa2 -#define TEGRA186_MEMORY_CLIENT_NVDECSRD1 0xa3 - -#endif diff --git a/include/dt-bindings/memory/tegra194-mc.h b/include/dt-bindings/memory/tegra194-mc.h deleted file mode 100644 index eed48b746bc..00000000000 --- a/include/dt-bindings/memory/tegra194-mc.h +++ /dev/null @@ -1,410 +0,0 @@ -#ifndef DT_BINDINGS_MEMORY_TEGRA194_MC_H -#define DT_BINDINGS_MEMORY_TEGRA194_MC_H - -/* special clients */ -#define TEGRA194_SID_INVALID 0x00 -#define TEGRA194_SID_PASSTHROUGH 0x7f - -/* host1x clients */ -#define TEGRA194_SID_HOST1X 0x01 -#define TEGRA194_SID_CSI 0x02 -#define TEGRA194_SID_VIC 0x03 -#define TEGRA194_SID_VI 0x04 -#define TEGRA194_SID_ISP 0x05 -#define TEGRA194_SID_NVDEC 0x06 -#define TEGRA194_SID_NVENC 0x07 -#define TEGRA194_SID_NVJPG 0x08 -#define TEGRA194_SID_NVDISPLAY 0x09 -#define TEGRA194_SID_TSEC 0x0a -#define TEGRA194_SID_TSECB 0x0b -#define TEGRA194_SID_SE 0x0c -#define TEGRA194_SID_SE1 0x0d -#define TEGRA194_SID_SE2 0x0e -#define TEGRA194_SID_SE3 0x0f - -/* GPU clients */ -#define TEGRA194_SID_GPU 0x10 - -/* other SoC clients */ -#define TEGRA194_SID_AFI 0x11 -#define TEGRA194_SID_HDA 0x12 -#define TEGRA194_SID_ETR 0x13 -#define TEGRA194_SID_EQOS 0x14 -#define TEGRA194_SID_UFSHC 0x15 -#define TEGRA194_SID_AON 0x16 -#define TEGRA194_SID_SDMMC4 0x17 -#define TEGRA194_SID_SDMMC3 0x18 -#define TEGRA194_SID_SDMMC2 0x19 -#define TEGRA194_SID_SDMMC1 0x1a -#define TEGRA194_SID_XUSB_HOST 0x1b -#define TEGRA194_SID_XUSB_DEV 0x1c -#define TEGRA194_SID_SATA 0x1d -#define TEGRA194_SID_APE 0x1e -#define TEGRA194_SID_SCE 0x1f - -/* GPC DMA clients */ -#define TEGRA194_SID_GPCDMA_0 0x20 -#define TEGRA194_SID_GPCDMA_1 0x21 -#define TEGRA194_SID_GPCDMA_2 0x22 -#define TEGRA194_SID_GPCDMA_3 0x23 -#define TEGRA194_SID_GPCDMA_4 0x24 -#define TEGRA194_SID_GPCDMA_5 0x25 -#define TEGRA194_SID_GPCDMA_6 0x26 -#define TEGRA194_SID_GPCDMA_7 0x27 - -/* APE DMA clients */ -#define TEGRA194_SID_APE_1 0x28 -#define TEGRA194_SID_APE_2 0x29 - -/* camera RTCPU */ -#define TEGRA194_SID_RCE 0x2a - -/* camera RTCPU on host1x address space */ -#define TEGRA194_SID_RCE_1X 0x2b - -/* APE DMA clients */ -#define TEGRA194_SID_APE_3 0x2c - -/* camera RTCPU running on APE */ -#define TEGRA194_SID_APE_CAM 0x2d -#define TEGRA194_SID_APE_CAM_1X 0x2e - -#define TEGRA194_SID_RCE_RM 0x2f -#define TEGRA194_SID_VI_FALCON 0x30 -#define TEGRA194_SID_ISP_FALCON 0x31 - -/* - * The BPMP has its SID value hardcoded in the firmware. Changing it requires - * considerable effort. - */ -#define TEGRA194_SID_BPMP 0x32 - -/* for SMMU tests */ -#define TEGRA194_SID_SMMU_TEST 0x33 - -/* host1x virtualization channels */ -#define TEGRA194_SID_HOST1X_CTX0 0x38 -#define TEGRA194_SID_HOST1X_CTX1 0x39 -#define TEGRA194_SID_HOST1X_CTX2 0x3a -#define TEGRA194_SID_HOST1X_CTX3 0x3b -#define TEGRA194_SID_HOST1X_CTX4 0x3c -#define TEGRA194_SID_HOST1X_CTX5 0x3d -#define TEGRA194_SID_HOST1X_CTX6 0x3e -#define TEGRA194_SID_HOST1X_CTX7 0x3f - -/* host1x command buffers */ -#define TEGRA194_SID_HOST1X_VM0 0x40 -#define TEGRA194_SID_HOST1X_VM1 0x41 -#define TEGRA194_SID_HOST1X_VM2 0x42 -#define TEGRA194_SID_HOST1X_VM3 0x43 -#define TEGRA194_SID_HOST1X_VM4 0x44 -#define TEGRA194_SID_HOST1X_VM5 0x45 -#define TEGRA194_SID_HOST1X_VM6 0x46 -#define TEGRA194_SID_HOST1X_VM7 0x47 - -/* SE data buffers */ -#define TEGRA194_SID_SE_VM0 0x48 -#define TEGRA194_SID_SE_VM1 0x49 -#define TEGRA194_SID_SE_VM2 0x4a -#define TEGRA194_SID_SE_VM3 0x4b -#define TEGRA194_SID_SE_VM4 0x4c -#define TEGRA194_SID_SE_VM5 0x4d -#define TEGRA194_SID_SE_VM6 0x4e -#define TEGRA194_SID_SE_VM7 0x4f - -#define TEGRA194_SID_MIU 0x50 - -#define TEGRA194_SID_NVDLA0 0x51 -#define TEGRA194_SID_NVDLA1 0x52 - -#define TEGRA194_SID_PVA0 0x53 -#define TEGRA194_SID_PVA1 0x54 -#define TEGRA194_SID_NVENC1 0x55 -#define TEGRA194_SID_PCIE0 0x56 -#define TEGRA194_SID_PCIE1 0x57 -#define TEGRA194_SID_PCIE2 0x58 -#define TEGRA194_SID_PCIE3 0x59 -#define TEGRA194_SID_PCIE4 0x5a -#define TEGRA194_SID_PCIE5 0x5b -#define TEGRA194_SID_NVDEC1 0x5c - -#define TEGRA194_SID_XUSB_VF0 0x5d -#define TEGRA194_SID_XUSB_VF1 0x5e -#define TEGRA194_SID_XUSB_VF2 0x5f -#define TEGRA194_SID_XUSB_VF3 0x60 - -#define TEGRA194_SID_RCE_VM3 0x61 -#define TEGRA194_SID_VI_VM2 0x62 -#define TEGRA194_SID_VI_VM3 0x63 -#define TEGRA194_SID_RCE_SERVER 0x64 - -/* - * memory client IDs - */ - -/* Misses from System Memory Management Unit (SMMU) Page Table Cache (PTC) */ -#define TEGRA194_MEMORY_CLIENT_PTCR 0x00 -/* MSS internal memqual MIU7 read clients */ -#define TEGRA194_MEMORY_CLIENT_MIU7R 0x01 -/* MSS internal memqual MIU7 write clients */ -#define TEGRA194_MEMORY_CLIENT_MIU7W 0x02 -/* High-definition audio (HDA) read clients */ -#define TEGRA194_MEMORY_CLIENT_HDAR 0x15 -/* Host channel data read clients */ -#define TEGRA194_MEMORY_CLIENT_HOST1XDMAR 0x16 -#define TEGRA194_MEMORY_CLIENT_NVENCSRD 0x1c -/* SATA read clients */ -#define TEGRA194_MEMORY_CLIENT_SATAR 0x1f -/* Reads from Cortex-A9 4 CPU cores via the L2 cache */ -#define TEGRA194_MEMORY_CLIENT_MPCORER 0x27 -#define TEGRA194_MEMORY_CLIENT_NVENCSWR 0x2b -/* High-definition audio (HDA) write clients */ -#define TEGRA194_MEMORY_CLIENT_HDAW 0x35 -/* Writes from Cortex-A9 4 CPU cores via the L2 cache */ -#define TEGRA194_MEMORY_CLIENT_MPCOREW 0x39 -/* SATA write clients */ -#define TEGRA194_MEMORY_CLIENT_SATAW 0x3d -/* ISP read client for Crossbar A */ -#define TEGRA194_MEMORY_CLIENT_ISPRA 0x44 -/* ISP read client 1 for Crossbar A */ -#define TEGRA194_MEMORY_CLIENT_ISPFALR 0x45 -/* ISP Write client for Crossbar A */ -#define TEGRA194_MEMORY_CLIENT_ISPWA 0x46 -/* ISP Write client Crossbar B */ -#define TEGRA194_MEMORY_CLIENT_ISPWB 0x47 -/* XUSB_HOST read clients */ -#define TEGRA194_MEMORY_CLIENT_XUSB_HOSTR 0x4a -/* XUSB_HOST write clients */ -#define TEGRA194_MEMORY_CLIENT_XUSB_HOSTW 0x4b -/* XUSB read clients */ -#define TEGRA194_MEMORY_CLIENT_XUSB_DEVR 0x4c -/* XUSB_DEV write clients */ -#define TEGRA194_MEMORY_CLIENT_XUSB_DEVW 0x4d -/* sdmmca memory read client */ -#define TEGRA194_MEMORY_CLIENT_SDMMCRA 0x60 -/* sdmmc memory read client */ -#define TEGRA194_MEMORY_CLIENT_SDMMCR 0x62 -/* sdmmcd memory read client */ -#define TEGRA194_MEMORY_CLIENT_SDMMCRAB 0x63 -/* sdmmca memory write client */ -#define TEGRA194_MEMORY_CLIENT_SDMMCWA 0x64 -/* sdmmc memory write client */ -#define TEGRA194_MEMORY_CLIENT_SDMMCW 0x66 -/* sdmmcd memory write client */ -#define TEGRA194_MEMORY_CLIENT_SDMMCWAB 0x67 -#define TEGRA194_MEMORY_CLIENT_VICSRD 0x6c -#define TEGRA194_MEMORY_CLIENT_VICSWR 0x6d -/* VI Write client */ -#define TEGRA194_MEMORY_CLIENT_VIW 0x72 -#define TEGRA194_MEMORY_CLIENT_NVDECSRD 0x78 -#define TEGRA194_MEMORY_CLIENT_NVDECSWR 0x79 -/* Audio Processing (APE) engine read clients */ -#define TEGRA194_MEMORY_CLIENT_APER 0x7a -/* Audio Processing (APE) engine write clients */ -#define TEGRA194_MEMORY_CLIENT_APEW 0x7b -#define TEGRA194_MEMORY_CLIENT_NVJPGSRD 0x7e -#define TEGRA194_MEMORY_CLIENT_NVJPGSWR 0x7f -/* AXI AP and DFD-AUX0/1 read clients Both share the same interface on the on MSS */ -#define TEGRA194_MEMORY_CLIENT_AXIAPR 0x82 -/* AXI AP and DFD-AUX0/1 write clients Both sahre the same interface on MSS */ -#define TEGRA194_MEMORY_CLIENT_AXIAPW 0x83 -/* ETR read clients */ -#define TEGRA194_MEMORY_CLIENT_ETRR 0x84 -/* ETR write clients */ -#define TEGRA194_MEMORY_CLIENT_ETRW 0x85 -/* AXI Switch read client */ -#define TEGRA194_MEMORY_CLIENT_AXISR 0x8c -/* AXI Switch write client */ -#define TEGRA194_MEMORY_CLIENT_AXISW 0x8d -/* EQOS read client */ -#define TEGRA194_MEMORY_CLIENT_EQOSR 0x8e -/* EQOS write client */ -#define TEGRA194_MEMORY_CLIENT_EQOSW 0x8f -/* UFSHC read client */ -#define TEGRA194_MEMORY_CLIENT_UFSHCR 0x90 -/* UFSHC write client */ -#define TEGRA194_MEMORY_CLIENT_UFSHCW 0x91 -/* NVDISPLAY read client */ -#define TEGRA194_MEMORY_CLIENT_NVDISPLAYR 0x92 -/* BPMP read client */ -#define TEGRA194_MEMORY_CLIENT_BPMPR 0x93 -/* BPMP write client */ -#define TEGRA194_MEMORY_CLIENT_BPMPW 0x94 -/* BPMPDMA read client */ -#define TEGRA194_MEMORY_CLIENT_BPMPDMAR 0x95 -/* BPMPDMA write client */ -#define TEGRA194_MEMORY_CLIENT_BPMPDMAW 0x96 -/* AON read client */ -#define TEGRA194_MEMORY_CLIENT_AONR 0x97 -/* AON write client */ -#define TEGRA194_MEMORY_CLIENT_AONW 0x98 -/* AONDMA read client */ -#define TEGRA194_MEMORY_CLIENT_AONDMAR 0x99 -/* AONDMA write client */ -#define TEGRA194_MEMORY_CLIENT_AONDMAW 0x9a -/* SCE read client */ -#define TEGRA194_MEMORY_CLIENT_SCER 0x9b -/* SCE write client */ -#define TEGRA194_MEMORY_CLIENT_SCEW 0x9c -/* SCEDMA read client */ -#define TEGRA194_MEMORY_CLIENT_SCEDMAR 0x9d -/* SCEDMA write client */ -#define TEGRA194_MEMORY_CLIENT_SCEDMAW 0x9e -/* APEDMA read client */ -#define TEGRA194_MEMORY_CLIENT_APEDMAR 0x9f -/* APEDMA write client */ -#define TEGRA194_MEMORY_CLIENT_APEDMAW 0xa0 -/* NVDISPLAY read client instance 2 */ -#define TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 0xa1 -#define TEGRA194_MEMORY_CLIENT_VICSRD1 0xa2 -#define TEGRA194_MEMORY_CLIENT_NVDECSRD1 0xa3 -/* MSS internal memqual MIU0 read clients */ -#define TEGRA194_MEMORY_CLIENT_MIU0R 0xa6 -/* MSS internal memqual MIU0 write clients */ -#define TEGRA194_MEMORY_CLIENT_MIU0W 0xa7 -/* MSS internal memqual MIU1 read clients */ -#define TEGRA194_MEMORY_CLIENT_MIU1R 0xa8 -/* MSS internal memqual MIU1 write clients */ -#define TEGRA194_MEMORY_CLIENT_MIU1W 0xa9 -/* MSS internal memqual MIU2 read clients */ -#define TEGRA194_MEMORY_CLIENT_MIU2R 0xae -/* MSS internal memqual MIU2 write clients */ -#define TEGRA194_MEMORY_CLIENT_MIU2W 0xaf -/* MSS internal memqual MIU3 read clients */ -#define TEGRA194_MEMORY_CLIENT_MIU3R 0xb0 -/* MSS internal memqual MIU3 write clients */ -#define TEGRA194_MEMORY_CLIENT_MIU3W 0xb1 -/* MSS internal memqual MIU4 read clients */ -#define TEGRA194_MEMORY_CLIENT_MIU4R 0xb2 -/* MSS internal memqual MIU4 write clients */ -#define TEGRA194_MEMORY_CLIENT_MIU4W 0xb3 -#define TEGRA194_MEMORY_CLIENT_DPMUR 0xb4 -#define TEGRA194_MEMORY_CLIENT_DPMUW 0xb5 -#define TEGRA194_MEMORY_CLIENT_NVL0R 0xb6 -#define TEGRA194_MEMORY_CLIENT_NVL0W 0xb7 -#define TEGRA194_MEMORY_CLIENT_NVL1R 0xb8 -#define TEGRA194_MEMORY_CLIENT_NVL1W 0xb9 -#define TEGRA194_MEMORY_CLIENT_NVL2R 0xba -#define TEGRA194_MEMORY_CLIENT_NVL2W 0xbb -/* VI FLACON read clients */ -#define TEGRA194_MEMORY_CLIENT_VIFALR 0xbc -/* VIFAL write clients */ -#define TEGRA194_MEMORY_CLIENT_VIFALW 0xbd -/* DLA0ARDA read clients */ -#define TEGRA194_MEMORY_CLIENT_DLA0RDA 0xbe -/* DLA0 Falcon read clients */ -#define TEGRA194_MEMORY_CLIENT_DLA0FALRDB 0xbf -/* DLA0 write clients */ -#define TEGRA194_MEMORY_CLIENT_DLA0WRA 0xc0 -/* DLA0 write clients */ -#define TEGRA194_MEMORY_CLIENT_DLA0FALWRB 0xc1 -/* DLA1ARDA read clients */ -#define TEGRA194_MEMORY_CLIENT_DLA1RDA 0xc2 -/* DLA1 Falcon read clients */ -#define TEGRA194_MEMORY_CLIENT_DLA1FALRDB 0xc3 -/* DLA1 write clients */ -#define TEGRA194_MEMORY_CLIENT_DLA1WRA 0xc4 -/* DLA1 write clients */ -#define TEGRA194_MEMORY_CLIENT_DLA1FALWRB 0xc5 -/* PVA0RDA read clients */ -#define TEGRA194_MEMORY_CLIENT_PVA0RDA 0xc6 -/* PVA0RDB read clients */ -#define TEGRA194_MEMORY_CLIENT_PVA0RDB 0xc7 -/* PVA0RDC read clients */ -#define TEGRA194_MEMORY_CLIENT_PVA0RDC 0xc8 -/* PVA0WRA write clients */ -#define TEGRA194_MEMORY_CLIENT_PVA0WRA 0xc9 -/* PVA0WRB write clients */ -#define TEGRA194_MEMORY_CLIENT_PVA0WRB 0xca -/* PVA0WRC write clients */ -#define TEGRA194_MEMORY_CLIENT_PVA0WRC 0xcb -/* PVA1RDA read clients */ -#define TEGRA194_MEMORY_CLIENT_PVA1RDA 0xcc -/* PVA1RDB read clients */ -#define TEGRA194_MEMORY_CLIENT_PVA1RDB 0xcd -/* PVA1RDC read clients */ -#define TEGRA194_MEMORY_CLIENT_PVA1RDC 0xce -/* PVA1WRA write clients */ -#define TEGRA194_MEMORY_CLIENT_PVA1WRA 0xcf -/* PVA1WRB write clients */ -#define TEGRA194_MEMORY_CLIENT_PVA1WRB 0xd0 -/* PVA1WRC write clients */ -#define TEGRA194_MEMORY_CLIENT_PVA1WRC 0xd1 -/* RCE read client */ -#define TEGRA194_MEMORY_CLIENT_RCER 0xd2 -/* RCE write client */ -#define TEGRA194_MEMORY_CLIENT_RCEW 0xd3 -/* RCEDMA read client */ -#define TEGRA194_MEMORY_CLIENT_RCEDMAR 0xd4 -/* RCEDMA write client */ -#define TEGRA194_MEMORY_CLIENT_RCEDMAW 0xd5 -#define TEGRA194_MEMORY_CLIENT_NVENC1SRD 0xd6 -#define TEGRA194_MEMORY_CLIENT_NVENC1SWR 0xd7 -/* PCIE0 read clients */ -#define TEGRA194_MEMORY_CLIENT_PCIE0R 0xd8 -/* PCIE0 write clients */ -#define TEGRA194_MEMORY_CLIENT_PCIE0W 0xd9 -/* PCIE1 read clients */ -#define TEGRA194_MEMORY_CLIENT_PCIE1R 0xda -/* PCIE1 write clients */ -#define TEGRA194_MEMORY_CLIENT_PCIE1W 0xdb -/* PCIE2 read clients */ -#define TEGRA194_MEMORY_CLIENT_PCIE2AR 0xdc -/* PCIE2 write clients */ -#define TEGRA194_MEMORY_CLIENT_PCIE2AW 0xdd -/* PCIE3 read clients */ -#define TEGRA194_MEMORY_CLIENT_PCIE3R 0xde -/* PCIE3 write clients */ -#define TEGRA194_MEMORY_CLIENT_PCIE3W 0xdf -/* PCIE4 read clients */ -#define TEGRA194_MEMORY_CLIENT_PCIE4R 0xe0 -/* PCIE4 write clients */ -#define TEGRA194_MEMORY_CLIENT_PCIE4W 0xe1 -/* PCIE5 read clients */ -#define TEGRA194_MEMORY_CLIENT_PCIE5R 0xe2 -/* PCIE5 write clients */ -#define TEGRA194_MEMORY_CLIENT_PCIE5W 0xe3 -/* ISP read client 1 for Crossbar A */ -#define TEGRA194_MEMORY_CLIENT_ISPFALW 0xe4 -#define TEGRA194_MEMORY_CLIENT_NVL3R 0xe5 -#define TEGRA194_MEMORY_CLIENT_NVL3W 0xe6 -#define TEGRA194_MEMORY_CLIENT_NVL4R 0xe7 -#define TEGRA194_MEMORY_CLIENT_NVL4W 0xe8 -/* DLA0ARDA1 read clients */ -#define TEGRA194_MEMORY_CLIENT_DLA0RDA1 0xe9 -/* DLA1ARDA1 read clients */ -#define TEGRA194_MEMORY_CLIENT_DLA1RDA1 0xea -/* PVA0RDA1 read clients */ -#define TEGRA194_MEMORY_CLIENT_PVA0RDA1 0xeb -/* PVA0RDB1 read clients */ -#define TEGRA194_MEMORY_CLIENT_PVA0RDB1 0xec -/* PVA1RDA1 read clients */ -#define TEGRA194_MEMORY_CLIENT_PVA1RDA1 0xed -/* PVA1RDB1 read clients */ -#define TEGRA194_MEMORY_CLIENT_PVA1RDB1 0xee -/* PCIE5r1 read clients */ -#define TEGRA194_MEMORY_CLIENT_PCIE5R1 0xef -#define TEGRA194_MEMORY_CLIENT_NVENCSRD1 0xf0 -#define TEGRA194_MEMORY_CLIENT_NVENC1SRD1 0xf1 -/* ISP read client for Crossbar A */ -#define TEGRA194_MEMORY_CLIENT_ISPRA1 0xf2 -/* PCIE0 read clients */ -#define TEGRA194_MEMORY_CLIENT_PCIE0R1 0xf3 -#define TEGRA194_MEMORY_CLIENT_NVL0RHP 0xf4 -#define TEGRA194_MEMORY_CLIENT_NVL1RHP 0xf5 -#define TEGRA194_MEMORY_CLIENT_NVL2RHP 0xf6 -#define TEGRA194_MEMORY_CLIENT_NVL3RHP 0xf7 -#define TEGRA194_MEMORY_CLIENT_NVL4RHP 0xf8 -#define TEGRA194_MEMORY_CLIENT_NVDEC1SRD 0xf9 -#define TEGRA194_MEMORY_CLIENT_NVDEC1SRD1 0xfa -#define TEGRA194_MEMORY_CLIENT_NVDEC1SWR 0xfb -/* MSS internal memqual MIU5 read clients */ -#define TEGRA194_MEMORY_CLIENT_MIU5R 0xfc -/* MSS internal memqual MIU5 write clients */ -#define TEGRA194_MEMORY_CLIENT_MIU5W 0xfd -/* MSS internal memqual MIU6 read clients */ -#define TEGRA194_MEMORY_CLIENT_MIU6R 0xfe -/* MSS internal memqual MIU6 write clients */ -#define TEGRA194_MEMORY_CLIENT_MIU6W 0xff - -#endif diff --git a/include/dt-bindings/memory/tegra20-mc.h b/include/dt-bindings/memory/tegra20-mc.h deleted file mode 100644 index 6f8829508ad..00000000000 --- a/include/dt-bindings/memory/tegra20-mc.h +++ /dev/null @@ -1,74 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef DT_BINDINGS_MEMORY_TEGRA20_MC_H -#define DT_BINDINGS_MEMORY_TEGRA20_MC_H - -#define TEGRA20_MC_RESET_AVPC 0 -#define TEGRA20_MC_RESET_DC 1 -#define TEGRA20_MC_RESET_DCB 2 -#define TEGRA20_MC_RESET_EPP 3 -#define TEGRA20_MC_RESET_2D 4 -#define TEGRA20_MC_RESET_HC 5 -#define TEGRA20_MC_RESET_ISP 6 -#define TEGRA20_MC_RESET_MPCORE 7 -#define TEGRA20_MC_RESET_MPEA 8 -#define TEGRA20_MC_RESET_MPEB 9 -#define TEGRA20_MC_RESET_MPEC 10 -#define TEGRA20_MC_RESET_3D 11 -#define TEGRA20_MC_RESET_PPCS 12 -#define TEGRA20_MC_RESET_VDE 13 -#define TEGRA20_MC_RESET_VI 14 - -#define TEGRA20_MC_DISPLAY0A 0 -#define TEGRA20_MC_DISPLAY0AB 1 -#define TEGRA20_MC_DISPLAY0B 2 -#define TEGRA20_MC_DISPLAY0BB 3 -#define TEGRA20_MC_DISPLAY0C 4 -#define TEGRA20_MC_DISPLAY0CB 5 -#define TEGRA20_MC_DISPLAY1B 6 -#define TEGRA20_MC_DISPLAY1BB 7 -#define TEGRA20_MC_EPPUP 8 -#define TEGRA20_MC_G2PR 9 -#define TEGRA20_MC_G2SR 10 -#define TEGRA20_MC_MPEUNIFBR 11 -#define TEGRA20_MC_VIRUV 12 -#define TEGRA20_MC_AVPCARM7R 13 -#define TEGRA20_MC_DISPLAYHC 14 -#define TEGRA20_MC_DISPLAYHCB 15 -#define TEGRA20_MC_FDCDRD 16 -#define TEGRA20_MC_G2DR 17 -#define TEGRA20_MC_HOST1XDMAR 18 -#define TEGRA20_MC_HOST1XR 19 -#define TEGRA20_MC_IDXSRD 20 -#define TEGRA20_MC_MPCORER 21 -#define TEGRA20_MC_MPE_IPRED 22 -#define TEGRA20_MC_MPEAMEMRD 23 -#define TEGRA20_MC_MPECSRD 24 -#define TEGRA20_MC_PPCSAHBDMAR 25 -#define TEGRA20_MC_PPCSAHBSLVR 26 -#define TEGRA20_MC_TEXSRD 27 -#define TEGRA20_MC_VDEBSEVR 28 -#define TEGRA20_MC_VDEMBER 29 -#define TEGRA20_MC_VDEMCER 30 -#define TEGRA20_MC_VDETPER 31 -#define TEGRA20_MC_EPPU 32 -#define TEGRA20_MC_EPPV 33 -#define TEGRA20_MC_EPPY 34 -#define TEGRA20_MC_MPEUNIFBW 35 -#define TEGRA20_MC_VIWSB 36 -#define TEGRA20_MC_VIWU 37 -#define TEGRA20_MC_VIWV 38 -#define TEGRA20_MC_VIWY 39 -#define TEGRA20_MC_G2DW 40 -#define TEGRA20_MC_AVPCARM7W 41 -#define TEGRA20_MC_FDCDWR 42 -#define TEGRA20_MC_HOST1XW 43 -#define TEGRA20_MC_ISPW 44 -#define TEGRA20_MC_MPCOREW 45 -#define TEGRA20_MC_MPECSWR 46 -#define TEGRA20_MC_PPCSAHBDMAW 47 -#define TEGRA20_MC_PPCSAHBSLVW 48 -#define TEGRA20_MC_VDEBSEVW 49 -#define TEGRA20_MC_VDEMBEW 50 -#define TEGRA20_MC_VDETPMW 51 - -#endif diff --git a/include/dt-bindings/memory/tegra210-mc.h b/include/dt-bindings/memory/tegra210-mc.h deleted file mode 100644 index 5e082547f17..00000000000 --- a/include/dt-bindings/memory/tegra210-mc.h +++ /dev/null @@ -1,78 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef DT_BINDINGS_MEMORY_TEGRA210_MC_H -#define DT_BINDINGS_MEMORY_TEGRA210_MC_H - -#define TEGRA_SWGROUP_PTC 0 -#define TEGRA_SWGROUP_DC 1 -#define TEGRA_SWGROUP_DCB 2 -#define TEGRA_SWGROUP_AFI 3 -#define TEGRA_SWGROUP_AVPC 4 -#define TEGRA_SWGROUP_HDA 5 -#define TEGRA_SWGROUP_HC 6 -#define TEGRA_SWGROUP_NVENC 7 -#define TEGRA_SWGROUP_PPCS 8 -#define TEGRA_SWGROUP_SATA 9 -#define TEGRA_SWGROUP_MPCORE 10 -#define TEGRA_SWGROUP_ISP2 11 -#define TEGRA_SWGROUP_XUSB_HOST 12 -#define TEGRA_SWGROUP_XUSB_DEV 13 -#define TEGRA_SWGROUP_ISP2B 14 -#define TEGRA_SWGROUP_TSEC 15 -#define TEGRA_SWGROUP_A9AVP 16 -#define TEGRA_SWGROUP_GPU 17 -#define TEGRA_SWGROUP_SDMMC1A 18 -#define TEGRA_SWGROUP_SDMMC2A 19 -#define TEGRA_SWGROUP_SDMMC3A 20 -#define TEGRA_SWGROUP_SDMMC4A 21 -#define TEGRA_SWGROUP_VIC 22 -#define TEGRA_SWGROUP_VI 23 -#define TEGRA_SWGROUP_NVDEC 24 -#define TEGRA_SWGROUP_APE 25 -#define TEGRA_SWGROUP_NVJPG 26 -#define TEGRA_SWGROUP_SE 27 -#define TEGRA_SWGROUP_AXIAP 28 -#define TEGRA_SWGROUP_ETR 29 -#define TEGRA_SWGROUP_TSECB 30 -#define TEGRA_SWGROUP_NV 31 -#define TEGRA_SWGROUP_NV2 32 -#define TEGRA_SWGROUP_PPCS1 33 -#define TEGRA_SWGROUP_DC1 34 -#define TEGRA_SWGROUP_PPCS2 35 -#define TEGRA_SWGROUP_HC1 36 -#define TEGRA_SWGROUP_SE1 37 -#define TEGRA_SWGROUP_TSEC1 38 -#define TEGRA_SWGROUP_TSECB1 39 -#define TEGRA_SWGROUP_NVDEC1 40 - -#define TEGRA210_MC_RESET_AFI 0 -#define TEGRA210_MC_RESET_AVPC 1 -#define TEGRA210_MC_RESET_DC 2 -#define TEGRA210_MC_RESET_DCB 3 -#define TEGRA210_MC_RESET_HC 4 -#define TEGRA210_MC_RESET_HDA 5 -#define TEGRA210_MC_RESET_ISP2 6 -#define TEGRA210_MC_RESET_MPCORE 7 -#define TEGRA210_MC_RESET_NVENC 8 -#define TEGRA210_MC_RESET_PPCS 9 -#define TEGRA210_MC_RESET_SATA 10 -#define TEGRA210_MC_RESET_VI 11 -#define TEGRA210_MC_RESET_VIC 12 -#define TEGRA210_MC_RESET_XUSB_HOST 13 -#define TEGRA210_MC_RESET_XUSB_DEV 14 -#define TEGRA210_MC_RESET_A9AVP 15 -#define TEGRA210_MC_RESET_TSEC 16 -#define TEGRA210_MC_RESET_SDMMC1 17 -#define TEGRA210_MC_RESET_SDMMC2 18 -#define TEGRA210_MC_RESET_SDMMC3 19 -#define TEGRA210_MC_RESET_SDMMC4 20 -#define TEGRA210_MC_RESET_ISP2B 21 -#define TEGRA210_MC_RESET_GPU 22 -#define TEGRA210_MC_RESET_NVDEC 23 -#define TEGRA210_MC_RESET_APE 24 -#define TEGRA210_MC_RESET_SE 25 -#define TEGRA210_MC_RESET_NVJPG 26 -#define TEGRA210_MC_RESET_AXIAP 27 -#define TEGRA210_MC_RESET_ETR 28 -#define TEGRA210_MC_RESET_TSECB 29 - -#endif diff --git a/include/dt-bindings/memory/tegra234-mc.h b/include/dt-bindings/memory/tegra234-mc.h deleted file mode 100644 index 6e60d55491b..00000000000 --- a/include/dt-bindings/memory/tegra234-mc.h +++ /dev/null @@ -1,544 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ -/* Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved. */ - -#ifndef DT_BINDINGS_MEMORY_TEGRA234_MC_H -#define DT_BINDINGS_MEMORY_TEGRA234_MC_H - -/* special clients */ -#define TEGRA234_SID_INVALID 0x00 -#define TEGRA234_SID_PASSTHROUGH 0x7f - -/* ISO stream IDs */ -#define TEGRA234_SID_ISO_NVDISPLAY 0x01 -#define TEGRA234_SID_ISO_VI 0x02 -#define TEGRA234_SID_ISO_VIFALC 0x03 -#define TEGRA234_SID_ISO_VI2 0x04 -#define TEGRA234_SID_ISO_VI2FALC 0x05 -#define TEGRA234_SID_ISO_VI_VM2 0x06 -#define TEGRA234_SID_ISO_VI2_VM2 0x07 - -/* NISO0 stream IDs */ -#define TEGRA234_SID_AON 0x01 -#define TEGRA234_SID_APE 0x02 -#define TEGRA234_SID_HDA 0x03 -#define TEGRA234_SID_GPCDMA 0x04 -#define TEGRA234_SID_ETR 0x05 -#define TEGRA234_SID_MGBE 0x06 -#define TEGRA234_SID_NVDISPLAY 0x07 -#define TEGRA234_SID_DCE 0x08 -#define TEGRA234_SID_PSC 0x09 -#define TEGRA234_SID_RCE 0x0a -#define TEGRA234_SID_SCE 0x0b -#define TEGRA234_SID_UFSHC 0x0c -#define TEGRA234_SID_APE_1 0x0d -#define TEGRA234_SID_GPCDMA_1 0x0e -#define TEGRA234_SID_GPCDMA_2 0x0f -#define TEGRA234_SID_GPCDMA_3 0x10 -#define TEGRA234_SID_GPCDMA_4 0x11 -#define TEGRA234_SID_PCIE0 0x12 -#define TEGRA234_SID_PCIE4 0x13 -#define TEGRA234_SID_PCIE5 0x14 -#define TEGRA234_SID_PCIE6 0x15 -#define TEGRA234_SID_RCE_VM2 0x16 -#define TEGRA234_SID_RCE_SERVER 0x17 -#define TEGRA234_SID_SMMU_TEST 0x18 -#define TEGRA234_SID_UFS_1 0x19 -#define TEGRA234_SID_UFS_2 0x1a -#define TEGRA234_SID_UFS_3 0x1b -#define TEGRA234_SID_UFS_4 0x1c -#define TEGRA234_SID_UFS_5 0x1d -#define TEGRA234_SID_UFS_6 0x1e -#define TEGRA234_SID_PCIE9 0x1f -#define TEGRA234_SID_VSE_GPCDMA_VM0 0x20 -#define TEGRA234_SID_VSE_GPCDMA_VM1 0x21 -#define TEGRA234_SID_VSE_GPCDMA_VM2 0x22 -#define TEGRA234_SID_NVDLA1 0x23 -#define TEGRA234_SID_NVENC 0x24 -#define TEGRA234_SID_NVJPG1 0x25 -#define TEGRA234_SID_OFA 0x26 -#define TEGRA234_SID_MGBE_VF1 0x49 -#define TEGRA234_SID_MGBE_VF2 0x4a -#define TEGRA234_SID_MGBE_VF3 0x4b -#define TEGRA234_SID_MGBE_VF4 0x4c -#define TEGRA234_SID_MGBE_VF5 0x4d -#define TEGRA234_SID_MGBE_VF6 0x4e -#define TEGRA234_SID_MGBE_VF7 0x4f -#define TEGRA234_SID_MGBE_VF8 0x50 -#define TEGRA234_SID_MGBE_VF9 0x51 -#define TEGRA234_SID_MGBE_VF10 0x52 -#define TEGRA234_SID_MGBE_VF11 0x53 -#define TEGRA234_SID_MGBE_VF12 0x54 -#define TEGRA234_SID_MGBE_VF13 0x55 -#define TEGRA234_SID_MGBE_VF14 0x56 -#define TEGRA234_SID_MGBE_VF15 0x57 -#define TEGRA234_SID_MGBE_VF16 0x58 -#define TEGRA234_SID_MGBE_VF17 0x59 -#define TEGRA234_SID_MGBE_VF18 0x5a -#define TEGRA234_SID_MGBE_VF19 0x5b -#define TEGRA234_SID_MGBE_VF20 0x5c -#define TEGRA234_SID_APE_2 0x5e -#define TEGRA234_SID_APE_3 0x5f -#define TEGRA234_SID_UFS_7 0x60 -#define TEGRA234_SID_UFS_8 0x61 -#define TEGRA234_SID_UFS_9 0x62 -#define TEGRA234_SID_UFS_10 0x63 -#define TEGRA234_SID_UFS_11 0x64 -#define TEGRA234_SID_UFS_12 0x65 -#define TEGRA234_SID_UFS_13 0x66 -#define TEGRA234_SID_UFS_14 0x67 -#define TEGRA234_SID_UFS_15 0x68 -#define TEGRA234_SID_UFS_16 0x69 -#define TEGRA234_SID_UFS_17 0x6a -#define TEGRA234_SID_UFS_18 0x6b -#define TEGRA234_SID_UFS_19 0x6c -#define TEGRA234_SID_UFS_20 0x6d -#define TEGRA234_SID_GPCDMA_5 0x6e -#define TEGRA234_SID_GPCDMA_6 0x6f -#define TEGRA234_SID_GPCDMA_7 0x70 -#define TEGRA234_SID_GPCDMA_8 0x71 -#define TEGRA234_SID_GPCDMA_9 0x72 - -/* NISO1 stream IDs */ -#define TEGRA234_SID_SDMMC1A 0x01 -#define TEGRA234_SID_SDMMC4 0x02 -#define TEGRA234_SID_EQOS 0x03 -#define TEGRA234_SID_HWMP_PMA 0x04 -#define TEGRA234_SID_PCIE1 0x05 -#define TEGRA234_SID_PCIE2 0x06 -#define TEGRA234_SID_PCIE3 0x07 -#define TEGRA234_SID_PCIE7 0x08 -#define TEGRA234_SID_PCIE8 0x09 -#define TEGRA234_SID_PCIE10 0x0b -#define TEGRA234_SID_QSPI0 0x0c -#define TEGRA234_SID_QSPI1 0x0d -#define TEGRA234_SID_XUSB_HOST 0x0e -#define TEGRA234_SID_XUSB_DEV 0x0f -#define TEGRA234_SID_BPMP 0x10 -#define TEGRA234_SID_FSI 0x11 -#define TEGRA234_SID_PVA0_VM0 0x12 -#define TEGRA234_SID_PVA0_VM1 0x13 -#define TEGRA234_SID_PVA0_VM2 0x14 -#define TEGRA234_SID_PVA0_VM3 0x15 -#define TEGRA234_SID_PVA0_VM4 0x16 -#define TEGRA234_SID_PVA0_VM5 0x17 -#define TEGRA234_SID_PVA0_VM6 0x18 -#define TEGRA234_SID_PVA0_VM7 0x19 -#define TEGRA234_SID_XUSB_VF0 0x1a -#define TEGRA234_SID_XUSB_VF1 0x1b -#define TEGRA234_SID_XUSB_VF2 0x1c -#define TEGRA234_SID_XUSB_VF3 0x1d -#define TEGRA234_SID_EQOS_VF1 0x1e -#define TEGRA234_SID_EQOS_VF2 0x1f -#define TEGRA234_SID_EQOS_VF3 0x20 -#define TEGRA234_SID_EQOS_VF4 0x21 -#define TEGRA234_SID_ISP_VM2 0x22 -#define TEGRA234_SID_HOST1X 0x27 -#define TEGRA234_SID_ISP 0x28 -#define TEGRA234_SID_NVDEC 0x29 -#define TEGRA234_SID_NVJPG 0x2a -#define TEGRA234_SID_NVDLA0 0x2b -#define TEGRA234_SID_PVA0 0x2c -#define TEGRA234_SID_SES_SE0 0x2d -#define TEGRA234_SID_SES_SE1 0x2e -#define TEGRA234_SID_SES_SE2 0x2f -#define TEGRA234_SID_SEU1_SE0 0x30 -#define TEGRA234_SID_SEU1_SE1 0x31 -#define TEGRA234_SID_SEU1_SE2 0x32 -#define TEGRA234_SID_TSEC 0x33 -#define TEGRA234_SID_VIC 0x34 -#define TEGRA234_SID_HC_VM0 0x3d -#define TEGRA234_SID_HC_VM1 0x3e -#define TEGRA234_SID_HC_VM2 0x3f -#define TEGRA234_SID_HC_VM3 0x40 -#define TEGRA234_SID_HC_VM4 0x41 -#define TEGRA234_SID_HC_VM5 0x42 -#define TEGRA234_SID_HC_VM6 0x43 -#define TEGRA234_SID_HC_VM7 0x44 -#define TEGRA234_SID_SE_VM0 0x45 -#define TEGRA234_SID_SE_VM1 0x46 -#define TEGRA234_SID_SE_VM2 0x47 -#define TEGRA234_SID_ISPFALC 0x48 -#define TEGRA234_SID_NISO1_SMMU_TEST 0x49 -#define TEGRA234_SID_TSEC_VM0 0x4a - -/* Shared stream IDs */ -#define TEGRA234_SID_HOST1X_CTX0 0x35 -#define TEGRA234_SID_HOST1X_CTX1 0x36 -#define TEGRA234_SID_HOST1X_CTX2 0x37 -#define TEGRA234_SID_HOST1X_CTX3 0x38 -#define TEGRA234_SID_HOST1X_CTX4 0x39 -#define TEGRA234_SID_HOST1X_CTX5 0x3a -#define TEGRA234_SID_HOST1X_CTX6 0x3b -#define TEGRA234_SID_HOST1X_CTX7 0x3c - -/* - * memory client IDs - */ - -/* Misses from System Memory Management Unit (SMMU) Page Table Cache (PTC) */ -#define TEGRA234_MEMORY_CLIENT_PTCR 0x00 -/* MSS internal memqual MIU7 read clients */ -#define TEGRA234_MEMORY_CLIENT_MIU7R 0x01 -/* MSS internal memqual MIU7 write clients */ -#define TEGRA234_MEMORY_CLIENT_MIU7W 0x02 -/* MSS internal memqual MIU8 read clients */ -#define TEGRA234_MEMORY_CLIENT_MIU8R 0x03 -/* MSS internal memqual MIU8 write clients */ -#define TEGRA234_MEMORY_CLIENT_MIU8W 0x04 -/* MSS internal memqual MIU9 read clients */ -#define TEGRA234_MEMORY_CLIENT_MIU9R 0x05 -/* MSS internal memqual MIU9 write clients */ -#define TEGRA234_MEMORY_CLIENT_MIU9W 0x06 -/* MSS internal memqual MIU10 read clients */ -#define TEGRA234_MEMORY_CLIENT_MIU10R 0x07 -/* MSS internal memqual MIU10 write clients */ -#define TEGRA234_MEMORY_CLIENT_MIU10W 0x08 -/* MSS internal memqual MIU11 read clients */ -#define TEGRA234_MEMORY_CLIENT_MIU11R 0x09 -/* MSS internal memqual MIU11 write clients */ -#define TEGRA234_MEMORY_CLIENT_MIU11W 0x0a -/* MSS internal memqual MIU12 read clients */ -#define TEGRA234_MEMORY_CLIENT_MIU12R 0x0b -/* MSS internal memqual MIU12 write clients */ -#define TEGRA234_MEMORY_CLIENT_MIU12W 0x0c -/* MSS internal memqual MIU13 read clients */ -#define TEGRA234_MEMORY_CLIENT_MIU13R 0x0d -/* MSS internal memqual MIU13 write clients */ -#define TEGRA234_MEMORY_CLIENT_MIU13W 0x0e -#define TEGRA234_MEMORY_CLIENT_NVL5RHP 0x13 -#define TEGRA234_MEMORY_CLIENT_NVL5R 0x14 -/* High-definition audio (HDA) read clients */ -#define TEGRA234_MEMORY_CLIENT_HDAR 0x15 -/* Host channel data read clients */ -#define TEGRA234_MEMORY_CLIENT_HOST1XDMAR 0x16 -#define TEGRA234_MEMORY_CLIENT_NVL5W 0x17 -#define TEGRA234_MEMORY_CLIENT_NVL6RHP 0x18 -#define TEGRA234_MEMORY_CLIENT_NVL6R 0x19 -#define TEGRA234_MEMORY_CLIENT_NVL6W 0x1a -#define TEGRA234_MEMORY_CLIENT_NVL7RHP 0x1b -#define TEGRA234_MEMORY_CLIENT_NVENCSRD 0x1c -#define TEGRA234_MEMORY_CLIENT_NVL7R 0x1d -#define TEGRA234_MEMORY_CLIENT_NVL7W 0x1e -#define TEGRA234_MEMORY_CLIENT_NVL8RHP 0x20 -#define TEGRA234_MEMORY_CLIENT_NVL8R 0x21 -#define TEGRA234_MEMORY_CLIENT_NVL8W 0x22 -#define TEGRA234_MEMORY_CLIENT_NVL9RHP 0x23 -#define TEGRA234_MEMORY_CLIENT_NVL9R 0x24 -#define TEGRA234_MEMORY_CLIENT_NVL9W 0x25 -/* PCIE6 read clients */ -#define TEGRA234_MEMORY_CLIENT_PCIE6AR 0x28 -/* PCIE6 write clients */ -#define TEGRA234_MEMORY_CLIENT_PCIE6AW 0x29 -/* PCIE7 read clients */ -#define TEGRA234_MEMORY_CLIENT_PCIE7AR 0x2a -#define TEGRA234_MEMORY_CLIENT_NVENCSWR 0x2b -/* DLA0ARDB read clients */ -#define TEGRA234_MEMORY_CLIENT_DLA0RDB 0x2c -/* DLA0ARDB1 read clients */ -#define TEGRA234_MEMORY_CLIENT_DLA0RDB1 0x2d -/* DLA0 writes */ -#define TEGRA234_MEMORY_CLIENT_DLA0WRB 0x2e -/* DLA1ARDB read clients */ -#define TEGRA234_MEMORY_CLIENT_DLA1RDB 0x2f -/* PCIE7 write clients */ -#define TEGRA234_MEMORY_CLIENT_PCIE7AW 0x30 -/* PCIE8 read clients */ -#define TEGRA234_MEMORY_CLIENT_PCIE8AR 0x32 -/* High-definition audio (HDA) write clients */ -#define TEGRA234_MEMORY_CLIENT_HDAW 0x35 -/* Writes from Cortex-A9 4 CPU cores via the L2 cache */ -#define TEGRA234_MEMORY_CLIENT_MPCOREW 0x39 -/* OFAA client */ -#define TEGRA234_MEMORY_CLIENT_OFAR1 0x3a -/* PCIE8 write clients */ -#define TEGRA234_MEMORY_CLIENT_PCIE8AW 0x3b -/* PCIE9 read clients */ -#define TEGRA234_MEMORY_CLIENT_PCIE9AR 0x3c -/* PCIE6r1 read clients */ -#define TEGRA234_MEMORY_CLIENT_PCIE6AR1 0x3d -/* PCIE9 write clients */ -#define TEGRA234_MEMORY_CLIENT_PCIE9AW 0x3e -/* PCIE10 read clients */ -#define TEGRA234_MEMORY_CLIENT_PCIE10AR 0x3f -/* PCIE10 write clients */ -#define TEGRA234_MEMORY_CLIENT_PCIE10AW 0x40 -/* ISP read client for Crossbar A */ -#define TEGRA234_MEMORY_CLIENT_ISPRA 0x44 -/* ISP read client 1 for Crossbar A */ -#define TEGRA234_MEMORY_CLIENT_ISPFALR 0x45 -/* ISP Write client for Crossbar A */ -#define TEGRA234_MEMORY_CLIENT_ISPWA 0x46 -/* ISP Write client Crossbar B */ -#define TEGRA234_MEMORY_CLIENT_ISPWB 0x47 -/* PCIE10r1 read clients */ -#define TEGRA234_MEMORY_CLIENT_PCIE10AR1 0x48 -/* PCIE7r1 read clients */ -#define TEGRA234_MEMORY_CLIENT_PCIE7AR1 0x49 -/* XUSB_HOST read clients */ -#define TEGRA234_MEMORY_CLIENT_XUSB_HOSTR 0x4a -/* XUSB_HOST write clients */ -#define TEGRA234_MEMORY_CLIENT_XUSB_HOSTW 0x4b -/* XUSB read clients */ -#define TEGRA234_MEMORY_CLIENT_XUSB_DEVR 0x4c -/* XUSB_DEV write clients */ -#define TEGRA234_MEMORY_CLIENT_XUSB_DEVW 0x4d -/* TSEC Memory Return Data Client Description */ -#define TEGRA234_MEMORY_CLIENT_TSECSRD 0x54 -/* TSEC Memory Write Client Description */ -#define TEGRA234_MEMORY_CLIENT_TSECSWR 0x55 -/* XSPI writes */ -#define TEGRA234_MEMORY_CLIENT_XSPI1W 0x56 -/* MGBE0 read client */ -#define TEGRA234_MEMORY_CLIENT_MGBEARD 0x58 -/* MGBEB read client */ -#define TEGRA234_MEMORY_CLIENT_MGBEBRD 0x59 -/* MGBEC read client */ -#define TEGRA234_MEMORY_CLIENT_MGBECRD 0x5a -/* MGBED read client */ -#define TEGRA234_MEMORY_CLIENT_MGBEDRD 0x5b -/* MGBE0 write client */ -#define TEGRA234_MEMORY_CLIENT_MGBEAWR 0x5c -/* OFAA client */ -#define TEGRA234_MEMORY_CLIENT_OFAR 0x5d -/* OFAA writes */ -#define TEGRA234_MEMORY_CLIENT_OFAW 0x5e -/* MGBEB write client */ -#define TEGRA234_MEMORY_CLIENT_MGBEBWR 0x5f -/* sdmmca memory read client */ -#define TEGRA234_MEMORY_CLIENT_SDMMCRA 0x60 -/* MGBEC write client */ -#define TEGRA234_MEMORY_CLIENT_MGBECWR 0x61 -/* sdmmcd memory read client */ -#define TEGRA234_MEMORY_CLIENT_SDMMCRAB 0x63 -/* sdmmca memory write client */ -#define TEGRA234_MEMORY_CLIENT_SDMMCWA 0x64 -/* MGBED write client */ -#define TEGRA234_MEMORY_CLIENT_MGBEDWR 0x65 -/* sdmmcd memory write client */ -#define TEGRA234_MEMORY_CLIENT_SDMMCWAB 0x67 -/* SE Memory Return Data Client Description */ -#define TEGRA234_MEMORY_CLIENT_SEU1RD 0x68 -/* SE Memory Write Client Description */ -#define TEGRA234_MEMORY_CLIENT_SUE1WR 0x69 -#define TEGRA234_MEMORY_CLIENT_VICSRD 0x6c -#define TEGRA234_MEMORY_CLIENT_VICSWR 0x6d -/* DLA1ARDB1 read clients */ -#define TEGRA234_MEMORY_CLIENT_DLA1RDB1 0x6e -/* DLA1 writes */ -#define TEGRA234_MEMORY_CLIENT_DLA1WRB 0x6f -/* VI FLACON read clients */ -#define TEGRA234_MEMORY_CLIENT_VI2FALR 0x71 -/* VI Write client */ -#define TEGRA234_MEMORY_CLIENT_VI2W 0x70 -/* VI Write client */ -#define TEGRA234_MEMORY_CLIENT_VIW 0x72 -/* NISO display read client */ -#define TEGRA234_MEMORY_CLIENT_NVDISPNISOR 0x73 -/* NVDISPNISO writes */ -#define TEGRA234_MEMORY_CLIENT_NVDISPNISOW 0x74 -/* XSPI client */ -#define TEGRA234_MEMORY_CLIENT_XSPI0R 0x75 -/* XSPI writes */ -#define TEGRA234_MEMORY_CLIENT_XSPI0W 0x76 -/* XSPI client */ -#define TEGRA234_MEMORY_CLIENT_XSPI1R 0x77 -#define TEGRA234_MEMORY_CLIENT_NVDECSRD 0x78 -#define TEGRA234_MEMORY_CLIENT_NVDECSWR 0x79 -/* Audio Processing (APE) engine read clients */ -#define TEGRA234_MEMORY_CLIENT_APER 0x7a -/* Audio Processing (APE) engine write clients */ -#define TEGRA234_MEMORY_CLIENT_APEW 0x7b -/* VI2FAL writes */ -#define TEGRA234_MEMORY_CLIENT_VI2FALW 0x7c -#define TEGRA234_MEMORY_CLIENT_NVJPGSRD 0x7e -#define TEGRA234_MEMORY_CLIENT_NVJPGSWR 0x7f -/* SE Memory Return Data Client Description */ -#define TEGRA234_MEMORY_CLIENT_SESRD 0x80 -/* SE Memory Write Client Description */ -#define TEGRA234_MEMORY_CLIENT_SESWR 0x81 -/* AXI AP and DFD-AUX0/1 read clients Both share the same interface on the on MSS */ -#define TEGRA234_MEMORY_CLIENT_AXIAPR 0x82 -/* AXI AP and DFD-AUX0/1 write clients Both sahre the same interface on MSS */ -#define TEGRA234_MEMORY_CLIENT_AXIAPW 0x83 -/* ETR read clients */ -#define TEGRA234_MEMORY_CLIENT_ETRR 0x84 -/* ETR write clients */ -#define TEGRA234_MEMORY_CLIENT_ETRW 0x85 -/* AXI Switch read client */ -#define TEGRA234_MEMORY_CLIENT_AXISR 0x8c -/* AXI Switch write client */ -#define TEGRA234_MEMORY_CLIENT_AXISW 0x8d -/* EQOS read client */ -#define TEGRA234_MEMORY_CLIENT_EQOSR 0x8e -/* EQOS write client */ -#define TEGRA234_MEMORY_CLIENT_EQOSW 0x8f -/* UFSHC read client */ -#define TEGRA234_MEMORY_CLIENT_UFSHCR 0x90 -/* UFSHC write client */ -#define TEGRA234_MEMORY_CLIENT_UFSHCW 0x91 -/* NVDISPLAY read client */ -#define TEGRA234_MEMORY_CLIENT_NVDISPLAYR 0x92 -/* BPMP read client */ -#define TEGRA234_MEMORY_CLIENT_BPMPR 0x93 -/* BPMP write client */ -#define TEGRA234_MEMORY_CLIENT_BPMPW 0x94 -/* BPMPDMA read client */ -#define TEGRA234_MEMORY_CLIENT_BPMPDMAR 0x95 -/* BPMPDMA write client */ -#define TEGRA234_MEMORY_CLIENT_BPMPDMAW 0x96 -/* AON read client */ -#define TEGRA234_MEMORY_CLIENT_AONR 0x97 -/* AON write client */ -#define TEGRA234_MEMORY_CLIENT_AONW 0x98 -/* AONDMA read client */ -#define TEGRA234_MEMORY_CLIENT_AONDMAR 0x99 -/* AONDMA write client */ -#define TEGRA234_MEMORY_CLIENT_AONDMAW 0x9a -/* SCE read client */ -#define TEGRA234_MEMORY_CLIENT_SCER 0x9b -/* SCE write client */ -#define TEGRA234_MEMORY_CLIENT_SCEW 0x9c -/* SCEDMA read client */ -#define TEGRA234_MEMORY_CLIENT_SCEDMAR 0x9d -/* SCEDMA write client */ -#define TEGRA234_MEMORY_CLIENT_SCEDMAW 0x9e -/* APEDMA read client */ -#define TEGRA234_MEMORY_CLIENT_APEDMAR 0x9f -/* APEDMA write client */ -#define TEGRA234_MEMORY_CLIENT_APEDMAW 0xa0 -/* NVDISPLAY read client instance 2 */ -#define TEGRA234_MEMORY_CLIENT_NVDISPLAYR1 0xa1 -#define TEGRA234_MEMORY_CLIENT_VICSRD1 0xa2 -/* MSS internal memqual MIU0 read clients */ -#define TEGRA234_MEMORY_CLIENT_MIU0R 0xa6 -/* MSS internal memqual MIU0 write clients */ -#define TEGRA234_MEMORY_CLIENT_MIU0W 0xa7 -/* MSS internal memqual MIU1 read clients */ -#define TEGRA234_MEMORY_CLIENT_MIU1R 0xa8 -/* MSS internal memqual MIU1 write clients */ -#define TEGRA234_MEMORY_CLIENT_MIU1W 0xa9 -/* MSS internal memqual MIU2 read clients */ -#define TEGRA234_MEMORY_CLIENT_MIU2R 0xae -/* MSS internal memqual MIU2 write clients */ -#define TEGRA234_MEMORY_CLIENT_MIU2W 0xaf -/* MSS internal memqual MIU3 read clients */ -#define TEGRA234_MEMORY_CLIENT_MIU3R 0xb0 -/* MSS internal memqual MIU3 write clients */ -#define TEGRA234_MEMORY_CLIENT_MIU3W 0xb1 -/* MSS internal memqual MIU4 read clients */ -#define TEGRA234_MEMORY_CLIENT_MIU4R 0xb2 -/* MSS internal memqual MIU4 write clients */ -#define TEGRA234_MEMORY_CLIENT_MIU4W 0xb3 -#define TEGRA234_MEMORY_CLIENT_DPMUR 0xb4 -#define TEGRA234_MEMORY_CLIENT_DPMUW 0xb5 -#define TEGRA234_MEMORY_CLIENT_NVL0R 0xb6 -#define TEGRA234_MEMORY_CLIENT_NVL0W 0xb7 -#define TEGRA234_MEMORY_CLIENT_NVL1R 0xb8 -#define TEGRA234_MEMORY_CLIENT_NVL1W 0xb9 -#define TEGRA234_MEMORY_CLIENT_NVL2R 0xba -#define TEGRA234_MEMORY_CLIENT_NVL2W 0xbb -/* VI FLACON read clients */ -#define TEGRA234_MEMORY_CLIENT_VIFALR 0xbc -/* VIFAL write clients */ -#define TEGRA234_MEMORY_CLIENT_VIFALW 0xbd -/* DLA0ARDA read clients */ -#define TEGRA234_MEMORY_CLIENT_DLA0RDA 0xbe -/* DLA0 Falcon read clients */ -#define TEGRA234_MEMORY_CLIENT_DLA0FALRDB 0xbf -/* DLA0 write clients */ -#define TEGRA234_MEMORY_CLIENT_DLA0WRA 0xc0 -/* DLA0 write clients */ -#define TEGRA234_MEMORY_CLIENT_DLA0FALWRB 0xc1 -/* DLA1ARDA read clients */ -#define TEGRA234_MEMORY_CLIENT_DLA1RDA 0xc2 -/* DLA1 Falcon read clients */ -#define TEGRA234_MEMORY_CLIENT_DLA1FALRDB 0xc3 -/* DLA1 write clients */ -#define TEGRA234_MEMORY_CLIENT_DLA1WRA 0xc4 -/* DLA1 write clients */ -#define TEGRA234_MEMORY_CLIENT_DLA1FALWRB 0xc5 -/* PVA0RDA read clients */ -#define TEGRA234_MEMORY_CLIENT_PVA0RDA 0xc6 -/* PVA0RDB read clients */ -#define TEGRA234_MEMORY_CLIENT_PVA0RDB 0xc7 -/* PVA0RDC read clients */ -#define TEGRA234_MEMORY_CLIENT_PVA0RDC 0xc8 -/* PVA0WRA write clients */ -#define TEGRA234_MEMORY_CLIENT_PVA0WRA 0xc9 -/* PVA0WRB write clients */ -#define TEGRA234_MEMORY_CLIENT_PVA0WRB 0xca -/* PVA0WRC write clients */ -#define TEGRA234_MEMORY_CLIENT_PVA0WRC 0xcb -/* RCE read client */ -#define TEGRA234_MEMORY_CLIENT_RCER 0xd2 -/* RCE write client */ -#define TEGRA234_MEMORY_CLIENT_RCEW 0xd3 -/* RCEDMA read client */ -#define TEGRA234_MEMORY_CLIENT_RCEDMAR 0xd4 -/* RCEDMA write client */ -#define TEGRA234_MEMORY_CLIENT_RCEDMAW 0xd5 -/* PCIE0 read clients */ -#define TEGRA234_MEMORY_CLIENT_PCIE0R 0xd8 -/* PCIE0 write clients */ -#define TEGRA234_MEMORY_CLIENT_PCIE0W 0xd9 -/* PCIE1 read clients */ -#define TEGRA234_MEMORY_CLIENT_PCIE1R 0xda -/* PCIE1 write clients */ -#define TEGRA234_MEMORY_CLIENT_PCIE1W 0xdb -/* PCIE2 read clients */ -#define TEGRA234_MEMORY_CLIENT_PCIE2AR 0xdc -/* PCIE2 write clients */ -#define TEGRA234_MEMORY_CLIENT_PCIE2AW 0xdd -/* PCIE3 read clients */ -#define TEGRA234_MEMORY_CLIENT_PCIE3R 0xde -/* PCIE3 write clients */ -#define TEGRA234_MEMORY_CLIENT_PCIE3W 0xdf -/* PCIE4 read clients */ -#define TEGRA234_MEMORY_CLIENT_PCIE4R 0xe0 -/* PCIE4 write clients */ -#define TEGRA234_MEMORY_CLIENT_PCIE4W 0xe1 -/* PCIE5 read clients */ -#define TEGRA234_MEMORY_CLIENT_PCIE5R 0xe2 -/* PCIE5 write clients */ -#define TEGRA234_MEMORY_CLIENT_PCIE5W 0xe3 -/* ISP read client 1 for Crossbar A */ -#define TEGRA234_MEMORY_CLIENT_ISPFALW 0xe4 -#define TEGRA234_MEMORY_CLIENT_NVL3R 0xe5 -#define TEGRA234_MEMORY_CLIENT_NVL3W 0xe6 -#define TEGRA234_MEMORY_CLIENT_NVL4R 0xe7 -#define TEGRA234_MEMORY_CLIENT_NVL4W 0xe8 -/* DLA0ARDA1 read clients */ -#define TEGRA234_MEMORY_CLIENT_DLA0RDA1 0xe9 -/* DLA1ARDA1 read clients */ -#define TEGRA234_MEMORY_CLIENT_DLA1RDA1 0xea -/* PVA0RDA1 read clients */ -#define TEGRA234_MEMORY_CLIENT_PVA0RDA1 0xeb -/* PVA0RDB1 read clients */ -#define TEGRA234_MEMORY_CLIENT_PVA0RDB1 0xec -/* PCIE5r1 read clients */ -#define TEGRA234_MEMORY_CLIENT_PCIE5R1 0xef -#define TEGRA234_MEMORY_CLIENT_NVENCSRD1 0xf0 -/* ISP read client for Crossbar A */ -#define TEGRA234_MEMORY_CLIENT_ISPRA1 0xf2 -#define TEGRA234_MEMORY_CLIENT_NVL0RHP 0xf4 -#define TEGRA234_MEMORY_CLIENT_NVL1RHP 0xf5 -#define TEGRA234_MEMORY_CLIENT_NVL2RHP 0xf6 -#define TEGRA234_MEMORY_CLIENT_NVL3RHP 0xf7 -#define TEGRA234_MEMORY_CLIENT_NVL4RHP 0xf8 -/* MSS internal memqual MIU5 read clients */ -#define TEGRA234_MEMORY_CLIENT_MIU5R 0xfc -/* MSS internal memqual MIU5 write clients */ -#define TEGRA234_MEMORY_CLIENT_MIU5W 0xfd -/* MSS internal memqual MIU6 read clients */ -#define TEGRA234_MEMORY_CLIENT_MIU6R 0xfe -/* MSS internal memqual MIU6 write clients */ -#define TEGRA234_MEMORY_CLIENT_MIU6W 0xff -#define TEGRA234_MEMORY_CLIENT_NVJPG1SRD 0x123 -#define TEGRA234_MEMORY_CLIENT_NVJPG1SWR 0x124 - -/* ICC ID's for dummy MC clients used to represent CPU Clusters */ -#define TEGRA_ICC_MC_CPU_CLUSTER0 1003 -#define TEGRA_ICC_MC_CPU_CLUSTER1 1004 -#define TEGRA_ICC_MC_CPU_CLUSTER2 1005 - -#endif diff --git a/include/dt-bindings/memory/tegra30-mc.h b/include/dt-bindings/memory/tegra30-mc.h deleted file mode 100644 index 930f708aca1..00000000000 --- a/include/dt-bindings/memory/tegra30-mc.h +++ /dev/null @@ -1,111 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef DT_BINDINGS_MEMORY_TEGRA30_MC_H -#define DT_BINDINGS_MEMORY_TEGRA30_MC_H - -#define TEGRA_SWGROUP_PTC 0 -#define TEGRA_SWGROUP_DC 1 -#define TEGRA_SWGROUP_DCB 2 -#define TEGRA_SWGROUP_EPP 3 -#define TEGRA_SWGROUP_G2 4 -#define TEGRA_SWGROUP_MPE 5 -#define TEGRA_SWGROUP_VI 6 -#define TEGRA_SWGROUP_AFI 7 -#define TEGRA_SWGROUP_AVPC 8 -#define TEGRA_SWGROUP_NV 9 -#define TEGRA_SWGROUP_NV2 10 -#define TEGRA_SWGROUP_HDA 11 -#define TEGRA_SWGROUP_HC 12 -#define TEGRA_SWGROUP_PPCS 13 -#define TEGRA_SWGROUP_SATA 14 -#define TEGRA_SWGROUP_VDE 15 -#define TEGRA_SWGROUP_MPCORELP 16 -#define TEGRA_SWGROUP_MPCORE 17 -#define TEGRA_SWGROUP_ISP 18 - -#define TEGRA30_MC_RESET_AFI 0 -#define TEGRA30_MC_RESET_AVPC 1 -#define TEGRA30_MC_RESET_DC 2 -#define TEGRA30_MC_RESET_DCB 3 -#define TEGRA30_MC_RESET_EPP 4 -#define TEGRA30_MC_RESET_2D 5 -#define TEGRA30_MC_RESET_HC 6 -#define TEGRA30_MC_RESET_HDA 7 -#define TEGRA30_MC_RESET_ISP 8 -#define TEGRA30_MC_RESET_MPCORE 9 -#define TEGRA30_MC_RESET_MPCORELP 10 -#define TEGRA30_MC_RESET_MPE 11 -#define TEGRA30_MC_RESET_3D 12 -#define TEGRA30_MC_RESET_3D2 13 -#define TEGRA30_MC_RESET_PPCS 14 -#define TEGRA30_MC_RESET_SATA 15 -#define TEGRA30_MC_RESET_VDE 16 -#define TEGRA30_MC_RESET_VI 17 - -#define TEGRA30_MC_PTCR 0 -#define TEGRA30_MC_DISPLAY0A 1 -#define TEGRA30_MC_DISPLAY0AB 2 -#define TEGRA30_MC_DISPLAY0B 3 -#define TEGRA30_MC_DISPLAY0BB 4 -#define TEGRA30_MC_DISPLAY0C 5 -#define TEGRA30_MC_DISPLAY0CB 6 -#define TEGRA30_MC_DISPLAY1B 7 -#define TEGRA30_MC_DISPLAY1BB 8 -#define TEGRA30_MC_EPPUP 9 -#define TEGRA30_MC_G2PR 10 -#define TEGRA30_MC_G2SR 11 -#define TEGRA30_MC_MPEUNIFBR 12 -#define TEGRA30_MC_VIRUV 13 -#define TEGRA30_MC_AFIR 14 -#define TEGRA30_MC_AVPCARM7R 15 -#define TEGRA30_MC_DISPLAYHC 16 -#define TEGRA30_MC_DISPLAYHCB 17 -#define TEGRA30_MC_FDCDRD 18 -#define TEGRA30_MC_FDCDRD2 19 -#define TEGRA30_MC_G2DR 20 -#define TEGRA30_MC_HDAR 21 -#define TEGRA30_MC_HOST1XDMAR 22 -#define TEGRA30_MC_HOST1XR 23 -#define TEGRA30_MC_IDXSRD 24 -#define TEGRA30_MC_IDXSRD2 25 -#define TEGRA30_MC_MPE_IPRED 26 -#define TEGRA30_MC_MPEAMEMRD 27 -#define TEGRA30_MC_MPECSRD 28 -#define TEGRA30_MC_PPCSAHBDMAR 29 -#define TEGRA30_MC_PPCSAHBSLVR 30 -#define TEGRA30_MC_SATAR 31 -#define TEGRA30_MC_TEXSRD 32 -#define TEGRA30_MC_TEXSRD2 33 -#define TEGRA30_MC_VDEBSEVR 34 -#define TEGRA30_MC_VDEMBER 35 -#define TEGRA30_MC_VDEMCER 36 -#define TEGRA30_MC_VDETPER 37 -#define TEGRA30_MC_MPCORELPR 38 -#define TEGRA30_MC_MPCORER 39 -#define TEGRA30_MC_EPPU 40 -#define TEGRA30_MC_EPPV 41 -#define TEGRA30_MC_EPPY 42 -#define TEGRA30_MC_MPEUNIFBW 43 -#define TEGRA30_MC_VIWSB 44 -#define TEGRA30_MC_VIWU 45 -#define TEGRA30_MC_VIWV 46 -#define TEGRA30_MC_VIWY 47 -#define TEGRA30_MC_G2DW 48 -#define TEGRA30_MC_AFIW 49 -#define TEGRA30_MC_AVPCARM7W 50 -#define TEGRA30_MC_FDCDWR 51 -#define TEGRA30_MC_FDCDWR2 52 -#define TEGRA30_MC_HDAW 53 -#define TEGRA30_MC_HOST1XW 54 -#define TEGRA30_MC_ISPW 55 -#define TEGRA30_MC_MPCORELPW 56 -#define TEGRA30_MC_MPCOREW 57 -#define TEGRA30_MC_MPECSWR 58 -#define TEGRA30_MC_PPCSAHBDMAW 59 -#define TEGRA30_MC_PPCSAHBSLVW 60 -#define TEGRA30_MC_SATAW 61 -#define TEGRA30_MC_VDEBSEVW 62 -#define TEGRA30_MC_VDEDBGW 63 -#define TEGRA30_MC_VDEMBEW 64 -#define TEGRA30_MC_VDETPMW 65 - -#endif |