diff options
Diffstat (limited to 'include/dt-bindings/net/ti-dp83869.h')
| -rw-r--r-- | include/dt-bindings/net/ti-dp83869.h | 34 |
1 files changed, 26 insertions, 8 deletions
diff --git a/include/dt-bindings/net/ti-dp83869.h b/include/dt-bindings/net/ti-dp83869.h index 917114aad7d..b3a5ac4a17b 100644 --- a/include/dt-bindings/net/ti-dp83869.h +++ b/include/dt-bindings/net/ti-dp83869.h @@ -1,10 +1,7 @@ -/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ +/* SPDX-License-Identifier: GPL-2.0 */ /* - * Device Tree constants for the Texas Instruments DP83869 PHY + * TI DP83869 PHY drivers * - * Author: Dan Murphy <dmurphy@ti.com> - * - * Copyright (C) 2015-2024 Texas Instruments Incorporated - https://www.ti.com/ */ #ifndef _DT_BINDINGS_TI_DP83869_H @@ -16,6 +13,24 @@ #define DP83869_PHYCR_FIFO_DEPTH_6_B_NIB 0x02 #define DP83869_PHYCR_FIFO_DEPTH_8_B_NIB 0x03 +/* RGMIIDCTL internal delay for rx and tx */ +#define DP83869_RGMIIDCTL_250_PS 0x0 +#define DP83869_RGMIIDCTL_500_PS 0x1 +#define DP83869_RGMIIDCTL_750_PS 0x2 +#define DP83869_RGMIIDCTL_1_NS 0x3 +#define DP83869_RGMIIDCTL_1_25_NS 0x4 +#define DP83869_RGMIIDCTL_1_50_NS 0x5 +#define DP83869_RGMIIDCTL_1_75_NS 0x6 +#define DP83869_RGMIIDCTL_2_00_NS 0x7 +#define DP83869_RGMIIDCTL_2_25_NS 0x8 +#define DP83869_RGMIIDCTL_2_50_NS 0x9 +#define DP83869_RGMIIDCTL_2_75_NS 0xa +#define DP83869_RGMIIDCTL_3_00_NS 0xb +#define DP83869_RGMIIDCTL_3_25_NS 0xc +#define DP83869_RGMIIDCTL_3_50_NS 0xd +#define DP83869_RGMIIDCTL_3_75_NS 0xe +#define DP83869_RGMIIDCTL_4_00_NS 0xf + /* IO_MUX_CFG - Clock output selection */ #define DP83869_CLK_O_SEL_CHN_A_RCLK 0x0 #define DP83869_CLK_O_SEL_CHN_B_RCLK 0x1 @@ -27,10 +42,13 @@ #define DP83869_CLK_O_SEL_CHN_D_RCLK_DIV5 0x7 #define DP83869_CLK_O_SEL_CHN_A_TCLK 0x8 #define DP83869_CLK_O_SEL_CHN_B_TCLK 0x9 -#define DP83869_CLK_O_SEL_CHN_C_TCLK 0xa -#define DP83869_CLK_O_SEL_CHN_D_TCLK 0xb -#define DP83869_CLK_O_SEL_REF_CLK 0xc +#define DP83869_CLK_O_SEL_CHN_C_TCLK 0xA +#define DP83869_CLK_O_SEL_CHN_D_TCLK 0xB +#define DP83869_CLK_O_SEL_REF_CLK 0xC +/* Special flag to indicate clock should be off */ +#define DP83869_CLK_O_SEL_OFF 0xFFFFFFFF +/* OPMODE - Operation mode */ #define DP83869_RGMII_COPPER_ETHERNET 0x00 #define DP83869_RGMII_1000_BASE 0x01 #define DP83869_RGMII_100_BASE 0x02 |