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-rw-r--r--include/configs/alt.h10
-rw-r--r--include/configs/blanche.h4
-rw-r--r--include/configs/condor.h13
-rw-r--r--include/configs/ebisu.h2
-rw-r--r--include/configs/falcon.h3
-rw-r--r--include/configs/genmai.h15
-rw-r--r--include/configs/gose.h10
-rw-r--r--include/configs/grpeach.h12
-rw-r--r--include/configs/koelsch.h12
-rw-r--r--include/configs/lager.h12
-rw-r--r--include/configs/porter.h12
-rw-r--r--include/configs/silk.h12
-rw-r--r--include/configs/stout.h12
-rw-r--r--include/configs/v3hsk.h13
-rw-r--r--include/dm/uclass-id.h1
-rw-r--r--include/uboot_aes.h251
16 files changed, 267 insertions, 127 deletions
diff --git a/include/configs/alt.h b/include/configs/alt.h
index 8f03762583e..4c5d2de2bdf 100644
--- a/include/configs/alt.h
+++ b/include/configs/alt.h
@@ -20,16 +20,6 @@
#define RCAR_GEN2_SDRAM_SIZE (1024u * 1024 * 1024)
#define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024)
-/* SH Ether */
-#define CFG_SH_ETHER_USE_PORT 0
-#define CFG_SH_ETHER_PHY_ADDR 0x1
-#define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
-#define CFG_SH_ETHER_CACHE_WRITEBACK
-#define CFG_SH_ETHER_CACHE_INVALIDATE
-#define CFG_SH_ETHER_ALIGNE_SIZE 64
-
-/* Board Clock */
-
#define CFG_EXTRA_ENV_SETTINGS \
"bootm_size=0x10000000\0" \
"usb_pgood_delay=2000\0"
diff --git a/include/configs/blanche.h b/include/configs/blanche.h
index d4e0f677e67..46521aa16bf 100644
--- a/include/configs/blanche.h
+++ b/include/configs/blanche.h
@@ -29,8 +29,4 @@
#define CFG_SYS_FLASH_BANKS_SIZES { (CFG_SYS_FLASH_SIZE) }
#endif
-/* Board Clock */
-
-/* ENV setting */
-
#endif /* __BLANCHE_H */
diff --git a/include/configs/condor.h b/include/configs/condor.h
index 50c8d173383..b340800cc11 100644
--- a/include/configs/condor.h
+++ b/include/configs/condor.h
@@ -11,17 +11,4 @@
#include "rcar-gen3-common.h"
-/* Environment compatibility */
-
-/* SH Ether */
-#define CFG_SH_ETHER_USE_PORT 0
-#define CFG_SH_ETHER_PHY_ADDR 0x1
-#define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
-#define CFG_SH_ETHER_CACHE_WRITEBACK
-#define CFG_SH_ETHER_CACHE_INVALIDATE
-#define CFG_SH_ETHER_ALIGNE_SIZE 64
-
-/* Board Clock */
-/* XTAL_CLK : 33.33MHz */
-
#endif /* __CONDOR_H */
diff --git a/include/configs/ebisu.h b/include/configs/ebisu.h
index ad5944230a6..707e7c28d55 100644
--- a/include/configs/ebisu.h
+++ b/include/configs/ebisu.h
@@ -9,8 +9,6 @@
#ifndef __EBISU_H
#define __EBISU_H
-#undef DEBUG
-
#include "rcar-gen3-common.h"
/* Environment in eMMC, at the end of 2nd "boot sector" */
diff --git a/include/configs/falcon.h b/include/configs/falcon.h
index 0b62ff9fbe1..e1cace73550 100644
--- a/include/configs/falcon.h
+++ b/include/configs/falcon.h
@@ -11,7 +11,4 @@
#include "rcar-gen4-common.h"
-/* Board Clock */
-/* XTAL_CLK : 16.66MHz */
-
#endif /* __FALCON_H */
diff --git a/include/configs/genmai.h b/include/configs/genmai.h
new file mode 100644
index 00000000000..1d43f8e06af
--- /dev/null
+++ b/include/configs/genmai.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Configuration settings for the Renesas GENMAI board
+ *
+ * Copyright (C) 2017-2019 Renesas Electronics
+ */
+
+#ifndef __GENMAI_H
+#define __GENMAI_H
+
+/* Internal RAM Size (RZ/A1=3M, RZ/A1M=5M, RZ/A1H=10M) */
+#define CFG_SYS_SDRAM_BASE 0x20000000
+#define CFG_SYS_SDRAM_SIZE (10 * 1024 * 1024)
+
+#endif /* __GENAMI_H */
diff --git a/include/configs/gose.h b/include/configs/gose.h
index 7ae0726518d..4a5954af76f 100644
--- a/include/configs/gose.h
+++ b/include/configs/gose.h
@@ -19,16 +19,6 @@
#define RCAR_GEN2_SDRAM_SIZE (1048u * 1024 * 1024)
#define RCAR_GEN2_UBOOT_SDRAM_SIZE (512u * 1024 * 1024)
-/* SH Ether */
-#define CFG_SH_ETHER_USE_PORT 0
-#define CFG_SH_ETHER_PHY_ADDR 0x1
-#define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
-#define CFG_SH_ETHER_CACHE_WRITEBACK
-#define CFG_SH_ETHER_CACHE_INVALIDATE
-#define CFG_SH_ETHER_ALIGNE_SIZE 64
-
-/* Board Clock */
-
#define CFG_EXTRA_ENV_SETTINGS \
"bootm_size=0x10000000\0"
diff --git a/include/configs/grpeach.h b/include/configs/grpeach.h
index 8de4a36e931..e4564b67a79 100644
--- a/include/configs/grpeach.h
+++ b/include/configs/grpeach.h
@@ -8,20 +8,8 @@
#ifndef __GRPEACH_H
#define __GRPEACH_H
-/* Board Clock , P1 clock frequency (XTAL=13.33MHz) */
-
-/* Miscellaneous */
-
/* Internal RAM Size (RZ/A1=3M, RZ/A1M=5M, RZ/A1H=10M) */
#define CFG_SYS_SDRAM_BASE 0x20000000
#define CFG_SYS_SDRAM_SIZE (10 * 1024 * 1024)
-/* Network interface */
-#define CFG_SH_ETHER_USE_PORT 0
-#define CFG_SH_ETHER_PHY_ADDR 0
-#define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII
-#define CFG_SH_ETHER_CACHE_WRITEBACK
-#define CFG_SH_ETHER_CACHE_INVALIDATE
-#define CFG_SH_ETHER_ALIGNE_SIZE 64
-
#endif /* __GRPEACH_H */
diff --git a/include/configs/koelsch.h b/include/configs/koelsch.h
index d47d70178cc..c2713b77e0a 100644
--- a/include/configs/koelsch.h
+++ b/include/configs/koelsch.h
@@ -19,19 +19,7 @@
#define RCAR_GEN2_SDRAM_SIZE (2048u * 1024 * 1024)
#define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024)
-/* SH Ether */
-#define CFG_SH_ETHER_USE_PORT 0
-#define CFG_SH_ETHER_PHY_ADDR 0x1
-#define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
-#define CFG_SH_ETHER_CACHE_WRITEBACK
-#define CFG_SH_ETHER_CACHE_INVALIDATE
-#define CFG_SH_ETHER_ALIGNE_SIZE 64
-
-/* Board Clock */
-
#define CFG_EXTRA_ENV_SETTINGS \
"bootm_size=0x10000000\0"
-/* SPL support */
-
#endif /* __KOELSCH_H */
diff --git a/include/configs/lager.h b/include/configs/lager.h
index 2577c7a7da6..13f327fabf2 100644
--- a/include/configs/lager.h
+++ b/include/configs/lager.h
@@ -20,19 +20,7 @@
#define RCAR_GEN2_SDRAM_SIZE (2048u * 1024 * 1024)
#define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024)
-/* SH Ether */
-#define CFG_SH_ETHER_USE_PORT 0
-#define CFG_SH_ETHER_PHY_ADDR 0x1
-#define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
-#define CFG_SH_ETHER_CACHE_WRITEBACK
-#define CFG_SH_ETHER_CACHE_INVALIDATE
-#define CFG_SH_ETHER_ALIGNE_SIZE 64
-
-/* Board Clock */
-
#define CFG_EXTRA_ENV_SETTINGS \
"bootm_size=0x10000000\0"
-/* SPL support */
-
#endif /* __LAGER_H */
diff --git a/include/configs/porter.h b/include/configs/porter.h
index 2cb430be8b0..4612845db19 100644
--- a/include/configs/porter.h
+++ b/include/configs/porter.h
@@ -21,19 +21,7 @@
#define RCAR_GEN2_SDRAM_SIZE (2048u * 1024 * 1024)
#define RCAR_GEN2_UBOOT_SDRAM_SIZE (1024u * 1024 * 1024)
-/* SH Ether */
-#define CFG_SH_ETHER_USE_PORT 0
-#define CFG_SH_ETHER_PHY_ADDR 0x1
-#define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
-#define CFG_SH_ETHER_CACHE_WRITEBACK
-#define CFG_SH_ETHER_CACHE_INVALIDATE
-#define CFG_SH_ETHER_ALIGNE_SIZE 64
-
-/* Board Clock */
-
#define CFG_EXTRA_ENV_SETTINGS \
"bootm_size=0x10000000\0"
-/* SPL support */
-
#endif /* __PORTER_H */
diff --git a/include/configs/silk.h b/include/configs/silk.h
index 7bed32d8553..09ef2a848bd 100644
--- a/include/configs/silk.h
+++ b/include/configs/silk.h
@@ -21,19 +21,7 @@
#define RCAR_GEN2_SDRAM_SIZE (1024u * 1024 * 1024)
#define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024)
-/* SH Ether */
-#define CFG_SH_ETHER_USE_PORT 0
-#define CFG_SH_ETHER_PHY_ADDR 0x1
-#define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
-#define CFG_SH_ETHER_CACHE_WRITEBACK
-#define CFG_SH_ETHER_CACHE_INVALIDATE
-#define CFG_SH_ETHER_ALIGNE_SIZE 64
-
-/* Board Clock */
-
#define CFG_EXTRA_ENV_SETTINGS \
"bootm_size=0x10000000\0"
-/* SPL support */
-
#endif /* __SILK_H */
diff --git a/include/configs/stout.h b/include/configs/stout.h
index 1278ba63f4f..f98ebb324f3 100644
--- a/include/configs/stout.h
+++ b/include/configs/stout.h
@@ -25,19 +25,7 @@
/* SCIF */
#define CFG_SCIF_A
-/* SH Ether */
-#define CFG_SH_ETHER_USE_PORT 0
-#define CFG_SH_ETHER_PHY_ADDR 0x1
-#define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
-#define CFG_SH_ETHER_CACHE_WRITEBACK
-#define CFG_SH_ETHER_CACHE_INVALIDATE
-#define CFG_SH_ETHER_ALIGNE_SIZE 64
-
-/* Board Clock */
-
#define CFG_EXTRA_ENV_SETTINGS \
"bootm_size=0x10000000\0"
-/* SPL support */
-
#endif /* __STOUT_H */
diff --git a/include/configs/v3hsk.h b/include/configs/v3hsk.h
index 58c2e88c0b7..3298e627e53 100644
--- a/include/configs/v3hsk.h
+++ b/include/configs/v3hsk.h
@@ -12,17 +12,4 @@
#include "rcar-gen3-common.h"
-/* Environment compatibility */
-
-/* SH Ether */
-#define CFG_SH_ETHER_USE_PORT 0
-#define CFG_SH_ETHER_PHY_ADDR 0x0
-#define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RGMII_ID
-#define CFG_SH_ETHER_CACHE_WRITEBACK
-#define CFG_SH_ETHER_CACHE_INVALIDATE
-#define CFG_SH_ETHER_ALIGNE_SIZE 64
-
-/* Board Clock */
-/* XTAL_CLK : 33.33MHz */
-
#endif /* __V3HSK_H */
diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h
index 270088ad94f..5c0fd6d171b 100644
--- a/include/dm/uclass-id.h
+++ b/include/dm/uclass-id.h
@@ -38,6 +38,7 @@ enum uclass_id {
/* U-Boot uclasses start here - in alphabetical order */
UCLASS_ACPI_PMC, /* (x86) Power-management controller (PMC) */
UCLASS_ADC, /* Analog-to-digital converter */
+ UCLASS_AES, /* AES cryptographic engine */
UCLASS_AHCI, /* SATA disk controller */
UCLASS_AUDIO_CODEC, /* Audio codec with control and data path */
UCLASS_AXI, /* AXI bus */
diff --git a/include/uboot_aes.h b/include/uboot_aes.h
index d2583bed992..592b7dbee43 100644
--- a/include/uboot_aes.h
+++ b/include/uboot_aes.h
@@ -7,6 +7,8 @@
#ifndef _AES_REF_H_
#define _AES_REF_H_
+#include <errno.h>
+
#ifdef USE_HOSTCC
/* Define compat stuff for use in fw_* tools. */
typedef unsigned char u8;
@@ -107,4 +109,253 @@ void aes_cbc_encrypt_blocks(u32 key_size, u8 *key_exp, u8 *iv, u8 *src, u8 *dst,
void aes_cbc_decrypt_blocks(u32 key_size, u8 *key_exp, u8 *iv, u8 *src, u8 *dst,
u32 num_aes_blocks);
+/* An AES block filled with zeros */
+static const u8 AES_ZERO_BLOCK[AES_BLOCK_LENGTH] = { 0 };
+struct udevice;
+
+/**
+ * struct struct aes_ops - Driver model for AES related operations
+ *
+ * The uclass interface is implemented by AES crypto devices which use driver model.
+ *
+ * Some AES crypto devices use key slots to store the key for the encrypt/decrypt
+ * operations, while others may simply pass the key on each operation.
+ *
+ * In case the device does not implement hardware slots, driver can emulate or simply
+ * store one active key slot at 0 in the driver state and pass it on each underlying
+ * hw calls for AES operations.
+ *
+ * Note that some devices like Tegra AES engine may contain preloaded keys by bootrom,
+ * thus in those cases the set_key_for_key_slot() may be skipped.
+ *
+ * Sequence for a series of AES CBC encryption, one decryption and a CMAC hash example
+ * with 128bits key at slot 0 would be as follow:
+ *
+ * set_key_for_key_slot(DEV, 128, KEY, 0);
+ * select_key_slot(DEV, 128, 0);
+ * aes_cbc_encrypt(DEV, IV1, SRC1, DST1, LEN1);
+ * aes_cbc_encrypt(DEV, IV2, SRC2, DST2, LEN2);
+ * aes_cbc_decrypt(DEV, IV3, SRC3, DST3, LEN3);
+ */
+struct aes_ops {
+ /**
+ * available_key_slots() - How many key slots this AES device has
+ *
+ * @dev The AES udevice
+ * @return Available slots to use, 0 for none
+ */
+ int (*available_key_slots)(struct udevice *dev);
+
+ /**
+ * select_key_slot() - Selects the AES key slot to use for following operations
+ *
+ * @dev The AES udevice
+ * @key_size Size of the aes key (in bits)
+ * @slot The key slot to set as selected
+ * @return 0 on success, negative value on failure
+ */
+ int (*select_key_slot)(struct udevice *dev, u32 key_size, u8 slot);
+
+ /**
+ * set_key_for_key_slot() - Sets the AES key to use for specified key slot
+ *
+ * @dev The AES udevice
+ * @key_size Size of the aes key (in bits)
+ * @key An AES key to set
+ * @slot The slot to load the key at
+ * @return 0 on success, negative value on failure
+ */
+ int (*set_key_for_key_slot)(struct udevice *dev, u32 key_size, u8 *key,
+ u8 slot);
+
+ /**
+ * aes_ecb_encrypt() - Encrypt multiple blocks of data with AES ECB.
+ *
+ * @dev The AES udevice
+ * @src Source data of length 'num_aes_blocks' blocks
+ * @dst Destination data of length 'num_aes_blocks' blocks
+ * @num_aes_blocks Number of AES blocks to encrypt/decrypt
+ * @return 0 on success, negative value on failure
+ */
+ int (*aes_ecb_encrypt)(struct udevice *dev, u8 *src, u8 *dst, u32 num_aes_blocks);
+
+ /**
+ * aes_ecb_decrypt() - Decrypt multiple blocks of data with AES ECB.
+ *
+ * @dev The AES udevice
+ * @src Source data of length 'num_aes_blocks' blocks
+ * @dst Destination data of length 'num_aes_blocks' blocks
+ * @num_aes_blocks Number of AES blocks to encrypt/decrypt
+ * @return 0 on success, negative value on failure
+ */
+ int (*aes_ecb_decrypt)(struct udevice *dev, u8 *src, u8 *dst, u32 num_aes_blocks);
+
+ /**
+ * aes_cbc_encrypt() - Encrypt multiple blocks of data with AES CBC.
+ *
+ * @dev The AES udevice
+ * @iv Initialization vector
+ * @src Source data of length 'num_aes_blocks' blocks
+ * @dst Destination data of length 'num_aes_blocks' blocks
+ * @num_aes_blocks Number of AES blocks to encrypt/decrypt
+ * @return 0 on success, negative value on failure
+ */
+ int (*aes_cbc_encrypt)(struct udevice *dev, u8 *iv,
+ u8 *src, u8 *dst, u32 num_aes_blocks);
+
+ /**
+ * aes_cbc_decrypt() - Decrypt multiple blocks of data with AES CBC.
+ *
+ * @dev The AES udevice
+ * @iv Initialization vector
+ * @src Source data of length 'num_aes_blocks' blocks
+ * @dst Destination data of length 'num_aes_blocks' blocks
+ * @num_aes_blocks Number of AES blocks to encrypt/decrypt
+ * @return 0 on success, negative value on failure
+ */
+ int (*aes_cbc_decrypt)(struct udevice *dev, u8 *iv,
+ u8 *src, u8 *dst, u32 num_aes_blocks);
+};
+
+#define aes_get_ops(dev) ((struct aes_ops *)(dev)->driver->ops)
+
+#if CONFIG_IS_ENABLED(DM_AES)
+
+/**
+ * dm_aes_get_available_key_slots - How many key slots this AES device has
+ *
+ * @dev The AES udevice
+ * Return: Available slots to use, 0 for none, -ve on failure
+ */
+int dm_aes_get_available_key_slots(struct udevice *dev);
+
+/**
+ * dm_aes_select_key_slot - Selects the AES key slot to use for following operations
+ *
+ * @dev The AES udevice
+ * @key_size Size of the aes key (in bits)
+ * @slot The key slot to set as selected
+ * Return: 0 on success, -ve on failure
+ */
+int dm_aes_select_key_slot(struct udevice *dev, u32 key_size, u8 slot);
+
+/**
+ * dm_aes_set_key_for_key_slot - Sets the AES key to use for specified key slot
+ *
+ * @dev The AES udevice
+ * @key_size Size of the aes key (in bits)
+ * @key An AES key to set
+ * @slot The slot to load the key at
+ * Return: 0 on success, negative value on failure
+ */
+int dm_aes_set_key_for_key_slot(struct udevice *dev, u32 key_size, u8 *key, u8 slot);
+
+/**
+ * dm_aes_ecb_encrypt - Encrypt multiple blocks of data with AES ECB.
+ *
+ * @dev The AES udevice
+ * @src Source data of length 'num_aes_blocks' blocks
+ * @dst Destination data of length 'num_aes_blocks' blocks
+ * @num_aes_blocks Number of AES blocks to encrypt/decrypt
+ * Return: 0 on success, negative value on failure
+ */
+int dm_aes_ecb_encrypt(struct udevice *dev, u8 *src, u8 *dst, u32 num_aes_blocks);
+
+/**
+ * dm_aes_ecb_decrypt - Decrypt multiple blocks of data with AES ECB.
+ *
+ * @dev The AES udevice
+ * @src Source data of length 'num_aes_blocks' blocks
+ * @dst Destination data of length 'num_aes_blocks' blocks
+ * @num_aes_blocks Number of AES blocks to encrypt/decrypt
+ * Return: 0 on success, negative value on failure
+ */
+int dm_aes_ecb_decrypt(struct udevice *dev, u8 *src, u8 *dst, u32 num_aes_blocks);
+
+/**
+ * dm_aes_cbc_encrypt - Encrypt multiple blocks of data with AES CBC.
+ *
+ * @dev The AES udevice
+ * @iv Initialization vector
+ * @src Source data of length 'num_aes_blocks' blocks
+ * @dst Destination data of length 'num_aes_blocks' blocks
+ * @num_aes_blocks Number of AES blocks to encrypt/decrypt
+ * Return: 0 on success, negative value on failure
+ */
+int dm_aes_cbc_encrypt(struct udevice *dev, u8 *iv, u8 *src, u8 *dst, u32 num_aes_blocks);
+
+/**
+ * dm_aes_cbc_decrypt - Decrypt multiple blocks of data with AES CBC.
+ *
+ * @dev The AES udevice
+ * @iv Initialization vector
+ * @src Source data of length 'num_aes_blocks' blocks
+ * @dst Destination data of length 'num_aes_blocks' blocks
+ * @num_aes_blocks Number of AES blocks to encrypt/decrypt
+ * Return: 0 on success, negative value on failure
+ */
+int dm_aes_cbc_decrypt(struct udevice *dev, u8 *iv, u8 *src, u8 *dst, u32 num_aes_blocks);
+
+/**
+ * dm_aes_cmac - Hashes the input data with AES-CMAC, putting the result into dst.
+ * The key slot must be selected already.
+ *
+ * @dev The AES udevice
+ * @key_size Size of the aes key (in bits)
+ * @src Source data of length 'num_aes_blocks' blocks
+ * @dst Destination for hash result
+ * @num_aes_blocks Number of AES blocks to encrypt
+ * Return: 0 on success, negative value on failure.
+ */
+int dm_aes_cmac(struct udevice *dev, u8 *src, u8 *dst, u32 num_aes_blocks);
+
+#else
+
+static inline int dm_aes_get_available_key_slots(struct udevice *dev)
+{
+ return -ENOSYS;
+}
+
+static inline int dm_aes_select_key_slot(struct udevice *dev, u32 key_size, u8 slot)
+{
+ return -ENOSYS;
+}
+
+static inline int dm_aes_set_key_for_key_slot(struct udevice *dev, u32 key_size, u8 *key,
+ u8 slot)
+{
+ return -ENOSYS;
+}
+
+static inline int dm_aes_ecb_encrypt(struct udevice *dev, u8 *src, u8 *dst,
+ u32 num_aes_blocks)
+{
+ return -ENOSYS;
+}
+
+static inline int dm_aes_ecb_decrypt(struct udevice *dev, u8 *src, u8 *dst,
+ u32 num_aes_blocks)
+{
+ return -ENOSYS;
+}
+
+static inline int dm_aes_cbc_encrypt(struct udevice *dev, u8 *iv, u8 *src,
+ u8 *dst, u32 num_aes_blocks)
+{
+ return -ENOSYS;
+}
+
+static inline int dm_aes_cbc_decrypt(struct udevice *dev, u8 *iv, u8 *src,
+ u8 *dst, u32 num_aes_blocks)
+{
+ return -ENOSYS;
+}
+
+static inline int dm_aes_cmac(struct udevice *dev, u8 *src, u8 *dst, u32 num_aes_blocks)
+{
+ return -ENOSYS;
+}
+
+#endif /* CONFIG_DM_AES */
+
#endif /* _AES_REF_H_ */
generated by cgit v1.2.3 (git 2.0.4) at 2025-07-13 02:47:21 +0000