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-rw-r--r--include/configs/km/km_arm.h4
-rw-r--r--include/configs/kmcent2.h513
-rw-r--r--include/configs/kmp204x.h6
-rw-r--r--include/configs/kontron_sl28.h1
-rw-r--r--include/configs/ls1012a_common.h7
-rw-r--r--include/configs/ls1021aqds.h7
-rw-r--r--include/configs/ls1021atwr.h7
-rw-r--r--include/configs/ls1028a_common.h7
-rw-r--r--include/configs/ls1043a_common.h7
-rw-r--r--include/configs/ls1046a_common.h7
-rw-r--r--include/configs/ls1088a_common.h7
-rw-r--r--include/configs/ls1088aqds.h12
-rw-r--r--include/configs/ls2080a_common.h7
-rw-r--r--include/configs/lx2160a_common.h7
-rw-r--r--include/spi-mem.h3
15 files changed, 592 insertions, 10 deletions
diff --git a/include/configs/km/km_arm.h b/include/configs/km/km_arm.h
index 29060fa96b3..4115906c5d7 100644
--- a/include/configs/km/km_arm.h
+++ b/include/configs/km/km_arm.h
@@ -110,10 +110,6 @@
#include <linux/delay.h>
#include <linux/stringify.h>
extern void __set_direction(unsigned pin, int high);
-void set_sda(int state);
-void set_scl(int state);
-int get_sda(void);
-int get_scl(void);
#define KM_KIRKWOOD_SDA_PIN 8
#define KM_KIRKWOOD_SCL_PIN 9
#define KM_KIRKWOOD_SOFT_I2C_GPIOS 0x0300
diff --git a/include/configs/kmcent2.h b/include/configs/kmcent2.h
new file mode 100644
index 00000000000..51a01d860f0
--- /dev/null
+++ b/include/configs/kmcent2.h
@@ -0,0 +1,513 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2016 Keymile AG
+ * Rainer Boschung <rainer.boschung@keymile.com>
+ *
+ */
+
+#ifndef __KMCENT2_H
+#define __KMCENT2_H
+
+#define CONFIG_HOSTNAME "kmcent2"
+#define KM_BOARD_NAME CONFIG_HOSTNAME
+
+/*
+ * The Linux fsl_fman driver needs to be able to process frames with more
+ * than just the VLAN tag (i.e. eDSA tag). It is passed as a kernel boot
+ * parameters
+ */
+#define CONFIG_KM_DEF_BOOT_ARGS_CPU "fsl_dpaa_fman.fsl_fm_max_frm=1558"
+
+#include "km/keymile-common.h"
+
+/* Application IFC chip selects */
+#define SYS_LAWAPP_BASE 0xc0000000
+#define SYS_LAWAPP_BASE_PHYS (0xf00000000ull | SYS_LAWAPP_BASE)
+
+/* Application IFC CS4 MRAM */
+#define CONFIG_SYS_MRAM_BASE SYS_LAWAPP_BASE
+#define SYS_MRAM_BASE_PHYS SYS_LAWAPP_BASE_PHYS
+#define SYS_MRAM_CSPR_EXT (0x0f)
+#define SYS_MRAM_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_MRAM_BASE) | \
+ CSPR_PORT_SIZE_8 | /* 8 bit */ \
+ CSPR_MSEL_GPCM | /* msel = gpcm */ \
+ CSPR_V /* bank is valid */)
+#define SYS_MRAM_AMASK IFC_AMASK(2 * 1024 * 1024) /* 2 MiB */
+#define SYS_MRAM_CSOR CSOR_GPCM_TRHZ_40
+/* MRAM Timing parameters for IFC CS4 */
+#define SYS_MRAM_FTIM0 (FTIM0_GPCM_TACSE(0x6) | \
+ FTIM0_GPCM_TEADC(0x8) | \
+ FTIM0_GPCM_TEAHC(0x2))
+#define SYS_MRAM_FTIM1 (FTIM1_GPCM_TACO(0x2) | \
+ FTIM1_GPCM_TRAD(0xe))
+#define SYS_MRAM_FTIM2 (FTIM2_GPCM_TCS(0x2) | \
+ FTIM2_GPCM_TCH(0x2) | \
+ FTIM2_GPCM_TWP(0x8))
+#define SYS_MRAM_FTIM3 0x04000000
+#define CONFIG_SYS_CSPR4_EXT SYS_MRAM_CSPR_EXT
+#define CONFIG_SYS_CSPR4 SYS_MRAM_CSPR
+#define CONFIG_SYS_AMASK4 SYS_MRAM_AMASK
+#define CONFIG_SYS_CSOR4 SYS_MRAM_CSOR
+#define CONFIG_SYS_CS4_FTIM0 SYS_MRAM_FTIM0
+#define CONFIG_SYS_CS4_FTIM1 SYS_MRAM_FTIM1
+#define CONFIG_SYS_CS4_FTIM2 SYS_MRAM_FTIM2
+#define CONFIG_SYS_CS4_FTIM3 SYS_MRAM_FTIM3
+
+/* Application IFC CS6: BFTIC */
+#define SYS_BFTIC_BASE 0xd0000000
+#define SYS_BFTIC_BASE_PHYS (0xf00000000ull | SYS_BFTIC_BASE)
+#define SYS_BFTIC_CSPR_EXT (0x0f)
+#define SYS_BFTIC_CSPR (CSPR_PHYS_ADDR(SYS_BFTIC_BASE) | \
+ CSPR_PORT_SIZE_8 | /* Port size = 8 bit */\
+ CSPR_MSEL_GPCM | /* MSEL = GPCM */\
+ CSPR_V) /* valid */
+#define SYS_BFTIC_AMASK IFC_AMASK(64 * 1024) /* 64kB */
+#define SYS_BFTIC_CSOR CSOR_GPCM_TRHZ_40
+/* BFTIC Timing parameters for IFC CS6 */
+#define SYS_BFTIC_FTIM0 (FTIM0_GPCM_TACSE(0x6) | \
+ FTIM0_GPCM_TEADC(0x8) | \
+ FTIM0_GPCM_TEAHC(0x2))
+#define SYS_BFTIC_FTIM1 (FTIM1_GPCM_TACO(0x2) | \
+ FTIM1_GPCM_TRAD(0x12))
+#define SYS_BFTIC_FTIM2 (FTIM2_GPCM_TCS(0x3) | \
+ FTIM2_GPCM_TCH(0x1) | \
+ FTIM2_GPCM_TWP(0x12))
+#define SYS_BFTIC_FTIM3 0x04000000
+#define CONFIG_SYS_CSPR6_EXT SYS_BFTIC_CSPR_EXT
+#define CONFIG_SYS_CSPR6 SYS_BFTIC_CSPR
+#define CONFIG_SYS_AMASK6 SYS_BFTIC_AMASK
+#define CONFIG_SYS_CSOR6 SYS_BFTIC_CSOR
+#define CONFIG_SYS_CS6_FTIM0 SYS_BFTIC_FTIM0
+#define CONFIG_SYS_CS6_FTIM1 SYS_BFTIC_FTIM1
+#define CONFIG_SYS_CS6_FTIM2 SYS_BFTIC_FTIM2
+#define CONFIG_SYS_CS6_FTIM3 SYS_BFTIC_FTIM3
+
+/* Application IFC CS7 PAXE */
+#define CONFIG_SYS_PAXE_BASE 0xd8000000
+#define SYS_PAXE_BASE_PHYS (0xf00000000ull | CONFIG_SYS_PAXE_BASE)
+#define SYS_PAXE_CSPR_EXT (0x0f)
+#define SYS_PAXE_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_PAXE_BASE) | \
+ CSPR_PORT_SIZE_8 | /* Port size = 8 bit */\
+ CSPR_MSEL_GPCM | /* MSEL = GPCM */\
+ CSPR_V) /* valid */
+#define SYS_PAXE_AMASK IFC_AMASK(64 * 1024) /* 64kB */
+#define SYS_PAXE_CSOR CSOR_GPCM_TRHZ_40
+/* PAXE Timing parameters for IFC CS7 */
+#define SYS_PAXE_FTIM0 (FTIM0_GPCM_TACSE(0x6) | \
+ FTIM0_GPCM_TEADC(0x8) | \
+ FTIM0_GPCM_TEAHC(0x2))
+#define SYS_PAXE_FTIM1 (FTIM1_GPCM_TACO(0x2) | \
+ FTIM1_GPCM_TRAD(0x12))
+#define SYS_PAXE_FTIM2 (FTIM2_GPCM_TCS(0x3) | \
+ FTIM2_GPCM_TCH(0x1) | \
+ FTIM2_GPCM_TWP(0x12))
+#define SYS_PAXE_FTIM3 0x04000000
+#define CONFIG_SYS_CSPR7_EXT SYS_PAXE_CSPR_EXT
+#define CONFIG_SYS_CSPR7 SYS_PAXE_CSPR
+#define CONFIG_SYS_AMASK7 SYS_PAXE_AMASK
+#define CONFIG_SYS_CSOR7 SYS_PAXE_CSOR
+#define CONFIG_SYS_CS7_FTIM0 SYS_PAXE_FTIM0
+#define CONFIG_SYS_CS7_FTIM1 SYS_PAXE_FTIM1
+#define CONFIG_SYS_CS7_FTIM2 SYS_PAXE_FTIM2
+#define CONFIG_SYS_CS7_FTIM3 SYS_PAXE_FTIM3
+
+/* PRST */
+#define KM_BFTIC4_RST 0
+#define KM_DPAXE_RST 1
+#define KM_FEMT_RST 3
+#define KM_FOAM_RST 4
+#define KM_EFE_RST 5
+#define KM_ES_PHY_RST 6
+#define KM_XES_PHY_RST 7
+#define KM_ZL30158_RST 8
+#define KM_ZL30364_RST 9
+#define KM_BOBCAT_RST 10
+#define KM_ETHSW_DDR_RST 12
+#define KM_CFE_RST 13
+#define KM_PEXSW_RST 14
+#define KM_PEXSW_NT_RST 15
+
+/* QRIO GPIOs used for deblocking */
+#define KM_I2C_DEBLOCK_PORT QRIO_GPIO_A
+#define KM_I2C_DEBLOCK_SCL 20
+#define KM_I2C_DEBLOCK_SDA 21
+
+/* High Level Configuration Options */
+#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
+#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
+
+#define CONFIG_RESET_VECTOR_ADDRESS 0xebfffffc
+
+#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
+#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
+#define CONFIG_PCIE1 /* PCIE controller 1 */
+#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
+
+/* Environment in parallel NOR-Flash */
+#define CONFIG_ENV_TOTAL_SIZE 0x040000
+#define ENV_DEL_ADDR 0xebf00000 /*direct for newenv*/
+
+#define CONFIG_SYS_CLK_FREQ 66666666
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_SYS_CACHE_STASHING
+#define CONFIG_BACKSIDE_L2_CACHE
+#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
+#define CONFIG_BTB /* toggle branch predition */
+
+#define CONFIG_ENABLE_36BIT_PHYS
+
+/* POST memory regions test */
+#define CONFIG_POST CONFIG_SYS_POST_MEM_REGIONS
+
+/*
+ * Config the L3 Cache as L3 SRAM
+ */
+#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
+#define CONFIG_SYS_L3_SIZE 256 << 10
+
+#define CONFIG_SYS_DCSRBAR 0xf0000000
+#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
+
+/*
+ * DDR Setup
+ */
+#define CONFIG_VERY_BIG_RAM
+#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
+#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+#define CONFIG_DDR_CLK_FREQ 66666666
+
+#define CONFIG_DIMM_SLOTS_PER_CTLR 1
+#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
+
+#define CONFIG_DDR_SPD
+
+#define CONFIG_SYS_SPD_BUS_NUM 0
+#define SPD_EEPROM_ADDRESS 0x54
+#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
+
+#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
+#define CONFIG_SYS_I2C_EEPROM_ADDR CONFIG_SYS_IVM_EEPROM_ADR
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
+
+/******************************************************************************
+ * (PRAM usage)
+ * ... -------------------------------------------------------
+ * ... |ROOTFSSIZE | PNVRAM |PHRAM |RESERVED_PRAM | END_OF_RAM
+ * ... |<------------------- pram -------------------------->|
+ * ... -------------------------------------------------------
+ * @END_OF_RAM:
+ * @CONFIG_KM_RESERVED_PRAM: reserved pram for special purpose
+ * @CONFIG_KM_PHRAM: address for /var
+ * @CONFIG_KM_PNVRAM: address for PNVRAM (for the application)
+ * @CONFIG_KM_ROOTFSSIZE: address for rootfilesystem in RAM
+ */
+
+/* size of rootfs in RAM */
+#define CONFIG_KM_ROOTFSSIZE 0x0
+/* set the default PRAM value to at least PNVRAM + PHRAM when pram env variable
+ * is not valid yet, which is the case for when u-boot copies itself to RAM
+ */
+#define CONFIG_PRAM ((CONFIG_KM_PNVRAM + CONFIG_KM_PHRAM) >> 10)
+
+/*
+ * IFC Definitions
+ */
+/* NOR flash on IFC CS0 */
+#define CONFIG_SYS_FLASH_BASE 0xe8000000
+#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | \
+ CONFIG_SYS_FLASH_BASE)
+
+#define CONFIG_SYS_NOR_CSPR_EXT (0x0f)
+#define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) | \
+ CSPR_PORT_SIZE_16 | /* Port size = 16 bit */\
+ 0x00000010 | /* drive TE high */\
+ CSPR_MSEL_NOR | /* MSEL = NOR */\
+ CSPR_V) /* valid */
+#define CONFIG_SYS_NOR_AMASK IFC_AMASK(64 * 1024 * 1024) /* 64MB */
+#define CONFIG_SYS_NOR_CSOR (CSOR_NOR_AVD_TGL_PGM_EN | /* AVD toggle */\
+ CSOR_NOR_TRHZ_20 | \
+ CSOR_NOR_BCTLD)
+
+/* NOR Flash Timing Params */
+#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \
+ FTIM0_NOR_TEADC(0x7) | \
+ FTIM0_NOR_TEAHC(0x1))
+#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1) | \
+ FTIM1_NOR_TRAD_NOR(0x21) | \
+ FTIM1_NOR_TSEQRAD_NOR(0x21))
+#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCH(0x1) | \
+ FTIM2_NOR_TCS(0x1) | \
+ FTIM2_NOR_TWP(0xb) | \
+ FTIM2_NOR_TWPH(0x6))
+#define CONFIG_SYS_NOR_FTIM3 0x0
+
+#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT
+#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR
+#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
+
+/* More NOR Flash params */
+#define CONFIG_SYS_FLASH_QUIET_TEST
+
+#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
+
+/* NAND Flash on IFC CS1*/
+#define CONFIG_NAND_FSL_IFC
+#define CONFIG_SYS_NAND_BASE 0xfa000000
+#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
+
+#define CONFIG_SYS_NAND_CSPR_EXT (0x0f)
+#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE) | \
+ CSPR_PORT_SIZE_8 | /* Port Size = 8 bit */\
+ 0x00000010 | /* drive TE high */\
+ CSPR_MSEL_NAND | /* MSEL = NAND */\
+ CSPR_V) /* valid */
+#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) /* 64kB */
+
+#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN | /* ECC encoder on */ \
+ CSOR_NAND_ECC_DEC_EN | /* ECC decoder on */ \
+ CSOR_NAND_ECC_MODE_4 | /* 4-bit ECC */ \
+ CSOR_NAND_RAL_3 | /* RAL = 3Bytes */ \
+ CSOR_NAND_PGS_2K | /* Page size = 2K */ \
+ CSOR_NAND_SPRZ_128 | /* Spare size = 128 */ \
+ CSOR_NAND_PB(64) | /* 64 Pages/Block */ \
+ CSOR_NAND_TRHZ_40 | /**/ \
+ CSOR_NAND_BCTLD) /**/
+
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+/* ONFI NAND Flash mode0 Timing Params */
+#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x3) | \
+ FTIM0_NAND_TWP(0x8) | \
+ FTIM0_NAND_TWCHT(0x3) | \
+ FTIM0_NAND_TWH(0x5))
+#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x1e) | \
+ FTIM1_NAND_TWBE(0x1e) | \
+ FTIM1_NAND_TRR(0x6) | \
+ FTIM1_NAND_TRP(0x8))
+#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x9) | \
+ FTIM2_NAND_TREH(0x5) | \
+ FTIM2_NAND_TWHRE(0x3c))
+#define CONFIG_SYS_NAND_FTIM3 (FTIM3_NAND_TWW(0x1e))
+
+#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
+
+/* More NAND Flash Params */
+#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+
+/* QRIO on IFC CS2 */
+#define CONFIG_SYS_QRIO_BASE 0xfb000000
+#define CONFIG_SYS_QRIO_BASE_PHYS (0xf00000000ull | CONFIG_SYS_QRIO_BASE)
+#define SYS_QRIO_CSPR_EXT (0x0f)
+#define SYS_QRIO_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_QRIO_BASE) | \
+ CSPR_PORT_SIZE_8 | /* Port size = 8 bit */\
+ 0x00000010 | /* drive TE high */\
+ CSPR_MSEL_GPCM | /* MSEL = GPCM */\
+ CSPR_V) /* valid */
+#define SYS_QRIO_AMASK IFC_AMASK(64 * 1024) /* 64kB */
+#define SYS_QRIO_CSOR (CSOR_GPCM_TRHZ_20 |\
+ CSOR_GPCM_BCTLD)
+/* QRIO Timing parameters for IFC CS2 */
+#define SYS_QRIO_FTIM0 (FTIM0_GPCM_TACSE(0x2) | \
+ FTIM0_GPCM_TEADC(0x8) | \
+ FTIM0_GPCM_TEAHC(0x2))
+#define SYS_QRIO_FTIM1 (FTIM1_GPCM_TACO(0x2) | \
+ FTIM1_GPCM_TRAD(0x6))
+#define SYS_QRIO_FTIM2 (FTIM2_GPCM_TCS(0x1) | \
+ FTIM2_GPCM_TCH(0x1) | \
+ FTIM2_GPCM_TWP(0x7))
+#define SYS_QRIO_FTIM3 0x04000000
+#define CONFIG_SYS_CSPR2_EXT SYS_QRIO_CSPR_EXT
+#define CONFIG_SYS_CSPR2 SYS_QRIO_CSPR
+#define CONFIG_SYS_AMASK2 SYS_QRIO_AMASK
+#define CONFIG_SYS_CSOR2 SYS_QRIO_CSOR
+#define CONFIG_SYS_CS2_FTIM0 SYS_QRIO_FTIM0
+#define CONFIG_SYS_CS2_FTIM1 SYS_QRIO_FTIM1
+#define CONFIG_SYS_CS2_FTIM2 SYS_QRIO_FTIM2
+#define CONFIG_SYS_CS2_FTIM3 SYS_QRIO_FTIM3
+
+#define CONFIG_MISC_INIT_F
+#define CONFIG_HWCONFIG
+
+/* define to use L1 as initial stack */
+#define CONFIG_SYS_INIT_RAM_LOCK
+#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
+/* The assembler doesn't like typecast */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
+ ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
+
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
+#define CONFIG_SYS_MONITOR_LEN 0xc0000 /* 768k */
+
+#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
+
+/*
+ * Serial Port - controlled on board with jumper J8
+ * open - index 2
+ * shorted - index 1
+ * Retain non-DM serial port for debug purposes.
+ */
+#if !defined(CONFIG_DM_SERIAL)
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE 1
+#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0) / 2)
+#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x11C500)
+#endif
+
+#ifndef __ASSEMBLY__
+void set_sda(int state);
+void set_scl(int state);
+int get_sda(void);
+int get_scl(void);
+#endif
+
+/*
+ * General PCI
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+/* controller 1 */
+#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
+#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
+#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
+
+#define CONFIG_SYS_BMAN_NUM_PORTALS 10
+#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
+#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
+#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
+#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
+#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
+#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
+ CONFIG_SYS_BMAN_CENA_SIZE)
+#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
+#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
+#define CONFIG_SYS_QMAN_NUM_PORTALS 10
+#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
+#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
+#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
+#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
+#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
+#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
+ CONFIG_SYS_QMAN_CENA_SIZE)
+#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
+#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
+
+#define CONFIG_SYS_DPAA_FMAN
+#define CONFIG_SYS_DPAA_PME
+
+/* Default address of microcode for the Linux Fman driver */
+#define CONFIG_SYS_FMAN_FW_ADDR 0xE8020000
+#define CONFIG_SYS_QE_FW_ADDR 0xE8040000
+#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
+#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
+
+/* Qman / Bman */
+/* RGMII (FM1@DTESC5) is local managemant interface */
+#define CONFIG_SYS_RGMII2_PHY_ADDR 0x11
+#define CONFIG_ETHPRIME "fm1-mac5"
+
+/*
+ * Hardware Watchdog
+ */
+#define CONFIG_WATCHDOG_PRESC 34 /* wdog prescaler 2^(64-34) ~10min */
+#define CONFIG_WATCHDOG_RC WRC_CHIP /* reset chip on watchdog event */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 64 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
+#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
+
+/*
+ * Environment Configuration
+ */
+#ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */
+#define CONFIG_KM_DEF_ENV
+#endif
+
+#define __USB_PHY_TYPE utmi
+
+#define CONFIG_KM_DEF_ENV_CPU \
+ "boot=bootm ${load_addr_r} - ${fdt_addr_r}\0" \
+ "cramfsloadfdt=" \
+ "cramfsload ${fdt_addr_r} " \
+ "fdt_0x${IVM_BoardId}_0x${IVM_HWKey}.dtb\0" \
+ "u-boot=" CONFIG_HOSTNAME "/u-boot.bin\0" \
+ "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \
+ " +${filesize} && " \
+ "erase " __stringify(CONFIG_SYS_MONITOR_BASE) \
+ " +${filesize} && " \
+ "cp.b ${load_addr_r} " \
+ __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize} && " \
+ "protect on " __stringify(CONFIG_SYS_MONITOR_BASE) \
+ " +${filesize}\0" \
+ "update-nor=protect off " __stringify(CONFIG_SYS_FLASH_BASE) \
+ " +${filesize} && " \
+ "erase " __stringify(CONFIG_SYS_FLASH_BASE) \
+ " +${filesize} && " \
+ "cp.b ${load_addr_r} " \
+ __stringify(CONFIG_SYS_FLASH_BASE) " ${filesize} && " \
+ "protect on " __stringify(CONFIG_SYS_MONITOR_BASE) \
+ " +" __stringify(CONFIG_SYS_MONITOR_LEN) "\0" \
+ "set_fdthigh=true\0" \
+ "checkfdt=true\0" \
+ "fpgacfg=true\0" \
+ ""
+
+#define CONFIG_HW_ENV_SETTINGS \
+ "hwconfig=fsl_ddr:ctlr_intlv=cacheline\0" \
+ "usb_phy_type=" __stringify(__USB_PHY_TYPE) "\0" \
+ "usb_dr_mode=host\0"
+
+#define CONFIG_KM_NEW_ENV \
+ "newenv=protect off " __stringify(ENV_DEL_ADDR) \
+ " +" __stringify(CONFIG_ENV_TOTAL_SIZE) " && " \
+ "erase " __stringify(ENV_DEL_ADDR) \
+ " +" __stringify(CONFIG_ENV_TOTAL_SIZE) " && " \
+ "protect on " __stringify(ENV_DEL_ADDR) \
+ " +" __stringify(CONFIG_ENV_TOTAL_SIZE) "\0"
+
+/* ppc_82xx is the equivalent to ppc_6xx, the generic ppc toolchain */
+#ifndef CONFIG_KM_DEF_ARCH
+#define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0"
+#endif
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ CONFIG_KM_DEF_ENV \
+ CONFIG_KM_DEF_ARCH \
+ CONFIG_KM_NEW_ENV \
+ CONFIG_HW_ENV_SETTINGS \
+ "EEprom_ivm=pca9547:70:9\0" \
+ ""
+
+#endif /* __KMCENT2_H */
diff --git a/include/configs/kmp204x.h b/include/configs/kmp204x.h
index d1eb7b574b4..90e3702bd80 100644
--- a/include/configs/kmp204x.h
+++ b/include/configs/kmp204x.h
@@ -237,12 +237,6 @@ unsigned long get_board_sys_clk(unsigned long dummy);
{0, {{I2C_MUX_PCA9547, 0x70, 1 } } }, \
{0, {{I2C_MUX_PCA9547, 0x70, 2 } } }, \
}
-#ifndef __ASSEMBLY__
-void set_sda(int state);
-void set_scl(int state);
-int get_sda(void);
-int get_scl(void);
-#endif
#define CONFIG_KM_IVM_BUS 1 /* I2C1 (Mux-Port 1)*/
diff --git a/include/configs/kontron_sl28.h b/include/configs/kontron_sl28.h
index 442fb58b979..5d818a708d0 100644
--- a/include/configs/kontron_sl28.h
+++ b/include/configs/kontron_sl28.h
@@ -93,6 +93,7 @@
func(MMC, mmc, 1) \
func(NVME, nvme, 0) \
func(USB, usb, 0) \
+ func(SCSI, scsi, 0) \
func(DHCP, dhcp, 0) \
func(PXE, pxe, 0)
#include <config_distro_bootcmd.h>
diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h
index 6cf6a31d767..f6b5d47c255 100644
--- a/include/configs/ls1012a_common.h
+++ b/include/configs/ls1012a_common.h
@@ -62,6 +62,13 @@
#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0
#endif
+/* GPIO */
+#ifdef CONFIG_DM_GPIO
+#ifndef CONFIG_MPC8XXX_GPIO
+#define CONFIG_MPC8XXX_GPIO
+#endif
+#endif
+
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK (get_serial_clock())
diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h
index eb6f1c1e5be..b4c70333def 100644
--- a/include/configs/ls1021aqds.h
+++ b/include/configs/ls1021aqds.h
@@ -341,6 +341,13 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
+/* GPIO */
+#ifdef CONFIG_DM_GPIO
+#ifndef CONFIG_MPC8XXX_GPIO
+#define CONFIG_MPC8XXX_GPIO
+#endif
+#endif
+
/* EEPROM */
#define CONFIG_ID_EEPROM
#define CONFIG_SYS_I2C_EEPROM_NXID
diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h
index 3e85bb3850b..dfb56437d97 100644
--- a/include/configs/ls1021atwr.h
+++ b/include/configs/ls1021atwr.h
@@ -219,6 +219,13 @@
#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
+/* GPIO */
+#ifdef CONFIG_DM_GPIO
+#ifndef CONFIG_MPC8XXX_GPIO
+#define CONFIG_MPC8XXX_GPIO
+#endif
+#endif
+
/* EEPROM */
#define CONFIG_ID_EEPROM
#define CONFIG_SYS_I2C_EEPROM_NXID
diff --git a/include/configs/ls1028a_common.h b/include/configs/ls1028a_common.h
index 8345cd7acfc..1c4af7d1760 100644
--- a/include/configs/ls1028a_common.h
+++ b/include/configs/ls1028a_common.h
@@ -36,6 +36,13 @@
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024)
+/* GPIO */
+#ifdef CONFIG_DM_GPIO
+#ifndef CONFIG_MPC8XXX_GPIO
+#define CONFIG_MPC8XXX_GPIO
+#endif
+#endif
+
/* I2C */
#ifndef CONFIG_DM_I2C
#define CONFIG_SYS_I2C
diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h
index 6584e391993..4e3e1a946b6 100644
--- a/include/configs/ls1043a_common.h
+++ b/include/configs/ls1043a_common.h
@@ -119,6 +119,13 @@
#endif
+/* GPIO */
+#ifdef CONFIG_DM_GPIO
+#ifndef CONFIG_MPC8XXX_GPIO
+#define CONFIG_MPC8XXX_GPIO
+#endif
+#endif
+
/* IFC */
#ifndef SPL_NO_IFC
#if defined(CONFIG_TFABOOT) || \
diff --git a/include/configs/ls1046a_common.h b/include/configs/ls1046a_common.h
index d44a7f105e6..32658cf641f 100644
--- a/include/configs/ls1046a_common.h
+++ b/include/configs/ls1046a_common.h
@@ -126,6 +126,13 @@
#define CONFIG_SYS_MONITOR_LEN 0xa0000
#endif
+/* GPIO */
+#ifdef CONFIG_DM_GPIO
+#ifndef CONFIG_MPC8XXX_GPIO
+#define CONFIG_MPC8XXX_GPIO
+#endif
+#endif
+
/* I2C */
#ifndef CONFIG_DM_I2C
#define CONFIG_SYS_I2C
diff --git a/include/configs/ls1088a_common.h b/include/configs/ls1088a_common.h
index f9e349871c8..b9a956b90b5 100644
--- a/include/configs/ls1088a_common.h
+++ b/include/configs/ls1088a_common.h
@@ -53,6 +53,13 @@
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024)
+/* GPIO */
+#ifdef CONFIG_DM_GPIO
+#ifndef CONFIG_MPC8XXX_GPIO
+#define CONFIG_MPC8XXX_GPIO
+#endif
+#endif
+
/* I2C */
#ifndef CONFIG_DM_I2C
#define CONFIG_SYS_I2C
diff --git a/include/configs/ls1088aqds.h b/include/configs/ls1088aqds.h
index b92ec14c691..1626e65056b 100644
--- a/include/configs/ls1088aqds.h
+++ b/include/configs/ls1088aqds.h
@@ -371,10 +371,18 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_ESDHC_DETECT_QUIRK ((readb(QIXIS_BASE + QIXIS_STAT_PRES1) & \
QIXIS_SDID_MASK) != QIXIS_ESDHC_NO_ADAPTER)
+#define COMMON_ENV \
+ "kernelheader_addr_r=0x80200000\0" \
+ "fdtheader_addr_r=0x80100000\0" \
+ "kernel_addr_r=0x81000000\0" \
+ "fdt_addr_r=0x90000000\0" \
+ "load_addr=0xa0000000\0"
+
/* Initial environment variables */
#ifdef CONFIG_NXP_ESBC
#undef CONFIG_EXTRA_ENV_SETTINGS
#define CONFIG_EXTRA_ENV_SETTINGS \
+ COMMON_ENV \
"hwconfig=fsl_ddr:bank_intlv=auto\0" \
"loadaddr=0x90100000\0" \
"kernel_addr=0x100000\0" \
@@ -406,6 +414,7 @@ unsigned long get_board_ddr_clk(void);
#undef CONFIG_EXTRA_ENV_SETTINGS
#define CONFIG_EXTRA_ENV_SETTINGS \
+ COMMON_ENV \
"hwconfig=fsl_ddr:bank_intlv=auto\0" \
"loadaddr=0x90100000\0" \
"kernel_addr=0x100000\0" \
@@ -467,6 +476,7 @@ unsigned long get_board_ddr_clk(void);
#if defined(CONFIG_QSPI_BOOT)
#undef CONFIG_EXTRA_ENV_SETTINGS
#define CONFIG_EXTRA_ENV_SETTINGS \
+ COMMON_ENV \
"hwconfig=fsl_ddr:bank_intlv=auto\0" \
"loadaddr=0x90100000\0" \
"kernel_addr=0x100000\0" \
@@ -484,6 +494,7 @@ unsigned long get_board_ddr_clk(void);
#elif defined(CONFIG_SD_BOOT)
#undef CONFIG_EXTRA_ENV_SETTINGS
#define CONFIG_EXTRA_ENV_SETTINGS \
+ COMMON_ENV \
"hwconfig=fsl_ddr:bank_intlv=auto\0" \
"loadaddr=0x90100000\0" \
"kernel_addr=0x800\0" \
@@ -501,6 +512,7 @@ unsigned long get_board_ddr_clk(void);
#else /* NOR BOOT */
#undef CONFIG_EXTRA_ENV_SETTINGS
#define CONFIG_EXTRA_ENV_SETTINGS \
+ COMMON_ENV \
"hwconfig=fsl_ddr:bank_intlv=auto\0" \
"loadaddr=0x90100000\0" \
"kernel_addr=0x100000\0" \
diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h
index 444bb8c3b5c..1042555a8cf 100644
--- a/include/configs/ls2080a_common.h
+++ b/include/configs/ls2080a_common.h
@@ -66,6 +66,13 @@
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024)
+/* GPIO */
+#ifdef CONFIG_DM_GPIO
+#ifndef CONFIG_MPC8XXX_GPIO
+#define CONFIG_MPC8XXX_GPIO
+#endif
+#endif
+
/* I2C */
#ifndef CONFIG_DM_I2C
#define CONFIG_SYS_I2C
diff --git a/include/configs/lx2160a_common.h b/include/configs/lx2160a_common.h
index 4bd0ddbdad2..466484c1997 100644
--- a/include/configs/lx2160a_common.h
+++ b/include/configs/lx2160a_common.h
@@ -160,6 +160,13 @@
#define NXP_FSPI_FLASH_NUM 1
#endif
+/* GPIO */
+#ifdef CONFIG_DM_GPIO
+#ifndef CONFIG_MPC8XXX_GPIO
+#define CONFIG_MPC8XXX_GPIO
+#endif
+#endif
+
#ifndef __ASSEMBLY__
unsigned long get_board_sys_clk(void);
unsigned long get_board_ddr_clk(void);
diff --git a/include/spi-mem.h b/include/spi-mem.h
index ca0f55c8fdf..8be3e2bf6b5 100644
--- a/include/spi-mem.h
+++ b/include/spi-mem.h
@@ -240,6 +240,9 @@ bool spi_mem_supports_op(struct spi_slave *slave, const struct spi_mem_op *op);
int spi_mem_exec_op(struct spi_slave *slave, const struct spi_mem_op *op);
+bool spi_mem_default_supports_op(struct spi_slave *mem,
+ const struct spi_mem_op *op);
+
#ifndef __UBOOT__
int spi_mem_driver_register_with_owner(struct spi_mem_driver *drv,
struct module *owner);
generated by cgit v1.2.3 (git 2.0.4) at 2025-08-03 12:18:29 +0000