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2022-04-06binman: Correct Chromium OS entry typesSimon Glass
The conversion to bintools broke the invocation of the utility, since the arguments are not correct. Fix it. Signed-off-by: Simon Glass <sjg@chromium.org>
2022-04-06Merge https://source.denx.de/u-boot/custodians/u-boot-riscvTom Rini
2022-04-06Merge branch '2022-04-06-assorted-updates'Tom Rini
- Add DM_PMIC support to TPS65217 and migrate some platforms to it. - mkimage verification fixes - DM rST fix, add missing flag when linking u-boot-elf.o
2022-04-06dm: fix function documentation in include/dm/ofnode.hHeinrich Schuchardt
We use Sphinx style comments to describe functions. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2022-04-06tools: mkimage: Call verify_header after writing image to diskPali Rohár
If image backend provides verify_header callback then call it after writing image to disk. This ensures that written image is correct. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-04-06tools: mkimage: No need to verify_header for header_v2Yi Liu
rockchip header_v2 do not have a spl_hdr, so remove the verify. Signed-off-by: Yi Liu <liuyi@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2022-04-06Makefile: add endian link flag to u-boot-elf.oDu Huanpeng
fix compile error when using a little-endian to build with configs: sfr_nb4-ser_ram_defconfig comtrend_wap5813n_ram_defconfig comtrend_ar5387un_ram_defconfig comtrend_ct5361_ram_defconfig comtrend_vr3032u_ram_defconfig comtrend_ar5315u_ram_defconfig huawei_hg556a_ram_defconfig netgear_dgnd3700v2_ram_defconfig Signed-off-by: Du Huanpeng <dhu@hodcarrier.org>
2022-04-06riscv: alloc space exhaustedHeinrich Schuchardt
When trying to run qemu-riscv64_smode_defconfig with 32 harts booting fails. The debug UART shows a message alloc space exhausted 32 is the current maximum number of harts for machine virt in QEMU 7.0. Raise the default for SYS_MALLOC_F_LEN to 16 KiB. Move the setting to /Kconfig where we define SYS_MALLOC_F_LEN for other architectures too. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
2022-04-06riscv: enable CONFIG_CMD_SBI for QEMU boardsHeinrich Schuchardt
Let CONFIG_TARGET_QEMU_VIRT imply CONFIG_CMD_SBI. The sbi command provides detailed information about the SBI. It is useful to test the discovery of extensions. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2022-04-06cmd/sbi: add missing SBI informationHeinrich Schuchardt
Let the sbi command display: * machine vendor ID * machine architecture ID * machine implementation ID With this patch the output for the HiFive Unmatched looks like => sbi SBI 0.3 OpenSBI 0.9 Machine: Vendor ID 489 Architecture ID 8000000000000007 Implementation ID 20181004 Extensions: sbi_set_timer sbi_console_putchar sbi_console_getchar sbi_clear_ipi sbi_send_ipi sbi_remote_fence_i sbi_remote_sfence_vma sbi_remote_sfence_vma_asid sbi_shutdown SBI Base Functionality Timer Extension IPI Extension RFENCE Extension Hart State Management Extension System Reset Extension Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Sean Anderson <seanga2@gmail.com>
2022-04-06riscv: provide missing base extension functionsHeinrich Schuchardt
Provide library functions to read: * machine vendor ID * machine architecture ID * machine implementation ID Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Sean Anderson <seanga2@gmail.com>
2022-04-06cmd: sbi: add Performance Monitoring Unit ExtensionHeinrich Schuchardt
Version 1.0-rc3 of the RISC-V Supervisor Binary Interface Specification has added the Performance Monitoring Unit Extension. The sbi command should be able to detect it. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2022-04-05power: pmic: Provide DM_PMIC support for tps65217 driverLukasz Majewski
The tps65217 PMIC driver is used with am335x SoC based designs. It is used in the SPL (MLO) as well, so the DM conversion only is for u-boot proper. This driver only allows simple reading/writing/dumping of the content of its registers and requires the DM_I2C for proper operation. Signed-off-by: Lukasz Majewski <lukma@denx.de> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2022-04-05power: Rename CONFIG_POWER_TPS65217 with CONFIG_PMIC_TPS65217Lukasz Majewski
Up till now the CONFIG_POWER_TPS65217 has been defined in several header files for am335x SoC. This patch renames it to CONFIG_PMIC_TPS65217, which better reflects the role of this IC circuit. Moreover, new CONFIG_PMIC_TPS65217 has been introduced in Kconfig to be used with boards, which both support DM_PMIC and DM_I2C. Signed-off-by: Lukasz Majewski <lukma@denx.de> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> [trini: Migrate all other platforms as well] Signed-off-by: Tom Rini <trini@konsulko.com>
2022-04-05Merge branch '2022-04-04-platform-updates'Tom Rini
- Updates for exynos78x0 and TI K3 platforms
2022-04-05Merge tag 'xilinx-for-v2022.07-rc1-v2' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-microblaze Xilinx changes for v2022.07-rc1 v2 xilinx: - Allow booting bigger kernels till 100MB zynqmp: - DT updates (reset IDs) - Remove unneeded low level uart initialization from psu_init* - Enable PWM features - Add support for 1EG device serial_zynq: - Change fifo behavior in DEBUG mode zynq_sdhci: - Fix BASECLK setting calculation clk_zynqmp: - Add support for showing video clock gpio: - Update slg driver to handle DT flags net: - Update ethernet_id code to support also DM_ETH_PHY - Add support for DM_ETH_PHY in gem driver - Enable dynamic mode for SGMII config in gem driver pwm: - Add driver for cadence PWM versal: - Add support for reserved memory firmware: - Handle PD enabling for SPL - Add support for IOUSLCR SGMII configurations include: - Sync phy.h with Linux - Update xilinx power domain dt binding headers
2022-04-05net: zynq_gem: Add SGMII dynamic config supportT Karthik Reddy
Add support for SGMII dynamic configuration which will takes care of configuring SGMII in the GEM secure (GEM_CLK_CTRL) configuration register. Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/a8915186e44015959978d080a31de652f544cd4a.1648631275.git.michal.simek@xilinx.com
2022-04-05firmware: firmware-zynqmp: Add zynqmp_pm_set_gem_config apiT Karthik Reddy
Add zynqmp_pm_set_gem_config() api to configure GEM secure registers. Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/f69e32355c6a6be7d2780663353c52757530207d.1648631275.git.michal.simek@xilinx.com
2022-04-05gpio: slg7xl45106: Update gpio desc flags from DTT Karthik Reddy
In current slg7xl45106 gpio driver xlate() function we are not updating gpio flags from DT. Read the given flag from DT and update the gpio desc flags variable with required gpio direction state. Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/a8d7b4799337bd99f61ace509889f02b192a9414.1648631275.git.michal.simek@xilinx.com
2022-04-05net: zynq_gem: Move ethernet info print statementT Karthik Reddy
As we are not reading the PHY address in case of CONFIG_ETH_PHY in plat function, phy address always prints as -1. So move the ethernet info print statement to probe function, to display proper phy address. Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/f6efc6719d767b1bebe65987c22c6d52329f4225.1648631275.git.michal.simek@xilinx.com
2022-04-05net: phy: Avoid phy gpio reset sequence if DM_ETH_PHY is enabledT Karthik Reddy
If DM_ETH_PHY config is enabled PHY gpio reset is taken care by the eth-phy-uclass driver, so use the PHY gpio reset functionality from ethernet_id file when this config is disabled to reset the PHY. Use debug() print instead of dev_err() to avoid warning incase if phy-id compatible string is not present. Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/4d0fd3f9f886c1d943776025e5efb5438b0eb389.1648631275.git.michal.simek@xilinx.com
2022-04-05net: zynq_gem: Use shared MDIO bus support for zynqmpMichal Simek
CONFIG_ETH_PHY enables support to utilize generic ethernet phy framework. Though if ethernet PHY node is in other ethernet node, it will use shared MDIO to access the PHY of other ethernet. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Link: https://lore.kernel.org/r/337b1a38ba36cde1951739af62fb3d2736d97f53.1648631275.git.michal.simek@xilinx.com
2022-04-05dt-bindings: xilinx: Add missing ids for PDMichal Simek
There are some new power domain IDs which are used in Linux kernel that's why add them here too. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/e6092e1d3766c0ac11bf620820739c93ab677a85.1648626981.git.michal.simek@xilinx.com
2022-04-05arm64: zynqmp: Record ID code for XCZU1EG deviceMichal Simek
Add ID code for 1eg device. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/5b6c9f6a25bba076f304bc4699f6f676a929a683.1648619516.git.michal.simek@xilinx.com
2022-04-05net: phy: Fix rgmii-id phy reset timeout issueT Karthik Reddy
While creating a phy device using phy_device_create(), we need to provide a valid phyaddr instead of 0 causing phy address being registered as 0 with mdio bus and shows mdio phy list as below ZynqMP> mdio list eth0: 0 - TI DP83867 <--> ethernet@ff0b0000 eth1: 0 - TI DP83867 <--> ethernet@ff0c0000 Also PHY soft reset is being requested on 0 instead of valid address causing "PHY reset timed out" error. So add phyaddr argument to phy_connect_phy_id() and to its prototype to create phy device with valid phyaddress. Fixes: a744a284e354 ("net: phy: Add support for ethernet-phy-id with gpio reset") Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Link: https://lore.kernel.org/r/fe35fddb9faa5af577ffdfabaec6879c935a30f8.1648562755.git.michal.simek@xilinx.com
2022-04-05clk: zynqmp: Add support for for DP audio/video clocksMichal Simek
Add support for getting rate for DP audio and video clocks. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/8792efe1fd9715f7c8a2e1e24f0454fb5b25d833.1648552434.git.michal.simek@xilinx.com
2022-04-05Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sunxiTom Rini
A big part is the DM pinctrl driver, which allows us to get rid of quite some custom pinmux code and make the whole port much more robust. Many thanks to Samuel for that nice contribution! There are some more or less cosmetic warnings about missing clocks right now, I will send the trivial fixes for that later. Another big chunk is the mkimage upgrade, which adds RISC-V and TOC0 (secure images) support. Both features are unused at the moment, but I have an always-secure board that will use that once the DT lands in the kernel. On top of those big things we have some smaller fixes, improving the I2C DM support, fixing some H6/H616 early clock setup and improving the eMMC boot partition support. The gitlab CI completed successfully, including the build test for all 161 sunxi boards. I also boot tested on a A64, A20, H3, H6, and F1C100 board. USB, SD card, eMMC, and Ethernet all work there (where applicable).
2022-04-05xilinx: Increase max size of image from 60 to 100MBMichal Simek
Recently big Linux kernels can have more then 60MB that's why increase this limit to also cover these large kernels. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/f52f7c8ea419d69b248ba1460a96d1635194e128.1648551279.git.michal.simek@xilinx.com
2022-04-05sunxi: defconfig: enable eMMC boot partition supportAndre Przywara
Now that the SPL can safely detect whether it was loaded from an eMMC boot partition or the normal user data partition, let's enable this feature on some boards that feature eMMC storage. That covers the boards where I could test this on, and allows the same build to be written to an SD card, eMMC user partition, eMMC boot partition, or into SPI NOR flash. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-04-05sunxi: eMMC: Improve automatic boot source detectionAndre Przywara
When the Allwinner BROM loads the SPL from an eMMC boot partition, it sets the boot source byte to the same value as when booting from the user data partition. This prevents us from determining the boot source to load U-Boot proper from the proper partition for sure. The generic SPL MMC code already looks at the enabled boot partition number, to load U-Boot proper from the same partition, but this fails if there is nothing bootable in this partition, as the BROM then silently falls back to the user data partition, which the SPL misses. To learn about the actual boot source anyway, we repeat the algorithm the BROM used to select the boot partition in the first place: - Test EXT_CSD[179] to check if an eMMC boot partition is enabled. - Test EXT_CSD[177] to check for valid MMC interface settings. - Check if BOOT_ACK is enabled. - Check the beginning of the first sector for a valid eGON signature. - Load the whole SPL. - Recalculate the checksum to verify the SPL is valid. If one of those steps fails, we bail out and continue loading from the user data partition. Otherwise we load from the selected boot partition. Since the boot source is needed twice in the boot process, we cache the result of this test to avoid doing this costly test multiple times. This allows the very same image file to be put onto an SD card, into the eMMC user data partition or into the eMMC boot partition, and safely loads the whole of U-Boot from there. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-04-04ram: k3-am654: Make VTT regulator optionalChristian Gmeiner
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2022-04-04ram: k3-am654: Write all configuration valuesDominic Rath
Makes it possible to use 16-bit DDR memory. Signed-off-by: Dominic Rath <rath@ibv-augsburg.net> Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2022-04-04configs: am64x_evm_r5: Add CONFIG_NR_DRAM_BANKS as done in a53 defconfigDave Gerlach
Add CONFIG_NR_DRAM_BANKS from am64x_evm_a53_defconfig as this is needed to calculate the size of DDR that is available. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2022-04-04arm: dts: k3-am64-ddr: Add ss_cfg reg entryDave Gerlach
Add 'ss_cfg' memory region for memorycontroller node which is required to enable ECC. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2022-04-04board: ti: am64x: Account for DDR size fixups if ECC is enabledDave Gerlach
Call into k3-ddrss driver to fixup device tree and resize the available amount of DDR if ECC is enabled. A second fixup is required from A53 SPL to take the fixup as done from R5 SPL and apply it to DT passed to A53 U-boot, which in turn passes this to the OS. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2022-04-04ram: k3-ddrss: Introduce ECC Functionality for full memory spaceDave Gerlach
Introduce ECC Functionality for full memory space as implemented in the DDRSS. The following is done to accomplish this: * Introduce a memory region "ss" to allow dt to provide DDRSS region, which is not the same as "ctl" which is the controller region. * Introduce a "ti,ecc-enable" flag which allows a memorycontroller instance to enable ecc. * Introduce functionality to properly program the DDRSS registers to enable ECC for the full DDR memory space if enabled with above flag. * Expose a k3_ddrss_ddr_fdt_fixup call to allow fixup of fdt blob to account from DDR memory that must be reserved for ECC operation. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2022-04-04ram: k3-ddrss: Rename ddrss_ss_regs to ddrss_ctl_regsDave Gerlach
The current address being read from dt actually represents the ddrss_ctl memory region, while ddrss_ss region is something else. Introduce ddrss_ctl_regs and use it to free up ddrss_ss_regs for its proper purpose later so that we can avoid confusion. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2022-04-04dt-bindings: memory-controller: Add information about ECC bindingsDave Gerlach
Add DT binding documentation for enabling ECC in the DDR sub system present on AM64 device. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2022-04-04board: ti: am64x: Use fdt functions for ram and bank initDave Gerlach
Use the appropriate fdtdec_setup_mem_size_base and fdtdec_setup_bank_size calls in dram_init and dram_bank_init to pull these values from DT, where they are already available, instead of hardcoding them. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2022-04-04arm: dts: k3-am642-r5-evm: Mark memory with u-boot, dm-splDave Gerlach
Mark the memory node with u-boot,dm-spl so we can use it from early SPL. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2022-04-04ARM: dts: k3-am642: Correct timer frequencyVignesh Raghavendra
Timer0 runs at 200MHz,and the clock-frequency defined in DT is incorrect. Fix it. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-By: Nishanth Menon <nm@ti.com>
2022-04-04configs: am64x_evm_a53_defconfig: Switch to per-cpu timer as tick providerVignesh Raghavendra
On arm64 systems, recommendation is to use per-cpu timer for time keeping. Currently AM64 ends up using DM timer as tick timer as driver is enabled in the config. Drop OMAP DM Timer related configs, this will switch to using armv8 per-cpu timer as tick timer for A53 SPL/U-Boot. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-By: Nishanth Menon <nm@ti.com>
2022-04-04configs: am64x_evm_r5_defconfig: Add support for ESMHari Nagalla
Enable ESM driver for AM64x R5 SPL/u-boot builds. Signed-off-by: Hari Nagalla <hnagalla@ti.com> Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2022-04-04arch: arm: mach-k3: am642_init: Probe ESM nodesHari Nagalla
On AM64x devices, it is possible to route Main ESM0 error events to MCU ESM. MCU ESM high error output can trigger the reset logic to reset the device. So, for these devices we expect two ESM device nodes in the device tree, one for Main ESM and the another MCU ESM in the device tree. When these ESM device nodes are properly configired it is possible to route the Main RTI0 WWDT output to the MCU ESM high output through Main ESM and trigger a device reset when CTRLMMR_MCU_RST_CTRL:MCU_ESM_ERROR_RESET_EN_Z is set to '0'. On K3 AM64x devices, the R5 SPL u-boot handles the ESM device node configurations. Signed-off-by: Hari Nagalla <hnagalla@ti.com> Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2022-04-04arm: dts: k3-am64: Add support for ESM device nodesHari Nagalla
Enable access to ESM0 configuration space and add Main ESM0 and MCU ESM nodes to the AM64 device tree. Signed-off-by: Hari Nagalla <hnagalla@ti.com> Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2022-04-04misc: k3_esm: Add functionality to set and route error events within K3SoCHari Nagalla
Add functionality to enable, set priority to the input events and to route to MCU ESM. On AM64x/AM62x devices, it is possible to route Main ESM0 error events to MCU ESM. When these error events are routed to MCU ESM high output, it can trigger the reset logic to reset the device, when CTRLMMR_MCU_RST_CTRL:MCU_ESM_ERROR_RESET_EN_Z is set to '0'. K3 based J7 devices (ex: J721e) also have ESM modules, and the changes to the driver does not impact those devices. Signed-off-by: Hari Nagalla <hnagalla@ti.com> Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2022-04-04board: axy17lte: get board usable - add bootcmd and docsDzmitry Sankouski
U-boot is intended to replace linux kernel in android boot image(ABL), and it's FIT payload to replace initramfs file. The boot process is similar to boot image with linux: - android bootloader (ABL) unpacks android boot image - ABL sets `linux,initrd-start property` in chosen node in unpacked FDT - ABL sets x0 register to FDT address, and passes control to u-boot - u-boot reads x0 register, and stores it in `prevbl_fdt_addr` env variable - u-boot reads `linux,initrd-start` property, and stores it in `prevbl_initrd_start_addr` In this way, u-boot bootcmd relies on `prevbl_initrd_start_addr` env variable, and boils down to `bootm $prevbl_initrd_start_addr`. If more control on boot process is desired, pack a boot script in FIT image, and put it to default configuration What done: - Rearrange defconfig option order - Add CONFIG_SAVE_PREV_BL_* options - Doc updates: - remove wrong SBOOT memory corruption note, because memory is changed during u-boot bringup process, not by SBOOT - put payload on ramdisk place in abl boot image creation step Signed-off-by: Dzmitry Sankouski <dsankouski@gmail.com>
2022-04-04spl: mmc: extend spl_mmc_boot_mode() to take mmc argumentAndre Przywara
Platforms can overwrite the weak definition of spl_mmc_boot_mode() to determine where to load U-Boot proper from. For most of them this is a trivial decision based on Kconfig variables, but it might be desirable the probe the actual device to answer this question. Pass the pointer to the mmc struct to that function, so implementations can make use of that. Compile-tested for all users changed. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Stefano Babic <sbabic@denx.de> Reviewed-by: Ley Foon Tan <ley.foon.tan@inte.com> (for SoCFPGA) Acked-by: Lokesh Vutla <lokeshvutla@ti.com> (for OMAP and K3) Reviewed-by: Simon Glass <sjg@chromium.org>
2022-04-04sunxi: clock: H6: Adjust PLL LDO before clock setupJernej Skrabec
BSP boot0 adjust PLL LDO regulator before clocks are initialized. Let's do that. Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-04-04sunxi: clock: H6/H616: Add resistor calibrationJernej Skrabec
BSP boot0 executes resistor calibration before clocks are initialized. Let's do that. Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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