summaryrefslogtreecommitdiff
AgeCommit message (Collapse)Author
2023-07-28rockchip: px30: Define variables for compressed image supportPaul Kocialkowski
The standard boot path expects the kernel_comp_addr_r and kernel_comp_size variables for booting compressed kernel images. Define them using the previous kernel_addr_c value (likely initially meant for this purpose) and usual size. This was tested on the PX30 EVB to successfully boot compressed Linux kernel images. Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-07-28rockchip: rk356x: Update PCIe config, IO and memory regionsJonas Karlman
Update config, IO and memory regions used based on [1] with pcie3x2 config reg address and reg size corrected. Before this change: PCI Autoconfig: Bus Memory region: [0-3eefffff], PCI Autoconfig: Bus I/O region: [3ef00000-3effffff], After this change: PCI Autoconfig: Bus Memory region: [40000000-7fffffff], PCI Autoconfig: Bus I/O region: [f0100000-f01fffff], [1] https://lore.kernel.org/lkml/20221112114125.1637543-2-aholmes@omnom.net/ Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-07-28rockchip: rk3568-rock-3a: Enable PCIe and NVMe supportJonas Karlman
Add missing pinctrl and defconfig options to enable PCIe and NVMe support on Radxa ROCK 3 Model A. Use of pcie20m1_pins and pcie30x2m1_pins ensure IO mux selection M1. The following pcie_reset_h and pcie3x2_reset_h ensure GPIO func is restored to the perstn pin, a workaround to avoid having to define a new rockchip,pins. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-07-28rockchip: clk: clk_rk3568: Add CLK_PCIEPHY2_REF supportJonas Karlman
Add dummy support for the CLK_PCIEPHY2_REF clock. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-07-28regulator: fixed: Add support for gpios propJonas Karlman
The commit 12df2c182ccb ("regulator: dt-bindings: fixed-regulator: allow gpios property") in linux v6.3-rc1 added support for use of either a gpios or gpio prop with a fixed-regulator. This adds support for the new gpios prop to the fixed-regulator driver. gpios prop is used by vcc3v3-pcie-regulator on Radxa ROCK 3 Model A. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-07-28pci: pcie_dw_rockchip: Disable unused BARs of the root complexJon Lin
The Root Complex BARs default to claim the full 1 GiB memory region on RK3568, leaving no space for any attached device. Fix this by disable the unused BAR 0 and BAR 1 of the RC. Signed-off-by: Jon Lin <jon.lin@rock-chips.com> [jonas@kwiboo.se: Move to rk_pcie_configure and use PCI_BASE_ADDRESS_0/1 const] Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-07-28pci: pcie_dw_rockchip: Speed up link probeJonas Karlman
Use a similar pattern and delay values as the linux mainline driver to speed up failing when nothing is connected. Reduce fail speed from around 5+ seconds down to around one second on a Radxa ROCK 3 Model A, where pcie2x1 is probed before pcie3x2 M2 slot. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-07-28pci: pcie_dw_rockchip: Use regulator_set_enable_if_allowedJonas Karlman
The vpcie3v3 regulator is typically a fixed regulator controlled using gpio. Change to use enable and disable calls on the regulator instead of trying to set a voltage value. Also remove the delay to match linux driver, for a fixed regulator the startup-delay-us prop can be used in case a startup delay is needed. Limited testing on ROCK 3A, ROCK 5B, Quartz64, Odroid-M1 has shown that this delay was not needed. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-07-28pci: pcie_dw_rockchip: Get config region from reg propJonas Karlman
Get the config region to use from the reg prop. Also update the referenced region index used in comment. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-07-28core: read: add dev_read_addr_size_index_ptr functionJonas Karlman
Add dev_read_addr_size_index_ptr function with the same functionality as dev_read_addr_size_index, but instead a return pointer is given. Use map_sysmem() function as cast for the return. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-07-28rockchip: veyron: Enable Winbond SPI flashAlper Nebi Yasak
Some veyron boards seem to have Winbond SPI flash chips instead of GigaDevice ones. At the very least, coreboot builds for veyron boards have them enabled [1]. Enable support for them here as well. [1] https://review.coreboot.org/c/coreboot/+/9719 Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-07-28arm: rockchip: Add Radxa ROCK 4SEChristopher Obbard
Add board-specific devicetree/config for the RK3399T-based Radxa ROCK 4SE board. This board offers similar peripherals in a similar form-factor to the existing ROCK Pi 4B but uses the cost-optimised RK3399T processor (which has different OPP table than the RK3399) and other minimal hardware changes. Kernel tag: next-20230719 Kernel commits: - 86a0e14a82ea ("arm64: dts: rockchip: Add Radxa ROCK 4SE") Signed-off-by: Christopher Obbard <chris.obbard@collabora.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-07-28arm: rockchip: sync ROCK Pi 4 SoCs from LinuxChristopher Obbard
To prepare for ROCK 4 SE support, changes are needed to the common ROCK Pi 4 devicetree to move the OPP from the common devicetree to individual board devicetrees. Sync the Rockchip RK3399 ROCK Pi 4-related DTs from Linux to gain from these changes. Kernel tag: next-20230719 Kernel commits: cfa12c32b96f ("arm64: dts: rockchip: correct wifi interrupt flag in Rock \ Pi 4B") cee572756aa2 ("arm64: dts: rockchip: Disable HS400 for eMMC on ROCK Pi 4") 2bd1d2dd808c ("arm64: dts: rockchip: Disable HS400 for eMMC on ROCK 4C+") fd2762a62646 ("arm64: dts: rockchip: Move OPP table from ROCK Pi 4 dtsi") Signed-off-by: Christopher Obbard <chris.obbard@collabora.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-07-28rockchip: evb_rk3229: Update/fix READMEAlex Bee
This updates the evb_rk3229's README on howto create / use the FIT image created by binman. Also fix some wrong paths and update filenames which have changed in recent upstream optee-os versions. Signed-off-by: Alex Bee <knaerzche@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-07-28rockchip: RK322x: Select SPL_OPTEE_IMAGEAlex Bee
For RK322x series ARM SoCs the OP-TEE is non-optional, as besides the TEE it also provides the PSCI implementation, which is expected to be available by upstream linux. Select CONFIG_SPL_OPTEE_IMAGE if an FIT image is built. Signed-off-by: Alex Bee <knaerzche@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-07-28configs: evb-rk3229: Increase SPL_STACK_R_MALLOC_SIMPLE_LENAlex Bee
An OP-TEE FIT image will fail to extract in SPL because the malloc stack size is currently limited to 0x2000 for evb-rk3229 board. In SPL we do not have to care about size limitations, since we are no longer bound to SRAM limits after DRAM initialization has been done in TPL. Use the default value for CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN in order successfully unpack the FIT image. Signed-off-by: Alex Bee <knaerzche@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-07-28rockchip: Support OP-TEE for ARM in FIT images created by binmanAlex Bee
CONFIG_SPL_OPTEE_IMAGE option is used during DRAM size detection for Rockchip ARM platform to indicate that an OP-TEE binary was already loaded and a Trusted Execution Environment (TEE) is available in order to block/reserve a memory-region for it. This adds a bunch of new `#if's` to u-boot-rockchip.dtsi to include the OP-TEE binary in the FIT image for ARM SOCs if CONFIG_SPL_OPTEE_IMAGE is selected. That makes it a little harder to read, but I opted for that, because all the duplicates in an extra ARM-OP-TEE-specfic .dtsi would be the greater evil, IMHO. Besides it's more likley being "forgotten" to sync when changes in u-boot-rockchip.dtsi are made. The no longer required rockchip-optee.dtsi and it's inclusions are dropped. The hardcoded load address is common across all OP-TEE implemenations for Rockchip (vendor and upstream). The OP-TEE-binary is non-optional if CONFIG_SPL_OPTEE_IMAGE is selected and there will be an error if the file does not exist and/or `TEE=` build option is missing. Signed-off-by: Alex Bee <knaerzche@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-07-28configs: rockchip: rock5b-rk3588: Enable CONFIG_PCI_INIT_RChristopher Obbard
Enable CONFIG_PCI_INIT_R for rock5b pci enumeration during boot in order to autodetect the PCI ethernet NIC during the boot process. Signed-off-by: Christopher Obbard <chris.obbard@collabora.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-07-28rockchip: rk3568: Fix alloc space exhausted in SPLJonas Karlman
Current SYS_MALLOC_F_LEN of 0x2000 (8 KB) used in SPL is too small for some RK3568 boards. SPL will print following during boot: alloc space exhausted Increase the default SYS_MALLOC_F_LEN to 0x20000 (128 KB) to mitigate. Fixes: 2a950e3ba506 ("rockchip: Add rk3568 architecture core") Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-07-28mtd: nand: raw: rockchip_nfc: copy hwecc PA data to oob_poi bufferJohan Jonker
Rockchip boot blocks are written per 4 x 512 byte sectors per page. Each page must have a page address (PA) pointer in OOB to the next page. Pages are written in a pattern depending on the NAND chip ID. This logic used to build a page pattern table is not fully disclosed and is not easy to fit in the MTD framework. The formula in rk_nfc_write_page_hwecc() function is not correct. Make hwecc and raw behavior identical. Generate boot block page address and pattern for hwecc in user space and copy PA data to/from the already reserved last 4 bytes before EEC in the chip->oob_poi data layout. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-07-28rockchip: puma: pass platform parameter to TF-AQuentin Schulz
Puma supports upstream TF-A and is configured to output serial on UART0 instead of the default UART2. Since U-Boot is properly configured to output on UART0, let's pass the DT to TF-A so there is no need for a custom TF-A to make the latter output to UART0 too. Cc: Quentin Schulz <foss+uboot@0leil.net> Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-07-28rockchip: rk3399: pass platform parameter to TF-A by default for new RK3399 ↵Quentin Schulz
boards Long are gone the times TF-A couldn't handle the FDT passed by U-Boot. Specifically, since commit e7b586987c0a ("rockchip: don't crash if we get an FDT we can't parse") in TF-A, failure to parse the FDT will use the fallback mechanism. This patch was merged in TF-A v2.4-rc0 from two years ago. New boards should likely have this option disabled or explicitly enable it in their respective defconfig. Because existing boards might depend on a TF-A version that predates v2.4, let's just enable this option in all RK3399 defconfigs. Maintainers of each board can decide for themselves if they would prefer to disable this option and allow U-Boot to pass the DT to TF-A. Cc: Quentin Schulz <foss+uboot@0leil.net> Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-07-28board: rockchip: Add Edgeble Neural Compute Module 6BJagan Teki
Neural Compute Module 6B(Neu6B) is a 96boards SoM-CB compute module based on Rockchip RK3588J from Edgeble AI. Add support for this SoM and IO board. Signed-off-by: Jagan Teki <jagan@edgeble.ai> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-07-28arm64: dts: rockchip: Add rk3588 Edgeble Neu6BJagan Teki
Neural Compute Module 6B(Neu6B) is a 96boards SoM-CB compute module based on Rockchip RK3588J from Edgeble AI. General features: - Rockchip RK3588J - up to 32GB LPDDR4x - up to 128GB eMMC - 2x MIPI CSI2 FPC - On module WiFi6/BT Neural Compute Module 6B(Neu6B) IO board is an industrial form factor ready-to-use IO board from Edgeble AI. General features: - microSD slot - 1x HDMI Out - 1x HDMI In - 2x DP - 1x eDP - 2x MIPI DSI connector - 4x MIPI CSI2 connector - 2x USB Host - 2x USB 3.0 OTG/Host - 1x SATA - 1x 2.5Gbps Ethernet - 1x M.2 B-Key for 4G/5G cards - 1x M.2 M-Key slot - 1x Onboard PoE - 1x RS485, RS232, CAN - 1x Audio, MIC port - RTC battery slot - 40-pin GPIO expansion Neu6B needs to mount on top of this IO board in order to create a complete Edgeble Neural Compute Module 6B(Neu6B) IO platform. Kernel commits: commit <5f06c3f508f7> ("arm64: dts: rockchip: Add rk3588 Edgeble Neu6 Model B SoM") commit <3a9181a43b94> ("arm64: dts: rockchip: Add rk3588 Edgeble Neu6 Model B IO") Signed-off-by: Jagan Teki <jagan@edgeble.ai> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-07-28ARM: dts: rockchip: Add rk3588j-u-boot.dtsiJagan Teki
Add rk3588j-u-boot.dtsi for adding U-Boot specific nodes and properties for Rockchip RK3588J SoC. Signed-off-by: Jagan Teki <jagan@edgeble.ai> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-07-28arm64: dts: rockchip: Add Rockchip RK3588JJagan Teki
Rockchip RK3588J is the industrial-grade version of RK3588 SoC and is operated with -40 °C to +85 °C temparature. Add rk3588j specific dtsi for adding rk3588j specific operating points and other changes to be add in future. Kernel commit: commit <8274a04ff1dc> ("arm64: dts: rockchip: Add Rockchip RK3588J") Signed-off-by: Jagan Teki <jagan@edgeble.ai> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-07-28arch: rockchip: rk3588: Fix missing suffix 'A' for Edgeble Neu6AJagan Teki
Add missing suffix 'A' for Edgeble Neu6A SoM and IO boards. Fixes: <15b2d1fb727> ("board: rockchip: Add Edgeble Neural Compute Module 6") Signed-off-by: Jagan Teki <jagan@edgeble.ai> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-07-28rockchip: rk3568: Add support for FriendlyARM NanoPi R5CTianling Shen
FriendlyARM NanoPi R5C is an open-sourced mini IoT gateway device. Specification: - Rockchip RK3568 - 1/4GB LPDDR4X RAM - 8/32GB eMMC - SD card slot - M.2 Connector - 2x USB 3.0 Port - 2x 2500 Base-T (PCIe, r8125) - HDMI 2.0 - MIPI DSI/CSI - USB Type C 5V The device tree is taken from kernel v6.4-rc1. Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Tianling Shen <cnsztl@gmail.com>
2023-07-28rockchip: rk3568: Add support for FriendlyARM NanoPi R5STianling Shen
FriendlyARM NanoPi R5S is an open-sourced mini IoT gateway device. Board Specifications - Rockchip RK3568 - 2 or 4GB LPDDR4X - 8GB or 16GB eMMC, SD card slot - GbE LAN (Native) - 2x 2.5G LAN (PCIe) - M.2 Connector - HDMI 2.0, MIPI DSI/CSI - 2xUSB 3.0 Host - USB Type C PD, 5V/9V/12V - GPIO: 12-pin 0.5mm FPC connector The device tree is taken from kernel v6.4-rc1. Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Tianling Shen <cnsztl@gmail.com>
2023-07-28rockchip: rk3328: Add support for Orange Pi R1 Plus LTSTianling Shen
The OrangePi R1 Plus LTS is a minor variant of OrangePi R1 Plus with the on-board NIC chip changed from rtl8211e to yt8531c, and RAM type changed from DDR4 to LPDDR3. The device tree is taken from kernel v6.4-rc1. Signed-off-by: Tianling Shen <cnsztl@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-07-28rockchip: rk3328: Add support for Orange Pi R1 PlusTianling Shen
Orange Pi R1 Plus is a Rockchip RK3328 based SBC by Xunlong. This device is similar to the NanoPi R2S, and has a 16MB SPI NOR (mx25l12805d). The reset button is changed to directly reset the power supply, another detail is that both network ports have independent MAC addresses. The device tree and description are taken from kernel v6.3-rc1. Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Tianling Shen <cnsztl@gmail.com>
2023-07-28doc: anbernic: Update RGxx3 Docs for panel detectionChris Morgan
Update the Anbernic RGxx3 documentation to note that panel detection has been added and how it works. Signed-off-by: Chris Morgan <macromorgan@hotmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-07-28configs: Update anbernic-rgxx3_defconfig for panel detectionChris Morgan
Update the anbernic-rgxx3_defconfig file to support panel autodetection and automatically updating the compatible string in the devicetree. Signed-off-by: Chris Morgan <macromorgan@hotmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-07-28board: rockchip: Add panel auto-detection for Anbernic RGxx3Chris Morgan
Add support to automatically detect the panel for the Anbernic RGxx3. This is done by creating a "pseudo driver" that provides only the bare minimum to start the DSI controller and DSI DPHY. Once started, we then can query the panel for its panel ID and compare it to a table of known values. The panel compatible string (which corresponds to the upstream Linux driver) is then defined as an environment variable "panel". The panel compatible string is also changed automatically via an ft_board_setup() call if what is detected differs from what is in the loaded tree. This way, end users can use the same bootloader without having to worry about which panel they have (as there is no obvious way of knowing). Signed-off-by: Chris Morgan <macromorgan@hotmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-07-28board: rockchip: Add support for RG353PS to RGxx3Chris Morgan
Add support for the RG353PS to the Anbernic RGxx3. This device is a slightly pared down version of the RG353P with no eMMC, no touchscreen, and only 1GB of RAM. Refactor board logic so that all supported devices are defined with ADC values and that future boards can be added by just defining the board values in the device array. Signed-off-by: Chris Morgan <macromorgan@hotmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-07-28board: rockchip: add DSI and DSI-DPHY for Anbernic RGxx3Chris Morgan
Add support for the DSI and DSI-DPHY to U-Boot for the RGxx3. These are needed so we can send a panel ID request to determine which panel is being used. Signed-off-by: Chris Morgan <macromorgan@hotmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-07-28board: rockchip: Correct i2c2 pinctrl for RGxx3Chris Morgan
The pinctrl on the Anbernic RGxx3 for the i2c2 bus does not use the default value, so explicitly define it. Fixes: 6cf6fe25370c ("board: rockchip: add Anbernic RGXX3 Series Devices") Signed-off-by: Chris Morgan <macromorgan@hotmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-07-28configs: rock5b-rk3588: enable USB 3.0 controller, command, gadgetEugen Hristev
Enable configuration for USB 3.0 controller, the commands required, and the gadget drivers. Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-07-28ARM: dts: rockchip: rk3588-rock-5b-u-boot: add USB3 supportEugen Hristev
Enable the USB3.0 host node, and gadget node. The gadget is available through the USB type C connector on the board. The connector is tied to a Fairchild fusb302b device, which currently does not have a driver in U-boot, but the node is here for correct description of the board + Linux future compatibility. It will be easier to move the node as-is when it will be available in the DT from Linux Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-07-28ARM: dts: rockchip: rk3588: add support for USB 3.0 devicesJoseph Chen
Add support for the USB 3.0 devices in rk3588: - USB DRD(dual role device) 3.0 #0 as usbdrd3_0 which is available in rk3588s - USB DRD(dual role device) 3.0 #1 as usbdrd3_1 which is available in rk3588 only - USB DP PHY (combo USB3.0 and DisplayPort Alt Mode ) #0 phy interface as usbdp_phy0 - USB DP PHY (combo USB3.0 and DisplayPort Alt Mode ) #1 phy interface as usbdp_phy1 - USB 2.0 phy #2 , the USB 3.0 device can work with this phy in USB 2.0 mode - associated GRFs (general register files) for the devices. Signed-off-by: Joseph Chen <chenjh@rock-chips.com> [eugen.hristev@collabora.com: move nodes to right place, adapt from latest linux kernel] Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-07-28phy: rockchip: add usbdp combo phy driverFrank Wang
This adds a new USBDP combo PHY with Samsung IP block driver. The PHY is a combo between USB 3.0 and DisplayPort alt mode. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> [eugen.hristev@collabora.com: ported to 2023.07, clean-up] Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-07-28ARM: dts: rockchip: rk3588: sync with LinuxEugen Hristev
Sync the devicetree with linux-next tag: next-20230525 Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-07-28video: rockchip: Add support for RK3399 to dw-mipi-dsi bridgeOndrej Jirman
This just needs some extra clocks enabled, and different registers configured. Copied from Linux, just like the original submitter of this driver did for rk3568. Tested on Pinephone Pro. Signed-off-by: Ondrej Jirman <megi@xff.cz> Cc: Anatolij Gustschin <agust@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Philipp Tomsich <philipp.tomsich@vrull.eu> Cc: Kever Yang <kever.yang@rock-chips.com> Cc: Chris Morgan <macromorgan@hotmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-07-28rockchip: board: Update Odroid Go2 to Support Additional RevisionsChris Morgan
Update the board.c file for the Odroid Go Advance to support the Black Edition and the Odroid Go Super. The Odroid Go Advance Black Edition differs from the original model with the addition of 2 extra buttons and an ESP8266 WiFi module. The Odroid Go Super adds an additional 2 buttons compared to the Black Edition, along with a larger panel and larger battery. This change uses the value of ADC0 to determine which of these 3 models it is, and then changes the ${fdtfile} environment variable to match the proper devicetree name in mainline Linux. Tested on an Odroid Go Advance (first revision) and an Odroid Go Super. The correct ${fdtfile} variable was set for each device. Signed-off-by: Chris Morgan <macromorgan@hotmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-07-28configs: rock5b-rk3588: add rtl8169 driverEugen Hristev
Add the rtl8169 driver, which supports the rtl8125b device, which is connected on the pciE bus on this board. Enable also CONFIG_SYS_HAS_NONCACHED_MEMORY to have the descriptors stored. Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-07-27Merge https://source.denx.de/u-boot/custodians/u-boot-usbTom Rini
2023-07-27usb: xhci: Fix double free on failureRichard Habeeb
drivers/core/device.c will call `device_free()` after xhci_register already frees the private device data. This can cause a crash later during the boot process, observed on aarch64 RPi4b as a synchronous exception. All callers of xhci_register use priv_auto, so this won't lead to memory leaks. Signed-off-by: Richard Habeeb <richard.habeeb@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-07-25Merge branch 'master' of git://git.denx.de/u-boot-coldfireTom Rini
- Watchdog updates, and more MAINTAINERS entries
2023-07-25Revert "travis-ci: Add m68k M5208EVBE machine"Tom Rini
This commit was not intended for this tree but rather u-boot-test-scripts (where it is applied). This reverts commit f04ef0a7a0166e91729b45b1db22f5cc3b3b2f99. Signed-off-by: Tom Rini <trini@konsulko.com>
2023-07-25MAINTAINERS: add myself as mcf_wdt.c maintainerAngelo Dureghello
Signed-off-by: Angelo Dureghello <angelo@kernel-space.org> --- Changes for v2: - none Changes for v3: - none
generated by cgit v1.2.3 (git 2.0.4) at 2025-08-06 23:24:31 +0000