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2025-07-18misc: Remove DS4510 driverTom Rini
As no platforms use this driver anymore and it's not been converted from to DM_I2C for use, remove it. Fixes: ed7fe2bee12a ("ppc: Remove xpedite boards") Signed-off-by: Tom Rini <trini@konsulko.com>
2025-07-18drivers: misc: Remove pca9551_led driverTom Rini
This driver has not been converted to DM_I2C and the last platform that used it was removed as well. Remove the driver. Fixes: 4bbcec08ebec ("arm: Remove mx6dlarm2 board") Signed-off-by: Tom Rini <trini@konsulko.com>
2025-07-18sandbox: Add dummy sync()Tom Rini
In order to compile more drivers, add an empty sync() function. Signed-off-by: Tom Rini <trini@konsulko.com>
2025-07-18input: Tighten dependency requirements for TEGRA_KEYBOARDTom Rini
This driver requires headers which only exist on Tegra. Express that requirement in Kconfig as well. Signed-off-by: Tom Rini <trini@konsulko.com>
2025-07-18misc: Tighten requirements on IHS_FPGA driverTom Rini
This driver requires that the gdsys legacy driver option also be enabled in order to build. Express that requirement in Kconfig as well. Signed-off-by: Tom Rini <trini@konsulko.com>
2025-07-17Merge tag 'u-boot-imx-master-20250717' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-imx CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/27088 - Add support for the i.MX95 B0 version. - Enable standard boot for phycore-imx8mp. - Kconfig fixes for i.MX MMC and FSL_SEC_MON. - Support 4Gb single die variant of the i.MX8MM Venice board.
2025-07-17Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-riscvTom Rini
CI: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/27087 - Board: mpfs_icicle: Fix board_fit_config_name_match and disable DEBUG_UART - Board: Add SD card support to the Beagle-V-Fire - Board: Add support for TH1520-integrated GMACs
2025-07-17Merge tag 'mmc-2025-07-16' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-mmc Drop unused kona_sdhci driver Tighten config dependencies and a minor cleanup
2025-07-17mmc: Remove unused kona_sdhci driverTom Rini
As no platforms use this driver anymore, remove it. Signed-off-by: Tom Rini <trini@konsulko.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2025-07-17mmc: Tighten some mmc driver dependenciesTom Rini
A large number of mmc drivers cannot build without access to some platform specific header files. Express those requirements in Kconfig as well. Signed-off-by: Tom Rini <trini@konsulko.com> Acked-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2025-07-17mmc: Take cleanup path to free memory on error exitAndrew Goodbody
Instead of returning -EINVAL directly which will not call the cleanup path to free memory, fix the code to set the error and then goto the cleanup code. This issue found by Smatch. Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2025-07-17venice: display DRAM MR registers and decoding if debug enabledTim Harvey
While this is interesting and useful for debugging there isn't extremely useful information so we will only show it if debug is enabled. Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2025-07-17venice: lpddr4_timing_imx8mm: update ddr phy config for mscale_v3.10Tim Harvey
Update the ddr phy config values to those created by the mscale_v3.10 tool. The original values were obtained using mscale_v3.10. The v3.10 tool removed ddr phy register values of 0x0. This has no functional change but makes comparing and patching ddr configuration easier in addition to slightly shrinking the DRAM config size. Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2025-07-17venice: lpddr4_timing_imx8mm: add 4gb single die supportTim Harvey
Add dram support for the MT53E1G32D2FW-046 RevC part which is a single die 32Gbit density part vs RevA/B which were dual-die parts: - use a previously unused EEPROM byte to denote a variant of the base config to be patched - add a dram description string - return the board struct from eeprom_init and pass it to the spl_dram_init function so that it has access to the EEPROM - move ddr_init into the spl_dram_init so that it can be patched in the per-soc init function Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2025-07-17venice: lpddr4_timing_imx8mm: add DDRC_ADDRMAP7 configTim Harvey
Add the configuration register for DDRC_ADDRMAP7 which was added in the RAP spreadsheet v19. This has no functional change but allows DRAM configuration to be patched in a later commit. Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2025-07-17armv8: ls1043a: make some erratas dependent from USBHolger Brunck
These erratas are only useful if USB is enabled. If it is disabled these erratas might cause issues. Signed-off-by: Holger Brunck <holger.brunck@hitachienergy.com>
2025-07-17soc: imx8ulp: Add celsius unit for temperatureDavid Zang
Make temperature unit (celsius) more clear to reduce confusion. Signed-off-by: David Zang <davidzangcs@gmail.com>
2025-07-17nxp: Move FSL_SEC_MON related options to arch/Kconfig.nxpTom Rini
The options related to FSL_SEC_MON are part of the chain of trust related options and should be under that menu, so move it there. Furthermore we don't need to prompt for the driver itself but do need to allow for configuration of the monitor endianess. Signed-off-by: Tom Rini <trini@konsulko.com>
2025-07-17arm: imx: Remove unused mxcmmc driverTom Rini
As no platforms use this driver anymore, remove it. Signed-off-by: Tom Rini <trini@konsulko.com>
2025-07-17brppt2: Use the correct MMC driverTom Rini
As part of splitting the i.MX parts of FSL_ESDHC out from the more legacy parts, the FSL_ESDHC_IMX symbol was added. This platform is the only one which was not converted correctly. Fixes: e37ac717d796 ("Convert to use fsl_esdhc_imx for i.MX platforms") Signed-off-by: Tom Rini <trini@konsulko.com>
2025-07-17phycore-imx8mp: Enable standard bootLeonard Anderweit
Enable standard boot for the phycore-imx8mp and use it as default. Add all variables required for standard boot to the environment. Signed-off-by: Leonard Anderweit <l.anderweit@phytec.de> Tested-by: Martin Schwan <m.schwan@phytec.de> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2025-07-17imx95_evk: Add i.MX95 B0 supportAlice Guo
i.MX95 B0 uses image container format v2 and needs DUMMY_DDR so that update imximage.cfg and container.cfg for it. Signed-off-by: Alice Guo <alice.guo@nxp.com>
2025-07-17spl: imx: Add support for new PQC containerYe Li
To support PQC container format which is used for post quantum authentication on new i.MX parts like i.MX94 The major changes compared to legacy container format is in signature block, new container tag and version, and new alignment of container header. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Alice Guo <alice.guo@nxp.com> Acked-by: Peng Fan <peng.fan@nxp.com>
2025-07-17tools: imx8image: Add 2 new commands CMD_CNTR_VERSION and CMD_DUMMY_DDRAlice Guo
i.MX95 B0 uses image container format v2, and `one container header occupies 0x4000, so that CMD_CNTR_VERSION needs to be added. The purpose of CMD_DUMMY_DDR is to create a dummy image entry in boot container prior the DDR OEI image entry. ROM reads the address of DUMMY DDR image entry and passes it to DDR OEI in OEI entry function as parameter value, in order to indicate the offset of training data with the boot container. Signed-off-by: Alice Guo <alice.guo@nxp.com>
2025-07-17arm: imx: Update ELE get_info structure for i.MX94Ye Li
Since i.MX94, the ELE get_info structure is updated to add OEM PQC SRK hash, so update it. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Alice Guo <alice.guo@nxp.com> Acked-by: Peng Fan <peng.fan@nxp.com>
2025-07-17configs: th1520_lpi4a: Enable network supportYao Zi
Enable the network stack, the designware ethernet driver and corresponding glue driver. The Lichee Pi 4A board ships two RTL8211F phys, both attached to GMAC 0, thus support for Realtek phys and DM support for MDIO devices are enabled as well. Signed-off-by: Yao Zi <ziyao@disroot.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-07-17riscv: dts: th1520: Describe GMACs and enable them on Lichee Pi 4AYao Zi
TH1520 SoC ships two MAC controllers based on Designware Ethernet IP that are capable of Gigabit operation. Describe them in SoC devicetree and enable them for Lichee Pi 4A. Signed-off-by: Yao Zi <ziyao@disroot.org> Acked-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-07-17drivers: net: Add T-Head DWMAC glue layerYao Zi
The Designware IP integrated in TH1520 SoC requires extra clock configuration to operate correctly. The Linux kernel's T-Head DWMAC glue driver is ported and adapted to U-Boot's API. Signed-off-by: Yao Zi <ziyao@disroot.org> Acked-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-07-17riscv: cpu: th1520: Limit upper RAM boundary to 4 GiBYao Zi
TH1520 SoC ships DMA peripherals that could only reach the first 32-bit range of memory, for example, the GMAC controllers. Let's limit the usable top of RAM below 4GiB to ensure DMA allocations are accessible to all peripherals. Signed-off-by: Yao Zi <ziyao@disroot.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-07-17clk: thead: th1520-ap: Correctly handle flags for dividersYao Zi
Unlike the gate clocks which make no use of flags, most dividers in TH1520 SoC are one-based, thus are applied with CLK_DIVIDER_ONE_BASED flag. We couldn't simply ignore the flag, which causes wrong results when calculating the clock rates. Add a member to ccu_div_internal for defining the flags, and pass it to divider_recalc_rate(). With this fix, frequency of all the clocks match the Linux kernel's calculation. Fixes: e6bfa6fc94f ("clk: thead: Port clock controller driver of TH1520 SoC") Signed-off-by: Yao Zi <ziyao@disroot.org> Acked-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-07-17spi: coreqspi: add xfer function for PolarFire SoCEoin Dickson
Add xfer function to PolarFire SoC coreqspi driver. The read and write operations are limited to one byte at a time instead of four as CMD18 (multiple block read) reads garbage when four byte ops are enabled. Signed-off-by: Eoin Dickson <eoin.dickson@microchip.com> Acked-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-07-17gpio: add PolarFire SoC GPIO and Core GPIO driverEoin Dickson
This driver adds GPIO support for PolarFire SoC family, this is required to add sd card support on the Beagle-V-Fire as it uses GPIO chip selects Signed-off-by: Eoin Dickson <eoin.dickson@microchip.com> Acked-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-07-17configs: microchip_mpfs_icicle: disable DEBUG_UARTConor Dooley
By default DEBUG_UART uses the SBI DBCN extension on S-Mode RISC-V platforms, but the Icicle Kit's firmware doesn't support it. Since DEBUG_UART is getting turned on automagically and this is somewhat misleading, disable it in the Icicle kit's defconfig. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-07-17board: mpfs_icicle: fix board_fit_config_name_match()Conor Dooley
The loop in the icicle implementation of board_fit_config_name_match() runs strtok() to split off the vendor portion of the compatible string using , as the delimiter. strtok() modifies a string in place, so where the first config and compatible do not match, the compatible has been modified by the time the loop hits the second iteration. Since stringlists in dt land are null separated strings, the nulls strtok() inserts to replace the delimiter increase the number of strings in the compatible list. When the second iteration of the loop calls fdt_stringlist_get(), it gets the vendorless portion of the first compatible string, rather than the second compatible string. Copy each compatible before calling strtok() to avoid this problem. The temporary string the compatible is copied to is statically allocated, as attempts to dynamically allocate it at this stage of boot were met with "alloc space exhausted" errors. Fixes: 7c16ebba1ed ("board: mpfs_icicle: implement board_fdt_blob_setup()/board_fit_config_name_match()") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-07-16board: vexpress_ca9x4: Enable D-cache and MMUMark Kettenis
Enable the D-cache, which will also enable the MMU. The latter make sure we don't do unaligned access on Strongly-ordered memory, which has UNPREDICTABLE behaviour according the architecture definition. This fixes using U-Boot with recent versions of QEMU's vexpress-ca9 emulation. Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
2025-07-16boot: Ensure method_flags is initialised before useAndrew Goodbody
The local variable method_flags is only assigned to in some of the code paths leaving it possibly uninitialised at first use. Initialise method_flags at declaration to ensure that it cannot be used uninitialised. Also remove now redundant assignments. Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
2025-07-16arm: dts: am335x-evm: remove duplicate chosen nodeRasmus Villemoes
The stdout-path property is already set to this value in the other chosen node ~15 lines above. Signed-off-by: Rasmus Villemoes <ravi@prevas.dk>
2025-07-16Merge tag 'u-boot-dfu-20250716' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-dfu u-boot-dfu-20250716 Android: - Fix printing lbaint_t format in AVB and android_ab messages DFU: - Fix dfu_config_interfaces() for single interface DFU syntax
2025-07-16dfu: Fix dfu_config_interfaces() for single interface DFU syntaxSam Protsenko
As stated in DFU documentation [1], the device interface part might be missing in dfu_alt_info: dfu_alt_info The DFU setting for the USB download gadget with a semicolon separated string of information on each alternate: dfu_alt_info="<alt1>;<alt2>;....;<altN>" When several devices are used, the format is: - <interface> <dev>'='alternate list (';' separated) So in first case dfu_alt_info might look like something like this: dfu_alt_info="mmc 0=rawemmc raw 0 0x747c000 mmcpart 1;" And in second case (when the interface is missing): dfu_alt_info="rawemmc raw 0 0x747c000 mmcpart 1;" When the interface is not specified the 'dfu' command crashes when called using 'dfu 0' or 'dfu list' syntax: => dfu list "Synchronous Abort" handler, esr 0x96000006, far 0x0 That's happening due to incorrect string handling in dfu_config_interfaces(). In case when the interface is not specified in dfu_alt_info it triggers this corner case: d = strsep(&s, "="); // now d contains s, and s is NULL if (!d) break; a = strsep(&s, "&"); // s is already NULL, so a is NULL too if (!a) // corner case a = s; // a is NULL now which causes NULL pointer dereference later in this call, due to 'a' being NULL: part = skip_spaces(part); That's because as per strsep() behavior, when delimiter ("&") is not found, the token (a) becomes the entire string (s), and string (s) becomes NULL. To fix that issue assign "a = d" instead of "a = s", because at that point variable d actually contains previous s, which should be used in this case. [1] doc/usage/dfu.rst Fixes: commit febabe3ed4f4 ("dfu: allow to manage DFU on several devices") Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Reviewed-by: Mattijs Korpershoek <mkorpershoek@kernel.org> Link: https://lore.kernel.org/r/20250709042342.13544-1-semen.protsenko@linaro.org Signed-off-by: Mattijs Korpershoek <mkorpershoek@kernel.org>
2025-07-16common/avb_verify.c: Make use of LBAF for printing lbaint_tTom Rini
When printing the contents of an lbaint_t variable we need to use LBAF to print it in order to get the correct format type depending on 32 or 64bit-ness. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> Reviewed-by: Mattijs Korpershoek <mkorpershoek@kernel.org> Link: https://lore.kernel.org/r/20250702010603.19354-2-trini@konsulko.com Signed-off-by: Mattijs Korpershoek <mkorpershoek@kernel.org>
2025-07-16boot/android_ab.c: Make use of LBAF for printing lbaint_tTom Rini
When printing the contents of an lbaint_t variable we need to use LBAF to print it in order to get the correct format type depending on 32 or 64bit-ness. Furthermore, printed message should not be split as that makes finding them harder, so bring this back to a single line. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> Reviewed-by: Mattijs Korpershoek <mkorpershoek@kernel.org> Link: https://lore.kernel.org/r/20250702010603.19354-1-trini@konsulko.com Signed-off-by: Mattijs Korpershoek <mkorpershoek@kernel.org>
2025-07-15MAINTAINERS: Update email of Stefan RoeseStefan Roese
Use the @mailbox.org mail address also for community work. Signed-off-by: Stefan Roese <stefan.roese@mailbox.org>
2025-07-15Merge patch series "drivers/net/airoha_eth: fixes"Tom Rini
Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu> says: Several fixes for the airoha ethernet driver. Link: https://lore.kernel.org/r/20250709092810.4032971-1-mikhail.kshevetskiy@iopsys.eu
2025-07-15drivers/net/airoha_eth: enable hw padding of short tx packetsMikhail Kshevetskiy
Transmission of short packets does not work good for XFI (GDM2) and HSGMII (GDM3) interfaces. The issue can be solved with: - padding of short packets to 60 bytes - setting of PAD_EN bit in the corresponding REG_GDM_FWD_CFG(n) register. The issue should present for the lan switch (GDM1) as well, but it does does not appear due to unknown reason. This patch set PAD_EN bit for the used GDM. Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
2025-07-15drivers/net/airoha_eth: fix stalling in package receivingMikhail Kshevetskiy
ARCH_DMA_MINALIGN is 64 for ARMv7a/ARMv8a architectures, but RX/TX descriptors are 32 bytes long. So they may not be aligned on an ARCH_DMA_MINALIGN boundary. In case of RX path, this may cause the following problem 1) Assume that a packet has arrived and the EVEN rx descriptor has been updated with the incoming data. The driver will invalidate and check the corresponding rx descriptor. 2) Now suppose the next descriptor (ODD) has not yet completed. Please note that all even descriptors starts on 64-byte boundary, and the odd ones are NOT aligned on 64-byte boundary. Inspecting even descriptor, we will read the entire CPU cache line (64 bytes). So we read and sore in CPU cache also the next (odd) descriptor. 3) Now suppose the next packet (for the odd rx descriptor) arrived while the first packet was being processed. So we have new data in memory but old data in cache. 4) After packet processing (in arht_eth_free_pkt() function) we will cleanup the descriptor and put it back to rx queue. This will call flush_dcache_range() function for the even descriptor, so the odd one will be flushed as well (it is in the same cache line). So the old data will be written to the next rx descriptor. 5) We get a freeze. The next descriptor is empty (so the driver is waiting for packets), but the hardware will continue to receive packets on other available descriptors. This will continue until the last available rx descriptor is full. Then the hardware will also freeze. The problem will be solved if the previous descriptor will be put back to the queue instead of the current one. If the current descriptor is even (starts on a 64-byte boundary), then putting the previous descriptor to the rx queue will affect the previous cache line. To be 100% ok, we must make sure that the previous and the one before the previous descriptor cannot be used for receiving at this moment. If the current descriptor is odd, then the previous descriptor is on the same cache line. Both (current and previous) descriptors are not currently in use, so issue will not arrise. WARNING: The following restrictions on PKTBUFSRX must be held: * PKTBUFSRX is even, * PKTBUFSRX >= 4. The bug appears on 32-bit airoha platform, but should be present on 64-bit as well. The code was tested both on 32-bit and 64-bit airoha boards. Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
2025-07-15drivers/net/airoha_eth: fix packet transmission errorsMikhail Kshevetskiy
The dma_map_single() function calls one of the functions * invalidate_dcache_range(), * flush_dcache_range(). Both of them expect that 'vaddr' is aligned to the ARCH_DMA_MINALIGN boundary. Unfortunately, RX/TX descriptors are 32-byte long. Thus they might not be aligned to the ARCH_DMA_MINALIGN boundary. Data flushing (or invalidating) might do nothing in this case. The same applies to dma_unmap_single() function. In the TX path case the issue might prevent package transmission (filled TX descriptor was not flushed). To fix an issue a special wrappers for * dma_map_single(), * dma_unmap_single() functions were created. The patch fix flushing/invalidatiog for the RX path as well. The bug appears on 32-bit airoha platform, but should be present on 64-bit as well. The code was tested both on 32-bit and 64-bit airoha boards. Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
2025-07-15drivers/net/airoha_eth: add missing terminator for compatible devices listMikhail Kshevetskiy
Compatible device list must have a terminator. If terminator is missed the u-boot driver subsystem will access random data placed after the list in the memory. The issue can be observed with the "dm compat" command. Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
2025-07-15Merge patch series "fs: exfat: Fix some Smatch issues"Tom Rini
Andrew Goodbody <andrew.goodbody@linaro.org> says: Smatch reported issues with variables being dereferenced before NULL checks and also testing an unsigned variable for being negative. Link: https://lore.kernel.org/r/20250707-exfat_fix-v1-0-e5783978cd11@linaro.org
2025-07-15fs: exfat: Remove pointless variable uoffsetAndrew Goodbody
In exfat_generic_pread and exfat_generic_pwrite offset is passed in as a off_t type which is defined as 'unsigned long long' so there is no need to create the variable uoffset as a uint64_t as this is just a direct copy of offset. Also remove the impossible test of 'offset < 0' as this is always false due to offset being unsigned. This issue found by Smatch. Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
2025-07-15fs: exfat: Perform NULL check before dereferenceAndrew Goodbody
In the functions exfat_pread and exfat_pwrite there is a NULL check for ctxt.cur_dev but this has already been derefenced twice before this happens. Refactor the code a bit to put the NULL check first. This issue found by Smatch. Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>