| Age | Commit message (Collapse) | Author |
|---|
|
The length of a property includes '\0' in a string type one, so
the length passed by needs to have that in account, if not,
when getting the property value it will fail because it
has the wrong size.
Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org>
Tested-by: caleb.connolly@linaro.org # db845c
Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20250227094911.497219-2-rui.silva@linaro.org
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
|
This is required for gadget modes to work on most platforms. It must be
disabled for dragonboard410c since that doesn't use dwc3. USB on other
MSM8916 platforms isn't supported by qcom_defconfig anyway.
Link: https://lore.kernel.org/r/20250324-sdm845-fixes-fastboot-v1-3-d177a10f336d@linaro.org
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
|
Andre Przywara <andre.przywara@arm.com> says:
C's implicit fallthrough behaviour in switch/case statements can lead to
subtle bugs. Quite some while ago many compilers introduced warnings in
those cases, requiring intentional fallthrough's to be annotated.
So far we were not enabling that compiler option, so many ambiguities
and some bugs in the code went unnoticed.
This series adds the required annotations in code paths that the first
stage of the U-Boot CI covers. There is a large number of cases left
in the libbz2 code. The usage of switch/case is borderline insane there,
labels are hidden in macros, and there are no breaks, but just goto's.
Upstream still uses very similar code, without any annotations. I still
am not 100% sure those are meant to fall through or not, and plan to do
further investigations, but didn't want to hold the rest of the patches
back. You can see for yourself by applying patch 18/18 and building for
sandbox64, for instance.
Because of this we cannot quite enable the warning in the Makefile yet,
but those fixes are worth regardless, and be it to increase readability.
Please note that those patches do not fix anything, really, they just add
those fallthrough annotations, so the series is not really critical.
Link: https://lore.kernel.org/r/20250327153313.2105227-1-andre.przywara@arm.com
|
|
The MMC boot mode selection for the TI AM62P series of SoCs uses an
implicit switch/case fallthrough for falling back to some default
boot mode.
Add our "fallthrough;" statement-like macro before the default branch in
the code, to avoid a warning when GCC's -Wimplicit-fallthrough warning
option is enabled.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
|
|
Heinrich Schuchardt <heinrich.schuchardt@canonical.com> says:
Introduce a new function to update ACPI table headers.
This allows to simplify the existing code.
Link: https://lore.kernel.org/r/20250321232121.251800-1-heinrich.schuchardt@canonical.com
|
|
According to the binding [1] the ITS node should be a subnode of the
GICv3 node. Thus move it now that the driver binds subnodes as well.
1: https://www.kernel.org/doc/Documentation/devicetree/bindings/interrupt-controller/arm%2Cgic-v3.txt
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
|
|
According to the binding [1] the ITS node should be a subnode of the
GICv3 node. Since the ITS node has it's own driver, manually probe for
possible subnodes after binding since dm_scan_fdt() is not recursive.
1: https://www.kernel.org/doc/Documentation/devicetree/bindings/interrupt-controller/arm%2Cgic-v3.txt
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
|
|
Use acpi_update_checksum() to update table header.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Reviewed-by: Matthias Brugger <mbrugger@suse.com>
|
|
in extlinux / PXE""
This reverts commit 8bc3542384e3a1219e5ffb62b79d16dddc1b1fb9, reversing
changes made to 698edd63eca090a2e299cd3facf90a0b97bed677.
There are still problems with this series to work out.
Link: https://lore.kernel.org/u-boot/CAFLszTjw_MJbK9tpzVYi3XKGazcv55auBAdgVzcAVUta7dRqcg@mail.gmail.com/
Signed-off-by: Tom Rini <trini@konsulko.com>
|
|
Include spl.h to avoid definition errors in custom builds.
Fixes: commit bc07851897bd ("board: ti: Pull redundant DDR functions to a common location and Fixup DDR size when ECC is enabled")
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
|
|
Currently in j721e_init.c we check which firewalls to remove using
the board configuration (e.g CONFIG_TARGET_J721E_R5_EVM). We do this
as J721e and J7200 have different IP and firewalls but use the same
SoC definition (SOC_K3_J721E) even though they are different SoCs.
The idea was they would be similar enough that they both could use
the same SoC config to help with common code sharing. Board checks
would then be used differentiate.
This has grown far too messy to maintain any more, especially now
that there is more than one board using J721e (EVM, SK, Beagle AI64).
As differentiation is done based on board, every one of these boards
would have to have checks added for them. Instead let's split J7200
support out from J721e like how normal new SoC support is done.
This patch touches several subsystems and could not be split much better
as when we add SOC_K3_J7200 we want to make use of it in all spots that
once used the combined SOC_K3_J721E so we can turn off SOC_K3_J721E when
building for J7200 boards.
Signed-off-by: Andrew Davis <afd@ti.com>
|
|
The file k3-am62a7.dtsi is part of upstream DT and should
have been removed when migrating to OF_UPSTREAM but must
have been missed. Do this here.
Signed-off-by: Andrew Davis <afd@ti.com>
|
|
We currently set both and print both PXN and UXN bits when removing
execution for pages. This happens even in the existing per platform
definitions of 'struct mm_region'.
That's not entirely correct though. For stage-1 translations, if a
platform runs on a translation regime with a single privilege level or the
the translation regime supports two privilege levels and we are not
in EL1&0 with HCR_EL2.{NV, NV1} = {1, 1} only BIT54 (XN) is needed
and BIT53(PXN) is reserved 0.
Currently we support Non-Secure EL2, Non-secure EL2&0 and Non-secure
EL1&0.
We already have get_effective_el() which returns 1 if we are
- Running in EL1 so we assume an EL1 translation regime but without
checking HCR_EL2.{NV, NV1} != {1,1}
- Running in EL2 with HCR_EL2.E2H = 1
The only problem with the above is that if we are in EL1&0 and
HCR_EL2.{NV1, NV} == {1, 1}, then
- Bit[54] holds the PXN instead of the UXN
- The Effective value of UXN is 0
- Bit[53] is RES0
So let's re-use that function and set PXN only when we are in
and EL[2|1]&0 translation regime.
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
|
|
Manorit Chawdhry <m-chawdhry@ti.com> says:
The series adds support for J742S2 family of SoCs. Also adds J742S2 EVM
Support and re-uses most of the stuff from the superset device J784s4.
This device is a subset of J784S4 and shares the same memory map and
thus the code is being reused from J784S4 to avoid duplication.
It initially cleans up the J784s4 and AM69 files so that they can be
re-usable for j742s2 and then it introduces J742S2.
The DT for the following SoC will be coming to U-boot during 6.13 Sync
so the series is kept as RFC till then.
Here are some of the salient features of the J742S2 automotive grade
application processor:
The J742S2 SoC belongs to the K3 Multicore SoC architecture platform,
providing advanced system integration in automotive, ADAS and industrial
applications requiring AI at the network edge. This SoC extends the K3
Jacinto 7 family of SoCs with focus on raising performance and
integration while providing interfaces, memory architecture and compute
performance for multi-sensor, high concurrency applications.
Some changes that this devices has from J784S4 are:
* 4x Cortex-A72 vs 8x Cortex-A72
* 3x C7x DSP vs 4x C7x DSP
* 4 port ethernet switch vs 8 port ethernet switch
* 2 DDR controller vs 4 DDR controller
Test logs:
https://gist.github.com/manorit2001/f7df0e8cca1e9973b4361f0559c6f53d
Link: https://lore.kernel.org/r/20250317-b4-upstream-j742s2-v4-0-4ba88bfd357a@ti.com
|
|
Include the U-boot device tree files needed to boot the board.
[ DDR config ]
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
|
|
Introduce the basic files needed to support the TI J742S2 family of SoCs.
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
|
|
J742S2 has the same part number as J784S4 but JTAG_DEVICE_ID has a
PKG bit that tells about J742S2.
Add support for reading JTAG_DEVICE_ID and set family as J742S2 based
on that.
Link: https://www.ti.com/lit/pdf/spruje3 (TRM)
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
|
|
Refactor J784s4 ddr file to a common file which uses the
superset device to allow reuse in j742s2-evm which uses the subset part.
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
|
|
Clean up templatized boot binaries for j784s4 soc. This includes
modifying the k3-j784s4-binman.dtsi to use SPL_BOARD_DTB,
BOARD_DESCRIPTION and UBOOT_BOARD_DESCRIPTION from the files that
include it to further reuse code.
k3-j784s4-binman.dtsi will contain only templates. Only required boot
binaries can be built from the templates in the boards' respective
-u-boot.dtsi file (or k3-<board>-binman.dtsi if it exists). This allows
clear distinction between the SoC common stuff vs. what is additionally
needed to boot up a specific board.
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
[ Do it only for j784s4 ]
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
|
|
Add MIDR entries for Cortex-A55, Cortex-A73 and
Cortex-A75 cores and update the is_coretex_a entries.
Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
|
|
The option ONENAND_BOOT is never set, so remove it. The option
SYS_ONENAND_BOOT was never migrated to Kconfig and any platforms which
supported that have long been removed from the code, so remove the
reference there as well.
Signed-off-by: Tom Rini <trini@konsulko.com>
|
|
Sam Edwards <cfsworks@gmail.com> says:
This is v2 of my "misc. fixes" series, sent to prepare the codebase for more
direct LLVM support in the near future. This series contains several fixes that
I found in the process of preparing that support and which address issues
independent of any future feature or enhancement. I am sending these now, both
so that their inclusion is not delayed by discussion on my upcoming series and
to make the latter more manageable.
Link: https://lore.kernel.org/r/20250315221813.1265193-1-CFSworks@gmail.com
|
|
While the _start label is only intended for use locally to populate the
(hand-written) PE header, the linker script includes ENTRY(_start) which
designates it as the entry point in the output ELF, resulting in linker
warnings under some linkers (e.g. LLVM's lld) due to _start not being a
globally-visible symbol. Since ELF is only an intermediary build
format, and the aforementioned PE header correctly points to _start, the
ENTRY(_start) directive could easily be removed to silence this warning.
However, since some developers who are debugging EFI by analyzing the
intermediary ELF may appreciate having correct entry-point information,
this patch instead promotes the _start labels to global symbols,
silencing the linker warning and making the intermediary ELF reflect the
true entry point.
This patch doesn't affect the final output binaries in any way.
Signed-off-by: Sam Edwards <CFSworks@gmail.com>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
|
|
LLVM's IAS does not (and cannot easily) support the 'adrl'
pseudoinstruction, and ARM developers generally do not consider it
portable across assembler implementations either.
Instead, expand it into the two subtract instructions it would emit
anyway. An explanation of the math follows:
The .+8 and .+4 refer to the same memory location; this is because the
.+4 expression occurs in a subsequent instruction, 4 bytes after the
first. This memory location is the value of the PC register when it is
read by the first sub instruction. Thus, both inner parenthesized
expressions evaluate to the same result: PC's offset relative to
image_base. The subtract instructions then remove one byte each
(low, then high) of the total offset, thereby getting the absolute
address of image_base loaded in r0.
Signed-off-by: Sam Edwards <CFSworks@gmail.com>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
|
|
There are a handful of sections that are not useful in the U-Boot output
binary. At present, the linker script moves these to the end of the
binary, after the _image_binary_end marker symbol, so that they don't
get loaded.
The linker script syntax supports discarding sections that shouldn't be
included in the output. Switch to this instead, to make the intention
clearer and reduce the ELF sections that have to be handled later in the
build. This is also consistent with the other architectures' linker
scripts.
Signed-off-by: Sam Edwards <CFSworks@gmail.com>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
|
|
These are sometimes used by LLVM's code-generator, when it can guarantee that
the memory buffer being passed is aligned on a (4- or 8-byte) boundary. They
can safely be aliased to the unaligned versions.
Signed-off-by: Sam Edwards <CFSworks@gmail.com>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
|
|
LLVM's code generator will sometimes emit calls to __aeabi_memclr. Add an
implementation of this for LLVM compatibility.
Signed-off-by: Sam Edwards <CFSworks@gmail.com>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
|
|
These symbols need to survive the IR-level dead function elimination pass,
since nothing at the IR level is referencing them (calls to these are inserted
later, at codegen time).
Signed-off-by: Sam Edwards <CFSworks@gmail.com>
Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
|
|
The .mmutable section was deprecated in 2012 [1] and finally removed
entirely from U-Boot in 2022 [2], so this special handling is no longer
necessary. Remove it to tidy up the linker script.
[1]: dde3b70dcf3d ("arm: add a common .lds link script")
[2]: 3135ba642f9a ("arm: pxa: Remove CONFIG_CPU_PXA25X")
Signed-off-by: Sam Edwards <CFSworks@gmail.com>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
|
|
As the code is today, we get a warning about "select" statements on
"choice" options not doing anything. In the case of OF_SEPARATE this is
the default so we do not need to do anything here normally to enforce
this.
Signed-off-by: Tom Rini <trini@konsulko.com>
|
|
Christian Marangi <ansuelsmth@gmail.com> says:
This little series adds initial support for Airoha AN7581 SoC.
With the help of some backport patch, this use OF_UPSTREAM
directly.
Posting this to have the targer and the very basic driver.
Ethernet, SNAND and eMMC support is already ready downstream
and will be posted shortly after this gets approved.
Having the first driver ready permits to separately push
dedicate series for SNAND, eMMC and Ethrnet as they all depends
on basic support of clock and reset and nothing else.
Link: https://lore.kernel.org/r/20250314185941.27834-1-ansuelsmth@gmail.com
|
|
Add initial support for Airoha AN7581 SoC. This adds the initial Kconfig
and Makefile entry for the SoC, an U-Boot specific DTSI and initial config
for it. Also add the initial code for CPU and RAM initialization.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
|
|
Udit Kumar <u-kumar1@ti.com> says:
This enables the ESMs and the associated PMIC.
Programming these bits is a requirement to make the watchdog actually reset the board.
After DT sync nodes bucka1 and main_esm has bootph property added in
pmic nodes.
RFC was sent
https://lore.kernel.org/all/20241126063543.2678052-1-u-kumar1@ti.com/
With current patch boot logs
https://gist.github.com/uditkumarti/adb647f86e6d166ea2d0ac98dceb7a9b
reset: https://gist.github.com/uditkumarti/adb647f86e6d166ea2d0ac98dceb7a9b#file-gistfile1-txt-L2344
Link: https://lore.kernel.org/r/20250314110411.2781732-1-u-kumar1@ti.com
|
|
On J7200 processor board MCU_SAFETY_ERROR signal is routed to PMIC for
ESM error handling. The PMIC resets the board on receipt of the signal.
Enable the support for the board by adding ESM PMIC node.
Signed-off-by: Gowtham Tammana <g-tammana@ti.com>
|
|
There's no fan in MedisTek's reference design. Disable it for now.
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
|
|
This patch adds pwm support for MediaTek MT7987 SoC.
Signed-off-by: Sam Shih <sam.shih@mediatek.com>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
|
|
The reserved-memory node 'wmcpu-reserved@50000000' only applies to
linux kernel and is useless in u-boot.
Remove it in *-u-boot.dtsi to make this memory region usable.
Fixes: 2d6962e0618 (arm: mediatek: add support for MediaTek MT7987 SoC)
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
|
|
into next
Assorted fixes, refactorings and additions that are ready, and shave
off some load from upcoming series'.
Improves MMC performance on D1/T113 (missed clock divider), enables
eMMC access on the H616 family (never worked, many thanks to Jernej for
the fix!), DRAM detection fixes for the H616 (now reportedly stable).
Some patches for the upcoming Allwinner A133 SoC support: a few
refactorings, plus the DM clock and pinctrl driver. The DRAM init
routines work, but need some more polishing, that also holds back the
actual enablement patch, which will hopefully follow for v2025.07 still.
Also some preparatory patches for the Allwinner A523 SoC support, for
now just to improve the FEL save/restore code. There will be more patches
coming up for this, ideally also in the coming cycle still.
Gitlab CI passed, and I booted that briefly on some boards.
|
|
Because the Allwinner BootROM always runs in AArch32, even on ARMv8 SoCs,
we need to switch to AArch64 first, but also need to save the CPU state,
when we later may need to return to the BootROM, for continuing with the
FEL USB protocol. This is done in 32-bit code, which we include into the
AArch64 boot assembly file as a series of .word directives, containing
the encoded AArch32 instructions. To be able to change and verify that
code, we also kept an assembly file with the respective 32-bit code, but
just for reference.
As this code is never compiled or assembled - it's just for
documentation - it became stale over time: we didn't really update this
along with the changes we made to the boot code. In particular the FEL
save code was completely missing.
Update that 32-bit assembly file, to match the current version used in
boot0.h, including the FEL save routine. Also update the build
instructions in the comments, to give people an actual chance to
assemble this code.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
|
|
To be able to return to the BootROM when booting via the FEL USB
protocol, we need to save the CPU state very early, which we need to do
in the embedded AArch32 code. At the moment the pointer to the buffer for
that state is located *after* the code, which makes the PC relative
code fragile: adding or removing instructions will change the distance
to that pointer variable.
The "new" Allwinner A523 SoC requires more state to be saved (GICv3
system registers), but we must do that *only* on that SoC. Conditional
compilation sounds like the easiest solution, but would mean that the
distance to that pointer would change.
Solve this rather easily by moving the pointer to the *front* of the
code: we load that pointer in the first instructions, so the distance
would always stay the same. Later in the code we won't need PC relative
addressing anymore, so this code can grow or shrink easily, for instance
due to conditional compilation.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
|
|
To return a 64-bit Allwinner chip back to the 32-bit BootROM code, we
have some embedded AArch32 code that restores the CPU state, before
branching back to the BootROM. At the moment the pointer to the buffer
with that state is located *after* the code, which makes the PC relative
code fragile: adding or removing instructions will change the distance
to that pointer variable.
The "new" Allwinner A523 SoC requires more state to be restored (GICv3
system registers), but we must do that *only* on that SoC. Conditional
compilation sounds like the easiest solution, but would mean that the
distance to that pointer would change.
Solve this rather easily by moving the pointer to the *front* of the
code: we load that pointer in the first instruction, so the distance
would always stay the same. Later in the code we won't need PC relative
addressing anymore, so this code can grow or shrink easily, for instance
due to conditional compilation.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
|
|
It turns out that checking just one write is not enough. Due to
unexplained reasons scan procedure detected double the size. By making
16 dword writes and comparisons that never happens.
New procedure is also inverted. Instead of writing two different values
to base address and some offset and then reading both and comparing
values, simplify this by writing pattern at the base address and then
search for this pattern at some offset.
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Tested-by: Ryan Walklin <ryan@testtoast.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
|
|
Since there is quite a few possible DRAM configurations in terms of bus
width, rank and rows and columns count, size detection algorithm must be
very careful not to test combination which would be bigger than H616 is
actually capable of handling.
Ideally, we should always detect memory aliasing, even for 4 GB memory
size, which is the maximum amount of memory that H616 is capable of
handling. For this reason, we have to configure minimum amount of
supported rows when testing for columns and vice versa. This way test
code will never step out of 4 GB boundary.
While at it, check for 17 rows maximum. This aligns code with BSP DRAM
driver. There is probably no such configuration which would make sense
with 4 GB memory.
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Reviewed-by: Icenowy Zheng <uwu@icenowy.me>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
|
|
The Allwinner A100 SoC has been around for a while, and has now seemingly
been replaced with its close sibling A133.
Add support for the CCU, as far as used by U-Boot proper. Linux has some
basic (clock and pinctrl) support for a while, so we can already use the
existing binding headers.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
|
|
Most Allwinner SoCs (used on 107 out of 172 boards) use a default CPU
frequency of 1008 MHz during the initial setup in the SPL.
Make this the fallback default, in case nothing else is selected, to
simplify the Kconfig stanza and make future additions easier.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
|
|
Some of the X-Power AXP PMICs can be ordered with an alternative I2C
address, for instance an AXP717 could be shipped with address 0x34 or
with address 0x35. Similarly the AXP803 lists two possible addresses.
For DM (DT) based drivers this is no problem, but the Allwinner SPL
code relies on exactly one hardcoded address per PMIC so far.
Add a Kconfig variable that holds the I2C address used by the PMIC
accessed in the SPL, and provide the (mostly only one) supported address
as its default, for the PMICs we use. Boards using the other address
can easily set this in their defconfig.
This effectively moves the hardcoding from C code to Kconfig.
That enables to use the AXP717 on some boards with the new Allwinner
A523 chip, which use the other I2C address there.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
|
|
On the Allwinner D1/R528/T113-s3 SoCs (NCAT2) the factors encoded in
the PLL register describe the doubled clock rate, as in the other SoCs.
Correct for that by always dividing the calculated rate by 2, except on
the H6, where we need a divisor of 4 (no change here).
This corrects the PERIPH0 clock rate as read by the MMC driver, and
actually doubles the MMC performance on those NCAT2 chips.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reported-by: Kuba Szczodrzyński <kuba@szczodrzynski.pl>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
|
|
The CHIP_DIP_SCAN configuration option
is relevant only to ARCH_SUNXI.
Make CHIP_DIP_SCAN dependent
on ARCH_SUNXI so that it does not show up on other goals.
Signed-off-by: Liya Huang <1425075683@qq.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
|
|
https://source.denx.de/u-boot/custodians/u-boot-tegra into next
- More Tegra video improvements
|
|
https://gitlab.denx.de/u-boot/custodians/u-boot-imx into next
CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/25324
- Imply the i.MX thermal driver by default on imx8, imx9, imx8m.
- Add clk_resolve_parent_clk() and fix up iMX clock drivers.
|
