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https://source.denx.de/u-boot/custodians/u-boot-nand-flash
CI: https://source.denx.de/u-boot/custodians/u-boot-nand-flash/-/pipelines/27258
This series address issues found by Andrew Goodbody and mostly drop
driver that are not used by any board
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- Pegatron Chagall, Samsung Galaxy R (GT-I9103) and Captivate Glide
(SGH-i927) support
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As no platforms use this driver anymore let's go ahead and remove it.
Signed-off-by: Tom Rini <trini@konsulko.com>
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As no platforms enable the ethernet driver, remove it.
Signed-off-by: Tom Rini <trini@konsulko.com>
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(SGH-i927) support
The Galaxy R (GT-I9103) and Captivate Glide (SGH-i927) are both Tegra 2
based Samsung smartphones released in 2011. They both feature 1 GB of RAM
and 8 GB of expandable flash memory. The key difference is that the
Captivate Glide has an OLED panel (contrary to LCD in Galaxy R) and a
QWERTY keyboard in form factor of a slider.
Signed-off-by: Ion Agorria <ion@agorria.com>
Reviewed-by: Svyatoslav Ryhel <clamor95@gmail.com>
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
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Configure pixel clock and data enable polarity according to panel flags.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
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The Pegatron Chagall (originally built by Pegatron, but later rebranded by
other vendors under names Fujitsu Stylistic M532, Olivetti Olipad 3,
Siragon 4N, Realpad Bunaken, DNS AirTab P110w / P110g etc) is a mostly
business-oriented tablet sold in 2012 in different variants, mostly in
Europe, with slight differences in storage size (16GB/32GB) and presence
of built-in cellular modem.
Tested-by: Raffaele Tranquillini <raffaele.tranquillini@gmail.com>
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
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Previously software based AES encryption was used with previously known
device specific keys (SBK), now that we have AES driver we can simply
delegate this to the engine without prior knowledge of the key (assuming
it is still loaded).
Signed-off-by: Ion Agorria <ion@agorria.com>
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Enable BSEV for devices that support u-boot self-upgrading feature.
Signed-off-by: Ion Agorria <ion@agorria.com>
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Add device tree nodes for BSEA and BSEV devices on Tegra20 and Tegra30.
Signed-off-by: Ion Agorria <ion@agorria.com>
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Now that we have working AES engine driver we can request the warmboot code
to be encrypted and signed with SBK if the device requires so. This
unlocks LP0 support for most devices in the wild as they use ODM Production
Secure.
We are not aware of any "ODM Production Open" device nor have access to
thus this has not been tested on one, merely added for completeness.
Signed-off-by: Ion Agorria <ion@agorria.com>
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This driver allows using Tegra AES engines within BSEV and BSEA blocks to
encrypt and decrypt data using different AES algorithms.
One use case is allowing u-boot to self update by using the already loaded
AES key in the engine's SBK slot by the bootrom.
Particular care must be taken as chainloaded u-boot's may not have the SBK
slot loaded as the vendor bootloader erases it before leaving it.
Signed-off-by: Ion Agorria <ion@agorria.com>
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Move a set of helpers used in warmboot code to more appropriate AP and FUSE
locations.
Signed-off-by: Ion Agorria <ion@agorria.com>
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https://source.denx.de/u-boot/custodians/u-boot-stm
CI: https://source.denx.de/u-boot/custodians/u-boot-stm/-/pipelines/27236
- Add support for STM32 TIMERS and STM32 PWM on STM32MP25
- Add STM32MP13xx SPL and OpTee-OS start support
- Fix header misuse in stm32 reset drivers
- Fix STMicroelectronics spelling
- Fix clk-stm32h7 wrong macros used in register read
- Fix PRE_CON_BUF_ADDR on STM32MP13
- Fix clock identifier passed to struct scmi_clk_parent_set_in
- Fix stm32 reset for STM32F4/F7 and H7
- Enable OF_UPSTREAM_BUILD_VENDOR for stm32mp13_defconfig
- Add STM32MP23 SoC and stm32mp235f-dk board support
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https://source.denx.de/u-boot/custodians/u-boot-socfpga
This pull request includes updates for the SoCFPGA platform intended for the 2025.10 release
cycle. The highlights focus on enabling the Power Manager for Agilex5, NAND boot support
enhancements, and various bug fixes and cleanups across SoCFPGA components.
CI:
* https://source.denx.de/u-boot/custodians/u-boot-socfpga/-/pipelines/27221
Summary of changes:
Agilex5 Power Manager:
* Initial driver support and DT bindings are added for the Agilex5 Power Manager, enabling
better power domain control.
NAND Boot Support for Agilex5:
* SPL support for NAND boot is enabled.
* UBI/UBIFS support is configured in defconfigs.
* Memory layout updates (malloc and BSS relocation) ensure proper boot behavior.
Code Quality Improvements:
* Coverity and runtime bug fixes (e.g., jtag_usercode check, sub-device conditionals).
* Several cleanup patches addressing formatting, logic, and initialization issues.
General Maintenance:
* SPDX license tags and header include fixes.
* Device tree updates to limit SPI clock frequency and other minor adjustments.
These contributions come from Alif Zakuan Yuslaimi, Andrew Goodbody, Dinesh Maniyam, Naresh
Kumar Ravulapalli, and Tingting Meng.
This patch set has been tested on Agilex 5 devkit.
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[1] https://git.kernel.org/pub/scm/linux/kernel/git/devicetree/devicetree-rebasing.git
Perform a few fixups in our dts* files to match upstream changes.
Signed-off-by: Tom Rini <trini@konsulko.com>
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Agilex5 FSBL is required to disable the power of unused peripheral SRAM
blocks to reduce power consumption.
Introducing a new power manager driver for Agilex5 which will be called
as part of Agilex5 SPL initialization process.
This driver will read the peripheral handoff data obtained from the
bitstream and will power off the specified peripheral's SRAM from the
handoff data values.
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
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Sub-device information is retrieved from the JTAG ID in Boot Scratch
Cold 4 Register. This interface is introduced to allow device-specific
errata workarounds to be applied in the future, based on the detected
sub-device type.
Signed-off-by: Tingting Meng <tingting.meng@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@intel.com>
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A redundant comparison (jtag_usercode >= 0) was removed from the
condition checking jtag_usercode. Since jtag_usercode is an unsigned
integer, the check for non-negativity was always true. The code was
simplified to resolve the Coverity warning.
Signed-off-by: Tingting Meng <tingting.meng@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@intel.com>
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Enable nand as one of the bootable media in SPL.
Signed-off-by: Dinesh Maniyam <dinesh.maniyam@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
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This configuration is not valid for N5X; removing it.
Signed-off-by: Naresh Kumar Ravulapalli <nareshkumar.ravulapalli@altera.com>
Signed-off-by: Tien Fong Chee <tien.fong.chee@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
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All the source code of secure_vab.c and secure_vab.h are from Intel
and Altera. Updating the license to use either GPL-2.0 or
BSD-3-Clause because this copy of code may be used for open source
and internal project.
Signed-off-by: Naresh Kumar Ravulapalli <nareshkumar.ravulapalli@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
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Appropriate header files are included according to U-Boot
coding style.
Signed-off-by: Tien Fong Chee <tien.fong.chee@altera.com>
Signed-off-by: Naresh Kumar Ravulapalli <nareshkumar.ravulapalli@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
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This patch is to set spi-max-freq to 50Mhz. This will add support to the
driver to set the operation speed according to the slave device up to
50Mhz. Without this node, the driver just can adjust the operation speed
to the default speed which is far below the best
operation speed of the SPI slave device.
Signed-off-by: Dinesh Maniyam <dinesh.maniyam@intel.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
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Fix STMicroelectronics spelling in comments.
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
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Since SYS_MALLOC_F_LEN increasing to 0x2100000 on STM32MP13, the
pre-console buffer is overlapped by stack (0xC0400000 + 0x2100000),
so the this buffer must be moved just before the bootstage to avoid issue.
After this patch the pre-relocation memory mapping for STM32MP13x is:
C3000000 = Bootstage CONFIG_BOOTSTAGE_STASH_ADDR
C2FFF000 = PreConsole CONFIG_PRE_CON_BUF_ADDR
with size CONFIG_PRE_CON_BUF_SZ = 4096
C0400000 = start for stack with CONFIG_CUSTOM_SYS_INIT_SP_ADDR
including CONFIG_SYS_MALLOC_F_LEN
C0000000 = Load Address of U-Boot with CONFIG_TEXT_BASE
Fixes: 93c962c7af7e ("configs: stm32mp13: increase SYS_MALLOC_F_LEN to 0x210000")
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
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Cosmetic update to replace space by tab in sys_proto.h
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
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Add U-Boot specific file for stm32mp235f-dk board
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
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Add STM32MP23 support which is a cost optimized of STM32MP25.
More details available at:
https://www.st.com/en/microcontrollers-microprocessors/stm32mp2-series.html
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
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Add SPL specific DT additions to DH STM32MP13xx DHCOR DHSBC . These
include I2C3 configuration which is required to access the PMIC,
PMIC regulator and QSPI NOR bootph-all properties to allow SPL to
configure PMIC buck regulators and load from QSPI NOR respectively,
etzpc bus switch to simple-bus to prevent interference from TFABOOT
specific configuration, and RCC configuration to define clock tree
configuration used by this platform.
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Marek Vasut <marek.vasut@mailbox.org>
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Add DT additions required by U-Boot SPL to bring up the hardware.
This includes binman node to generate STM32 Image v2.0 which can be
booted by the BootROM, clock entries used by the SPL clock driver
during clock tree initialization, and syscon-reboot node so U-Boot
can reset the system without having to rely on PSCI call.
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Marek Vasut <marek.vasut@mailbox.org>
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Add DRAM settings for 512 MiB of DRAM variant of DH STM32MP13xx DHCOR DHSBC.
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Marek Vasut <marek.vasut@mailbox.org>
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Factor out common parts of STM32MP15xx DRAM controller configuration DT
description into stm32mp1-ddr.dtsi and introduce stm32mp13-ddr.dtsi which
describes STM32MP13xx DRAM controller configuration in DT.
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Marek Vasut <marek.vasut@mailbox.org>
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The STM32MP13xx SRAM size is half that the SRAM size on STM32MP15xx,
disable early dcache start on STM32MP13xx as the TLB itself takes
about a quarter of the SPL size. The dcache will be enabled later,
once DRAM is available and TLB can be placed in DRAM.
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Marek Vasut <marek.vasut@mailbox.org>
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Add hardware initialization for the STM32MP13xx in SPL. This is
similar to STM32MP15xx except the code has to enable MCE to bring
DRAM controller up later.
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Marek Vasut <marek.vasut@mailbox.org>
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Introduce Kconfig options used by SPL on STM32MP13xx and isolate
the Kconfig options only used in case TFA BL2 is used as a SPL
behind CONFIG_TFABOOT dependency.
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Marek Vasut <marek.vasut@mailbox.org>
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Add support for STM32MP25 SoC.
Identification and hardware configuration registers allow to read the
timer version and capabilities (counter width, ...).
So, rework the probe to avoid touching ARR register by simply read the
counter width when available. This may avoid messing with a possibly
running timer.
Also add useful bit fields to stm32-timers header file.
Signed-off-by: Cheick Traore <cheick.traore@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
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https://source.denx.de/u-boot/custodians/u-boot-at91
Second set of u-boot-at91 features for the 2025.10 cycle:
This feature set includes the addition of new sama7d65 SoC and a new
board named sama7d65-curiosity.
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Signed-off-by: Andrew Davis <afd@ti.com>
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I updated the mailmap a while back but it's nice to have authorship
comments adjusted too.
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
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Add the basic Kconfig options, addresses and other values for the
existing Kconfig settings for the new Allwinner A523/T527/H728 SoC.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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Add reverse engineered code to add support for DDR3 DRAM chips on the
Allwinner A523 DRAM controller.
The timings are copying what boot0 set up on the X96QPro+ TV box, though
they seem quite suboptimal, with longer latencies that would be required
for DDR3-1600. The chips are also actually capable of DDR3-1833, so
there is room for future improvement.
Signed-off-by: Mikhail Kalashnikov <iuncuim@gmail.com>
[Andre: rework to copy from H616 DDR3 driver, calculate timings]
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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DRAM init code, as per reverse engineering and matching against
previous SoCs. As usual no real documentation, and the DRAM controller
is the usual mixture of close-to-previous IP and new inventions.
This version supports LPDDR4 for now only, as seen on the early boards.
This needs improvements, but it can be done later.
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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This adds the early A523 clock setup code, for the basic peripheral PLL
and the basic bus clocks (APB/AHB). This is quite close to the existing
H6 and H616 clock code, so this shares the same file. A few bits and bobs
are different, though, so filter for the A523 in a few occasions.
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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The cpu_sunxi_ncat2.h header file contains addresses of some peripherals
that are needed for the SPL, for chips that belong to the "NCAT2"
generation.
The Allwinner A523 is a member of this group, but a few addresses
differ, and we need a few more addresses, for playing with the core
reset, for instance.
Add the new addresses needed for the A523 and guard existing definitions
that conflict with that new chip.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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The watchdog in the Allwinner A523 SoC differs a bit from the one in the
previous SoCs: it lives in a separate register frame, so no longer
inside some timer device, and it manages to shuffle around some
registers a bit. But it also conveniently adds a direct reset
functionality, so we don't need to use a dummy timeout period.
Avoid introducing a new MMIO register frame C struct, but just define
the one needed register offset as a macro. Then just trigger this new
direct reset functionality in the A523 specific reset_cpu()
implementation.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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The Allwinner A523 features 8 CPU cores, organised in two clusters, both
driven by separate PLLs. Also there is the DSU PLL, which clocks the
hardware that connects the cores to the rest of the system.
And while the PLL registers itself are very similar, they are located in
a separate register frame, outside the main CCU, and also the register
controlling the CPU clock source (mux) is different.
Provide a separate function that reparents the two clusters and the DSU,
while their PLLs are programmed. For the actual PLL programming, we rely
on the existing shared routine.
The selection between the new A523 routine and the existing code is made
with C if statements, but since the choice is effectively made at compile
time already, the compiler optimises away the other code paths, leaving
just the one required function in.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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When we program the CPU PLL, we need to switch the CPU clock source away
from the PLL temporarily, then switch it back, once the PLL has
stabilised.
The CPU CLK register will be different on the A523, so move the current
code into a separate function, to allow using a different version of
that later for the A523.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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The SPL initial clock setup code for the Allwinner H6 and H616 SoCs uses
a simple CPU PLL setup routine, which programs all register bits at once,
then waits for the LOCK bit to clear.
The manual suggests to follow a certain procedure for bringing up any
PLLs, which involves several register writes, one at a time, and some
delays. Also the H616 and the new A523 require some tiny changes in this
sequence, and the different SoCs also feature some extra bits here and
there, which we should not just clear.
So factor out the PLL setup routine, and make it follow the manual's
suggestion. This will read the PLL register at the beginning, then tweak
the bits we need to manipulate, and writes the register several times on
the way. This allows to cover the specific bits for different SoCs.
Besides improving the reliability of the PLL setup, this helps with the
A523, which requires *three* CPU PLLs to be programmed.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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The Allwinner PLLs share most of their control bits, they differ mostly
in the factors and dividers.
Drop the PLL specific definition of those common bits, and use one
shared macro, for all PLLs.
This requires changing the users in the SPL clock and DRAM code.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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