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This symbol is not something that the user should be enabling or
disabling but rather the developer for a particular board should select
it when required.
This is mostly size neutral, however a few places do have changes. In
the case of i.MX6ULL systems, it is always the case that
arch_misc_init() could call setup_serial_number() and do useful work,
but was not enabled widely, but now is. In the case of i.MX23/28
systems, we should be able to call mx28_fixup_vt() again here, so do so.
Finally, some platforms were calling arch_misc_init() and then not doing
anything and this results in removing the option.
Acked-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
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Svyatoslav Ryhel <clamor95@gmail.com> says:
Add uclass for HW AES cryptographic devices found on some devices, like
Tegra20/Tegra30 SoC AES engine.
Link: https://lore.kernel.org/r/20250629105711.24687-1-clamor95@gmail.com
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Create a basic test suit for AES DM uclass that covers all available
operations.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
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https://gitlab.denx.de/u-boot/custodians/u-boot-imx
CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/27010
- Fix the i.MX8M Nano GPU path.
- Enable RNG support for KASLR on Toradex i.MX8 boards.
- Enable watchdog and clock driver for imx6ulz_smm_m2b.
- Tighten dependencies on CMD_BLOB.
- Remove the rest of i.MX31 support.
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- SH Ether clean ups, RZ/A1 clean ups, RZ/A1 Genmai support
- Gen3 EEPROM DT node clean up
- V4H SA0 BootROM compatible binman etype, SCIF compatible SREC
generation for Gen4
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Add r7s72100 Genmai board support. Serial console, NOR Flash and
Ethernet are known to work however on-board SDRAM is not yet enabled.
Signed-off-by: Magnus Damm <damm@opensource.se>
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Replace current ad-hoc generation of SA0 header with renesas_rcar4_sa0 binman
etype on Renesas R-Car V4H. The new binman etype generates header which is
almost identical to the current ad-hoc SA0 header, with one difference, the
load length matches the actual payload size, which slightly improves boot time.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
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Most of the sysinfo EEPROM node eeprom@50 is now part of the core DTs,
remove duplicate DT properties from *-u-boot.dtsi . Adjust the phandle
reference to i2c-eeprom in sysinfo node using <&{i2c_*/eeprom@50}> to
avoid need for DT label. No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
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Add Renesas R-Car Gen4 SCIF/HSCIF loader compatible SREC generation.
This is a regular U-Boot SPL SREC augmented with a short header which
describes where to store the received data and how much data to store.
This header is interpreted by the R-Car Gen4 BootROM SCIF/HSCIF loader.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
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Convert u-boot-spl.bin instead of u-boot-spl ELF into SCIF loader
compatible SREC. The u-boot-spl.bin includes SPL DT, while the ELF
does not, which leads to failure to start SPL via SCIF loader due
to missing SPL DT. Fix this by using u-boot-spl.bin which includes
the DT.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
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Add the 16, 32 and 64bit versions of the non-endian {clr,set,clrset}bits
macros.
Signed-off-by: Tom Rini <trini@konsulko.com>
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The SoC node is called 'soc@0', even on NXP branch 6.6-fslc. This fixes
the boot on i.MX8M Nano DualLite, as there is no GPU.
Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
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With the removal of the last i.MX31 platform we can remove the rest of
the underlying architecture code as well.
Fixes: f247354708ec ("arm: Remove mx31pdk board")
Signed-off-by: Tom Rini <trini@konsulko.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
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Green Eco"
Romain Gantois <romain.gantois@bootlin.com> says:
This is version one of my series which enables Ethernet support on the BBGE
board. This requires three main changes:
- Describing the MAC<->PHY link and DP83867 PHY accurately in the device
tree
- Enabling the RGMII1 pinmux configuration
- Enabling the DP83867 driver
These changes are all applied in patch 2.
Patch 1 enables excluding the DP83867 driver from SPL. This is done to
avoid size issues when adding the DP83867 driver to the am335x-evm
defconfig.
Link: https://lore.kernel.org/r/20250626-bbge-ethernet-v1-0-5b544fb1898f@bootlin.com
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Currently, the Ethernet interface of the BBGE board isn't properly
supported.
To support this interface, describe the MAC<->PHY RGMII link and the
DP83867 PHY in the BBGE device tree. Enable the DP83867 PHY driver in
U-Boot Proper and mux the relevant RGMII lines.
Signed-off-by: Romain Gantois <romain.gantois@bootlin.com>
Tested-by: Judith Mendez <jm@ti.com>
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ft_board_setup_ex()"
João Paulo Gonçalves <jpaulo.silvagoncalves@gmail.com> says:
In some use cases, board-specific device tree changes must not be overwritten
by system fixups. Although U-Boot provides ft_board_setup_ex() for this
purpose, it is currently only used on TI Keystone. This series makes
ft_board_setup_ex() a generic option, allowing its use by other architectures
and boards.
Additionally, considering that Toradex Verdin-AM62P hardware lifetime
guarantees are based on a 105°C junction temperature (while TI AM62Px supports
up to 125°C), this series implements necessary changes within TI K3 AM62P and
Toradex board code. These changes include exporting common fixup device Tree
functions used in TI K3 for board-code access and also fixup for AM62P thermal
zones to correctly reflect the number of CPU nodes according to the SoC part
number.
Link: https://lore.kernel.org/r/20250623-am62p-fdt-fixup-trip-points-v1-0-12355eb6a72f@toradex.com
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TI AM62Px devices support CPU throttling based on thermal alerts.
However, the device tree assumes a 4-core configuration. Since the AM62P
also supports 2-core configurations, add a fixup to dynamically adjust
the cooling-device nodes within thermal zones based on the actual number
of CPU cores available.
Signed-off-by: João Paulo Gonçalves <joao.goncalves@toradex.com>
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Avoid code duplication by making the common TI K3 device tree fixup
functions to be reusable by board-specific code.
Signed-off-by: João Paulo Gonçalves <joao.goncalves@toradex.com>
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In some use cases, board-specific device tree changes must not be
overwritten by system fixups. Although U-Boot provides
ft_board_setup_ex() for this purpose, it is currently only used on TI
Keystone. Make ft_board_setup_ex() to be a generic option, allowing its
use by other architectures/boards. To maintain backward compatibility,
enable it by default on TI Keystone.
Signed-off-by: João Paulo Gonçalves <joao.goncalves@toradex.com>
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This file does not need <asm/gpio.h> so remove it. This file does
however need <linux/types.h> so add that in. This also shows that
arch/arm/mach-rockchip/rk3399/rk3399.c and board/lg/star/star.c were
indirectly getting <asm/gpio.h> from here, so add <asm/gpio.h> to them.
Signed-off-by: Tom Rini <trini@konsulko.com>
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simple bus node and drivers not bringing up any value for mini
configuration that's why remove it and disable drivers for it to save some
space.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/a51b11fa21c504a19701ebdccc1e61e899e1aed5.1751016029.git.michal.simek@amd.com
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As part of the recent cleanup of dt-bindigns header files we did not
remove our copy of dt-bindings/clock/xlnx-zynqmp-clk.h at the time. This
is because the difference between ours and current upstream is that
current upstream has a #warning to not use it and to instead use
xlnx-zynqmp-clk.h. So we change zynqmp-clk-ccf.dtsi to use the other
and upstream-only file and then delete our dt-bindings file.
Signed-off-by: Tom Rini <trini@konsulko.com>
Tested-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/20250612181128.340232-1-trini@konsulko.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
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Select PINCTRL_TH1520 in CPU Kconfig entry and update defconfig for
existing TH1520-based boards to ensure PINCTRL is enabled.
Signed-off-by: Yao Zi <ziyao@disroot.org>
Acked-by: Leo Yu-Chi Liang <ycliang@andestech.com>
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Describe the three pin controllers integrated in TH1520 SoC. Since we
don't have support for clocks in the AON region, a dummy fixed-clock
node is added to supply the pin controller locating in it.
Signed-off-by: Yao Zi <ziyao@disroot.org>
Acked-by: Leo Yu-Chi Liang <ycliang@andestech.com>
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Test for big-endian either via __RISCVEB__ which migth be
rather old, or check the BYTE_ORDER if the compiler defines
it (which should be any modern gcc like v12)
Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
Acked-by: Leo Yu-Chi Liang <ycliang@andestech.com>
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Add support to build code big-endian if the board supports
it. Updates the makefile to pass the correct compiler and
elf flags.
Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
Reviewed-by: Tom Rini <trini@konsulko.com>
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Preserve CLINT node for SPL, whose IPI functionality is essential for
operation of a multi-core system.
Signed-off-by: Yao Zi <ziyao@disroot.org>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
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On coldboot, only HART 0 among the four HARTs of TH1520 is brought up by
hardware, and the remaining HARTs are in reset states, requiring manual
setup of reset address and deassertion to function normal. Introduce a
routine to do the work.
Signed-off-by: Yao Zi <ziyao@disroot.org>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
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C910 cores integrated in TH1520 SoC provide various customized CSRs for
configuring core behavior, including cache coherency and timing, branch
predication, and clock gating for internal components.
This patch sets them up for efficient operation and satisfying
requirements of an SMP system.
Signed-off-by: Yao Zi <ziyao@disroot.org>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
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Although timer component of the CLINT isn't fully compatible with the
generic RISC-V ACLINT, the IPI component behaves the same.
As the CLINT doesn't have corresponding riscv_aclint_timer driver
available, let's try looking for a compatible SYSCON device directly
when no riscv_aclint_timer device could be found on IPI initialization.
Signed-off-by: Yao Zi <ziyao@disroot.org>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
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The current file defines a struct gpio_regs identical to the one in
<asm/mach-imx/gpio.h>. To eliminate code duplication and align with
the approach used for i.MX8M, include the common header instead of
redefining the struct.
Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
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The commit e8a9521e649f
("vf500/vf610: synchronise device trees with linux")
has synchronized U-Boot's DTS with v5.19 Linux kernel.
It turned out that in Linux's upstream iomuxc node description the
'fsl,mux_mask' was missing, so the U-Boot's pinctrl driver for NXP's
Vybrid SoC was not working properly.
As by default the mux mask was set to 0, for example the vf610 based
boards (like BK4) were bricked, due to misconfiguration of gpio at
early boot stage.
The fix for all NXP eligible boards is to define .mux_mask field for
soc specific *pinctrl_soc_info structure and use it directly in pinctrl
MMIO driver, without the need to read the "fsl,mux_mask" property from
device tree.
This change brings the NXP's pinctrl driver in U-Boot closer to Linux
upstream one.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com> #for i.MX8ULP
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In the contemporary U-Boot the "spi-flash" compatible is used only when
CONFIG_$(PHASE_)SPI_FLASH_TINY is defined so spi-nor-tiny.c is compiled.
As vf610 devices are not using SPL at all, the SPI_FLASH_TINY is not
defined and no QSPI flash child nodes are considered as valid ones.
The result is that the 'sf probe' command fails and SPI NOR memory is not
accessible on e.g. BK4 device.
The fix is to use proper compatible - in this case "jedec,spi-nor".
Signed-off-by: Lukasz Majewski <lukma@denx.de>
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This reverts both commit 4628730ee6c4 ("mach-k3: add runtime memory
carveouts for MMU table") as well as commit b77066d73261 ("mach-k3: add
dynamic mmu fixups for SPL stage") as some feedback from previous
iterations was missed.
This reverts commit b77066d73261855af406422fbbe28a5d527f4dbf and commit
4628730ee6c40864dbe475e4ca91e47a92f371fe.
Signed-off-by: Tom Rini <trini@konsulko.com>
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Ilias Apalodimas <ilias.apalodimas@linaro.org> says:
Instructions that lead ito an exception in the hypervisor can't modify two
CPU registers at once for the ARM ISA.
These instructions cannot be emulated by KVM as they do not produce
syndrome information data that KVM can use to infer the destination
register, the faulting address, whether it was a load or store, or
if it's a 32 or 64 bit general-purpose register.
As a result an external abort is injected from QEMU, via ext_dabt_pending.
Link: https://lore.kernel.org/r/20250618065828.1312146-1-ilias.apalodimas@linaro.org
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commit 2e2c2a5e72a8 ("arm: qemu: override flash accessors to use virtualizable instructions")
explains why we can't have instructions with multiple output registers
when running under QEMU + KVM and the instruction leads to an exception
to the hypervisor.
USB XHCI is such a case (MMIO) where a ldr w1, [x0], #4 is emitted for
xhci_start() which works fine with QEMU but crashes for QEMU + KVM.
These instructions cannot be emulated by KVM as they do not produce
syndrome information data that KVM can use to infer the destination
register, the faulting address, whether it was a load or store, or
if it's a 32 or 64 bit general-purpose register.
As a result an external abort is injected from QEMU, via ext_dabt_pending
to KVM and we end up throwing an exception that looks like
U-Boot 2025.07-rc4 (Jun 10 2025 - 12:00:15 +0000)
[...]
Register 8001040 NbrPorts 8
Starting the controller
"Synchronous Abort" handler, esr 0x96000010, far 0x10100040
elr: 000000000005b1c8 lr : 000000000005b1ac (reloc)
elr: 00000000476fc1c8 lr : 00000000476fc1ac
x0 : 0000000010100040 x1 : 0000000000000001
x2 : 0000000000000000 x3 : 0000000000003e80
x4 : 0000000000000000 x5 : 00000000477a5694
x6 : 0000000000000038 x7 : 000000004666f360
x8 : 0000000000000000 x9 : 00000000ffffffd8
x10: 000000000000000d x11: 0000000000000006
x12: 0000000046560a78 x13: 0000000046560dd0
x14: 00000000ffffffff x15: 000000004666eed2
x16: 00000000476ee2f0 x17: 0000000000000000
x18: 0000000046660dd0 x19: 000000004666f480
x20: 0000000000000000 x21: 0000000010100040
x22: 0000000010100000 x23: 0000000000000000
x24: 0000000000000000 x25: 0000000000000000
x26: 0000000000000000 x27: 0000000000000000
x28: 0000000000000000 x29: 000000004666f360
Code: d5033fbf aa1503e0 5287d003 52800002 (b8004401)
Resetting CPU ...
There are two problems making this the default.
- It will emit ldr + add or str + add instead of ldr/str(post increment)
in somne cases
- Some platforms that depend on TPL/SPL grow in size enough so that the
binary doesn't fit anymore.
So let's add proper I/O accessors add a Kconfig option
to turn it off by default apart from our QEMU builds.
Reported-by: Mikko Rapeli <mikko.rapeli@linaro.org>
Tested-by: Mikko Rapeli <mikko.rapeli@linaro.org>
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
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This board is currently unmaintained. Remove it.
Acked-by: Angelo Dureghello <angelo@kernel-space.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
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Per section 14.2.1.3 Kick Protection Registers of AM62A TRM[1],
there is no partition 5. Delete it.
[1] https://www.ti.com/lit/pdf/spruj16
Fixes: b511b371ad76 ("arm: mach-k3: introduce basic files to support the am62a")
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Bryan Brattlof <bb@ti.com>
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On platforms with spl splash support i.e CONFIG_VIDEO=y, the top of DDR
is reserved for the framebuffer.
The size for the framebuffer is computed at runtime by video_reserve.
During the MMU configuration an entry corresponding to the framebuffer
should be dynamically created to properly map the required space for the
framebuffer.
Therefore this patch adds k3_spl_mem_map_init which adds the required
MMU entry by querying the gd after the framebuffer size has been
computed in spl_reserve_video_from_ram_top.
For non VIDEO=y platforms, the added k3_spl_mem_map_init function gets
optimized out of the final binary so overall, the spl size is not
impacted[1].
[1]: Tested on clang 19.1.7 and gcc 15.1.1
Signed-off-by: Anshul Dalal <anshuld@ti.com>
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In u-boot we only provide a single MMU table for all k3 platforms,
this does not scale for devices with reserved memory outside the range
0x9e780000 - 0xa0000000 or for devices with < 2GiB of memory (eg
am62-SIP with 512MiB of RAM).
To properly configure the MMU on various k3 platforms, the
reserved-memory regions need to be queried at runtime from the
device-tree and the MMU table should be updated accordingly.
This patch adds the required fixups to the MMU table (during proper
U-boot stage) by marking the reserved regions as non cacheable and
keeping the remaining area as cacheable.
For the A-core SPL, the 128MiB region starting from SPL_TEXT_BASE
is marked as cacheable i.e 0x80080000 to 0x88080000.
The 128MiB size is chosen to allow for future use cases such as falcon
boot from the A-Core SPL which would require loading kernel image from
the SPL stage. This change also ensures the reserved memory regions that
all exist past 0x88080000 are non cacheable preventing speculative
accesses to those addresses.
Signed-off-by: Anshul Dalal <anshuld@ti.com>
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Heinrich Schuchardt <heinrich.schuchardt@canonical.com> says:
The sandbox is used for a lot of generic development, we should run the
UEFI tests there, too.
The TPM emulation on the sandbox is incomplete. Disable the TCG test on
sandbox.
Link: https://lore.kernel.org/r/20250617061945.9266-1-heinrich.schuchardt@canonical.com
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The sandbox is used for a lot of generic development, we should run the
UEFI tests there, too.
Reported-by: Javier Martinez Canillas <javierm@redhat.com>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Javier Martinez Canillas <javierm@redhat.com>
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This is same as done in commit 27cd65ca1bf1 ("mach-k3: am62ax: enable
caches for the SPL stage").
This is resulting in ~2x speedup in the A53 SPL stage.
Signed-off-by: Heiko Thiery <heiko.thiery@gmail.com>
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CONFIG_LTO enables Link Time Optimizations that helps in reducing binary
size. The config has been validated on all K3 platforms so can be safely
enabled.
Signed-off-by: Anshul Dalal <anshuld@ti.com>
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Heinrich Schuchardt <heinrich.schuchardt@canonical.com> says:
To implement the EFI_SYSTEM_TABLE_POINTER we need 4 MiB aligned
memory.
On the sandbox LMB uses addresses relative to the start of a page aligned
RAM buffer allocated with mmap(). This leads to a mismatch of alignment
between EFI which uses pointers and LMB which uses phys_addr_t.
Ensure that the RAM buffer used for LMB is 4 MiB aligned.
Provide a unit test for efi_alloc_aligned_pages() verifying this alignment.
Do not overwrite RAM size in dram_init().
Link: https://lore.kernel.org/r/20250608075428.32631-1-heinrich.schuchardt@canonical.com
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To implement the EFI_SYSTEM_TABLE_POINTER we need 4 MiB aligned
memory.
On the sandbox LMB uses addresses relative to the start of a page aligned
RAM buffer allocated with mmap(). This leads to a mismatch of alignment
between EFI which uses pointers and LMB which uses phys_addr_t.
Ensure that the RAM buffer used for LMB is 4 MiB aligned.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
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Aristo Chen <jj251510319013@gmail.com> says:
This series introduces a validation step in mkimage to ensure that all image
names referenced under the /configurations node of a FIT source (ITS) are
actually defined under the /images node.
### Motivation
When using mkimage to build FIT images, it's easy to mistakenly reference
nonexistent image nodes in configurations (e.g., referencing a missing `fdt` or
`firmware` node). Such issues are often not caught until runtime in U-Boot.
This series aims to catch these errors early during FIT image creation by
validating the configuration references in mkimage itself.
Link: https://lore.kernel.org/r/20250610074121.8308-1-aristo.chen@canonical.com
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The phycore-am62x build was broken due to mkimage reporting an undefined
'image "tifsstub-hs"' in the 'loadables' property of the FIT configuration.
This occurred because the `loadables` field referenced `tifsstub-hs`,
`tifsstub-fs`, and `tifsstub-gp`, but no corresponding nodes were defined
under /images.
This patch was inspired by commit 622f826bf025704cbcc4f39252d4a83129a9cabb
("arm: dts: phycore-am62x: Package TIFS Stub"). It resolves the issue by
adding proper Binman nodes for each TIFS variant (`tifsstub-hs`,
`tifsstub-fs`, and `tifsstub-gp`).
Signed-off-by: Aristo Chen <aristo.chen@canonical.com>
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Sughosh Ganu <sughosh.ganu@linaro.org> says:
The LMB module has a bunch for API's which are used for allocating
memory. There are a couple of API's for requesting memory, and two
more for reserving regions of memory. Replace these different API's
with a single one, lmb_alloc_mem(). The type of allocation to be made
is specified through one of the parameters to the function.
Additionally, the two API's for reserving regions of memory,
lmb_reserve() and lmb_alloc_addr() are the same with one
difference. One can reserve any memory region with lmb_reserve(),
while lmb_alloc_addr() actually checks that the memory region being
requested is part of the LMB memory map. Reserving memory that is not
part of the LMB memory map is pretty futile -- the allocation
functions do not allocate memory which has not been added to the LMB
memory map.
This series also removes the functionality allowing for reserving
memory regions outside the LMB memory map. Any request for reserving a
region of memory outside the LMB memory map now returns an -EINVAL
error.
Certain places in the common code using the LMB API's were not
checking the return value of the functions. Checks have been added for
them. There are some calls being made from the architecture/platform
specific code which too do not check the return value. Those have been
kept the same, as I do not have the platform with me to check if it
causes any issues on those platforms.
In addition, there is a patch which refactors code in
lmb_overlaps_region() and lmb_can_reserve_region() so that both
functionalities can be put in a single function, lmb_overlap_checks().
Finally, a new patch has been added which checks the return value of
the lmb allocation function before copying the device-tree to the
allocated address.
Link: https://lore.kernel.org/r/20250617104346.1379981-1-sughosh.ganu@linaro.org
[trini: Rework arch/arm/mach-snapdragon/board.c merge]
Signed-off-by: Tom Rini <trini@konsulko.com>
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The board_late_init() function allocates memory for a bunch of
environment variables, including fdt_addr_r. The device-tree then gets
copied to the memory pointed to by fdt_addr_r. However, the memory
allocation request can fail, in which case the address that is being
written to would not be allocated. Add a check that the memory
allocation has succeeded before copying the device-tree.
Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org>
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