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2023-05-21ddr: imx93: Add 625M bypass clock supportJacky Bai
Add 625M bypass clock that may be used DRAM 625M bypass mode support. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-05-21ddr: imx9: Add workaround for DDRPHY rank-to-rank errataYe Li
According to DDRPHY errata, the Rank-to-Rank Spacing and tphy_rdcsgap specification does not include the Critical Delay Difference (CDD) to properly define the required rank-to-rank read command spacing after executing PHY training firmware. Following the errata workaround, at the end of data training, we get all CDD values through the MessageBlock, then re-configure the DDRC timing of WWT/WRT/RRT/RWT with comparing MAX CDD values. Signed-off-by: Ye Li <ye.li@nxp.com> Acked-by: Peng Fan <peng.fan@nxp.com>
2023-05-21arm: dts: imx93: add tmuPeng Fan
Add tmu nodes and thermal zone Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-05-21arm: dts: imx93: sync device tree with LinuxPeng Fan
Sync device tree with next-20230426 Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-05-21imx9: allow to bootaux Mcore with input addressYe Li
Currently bootaux only supports to boot M33 core from TCM. Since ATF has changed to use x2 parameter for M33 image address, update the bootaux command to use input address, so we can support boot from any possilbe address like TCM, DDR, Flexspi NOR. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-05-21imx9: use i.MX generic rom api functionPeng Fan
There is no need to save gd with using the generic rom api function, so simplify code. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-05-21imx9: correct coding stylePeng Fan
The end brace should be in a new line Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-05-21imx9: add i.MX93 variants supportPeng Fan
According to datasheet, iMX93 has fused parts with CORE1 or NPU or both disabled. So update code to support it, the kernel device tree runtime update will be added in future patches. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-05-21imx9: clock: config arm alt root to 500mhzPeng Fan
Config the A55 alt root clock to 500MHz(LD mode frequency) by default. Normally, this clock root is only used as an intermediate clock soure for A55 core/dsu when change the ARM PLL frequency. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-05-21imx9: clock: add CONFIG_IMX9_LOW_DRIVE_MODE supportPeng Fan
Add CONFIG_IMX9_LOW_DRIVE_MODE in imx9 clk, later we will add board support Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-05-21imx9: clock: clear HW_CTRL_SELPeng Fan
The HW_CTRL_SEL should be cleared when configuring PLL to avoid potential glitch Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-05-21imx9: Get market segment and speed gradingPeng Fan
Get the chip's market segment and speed grading from fuse and print them in boot log as other i.MX series. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-05-21imx9: soc: support reset causePeng Fan
Support print reset cause. Since SRSR is not accessible from non-secure world, so first save it to grp0, then read it in non-secure world. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-05-21imx9: Change hard coded MAC to read from fuseYe Li
The MAC addresses are hard coded for bring up. Change it to support reading from fuse. Reviewed-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-05-21imx9: cut off OPTEE memory region from U-BootPeng Fan
OPTEE memory region is set secure access only in ATF with configuration to TRDC, and need to remove it from U-Boot, otherwise U-Boot and Kernel may crash when accessing the memory Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-05-21imx9: simplify clk settingsPeng Fan
Simplify the clk root settings with an array Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-05-21imx9: correct getting LPI2C clkPeng Fan
LPI2C_CLK_ROOT should be used instead of LPUART_CLK_ROOT for i2c Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-05-21imx9: use parameter freq when set_arm_clkPeng Fan
The freq parameter was ignored, should use it when configuring ARM PLL Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-05-21imx9: add more PLL settingsPeng Fan
Add more PLL settings for A55 and Display Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-05-21imx9: configure M33 systick to 24MPeng Fan
The M33 systick should be 24M per reference mannual, so correct it. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-05-21imx: move imx8 sci header file to include/firmware/imxPeng Fan
Move imx8 sci header file to include/firmware/imx, then we could use build macro to reuse some i.MX8 drivers for i.MX9, such as drivers/cpu/imx8_cpu.c. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Stefano Babic <sbabic@denx.de>
2023-05-21imx: spl_imx_romapi: typo fixPeng Fan
Unknow->Unknown Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-05-21imx8ulp: build ahabPeng Fan
The ahab was missed to be compiled, so add it back. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-05-21ARM: dts: imx7d-sdb-u-boot: Fix usdhc1 UHS operationFabio Estevam
Commit 1a7904fdfa7d ("mmc: fsl_esdhc_imx: Use esdhc_soc_data flags to set host caps") exposed the following SD card error: U-Boot 2023.04-00652-g487e42f7bc5e (Apr 05 2023 - 22:14:21 -0300) CPU: Freescale i.MX7D rev1.0 1000 MHz (running at 792 MHz) CPU: Commercial temperature grade (0C to 95C) at 35C Reset cause: POR Model: Freescale i.MX7 SabreSD Board Board: i.MX7D SABRESD in non-secure mode DRAM: 1 GiB Core: 100 devices, 19 uclasses, devicetree: separate PMIC: PFUZE3000 DEV_ID=0x30 REV_ID=0x10 MMC: FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 2 Loading Environment from MMC... Card did not respond to voltage select! : -110 *** Warning - No block device, using default environment The reason of the problem, as explained by Ye Li: "When UHS is enabled in defconfig, the usdhc1 node in imx7d-sdb.dts does not configure pad for VSELECT, also the data pad should be set to 100Mhz/200Mhz pin states." Apply these changes into u-boot.dtsi for now. When these changes reach the Linux mainline imx7d-sdb, they can be dropped from u-boot.dtsi. This fixes UHS mode on the imx7d-sdb board. Suggested-by: Ye Li <ye.li@nxp.com> Signed-off-by: Fabio Estevam <festevam@denx.de> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2023-05-21thermal: imx_tmu: Move architecture code into driverMarek Vasut
Stop polluting the architecture directory with driver specific code, move it into driver where it should be. Split the code slightly so the MX8MM/MX8MN fuse readout and programming and MX8MP fuse readout and programming are in their separate functions, and called in case of matching SoC. Signed-off-by: Marek Vasut <marex@denx.de> Reviewed-by: Fabio Estevam <festevam@denx.de> Reviewed-by: Andrejs Cainikovs <andrejs.cainikovs@toradex.com>
2023-05-21ARM: imx: Fix parsing of ROM log event IDs on iMX8MFedor Ross
It seems like the ROM log events for the iMX8M are not fully covered by AN12853 i.MX ROMs Log Events, Rev. 0, May 2020. On iMX8M the ROM event ID 0x82 seems to use parameter0 which stops the parsing because the end of list is detected too early. This patch adds ROM event ID 0x82 and skips the next word if ID 0x82 is parsed. Fixes: a5ee05cf71 ("ARM: imx: Pick correct eMMC boot partition from ROM log") Signed-off-by: Fedor Ross <fedor.ross@ifm.com> Cc: Fabio Estevam <festevam@gmail.com> Cc: Marek Vasut <marex@denx.de> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2023-05-16Merge tag 'xilinx-for-v2023.07-rc3' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-microblaze Xilinx changes for v2023.07-rc3 .mailmap - Fix Xilinx IDs ZynqMP: - Fix R5 split boot mode - DT fixes - sync with Linux Xilinx: - Enable virtio and RNG support - Enable ADI ethernet phy SPI/Zynq: - Fix dummy byte calculation
2023-05-15arm64: zynqmp: Fix User MTD partition sizeMichal Simek
The commit c8630167e0dc ("arm64: zynqmp: Add mtd partition for secure OS storage area") didn't update User partition size that's why size was beyond actual device size. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/0a56405553b87a75e066cd71697cafe7c1c97eef.1681309812.git.michal.simek@amd.com
2023-05-15arm64: zynqmp: Fix issue of apps executing from R5 core 1Ashok Reddy Soma
In current implementation, applications can execute only on R5 core 0. The boot address for R5 core 1 is not supplied. Pass TCM address for R5 core 1 based on the argument to fix the issue. Remove incomplete comment. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/da865717d26648ab7a84345ca8749712efdddee5.1680699999.git.michal.simek@amd.com
2023-05-15ARM: zynq: Sync Microzed board with Linux kernelMichal Simek
Fix model name, node locations and also add pinctrl description for usb. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/3295fde73db13a712b65f4967eb5f39ced895ad4.1679988091.git.michal.simek@amd.com
2023-05-15ARM: zynq: Switch from earlyprintk to earlyconMichal Simek
Switch to earlycon which is preffered over earlyprintk. It is also sync with Linux kernel (zynq-microzed). Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/d280fa18068f80412cf12c235c5245651e7062e2.1679987839.git.michal.simek@amd.com
2023-05-15arch: arm: zynqmp: mp.c: tcminit halt both cores in split modeNeal Frager
The "zynqmp tcminit split" command should halt both cores and not just RPU1 when configuring the TCM memory for split mode. Signed-off-by: Neal Frager <neal.frager@amd.com> Link: https://lore.kernel.org/r/20230323082506.31576-1-neal.frager@amd.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-05-13board: schneider: add RZN1 board supportRalph Siemsen
Add support for Schneider Electric RZ/N1D and RZ/N1S boards, which are based on the Reneasas RZ/N1 SoC devices. The intention is to support both boards using a single defconfig, and to handle the differences at runtime. Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org> Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-05-13ARM: rmobile: Add support for Renesas RZ/N1 SoCRalph Siemsen
The RZ/N1 is a family of SoC devices from Renesas, featuring: * ARM Cortex-A7 CPU (single/dual core) and/or Cortex-M3 * Integrated SRAM up to 6MB * Integrated gigabit ethernet switch * Optional DDR2/3 controller * I2C, SPI, UART, NAND, QSPI, SDIO, USB, CAN, RTC, LCD Add basic support for this family, modeled on the existing RZA1. Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org> Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-05-13ARM: dts: add devicetree for Renesas RZ/N1 SoCRalph Siemsen
This is taken directly from Linux kernel 6.3 (commit 457391b0380335d5e9a5babdec90ac53928b23b4) Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org> Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-05-13ARM: armv7: add non-SPL enable for Cortex SMPENRalph Siemsen
Commit 2564fce7eea3 ("sunxi: move Cortex SMPEN setting into start.S") added SPL_ARMV7_SET_CORTEX_SMPEN to enable setting SMP bit. For platforms not using SPL boot, add the corresponding non-SPL config, so that CONFIG_IS_ENABLED(ARMV7_SET_CORTEX_SMPEN) works as expected. Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org> Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-05-11dm: Emit the arch_cpu_init_dm() even only before relocationSimon Glass
The original function was only called once, before relocation. The new one is called again after relocation. This was not the intent of the original call. Fix this by renaming and updating the calling logic. With this, chromebook_link64 makes it through SPL. Fixes: 7fe32b3442f0 ("event: Convert arch_cpu_init_dm() to use events") Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-05-09rockchip: handle peripheral as well as otg dr_modeJohn Keeping
The OTG port is identified by inspecting the "dr_mode" property which is expected to be "otg" for this port. But it will work just as well as a device controller when dr_mode is set to "peripheral", which may be required if the mode detection pin is not set up correctly and the device controller needs to be programmed to override this. Signed-off-by: John Keeping <john@metanate.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-05-09rockchip: use standard dr_mode parsing functionJohn Keeping
Instead of duplicating the string values here, use usb_get_dr_mode() to handle the property lookup and converting the values to an enum. This is implemented with a switch in preparation for the next patch which adds extra handling for peripheral mode. Signed-off-by: John Keeping <john@metanate.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-05-09arm: dts: rockchip: rock-3a: drop u-boot,spl-boot-orderFUKAUMI Naoki
use common one defined in rk356x-u-boot.dtsi. Signed-off-by: FUKAUMI Naoki <naoki@radxa.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-05-09arm: dts: rk356x: Makefile: sortFUKAUMI Naoki
sort alphanumerically. Signed-off-by: FUKAUMI Naoki <naoki@radxa.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-05-09arm: dts: rockchip: add Radxa ROCK 4C+FUKAUMI Naoki
Linux commit 246450344dad arm64: dts: rockchip: rk3399: Radxa ROCK 4C+ Add support for Radxa ROCK 4C+ SBC. Key differences of 4C+ compared to previous ROCK Pi 4. - Rockchip RK3399-T SoC - DP from 4C replaced with micro HDMI 2K@60fps - 4-lane MIPI DSI with 1920*1080 - RK817 Audio codec Also, an official naming convention from Radxa mention to remove Pi from board name, so this 4C+ is named as Radxa ROCK 4C+ not Radxa ROCK Pi 4C+. Signed-off-by: Stephen Chen <stephen@radxa.com> Signed-off-by: Manoj Sai <abbaraju.manojsai@amarulasolutions.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: FUKAUMI Naoki <naoki@radxa.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-05-09arm: dts: rockchip: rock-pi-4: sync with Linux 6.3FUKAUMI Naoki
sync dts{,i} files for Radxa ROCK Pi 4 series with Linux 6.3. because rk3399-rock-pi-4a.dts is enough for ROCK Pi 4A/B/A+/B+ and ROCK 4SE, delete dts{,i} for ROCK Pi 4B. Signed-off-by: FUKAUMI Naoki <naoki@radxa.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-05-09rockchip: rk3328: Add support for FriendlyARM NanoPi R2CTianling Shen
The NanoPi R2C is a minor variant of NanoPi R2S with the on-board NIC chip changed from rtl8211e to yt8521s, and otherwise identical to R2S. The device tree is taken from the kernel linux-next branch: https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/?id=004589ff9df5b75672a78b6c3c4cba93202b14c9 Signed-off-by: Tianling Shen <cnsztl@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-05-06board: rockchip: add Anbernic RGXX3 Series DevicesChris Morgan
The Anbernic RGxx3 is a "pseudo-device" that encompasses the following devices: - Anbernic RG353M - Anbernic RG353P - Anbernic RG353V - Anbernic RG353VS - Anbernic RG503 The rk3566-anbernic-rgxx3.dtsi is synced with upstream Linux, but rk3566-anbernic-rgxx3.dts is a U-Boot specific devicetree that is used for all RGxx3 devices. Via the board.c file, the bootloader automatically sets the correct fdtfile, board, and board_name environment variables so that the correct devicetree can be passed to Linux. It is also possible to simply hard-code a single devicetree in the boot.scr file and use that to load Linux as well. The common specifications for each device are: - Rockchip RK3566 SoC - 2 external SDMMC slots - 1 USB-C host port, 1 USB-C peripheral port - 1 mini-HDMI output - MIPI-DSI based display panel - ADC controlled joysticks with a GPIO mux - GPIO buttons - A PWM controlled vibrator - An ADC controlled button All of the common features are defined in the devicetree synced from upstream Linux. TODO: DSI panel auto-detection for the RG353 devices (requires porting of DSI controller driver and DSI-DPHY driver to send DSI commands to the panel). Signed-off-by: Chris Morgan <macromorgan@hotmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-05-06arm: stm32mp: spl: fix function with fdt_addr_t inputJohan Jonker
The fdt_addr_t and phys_addr_t size have been decoupled. A 32bit CPU can expect 64-bit data from the device tree parser, so fix ofnode_get_addr_size function with fdt_addr_t input to be able to handle both sizes for stm32mp SoC in spl.c file. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-05-06drivers: fix debug string with fdt_addr_t inputJohan Jonker
The fdt_addr_t and phys_addr_t size have been decoupled. A 32bit CPU can expect 64-bit data from the device tree parser, so fix some debug strings with fdt_addr_t to be able to handle both sizes. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-05-06drivers: use dev_read_addr_ptr when cast to pointerJohan Jonker
The fdt_addr_t and phys_addr_t size have been decoupled. A 32bit CPU can expect 64-bit data from the device tree parser, so use dev_read_addr_ptr instead of the dev_read_addr function in the various files in the drivers directory that cast to a pointer. As we are there also streamline the error response to -EINVAL on return. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-05-06rockchip: rk3288: syscon_rk3288: store syscon platdata in regmapJohan Jonker
The Rockchip SoC rk3288 has 2 types of device trees floating around. A 64bit reg size when synced from Linux and a 32bit for U-boot. A pre-probe function in the syscon class driver assumes only 32bit. For other odd reg structures the regmap must be defined in the individual syscon driver. Store rk3288 platdata in a regmap before pre-probe during bind. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2023-05-05Merge tag 'fsl-qoirq-2023-5-5' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-fsl-qoriq fsl-ls1088a device tree update enable DM_SERIAL for ten64 check for crypto node first in fdt_fixup_remove_jr
generated by cgit v1.2.3 (git 2.0.4) at 2025-08-06 09:06:21 +0000